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| SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Description The SX8723 is a data acquisition system based on Semtech's low power ZoomingADCTM technology. It directly connects most types of miniature sensors with a general purpose microcontroller. With 2 differential inputs, it can adapt to multiple sensor systems. Its digital outputs are used to bias or reset the sensing elements. Features * * * * * * * * * * Up to 16-bit differential data acquisition Programmable gain: (1/12 to 1000) Sensor offset compensation up to 15 times full scale of input signal 2 differential or 4 single-ended signal inputs Programmable Resolution versus Speed versus Supply current 2 digital outputs to bias Sensors Internal or external voltage reference Internal time base Low-power (250 uA for 16b @ 500 S/s) I2C interface Applications * * * * Industrial pressure sensing Industrial temperature sensing Barometer Compass Ordering Information Device Package SX8723E083TRT MLPD-W-12 4x4 1) Available in tape and reel only 2) Lead free, WEEE and RoHS compliant. Functional Block Diagram SX8723 - VBATT VREF + - + - AC0 AC1 AC2 AC3 AC4 AC5 SIGNAL MUX REF MUX + ZoomingADCTM PGA ADC READY CONTROL LOGIC D0 D1 GPIO CHARGE PUMP 4MHz OSC I2C SCL SDA MCU VPUMP VSS V1.5 (c) 2007 Semtech Corp. 1 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Table of Contents Description..............................................................................................................................................................1 Applications............................................................................................................................................................1 Features ..................................................................................................................................................................1 Ordering Information .............................................................................................................................................1 Functional Block Diagram.....................................................................................................................................1 Absolute Maximum Ratings ..................................................................................................................................4 Electrical Characteristics ......................................................................................................................................5 ZoomingADC Specifications.................................................................................................................................6 Timing Characteristics ..........................................................................................................................................8 2 I C Timing Waveforms ...........................................................................................................................................8 Pin Configuration ...................................................................................................................................................9 Marking Information...............................................................................................................................................9 Pin Description .......................................................................................................................................................9 Circuit Description ...............................................................................................................................................10 General Description .............................................................................................................................................. 10 Block Diagram ....................................................................................................................................................... 10 VREF ..................................................................................................................................................................... 10 GPIO ..................................................................................................................................................................... 11 Charge Pump ........................................................................................................................................................ 12 RC Oscillator ......................................................................................................................................................... 13 2 I C.......................................................................................................................................................................... 14 2 I C Communication Format ................................................................................................................................... 14 2 I C Address ........................................................................................................................................................... 14 ZoomingADC ........................................................................................................................................................15 Features ................................................................................................................................................................ 15 Overview ............................................................................................................................................................... 15 ZADC Description.................................................................................................................................................. 15 Acquisition Chain................................................................................................................................................... 15 Registers ............................................................................................................................................................... 17 ZADC Detailed Functionality Description .............................................................................................................. 18 Continuous-Time vs. On-Request......................................................................................................................... 18 Input Multiplexers .................................................................................................................................................. 19 Programmable Gain Amplifiers ............................................................................................................................. 20 PGA & ADC Enabling............................................................................................................................................ 21 PGA1 ..................................................................................................................................................................... 21 PGA2 ..................................................................................................................................................................... 21 PGA3 ..................................................................................................................................................................... 21 ADC Characteristics .............................................................................................................................................. 22 Conversion Sequence ........................................................................................................................................... 22 Over-Sampling Frequency .................................................................................................................................... 22 Over-Sampling Ratio ............................................................................................................................................. 23 Elementary Conversions ....................................................................................................................................... 23 Resolution ............................................................................................................................................................. 24 Conversion Time and Throughput......................................................................................................................... 25 Output Code Format ............................................................................................................................................. 26 Power Saving Modes ............................................................................................................................................ 27 Registers Map ....................................................................................................................................................... 28 Registers Descriptions .......................................................................................................................................... 28 RC Register........................................................................................................................................................... 28 GPIO Registers ..................................................................................................................................................... 29 ZADC Registers .................................................................................................................................................... 30 Mode Register ....................................................................................................................................................... 31 Optional Operating Modes: External Voltage Reference Option .......................................................................... 32 Application Hints..................................................................................................................................................33 Recommended Operation Mode and Registers Settings...................................................................................... 33 Operation Mode..................................................................................................................................................... 33 V1.5 (c) 2007 Semtech Corp. www.semtech.com 2 SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Registers Settings ................................................................................................................................................. 33 Schematic.............................................................................................................................................................. 34 Input Impedance.................................................................................................................................................... 35 Switched Capacitor Principle ................................................................................................................................ 36 PGA Settling or Input Channel Modifications ........................................................................................................ 37 PGA Gain & Offset, Linearity and Noise ............................................................................................................... 37 Frequency Response ............................................................................................................................................ 38 Power Reduction ................................................................................................................................................... 39 Typical Performance ............................................................................................................................................40 Linearity ................................................................................................................................................................. 40 Integral Non-Linearity............................................................................................................................................ 40 Differential Non-Linearity....................................................................................................................................... 43 Noise ..................................................................................................................................................................... 44 Gain Error and Offset Error ................................................................................................................................... 46 Power Consumption .............................................................................................................................................. 47 PCB Layout Considerations................................................................................................................................49 How to Evaluate....................................................................................................................................................49 Package Outline Drawing: MLPD-W-12 4x4.......................................................................................................50 Land Pattern Drawing: MLPD-W-12 4x4.............................................................................................................51 Tape and Reel Specification ...............................................................................................................................52 V1.5 (c) 2007 Semtech Corp. 3 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside the parameters specified in the Electrical Characteristics section is not implied. Parameter Power supply Storage temperature Temperature under bias Max sensor common mode Input voltage Peak reflow temperature TPKG Notes: This device is ESD sensitive. Use of standard ESD handling precautions is required. Symbol VBATT TSTORE TBIAS VVR_P VVR_N Comments / Conditions Min VSS - 0.3 -55 -40 VSS - 300 VSS - 300 Max 5.7 150 140 VBATT + 300 VBATT + 300 260 Unit V C C mV mV C V1.5 (c) 2007 Semtech Corp. 4 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Electrical Characteristics All values are valid within the operating conditions unless otherwise specified. Parameter Operating conditions Power supply Operating temperature VBATT TOP 2.4 -40 5.5 125 V C Symbol Comments / Conditions Min Typ Max Unit Current consumption Active current, @ 30 5.5 V C, I OP 16 b @ 250 Sample/s ADC, fs = 125 kHz 16 b @ 1 kSample/s PGA3 + ADC, fs= 500 kHz 16 b + gain 1000 @ 1 kSample/s PGA3,2,1 + ADC, fs = 500kHz Active current, @ 30 3.3 V C, I OP 16 b @ 250 Sample/s PGA3 + ADC, fs = 125 kHz 16 b @ 1 kSample/s PGA3 + ADC, fs= 500 kHz 16 b + gain 1000 @ 1 kSample/s PGA3,2,1 + ADC, fs = 500kHz Sleep current Isleep @ 30 C up to 85 C @125 C 250 700 1000 150 300 850 75 100 150 200 nA 300 800 1200 A A Time base Max ADC over-sampling frequency Min ADC over-sampling frequency FSmax FSmin @ 25 C @ 25 C 450 56.25 500 62.5 550 68.75 kHz kHz Digital I/O Input logic high Input logic low Output logic high Output logic low VIH VIL VOH VOL IOH < 4mA IOL < 4mA 0.4 0.7 0.3 VBATT-0.4 VBATT VBATT V V VREF: Internal Bandgap Reference Absolute output voltage Variation over Temperature Total Output Noise VBATT > 3V VBATT > 3V, ref to 25 C VBATT > 3V, rms, broadband 1.19 -1 1.22 1.25 +1 1 V % mV V1.5 (c) 2007 Semtech Corp. 5 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING ZoomingADC Specifications Unless otherwise specified: Temperature TA = +25 C, VDD = +5V, GND = 0V, VREF, ADC = +5V, VIN = 0V, over-sampling frequency fS = 250 kHz, PGA3 on with Gain = 1, PGA1&PGA2 off, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '01'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2. Bandgap chopped at NELCONV rate. Parameter Analog Input Symbol Comments / Conditions Gain = 1, OSR = 32 (Note 1) Min -2.42 -24.2 -2.42 Typ Max 2.42 24.2 2.42 VDD Unit V mV mV V Differential Input Voltage Ranges VIN = (VINP - VINN) Reference Voltage Range VREF, ADC = (VREFP - VREFN) Gain = 100, OSR = 32 Gain = 1000, OSR = 32 Programmable Gain Amplifier (PGA) Total PGA Gain PGA1 Gain PGA2 Gain PGA3 Gain Gain Setting Precision (each stage) Gain Temperature Dependence PGA2 Offset PGA3 Offset Offset Setting Precision (PGA2 or 3) Offset Temperature Dependence Input Impedance PGA1 Input Impedance PGA2, PGA3 Output RMS noise Gain = 1 (Note 3) Gain = 10 (Note 3) Maximal gain (Note 3) PGA1 (Note 4) PGA2 (Note 5) PGA3 (Note 6) 1500 150 150 205 340 365 GDoff2 GDoff3 Step = 0.2 V/V, See Table 7 Step = 1/12 V/V, See Table 9 (Note 2) -1 -63/12 -3 0.5 5 GDTOT GD1 GD2 GD3 (Note 1) See Table 5 See Table 6 Step = 1/12 V/V, See Table 8 1/12 1 1 0 -3 0.5 5 1 63/12 3 1000 10 10 127/12 3 V/V V/V V/V V/V % ppm/ C V/V V/V % ppm/ C k k k V V V ADC Static Performance Resolution, n No Missing Codes Gain Error Offset Error (Note 7) (Note 8) (Note 9) n = 16 bits (Note 10) n = 12 Bits (Note 11) n = 16 Bits (Note 11) n = 12 Bits (Note 12) n = 16 Bits (Note 12) VSS-0.3 PSRR VDD = 5V 0.3V (Note 13) VDD = 3V 0.3V (Note 13) 78 72 0.15 1 1 0.6 1.5 0.5 0.5 VBATT+0.3 6 16 16 Bits Bits % % LSB LSB LSB LSB LSB V dB dB Integral Non-Linearity, INL Differential Non-Linearity, DNL Common Mode input range Power Supply Rejection Ratio ADC Dynamic Performance Conversion Time Throughput Rate (Continuous Mode) Nbr of Initialization Cycles TCONV 1/TCONV NINIT n = 12 bits (Note 14) n = 16 bits (Note 14) n = 12 bits, fS = 250kHz n = 16 bits, fS = 250kHz 0 133 1027 1.88 0.485 2 cycles/fS cycles/fS kSps kSps cycles V1.5 (c) 2007 Semtech Corp. 6 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Parameter Nbr of End Conversion Cycles PGA Stabilization Delay Symbol NEND Comments / Conditions (Note 15) Min 0 Typ OSR Max 5 Unit cycles cycles ADC Digital Output Output Data Coding Binary Two's Complement See Table 15 and Table 16 Power Supply Voltage Supply Range Analog Quiescent Current Total Consumption ADC Only Consumption PGA1 Consumption PGA2 Consumption PGA3 Consumption Analog Power Dissipation Normal Power Mode 3/4 Power Reduction Mode 1/2 Power Reduction Mode 1/4 Power Reduction Mode IQ VDD Only ZoomingADC VDD = 5V/3V VDD = 5V/3V VDD = 5V/3V VDD = 5V/3V VDD = 5V/3V All PGAs & ADC Active VDD = 5V/3V (Note 16) VDD = 5V/3V (Note 17) VDD = 5V/3V (Note 18) VDD = 5V/3V (Note 19) 4.0/2.0 3.2/1.6 2.4/1.1 1.5/0.7 mW mW mW mW 800/675 260/190 190/170 150/135 200/180 A A A A A 2.4 5 5.5 V Temperature Operating Range -40 125 C Notes: (1) Gain defined as overall PGA gain GDTOT = GD1GD2GD3. Maximum input voltage is given by: VIN, MAX = (VREF,ADC/2)(OSR/OSR+1). (2) Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1. (3) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS = 500kHz. This figure must be multiplied by 2 for fS = 250kHz, 4 for fS = 125kHz. Input impedance is proportional to 1/ fS. (4) Figure independent on PGA1 gain and sampling frequency fS. (5) Figure independent on PGA2 gain and sampling frequency fS. (6) Figure independent on PGA3 gain and sampling frequency fS. (7) Resolution is given by n = 2log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8. (8) If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data. (9) Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function (with the offset error removed). (10) Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For 1 LSB offset, NELCONV must be 2. (11) INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over the full scale. (For 16 bits INL set PGA3 on). (12) DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes. (13) Figures for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage changes. (14) Conversion time is given by: TCONV = (NELCONV (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8. (15) PGAs are reset after each writing operation to registers RegACCfg1-5. The ADC must be started after a PGA or inputs commonmode stabilization delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching. Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without the PGAs. (16) Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = '11' and IB_AMP_ADC[1:0] = '11'. (17) Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '10', IB_AMP_ADC[1:0] = '10'. (18) Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = '01', IB_AMP_ADC[1:0] = '01'. (19) Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '00', IB_AMP_ADC[1:0] = '00'. V1.5 (c) 2007 Semtech Corp. 7 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Timing Characteristics Parameter READY pulse width (2) Symbol tIRQ Comments / Conditions Min Typ 1 Max Unit 1/FS Interrupt (Ready) timing specification I2C timing specifications(1) SCL clock frequency SCL low period SCL high period Data setup time Data hold time Repeated start setup time Start condition hold time Stop condition hold time Bus free time between stop and start fSCL tLOW tHIGH tSU;DAT tHD;DAT tSU;STA tHD;STA tSU;STO tBUF 0 1.3 0.6 100 0 0.6 0.6 0.6 1.3 400 kHz s s ns ns s s s s Input glitch suppression tSP 50 ns Notes: (1) All timing specifications are referred to VILmin and VIHmax voltage levels defined for the SCL and SDA pins. (2) The READY pulse indicates End of Conversion. This is a Low going pulse of duration equal to one cycle of the ADC sampling rate. I2C Timing Waveforms SDA SCL tSU;STA tHD;STA 2 tSU;STO tBUF Figure 1 - I C Start and Stop timings SDA SCL tLOW tHIGH 2 tSU;DAT tHD;DAT tSP Figure 2 - I C Data timings V1.5 (c) 2007 Semtech Corp. 8 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Pin Configuration Marking Information 8723 yyww xxxxx xxxxx Eyww = Date code xxxx = Semtech lot number Pin Description Pin 1 2 3 4 5 6 Name AC4 AC5 VBATT VSS READY D1 Type Analog Input Analog Input Power Input Power Input Digital Output Digital IO + analog Function Differential sensor input in conjunction with AC5 Differential sensor input in conjunction with AC4 2.4V to 5.5V power supply Chip Ground Conversion complete flag. Digital output sensor drive (VBATT or VSS) VREF Input in optional operating mode 7 8 9 10 11 12 13 D0 SDA SCL VPUMP AC2 AC3 VSS Digital IO + analog Digital IO Digital IO Power IO Analog Input Analog Input Power Input Digital output sensor drive (VBATT or VSS) VREF Output in optional operating mode I2C Data I2C Clock. Up to 400KHz. Charge pump output. Raises ADC supply above VBATT if VBATT supply is too low. Recommended range for capacitor is 1nF to 10 nF. Connect the capacitor to GND. Differential sensor input in conjunction with AC3 Differential sensor input in conjunction with AC2 Bottom ground pad (1) Notes: (1) This pin is internally connected to VSS. It should also be connected to VSS on PCB to reduce noise and improve thermal behavior. V1.5 (c) 2007 Semtech Corp. 9 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Circuit Description General Description The SX8723 is a complete low-power acquisition path with programmable gain, acquisition speed and resolution. Block Diagram SX8723 - VBATT VREF + - + - AC0 AC1 AC2 AC3 AC4 AC5 SIGNAL MUX REF MUX + ZoomingADC TM PGA ADC READY CONTROL LOGIC D0/REFOUT D1/REFIN GPIO CHARGE PUMP 4MHz OSC I 2C SCL SDA VPUMP VSS Figure 3 - SX8723 Block Diagram VREF The internally generated VREF is a trimmed bandgap reference with a nominal value of 1.22V that provides a stable voltage reference for the ZoomingADC. This reference voltage is directly connected to one of the ZoomingADC reference multiplexer inputs. The bandgap voltage stability is only guaranteed for VBATT voltages of 3V and above. As VBATT drops down to 2.4V, the bandgap voltage could reduce by up to 50mV. The bandgap has relatively weak output drive so it is recommended that if the bandgap is required as a signal input then PGA1 must be enabled with Gain = 1. V1.5 (c) 2007 Semtech Corp. 10 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING GPIO The GPIO block is a multipurpose 4 bit input/output port. In addition to digital behavior, D0 and D1 pins can be programmed as analog pins in order to be used as output (reference voltage monitoring) and input for an external reference voltage (For further details see Figure 14, Figure 15, Figure 16 and Figure 17). Each port terminal can be individually selected as digital input or output. RegOut[4] RegOut[0] 0 D0/REFOUT 1 RegIn[0] RegMode[1] + 0 1 VREF ZoomingADC RegMode[0] RegOut[5] RegOut[1] 1 D1/REFIN 0 RegIn[1] Figure 4 - GPIO Block Diagram The direction of each bit within the GPIO block (input only or input/output) can be individually set using the 4 th and 5 bits of the RegOut register. If D[x]_DIR = 1, both the input and output buffer are active on the corresponding GPIO block pin. If D[x]_DIR = 0, the corresponding GPIO block pin is an input only and the output buffer is in high impedance. After power on reset the GPIO block pins are in input/output mode (D[x]_DIR are reset to 1) The input values of GPIO block are available in RegIn register (read only). Reading is always direct - there is no debounce function in the GPIO block. In case of possible noise on input signals, an external hardware filter has to be realized. The input buffer is also active when the GPIO block is defined as output and the effective value on the pin can be read back. Data stored in the 1 and 2 bits of RegOut register are outputted at GPIO block if D[x]_DIR = 1. The default values after power on reset is low (0). The digital pins are able to deliver a driving current up to 8 mA. When the bits VREF_D0_OUT and VREF_D1_IN in the RegMode register are set to 1 the D0 and D1 pins digital behavior are automatically bypassed in order to either input or output the voltage reference signals. st nd th V1.5 (c) 2007 Semtech Corp. 11 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Charge Pump This block generates a supply voltage able to power the analog switch drive levels on the chip. The minimum acceptable switch supply is 3V which means that if VBATT drops below 3V then the block should be activated to generate a voltage of 3V or above. If VBATT is greater than 3V then VBATT may be switched straight through to the VPUMP output. If control input bit MULT_FORCE_OFF = 1 in RegMode register then the charge pump is disabled and VBATT is permanently connected to VPUMP. If control input bit MULT_FORCE_ON = 1 in RegMode register then the charge pump is permanently enabled. This overrides MULT_FORCE_OFF bit in RegMode register. If MULT_FORCE_ON = 0 and MULT_FORCE_OFF = 0 bits in RegMode register then the charge pump will start if VBATT drops below 3V, otherwise VBATT will be switched directly through to VPUMP. These controls are supplied to give the user the option of fixing the charge pump state to avoid it turning off and on when VBATT is close to 3V. The cell will use the on-chip bandgap reference and comparator to detect when VBATT is too low. When activated, the block will use the charge pump to boost the VBATT voltage to above 3V but with diode limiting to ensure that the generated voltage never exceeds 0.7V above VBATT. An external capacitor is required on VPUMP whenever the power supply is supposed to be less or drop below 3V. This capacitor should be large enough to ensure that generated voltage is smooth enough to avoid affecting conversion accuracy but not so large that it gives an unacceptable settling time. A recommended value is around 2.2nF. The block will also indicate when the pumped output voltage is sufficiently high to allow ADC conversions to be started. This will be a simple comparison which will give a ready signal when the VPUMP output is 3V or above. V1.5 (c) 2007 Semtech Corp. 12 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING RC Oscillator This block provides the master clock reference for the chip. It produces a clock at 4 MHz which is divided internally in order to generate the clock sources needed by the other blocks. The oscillator technique is a low power relaxation design and it is designed to vary as little as possible over temperature and supply voltage. This oscillator is trimmed at manufacture chip test. The RC oscillator will start up after a chip reset to allow the trimming values to be read and calibration registers 2 and I C address set to their programmed values. Once this has been done, the oscillator will be shut down and 2 the chip will enter a sleep state while waiting for an I C communication. V1.5 (c) 2007 Semtech Corp. 13 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING I2C The I C interface gives access to the chip registers. It complies with the I C protocol specifications, restricted to the slave side of the communication. General features: * Slave only operation * Fast mode operation (up to 400 kHz) * Combined read and write mode support * General call reset support * 7-bit device address customization 2 * Stretch I C clock SCL only before sending ACK/NACK The interface handles I C communication at the transaction level: the processor is only aware of read and writes transactions. A read transaction is an external request to get the content of system memory location and a write transaction is an external request to write the content of a system memory location. I C Communication Format Start Slave Address W ACK Memory Address ACK Start Slave Address R ACK Data NACK Stop SDA SCL 1 Master 9 SX8723 1 Master 9 SX8723 1 Master 9 1 SX8723 9 Master 1 0 0 1 0 0 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 2 2 2 2 Figure 5 - Timing Diagram for Reading from SX8723 Start Slave Address W ACK Memory Address ACK Start Slave Address W ACK Data ACK Stop SDA SCL 1 0 0 1 0 0 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 Master 9 SX8723 1 Master 9 SX8723 1 Master 9 SX8723 1 Master 9 SX8723 Master Figure 6 - Timing Diagram for Writing to the SX8723 Start Slave Address W ACK RegACOutMsb ACK Start Slave Address R ACK Data NACK Stop SDA SCL Ready 1 9 1 9 1 9 1 9 0 0 0 0 0 1 0 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 ... ... 1 0 0 1 0 0 0 0 0 1 1 1 Master Start Slave Address W SX8723 ACK Master RegACOutLsb SX8723 ACK Start Master Slave Address R ACK SX8723 Data Master NACK Stop SDA ... SCL ... Ready 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 9 1 9 1 9 1 9 Master SX8723 Master SX8723 Master SX8723 Master Figure 7 - Timing Diagram for Reading an ADC Sample from SX8723 I C Address 2 The default I C slave address is 1001000 in binary. 2 This is the standard part I C slave address. Other addresses between 1001001 and 1001111 are available by special request. 2 V1.5 (c) 2007 Semtech Corp. 14 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING ZoomingADC Features The ZoomingADC is a complete and versatile low-power analog front-end interface typically intended for sensing applications. In the following text the ZoomingADC will be referred as ZADC. The key features of the ZADC are: * Programmable 6 to 16-bit dynamic range over-sampled ADC * Flexible gain programming between 0.5 and 1000 * Flexible and large range offset compensation * 3-channel differential or 5-channel single-ended input * 2-channel differential reference inputs * Power saving modes Overview VSS VREF AC2 AC3 AC4 AC5 AC0 AC1 fs PGA1 VIN GD1 VD1 GD2 PGA2 + - fs PGA3 VD2 GD3 + - Analog Inputs VIN,ADC ADC 16 OFF2 Input Selection VBATT Reference VSS Inputs VREF VSS + + VREF,ADC OFF3 Gain 1 Gain 2 Offset 2 ZOOM Gain 3 Offset 3 Reference Selection Figure 8 - ZADC General Functional Block Diagram The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an over sampled A/D converter. The reference voltage can be selected on two different channels. Two offset compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset allow the application to zoom in on a small portion of the reference voltage defined input range. ZADC Description Acquisition Chain Figure 8 shows the general block diagram of the acquisition chain (AC). A control block (not shown in Figure 8) manages all communications with the I2C peripheral. The clocking is derived from the internal 4 MHz Oscillator. Analog inputs can be selected through a 6 input multiplexer, while reference input is selected between two differential channels. It should however be noted that only 5 acquisition channels (including the VREF) are available when configured as single ended since the input amplifier is always operating in differential mode with both positive and negative input selected through the multiplexer. The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of an input and reference signals VIN and VREF,ADC combination, the input voltage is modulated and amplified through stages 1 to 3. Fine gain programming up to 1'000 V/V is possible. In addition, the last two stages provide programmable offset. Each amplifier can be bypassed if needed. V1.5 (c) 2007 Semtech Corp. 15 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal VIN,ADC into digital. Like most ADCs intended for instrumentation or sensing applications, the ZoomingADC is an over-sampled 1 converter (See Note ). The ADC is a so-called incremental converter; with bipolar operation (the ADC accepts both positive and negative differential input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers the quantity: VIN , ADC OUTADC FS / 2 VREF , ADC / 2 Equation 1 in two's complement (see Equation 4 and Equation 5 for details). The output code OUTADC is -FS/2 to +FS/2 for VIN,ADC -VREF,ADC/2 to +VREF,ADC/2 respectively. As will be shown, VIN,ADC is related to input voltage VIN by the relationship: VIN , ADC = GDTOT VIN - GDoff TOT VREF , ADC Equation 2 where GDTOT is the total PGA gain, and GDoffTOT is the total PGA offset. (V) 1 Note: Over-sampled converters are operated with a sampling frequency fS much higher than the input signal's Nyquist rate (typically fS is 20-1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications. V1.5 (c) 2007 Semtech Corp. 16 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Registers The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain (RegAcCfg0 to 5), and two registers are used to store the output code of the analog-to-digital conversion (RegAcOutMsb & Lsb). Bit Position 7 RegACOutLsb RegACOutMsb RegACCfg0 Default values: RegACCfg1 Default values: RegACCfg2 Default values: RegACCfg3 Default values: RegACCfg4 Default values: RegACCfg5 Default values: START 0 SET_NELC[1:0] 01 IB_AMP_PGA[1:0] 11 PGA2_GAIN[1:0] 00 Register Name 6 5 4 3 OUT[7:0] OUT[15:8] SET_OSR[2:0] 010 2 1 0 CONT 0 ENABLE[3:0] 0000 PGA2_OFFSET[3:0] 0000 0 IB_AMP_ADC[1:0] 11 FIN[1:0] 00 PGA1_G 0 0 BUSY 0 DEF 0 PGA3_GAIN[6:0] 0001100 PGA3_OFFSET[6:0] 0000000 AMUX[4:0] 00000 VMUX 0 Table 1 - Peripheral Registers to Configure the Acquisition Chain (AC) and to Store the Analog-to-Digital Conversion (ADC) Result With: * * * * * * * * * * * * * * * * * * * OUT: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15]) START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0. SET_NELC: (rw) sets the number of elementary conversions to 2 SET_NELC[1:0]. To compensate for offsets, the input signal is chopped between elementary conversions (1,2,4,8). SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]). OSR = 8, 16, 32, ..., 512, 1024. CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1. TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten. IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are disabled are bypassed. FIN: (rw) These bits set the over sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the sampling frequency is given as: 11 500 kHz, 10 250 kHz, 01 125 kHz, 00 62.5 kHz. PGA1_GAIN: (rw) sets the gain of the first stage: 0 1, 1 10. PGA2_GAIN: (rw) sets the gain of the second stage: 00 1, 01 2, 10 5, 11 10. PGA3_GAIN: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]1/12. PGA2_OFFSET: (rw) sets the offset of the second stage between -1 and +1, with increments of 0.2. The MSB gives the sign (0 positive, 1 negative); amplitude is coded with the bits PGA2_OFFSET[5:0]. PGA3_OFFSET: (rw) sets the offset of the third stage between -5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 positive, 1 negative); amplitude is coded with the bits PGA3_OFFSET[5:0]. BUSY: (r) set to 1 if a conversion is running. DEF: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one. AMUX(4:0): (rw) AMUX(4) sets the mode (0 differential inputs, 1 single ended inputs with A0 = common reference) AMUX(3) sets the sign (0 straight, 1 cross) AMUX(2:0) sets the channel. VMUX: (rw) sets the differential reference channel (0 VBATT, 1 VREF). (r = read; w = write; rw = read & write) V1.5 (c) 2007 Semtech Corp. 17 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING ZADC Detailed Functionality Description Continuous-Time vs. On-Request The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit CONT). In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new one is automatically initiated. The new value is then written in the result register, and the corresponding internal trigger pulse is generated. This operation is sketched in Figure 9. The conversion time in this case is defined as TCONV. TCONV Internal Trig Output Code RegACOut[15:0] BUSY IRQ/READY Figure 9 - ADC "Continuous-Time" Operation In the "on-request" mode, the internal behavior of the converter is the same as in the "continuous-time" mode, but the conversion is initiated on user request (with the START bit). As shown in Figure 10, the conversion time is also TCONV. TCONV Internal Trig START Request Output Code RegACOut[15:0] BUSY IRQ/READY Figure 10 - ADC "On-Request" Operation V1.5 (c) 2007 Semtech Corp. 18 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Input Multiplexers The ZoomingADC has eight analog inputs AC0 to AC7 and four reference inputs AC_R0 to AC_R3. Let us first define the differential input voltage VIN and reference voltage VREF,ADC respectively as: VIN = VINP - VINN Equation 3 and: (V) VREF , ADC = VREFP - VREFN Equation 4 (V) As shown in Table 2, the inputs can be configured in two ways: either as 4 differential channels (VIN1 = AC1 AC0,..., VIN3 = AC5 - AC4), or AC0 can be used as a common reference, providing 5 signal paths all referred to AC0. The control word for the analog input selection is AMUX[4:0]. Notice that the bit AMUX[3] controls the sign of the input voltage. AMUX[4:0] (RegACCfg5[5:1]) 00x00 00x01 00x10 10000 10001 10010 10011 10100 10101 VINP AC1 (VREF) AC3 AC5 AC0 (VSS) AC1 (VREF) AC2 VINN AC0 (VSS) AC2 AC4 AMUX[4:0] (RegACCfg5[5:1]) 01x00 01x01 01x10 11000 11001 11010 VINP AC0 (VSS) AC2 AC4 VINN AC1 (VREF) AC3 AC5 AC0 (VSS) AC1 (VREF) AC2 AC0 (VSS) AC3 AC4 AC5 11011 11100 11101 AC0 (VSS) AC3 AC4 AC5 Table 2 - Analog Input Selection Similarly, the reference voltage is chosen among two differential channels (VREF,ADC = AC_R1 - AC_R0 or VREF,ADC = AC_R3 - AC_R2) as shown in Table 3. The selection bit is VMUX. The reference inputs VREFP and VREFN (common-mode) can be up to the power supply range. VMUX (RegACCfg5[0]) 0 1 VREFP AC_R1 (VBATT) AC_R3 (VREF) VREFN AC_R0 (VSS) AC_R2 (VSS) Table 3 - Analog Reference Input Selection V1.5 (c) 2007 Semtech Corp. 19 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Programmable Gain Amplifiers As seen in Figure 8, the zooming function is implemented with three programmable gain amplifiers (PGA). These are: * PGA1: coarse gain tuning * PGA2: medium gain and offset tuning * PGA3: fine gain and offset tuning. Should be set ON for high linearity data acquisition All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and gain, as well as the offset of stages 2 and 3. These functions are examined hereafter. ENABLE[3:0] (RegACCfg1[3:0]) xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx Block ADC disabled ADC enabled PGA1 disabled PGA1 enabled PGA2 disabled PGA2 enabled PGA3 disabled PGA3 enabled PGA3_GAIN[6:0] (RegACCfg3[6:0]) 0000000 0000001 ... 0000110 ... 0001100 0010000 ... 0100000 ... 1000000 ... 1111111 PGA3 Gain GD3 (V/V) 0 1/12(=0.083) ... 6/12 ... 12/12 16/12 32/12 64/12 127/12(=10.58) Table 4 - ADC & PGA Enabling PGA1_GAIN (RegACCfg3[7]) 0 1 PGA1 Gain GD1 (V/V) 1 10 Table 8 - PGA3 Gain Settings PGA3_OFFSET[6:0] (RegACCfg4[6:0]) 0000000 0000001 0000010 ... 0010000 ... 0100000 ... 0111111 1000000 1000001 Table 5 - PGA1 Gain Settings PGA2_GAIN[1:0] (RegACCfg2[5:4]) 00 01 10 11 PGA2 Gain GD2 (V/V) 1 2 5 10 PGA3 Offset GDoff3 (V/V) 0 +1/12(=+0.083) +2/12 ... +16/12 ... +32/12 ... +63/12(=+5.25) 0 -1/12(=-0.083) Table 6 - PGA2 Gain Settings PGA2_OFFSET[3:0] (RegACCfg2[3:0]) 0000 0001 0010 0011 0100 0101 1001 1010 1011 1100 1101 PGA2 Offset GDoff2 (V/V) 0 +0.2 +0.4 +0.6 +0.8 +1 -0.2 -0.4 -0.6 -0.8 -1 1000010 ... 1010000 ... 1100000 ... 1111111 -2/12 ... -16/12 ... -32/12 ... -63/12(=-5.25) Table 9 - PGA3 Offset Settings Table 7 - PGA2 Offset Settings V1.5 (c) 2007 Semtech Corp. 20 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING PGA & ADC Enabling Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the word ENABLE and the coding given in Table 4. To reduce power dissipation, the ADC can also be inactivated while idle. PGA1 The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 5). The voltage VD1 at the output of PGA1 is: VD1 = GD1 VIN (V) Equation 5 where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN. PGA2 The second PGA has a finer gain and offset tuning capability, as shown in Table 6 and Table 7. The voltage VD2 at the output of PGA2 is given by: VD 2 = GD2 VD1 - GDoff 2 VREF , ADC (V) Equation 6 where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words PGA2_GAIN[1:0] and PGA2_OFFSET[3:0]. PGA3 The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table 8 and Table 9. The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the voltage entering the ADC is given by: VIN , ADC = GD3 VD 2 - GDoff 3 VREF , ADC (V) Equation 7 where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are PGA3_GAIN[6:0] and PGA3_OFFSET[6:0]. To remain within the signal compliance of the PGA stages, the condition: VD1 ,VD 2 < VDD (V) Equation 8 must be verified. Finally, combining equations 5 to 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related to VIN by: VIN , ADC = GDTOT VIN - GDoff TOT VREF , ADC (V) Equation 9 where the total PGA gain is defined as: GDTOT = GD3 GD2 GD1 Equation 10 and the total PGA offset is: (V/V) GDoff TOT = GDoff 3 + GD3 GDoff 2 Equation 11 V1.5 (c) 2007 Semtech Corp. 21 (V/V) www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING ADC Characteristics The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three programmable parameters. The setting of these parameters and the resulting performances are described later. * Over-sampling frequency fs * Over-Sampling Ratio OSR * Number of Elementary Conversions NELCONV Conversion Sequence A conversion is started each time the bit START or the bit DEF is set. As depicted in Figure 11, a complete analog-to-digital conversion sequence is made of a set of NELCONV elementary incremental conversions and a final quantization step. Each elementary conversion is made of (OSR+1) over-sampling periods Ts=1/fs, i.e.: TELCONV = (OSR + 1) fs (s) Equation 12 The result is the mean of the elementary conversion results. An important feature is that the elementary conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the output code. Thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.e. if NELCONV 2). A few additional clock cycles are also required to initiate and end the conversion properly. Elementary Conversion 1 + Elementary Conversion 2 Elementary Conversion NELCONV-1 + Elementary Conversion NELCONV Conversion Result Init Conversion index Offset End TCONV Figure 11 - Analog-to-Digital Conversion Sequence Note: The internal bandgap reference state may be forced High or Low, or may be set to toggle during conversion at either the same rate or half the rate of the Elementary Conversion. This may be useful to help eliminate bandgap related internal offset voltage and 1/fs noise. Over-Sampling Frequency The word FIN[1:0] (see Table 10) is used to select the over-sampling frequency fs. The over-sampling frequency is derived from the 4MHz oscillator clock. FIN[1:0] (RegACCfg2[7:6]) 00 01 10 11 Over-Sampling Frequency fs (Hz) 62.5 kHz 125 kHz 250 kHz 500 kHz Table 10 - Over-Sampling Frequency Settings V1.5 (c) 2007 Semtech Corp. 22 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Over-Sampling Ratio The over-sampling ratio (OSR) defines the number of integration cycles per elementary conversion. Its value is set with the word SET_OSR[2:0] in power of 2 steps (see Table 11) given by: OSR = 2 3+ SET _ OSR [2:0 ] Equation 13 SET_OSR[2:0] (RegACCfg0[4:2]) 000 001 010 011 100 101 110 111 Over-Sampling Ratio OSR (-) 8 16 32 64 128 256 512 1024 Table 11 - Over-Sampling Ratio Settings Elementary Conversions As mentioned previously, the whole conversion sequence is made of a set of NELCONV elementary incremental conversions. This number is set with the word SET_NELC[1:0] in power of 2 steps (see Table 12) given by: N ELCONV = 2 SET _ NELC [1:0 ] Equation 14 SET_NELC[1:0] (RegACCfg0[6:5]) 00 01 10 11 # of Elementary Conversions NELCONV (-) 1 2 4 8 Table 12 - Number of Elementary Conversion Settings As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier offsets. V1.5 (c) 2007 Semtech Corp. 23 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Resolution The theoretical resolution of the ADC, without considering thermal noise, is given by: n = 2 log 2 (OSR ) + log 2 ( N ELCONV ) Equation 15 17 15 Resolution - n [Bits] 13 11 9 7 5 000 001 010 011 100 101 110 (Bits) SET_NELC= 11 10 01 00 111 SET_OSR Figure 12 - Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] Using look-up Table 13 or the graph plotted in Figure 12, resolution can be set between 6 and 16 bits. Notice that, because of 16-bit register use for the ADC output, practically the resolution is limited to 16 bits, i.e. n 16. Even though the resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and NELCONV to higher values in order to reduce the influence of the thermal noise in the PGA and of external noises (see section "PGA Gain & Offset, Linearity and Noise" in page 37). SET_OSR [2:0] 000 001 010 011 100 101 110 SET_NELC[1:0] 00 6 8 10 12 14 16 16 01 7 9 11 13 15 16 16 10 8 10 12 14 16 16 16 11 9 11 13 15 16 16 16 111 16 16 16 16 Note: shaded area: resolution truncated to 16 bits due to output register size RegACOut[15:0] Table 13 - Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] Settings V1.5 (c) 2007 Semtech Corp. 24 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Conversion Time and Throughput As explained in Figure 12, conversion time is given by: TCONV = N ELCONV (OSR + 1) + 1 fs Equation 16 (s) and throughput is then simply 1/TCONV. For example, consider an over-sampling ratio of 256, 2 elementary conversions, and a over-sampling frequency of 500kHz (SET_OSR = "101", SET_NELC = "01", FIN = "00"). In this case, using Table 14, the conversion time is 515 over-sampling periods, or 1.03ms. This corresponds to a throughput of 971Hz in continuous-time mode. The plot of Figure 7 illustrates the classic trade-off between resolution and conversion time. SET_OSR [2:0] 000 001 010 011 100 101 110 111 SET_NELC[1:0] 01 10 19 35 67 131 259 515 1027 2051 37 69 133 261 517 1029 2053 4101 00 10 18 34 66 130 258 514 1026 11 73 137 265 521 1033 2057 4105 8201 Table 14 - Normalized Conversion Time (TCONV*fs) vs. SET_OSR[2:0] and SET_NELC[1:0] (Normalized to Over-Sampling Period 1/fs) 16.0 Resolution - n [Bits] 14.0 12.0 10.0 8.0 6.0 10 00 01 11 SET_NELC 4.0 10.0 100.0 1000.0 10000.0 Normalized Conversion Time - TCONV*fS [-] Figure 13 - Resolution vs. Normalized Conversion Time for Different SET_NELC[1:0] V1.5 (c) 2007 Semtech Corp. 25 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Output Code Format The ADC output code is a 16-bit word in two's complement format (see Table 15). For input voltages outside the range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller than 16 bits, the non-significant bits are forced to the values shown in Table 16. The output code, expressed in LSBs, corresponds to: OUTADC = 216 VIN , ADC VREF , ADC OSR + 1 OSR (LSB) Equation 17 Recalling equation 9, this can be rewritten as: OUTADC = 216 VIN VREF , ADC V GDTOT - GDoffTOT REF , ADC VIN Equation 18 OSR + 1 OSR (LSB) where, from Equation 10and Equation 11, the total PGA gain and offset are respectively: GDTOT = GD3 GD2 GD1 and: (V/V) GDoff TOT = GDoff 3 + GD3 GDoff 2 ADC Input Voltage VIN,ADC +2.46146V +2.46138V ... +75V 0V -75V ... -2.46146V -2.46154V (V/V) Output Code in Hex 7FFF 7FFE ... 0001 0000 8FFF ... 8001 8000 % of Full Scale (FS) +0.5FS ... ... ... 0 ... ... ... -0.5FS Output in LSBs +215-1=+32'767 +215-2=+32'766 ... +1 0 -1 ... -215-1=-32'767 -215=-32'768 Table 15 - Basic ADC Relationships (example for: VREF,ADC = 5V, OSR = 64, n = 16 bits) SET_OSR[2:0] 000 001 010 011 100 101 110 111 SET_NELC = 00 1000000000 10000000 100000 1000 10 - SET_NELC = 01 100000000 1000000 10000 100 1 - SET_NELC = 10 10000000 100000 1000 10 - SET_NELC = 11 1000000 10000 100 1 - Table 16 - Last Forced LSBs in Conversion Output Registers for Resolution Settings Smaller than 16 bits (n < 16) (RegACOutMsb[7:0] & RegACOutLsb[7:0]) V1.5 (c) 2007 Semtech Corp. 26 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING The equivalent LSB size at the input of the PGA chain is: LSB = 1 VREF , ADC OSR (V) 2 n GDTOT OSR + 1 Equation 19 Notice that the input voltage VIN,ADC of the ADC must satisfy the condition: VIN , ADC 1 OSR (VREFP - VREFN ) 2 OSR + 1 Equation 20 (V) to remain within the ADC input range. Power Saving Modes During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0] (see Table 17). If the system is idle, the PGAs and ADC can even be disabled, thus, reducing power consumption to its minimum. This can considerably improve battery life. IB_AMP_ADC[1:0] (RegACCfg1[7:6]) 00 01 11 00 x 01 11 x x IB_AMP_PGA[1:0] (RegACCfg1[5:4]) ADC Bias Current 1/4IADC 1/2 IADC IADC PGA Bias Current Max. fs [kHz] 125 x 250 500 1/4IPGA 1/2 IPGA IPGA 125 250 500 Table 17 - ADC & PGA Power Saving Modes and Maximum Sampling Frequency V1.5 (c) 2007 Semtech Corp. 27 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Registers Map Address RC Register 0x30 RegRCen 1 RC oscillator control Register Bits Description GPIO Registers 0x40 0x41 ADC Registers 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 RegACOutLsb RegACOutMsb RegACCfg0 RegACCfg1 RegACCfg2 RegACCfg3 RegACCfg4 RegACCfg5 8 8 7 8 8 8 7 8 LSB of the ADC result MSB of the ADC result ADC conversion control ADC conversion control ADC conversion control ADC conversion control ADC conversion control ADC conversion control RegOut RegIn 8 4 D0 to D3 pads data output and direction control D0 to D3 pads input data Mode Register 0x70 RegMode 6 Chip operating mode register Registers Descriptions The register descriptions are presented here in ascending order of Register Address. Some registers carry several individual data fields of various sizes; from single-bit values (e.g. flags), upwards. Some data fields are spread across multiple registers. Unused bits are `don't care' and writing either 0 or 1 will not affect any function of the device. After power on reset the registers will have the values indicated in the tables "Reset" column. RC Register Bit 7:1 0 RC_EN Name r Mode rw 1 Reset 000000 unused Description Enables RC oscillator. Set 0 for low power mode. Table 18 - RegRCen (0x30) V1.5 (c) 2007 Semtech Corp. 28 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING GPIO Registers Bit 7:6 5 4 3:2 1 0 D1_DIR D0_DIR D1_OUT D0_OUT Name r Mode 00 1 1 00 0 0 rw rw r rw rw Reset Unused D1 pad direction: D0 pad direction: Unused Description 1 = Output 1 = Output 0 = Input 0 = Input D1 pad output value. Only valid when D1_DIR = 1 and VREF_D1_IN = 0 D0 pad output value. VREF_D0_OUT = 0 Only valid when D0_DIR = 1 and Table - 19 RegOut (0x40) Bit 7:2 1 0 D1_IN D0_IN Name r r r Mode - Reset 000000 Unused D1 pad value D0 pad value Description Table - 20 RegIn (0x41) V1.5 (c) 2007 Semtech Corp. 29 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING ZADC Registers Bit 7:0 Name OUT[7:0] r Mode Reset 00000000 LSB of the ADC result Description Table 21 - RegACOutLsb (0x50) Bit 7:0 Name OUT[15:8] r Mode Reset 00000000 MSB of the ADC result Description Table 22 - RegACOutMsb (0x51) Bit 7 6:5 4:2 1 0 START SET_NELC[1:0] SET_OSR[2:0] CONT - Name Mode rw rw rw rw r 0 01 010 0 0 Reset Starts an ADC conversion Description Sets the number of elementary conversions Sets the ADC over-sampling rate Sets continuos ADC conversion mode unused Table 23 - RegACCfg0 (0x52) Bit 7:6 5:4 3:0 Name IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] Mode rw rw rw 11 11 Reset Description Bias current selection for the ADC Bias current selection for the PGA ADC and PGA stage enables 0000 Table 24 - RegACCfg1 (0x53) Bit 7:6 5:4 3:0 FIN[1:0] PGA2_GAIN[1:0] PGA2_OFFSET[3:0] Name Mode rw rw rw 00 00 Reset PGA2 gain selection PGA2 offset selection Description ADC Sampling Frequency selection 0000 Table 25 - RegACCfg2 (0x54) Bit 7 6:0 Name PGA1_GAIN PGA3_GAIN[6:0] Mode rw rw 0 Reset PGA1 gain selection PGA3 gain selection 0001100 Description Table 26 - RegACCfg3 (0x55) Bit 7 6:0 PGA3_OFFSET[6:0] rw 0000000 PGA3 offset selection Name Mode Reset Description Table 27 - RegACCfg4 (0x56) Bit 7 6 5:1 0 BUSY DEF AMUX[4:0] VMUX Name r Mode 0 0 rw rw rw Reset ADC activity flag Description Selects ADC & PGA default configuration Input channel configuration selector Reference source selector (VBATT = 0 or VREF = 1) 00000 0 Table 28 - RegACCfg5 (0x57) V1.5 (c) 2007 Semtech Corp. 30 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Mode Register Bit 7 6 5:4 Name MULT_READY MULT_ACTIVE CHOP r r Mode 1 0 00 Reset Function 1: Indicates that the charge pump has settled and the output voltage is sufficient for conversion 1: Indicates that the charge pump is running (either because VBATT<3V or it has been forced on) VREF chopping control 11: Chop at Nelconv/2 rate 10: Chop at Nelconv rate 01: Chop state = 1 00: Chop state = 0 (Note 1) Force charge pump On (takes priority) (Note 2) Force charge pump Off (Note 2) Enable VREF output on D0 pin rw 3 2 1 MULT_FORCE_ON MULT_FORCE_OFF VREF_D0_OUT rw rw rw 0 1 0 0 VREF_D1_IN rw 0 Enable VREF input on D1 pin Note1: The chop control is to allow chopping of the internal bandgap reference. This may be useful to help eliminate bandgap related internal offset voltage and 1/f noise. The bandgap chop state may be forced High or Low, or may be set to toggle during conversion at either the same rate or half the rate of the Elementary Conversion. (See Conversion Sequence in the ZoomingADC description) Note2: The internal charge pump may be forced On or Off to avoid conversion interruptions due to the pump switching off and on when the VBATT supply is near 3V. If the pump is on automatic, then it will activate when VBATT drops below 3V to ensure sufficient supply to the ADC. If the ADC is not being run at full rate or full accuracy then it may operate sufficiently well when VBATT is less than 3V. Table 29 - RegMode (0x70) V1.5 (c) 2007 Semtech Corp. 31 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Optional Operating Modes: External Voltage Reference Option D0 and D1 are multi-functional pins with the following functions in different operating modes (see RegMode register for control settings): 0 D0/REFOUT 1 GPIO 0 D0/REFOUT 1 GPIO RegMode[1] = 0 + 0 1 + - RegMode[1] = 1 0 1 VREF ZoomingADC VREF ZoomingADC RegMode[0] = 0 RegMode[0] = 0 1 D1/REFIN 0 1 GPIO D1/REFIN 0 GPIO Figure 14 - D0 and D1 are Digital Inputs / Outputs Figure 16 - D0 is Reference Voltage Output and D1 is Digital Input / Output 0 D0/REFOUT 0 D0/REFOUT 1 RegMode[1] = 1 RegMode[1] = 0 + 0 1 + 0 1 GPIO GPIO 1 VREF ZoomingADC ZoomingADC VREF RegMode[0] = 1 RegMode[0] = 1 1 1 D1/REFIN 0 D1/REFIN 0 GPIO GPIO Figure 15 - D0 is Digital Input / Output and D1 Reference Voltage Input Figure 17 - D0 is Reference Voltage Output and D1 is Reference Voltage Input This allows external monitoring of the internal bandgap reference or the ability to use an external reference input for the ADC, or the option to filter the internal VREF output before feeding back as VREF,ADC input. The internally generated VREF is a trimmed bandgap reference with a nominal value of 1.22V. When using an external VREF,ADC input, it may have any value between 0V and VBATT. Simply substitute the external value for 1.22 V in the ADC conversion calculations. V1.5 (c) 2007 Semtech Corp. 32 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Application Hints Recommended Operation Mode and Registers Settings Operation Mode Parameter VMUX AMUX VBATT VINP = AC3 & VINN = AC2 Value Analog multiplexers Units PGA PGA1 Gain PGA2 Gain PGA3 Gain Total Offset PGA2 Offset PGA3 Offset ADC Bias PGA Bias OFF OFF 1 0 OFF 0 50 50 V/V V/V V/V V/V V/V V/V % % ADC fs Resolution OSR NELCONV Continuous mode 250 16 512 2 ON kHz Bits OverSamples / ElementaryConversion ElementaryConversion / Conversion - Table 30 - Recommended Operation Mode Values Registers Settings Register Name RegACOutLsb RegACOutMsb RegACCfg0 RegACCfg1 RegACCfg2 RegACCfg3 RegACCfg4 RegACCfg5 START 0 SET_NELC[1:0] 01 IB_AMP_PGA[1:0] 01 PGA2_GAIN[1:0] Bit Position 7 6 5 4 OUT[7:0] OUT[15:8] SET_OSR[2:0] 110 CONT 1 ENABLE[3:0] 1001 PGA2_OFFSET[3:0] 0000 PGA3_GAIN[6:0] 0001100 PGA3_OFFSET[6:0] 0000000 DEF 0 AMUX[4:0] 00001 VMUX 0 0 3 2 1 0 Hexadecimal Value XXXXXXXX XXXXXXXX 0x3A 0x59 0x80 0x0C 0x00 0x02 IB_AMP_ADC[1:0] 01 FIN[1:0] 10 PGA1_G 0 0 BUSY 0 Table 31 - Registers Settings V1.5 (c) 2007 Semtech Corp. 33 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Schematic SX8723 VBATT REF MUX + ZoomingADC TM + 5V - VREF + - + - + 2.5V VIN AC2 AC3 SIGNAL MUX + AC4 AC5 PGA ADC READY CONTROL LOGIC D0 D1 GPIO CHARGE PUMP 4MHz OSC I 2C SCL SDA MCU VPUMP VSS Figure 18 - Recommended Operation Mode Schematic V1.5 (c) 2007 Semtech Corp. 34 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Input Impedance The PGAs of the ZoomingADC are a switched capacitor based blocks (see Switched Capacitor Principle chapter). This means that it does not use resistors to fix gains, but capacitors and switches. This has important implications on the nature of the input impedance of the block. Using switched capacitors is the reason why, while a conversion is done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency fs and to stage gain as given in Equation 21. 768 109 Hz Z in f s gain Equation 21 () The input impedance observed is the input impedance of the first PGA stage that is enabled or the input impedance of the ADC if all three stages are disabled. PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input impedance of 150 k at fs = 500 kHz (see ZoomingADC Specifications). Larger input impedance can be obtained by reducing the gain and/or by reducing the sampling frequency. Therefore, with a gain of 1 and a sampling frequency of 125 kHz, Zin > 6.1M. The input impedance on channels that are not selected is very high (>100M). V1.5 (c) 2007 Semtech Corp. 35 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Switched Capacitor Principle Basically, a switched capacitor is a way to emulate a resistor by using a capacitor. The capacitors are much easier to realize on CMOS technologies and they show a very good matching precision. V1 R V2 V1 f f V2 Figure 19 - The Switched Capacitor Principle A resistor is characterized by the current that flows through it (positive current leaves node V1): I= V1 - V2 R (A) Equation 22 One can verify that the mean current leaving node V1 with a capacitor switched at frequency f is: I = (V 1 - V 2) f C (A) Equation 23 Therefore as a mean value, the switched capacitor 1 is equivalent to a resistor. f C It is important to consider that this is only a mean value. If the current is not integrated (low impedance source), the impedance is infinite during the whole time but the transition. What does it mean for the ZoomingADC? If the fs clock is reduced, the mean impedance is increased. By dividing the fs clock by a factor 10, the impedance is increased by a factor 10. One can reduce the capacitor that is switched by using an amplifier set to its minimal gain. In particular if PGA1 is used with gain 1, its mean impedance is 10x bigger than when it is used with gain 10. Sensor impedence Sensor Current integration V1 ZoomingADC (model) f f V2 C Node Capacitance Figure 20 - The Switched Capacitor Principle One can increase the effective impedance by increasing the electrical bandwidth of the sensor node so that the switching current is absorbed through the sensor before the switching period is over. Measuring the sensor node will show short voltage spikes at the frequency fs, but these will not influence the measurement. Whereas if the bandwidth of the node is lower, no spikes will arise, but a small offset can be generated by the integration of the charges generated by the switched capacitors, this corresponds to the mean impedance effect. Note: One can increase the mean input impedance of the ZoomingADC by lowering the acquisition clock fs. One can increase the mean input impedance of the ZoomingADC by decreasing the gain of the first enabled amplifier. One can increase the effective input impedance of the ZoomingADC by having a source with a high electrical bandwidth (sensor electrical bandwidth much higher than fs). V1.5 (c) 2007 Semtech Corp. 36 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING PGA Settling or Input Channel Modifications PGAs are reset after each writing operation to registers RegAcCfg1-5. Similarly, input channels are switched after modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA or inputs common-mode stabilization delay. This is done by writing bit START several cycles after PGA settings modification or channel switching. Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without the PGAs. If the ADC is not settled within the specified period, there is most probably an input impedance problem (see previous section). PGA Gain & Offset, Linearity and Noise Hereafter are a few design guidelines that should be taken into account when using the ZoomingADCTM: 1. Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but degrades noise performance. 2. Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset. Bypass unnecessary PGAs. 3. Put most gain on PGA3 and use PGA2 and PGA1 only if necessary. 4. PGA3 should be always ON for best linearity. 5. For low-noise applications where power consumption is not a primary concern, maintain the largest bias currents in the PGAs and in the ADC; i.e. set IB_AMP_PGA[1:0] = IB_AMP_ADC[1:0] = '11'. 6. For lowest output offset error at the output of the ADC, bypass PGA2 and PGA3. Indeed, PGA2 and PGA3 typically introduce an offset of about 5 to 10 LSB (16 bit) at their output. Note, however, that the ADC output offset is easily calibrated out by software. V1.5 (c) 2007 Semtech Corp. 37 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Frequency Response The incremental ADC is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator. This filter determines the frequency response of the transfer function between the output of the ADC and the analog input VIN. Notice that the frequency axes are normalized to one elementary conversion period OSR / fs. The plots of Figure 21 also show that the frequency response changes with the number of elementary conversions NELCONV performed. In particular, notches appear for NELCONV 2. These notches occur at: f NOTCH (i ) = i fs OSR N ELCONV (Hz) for i = 1,2,..., ( N ELCONV - 1) Equation 24 and are repeated every fs / OSR. Information on the location of these notches is particularly useful when specific frequencies must be filtered out by the acquisition system. This chip has no dedicated 50/60 Hz rejection filtering but some rejection can be achieved by using Equation 24 and setting the appropriate values of OSR, fs and NELCONV. Examples: Rejection [Hz] 60 fNOTCH [Hz] 61 61 61 53 fs [kHz] 125 250 500 62.5 62.5 125 OSR [-] 1024 1024 1024 1024 1024 1024 NELCONV [-] 2 4 8 8 4 8 50 46 46 Table 32 - 60/50 Hz Line Rejection Examples Normalized Magnitude [-] Normalized Magnitude [-] 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-] 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-] 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-] N ELCONV = 1 N ELCONV = 2 Normalized Magnitude [-] Normalized Magnitude [-] 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-] N ELCONV = 4 NELCONV = 8 Figure 21 - Frequency Response: Normalized Magnitude vs. Frequency for Different NELCONV V1.5 (c) 2007 Semtech Corp. 38 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Power Reduction The ZoomingADCTM is particularly well suited for low-power applications. When very low power consumption is of primary concern, such as in battery operated systems, several parameters can be used to reduce power consumption as follows: 1. 2. 3. 4. Operate the acquisition chain with a reduced supply voltage VDD. Disable the PGAs which are not used during analog-to-digital conversion with ENABLE[3:0]. Disable all PGAs and the ADC when the system is idle and no conversion is performed. Use lower bias currents in the PGAs and the ADC using the control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0]. 5. Reduce sampling frequency. Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed. V1.5 (c) 2007 Semtech Corp. 39 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Typical Performance Note: The graphs and tables provided following this note are statistical summary based on limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range and therefore outside the warranted range. Linearity Integral Non-Linearity The different PGA stages have been designed to find the best compromise between the noise performance, the integral non-linearity and the power consumption. To obtain this, the first stage has the best noise performance and the third stage the best linearity performance. For large input signals (small PGA gains, i.e. up to about 50), the noise added by the PGA is very small with respect to the input signal and the second and third stage of the PGA should be used to get the best linearity. For small input signals (large gains, i.e. above 50), the noise level in the PGA is important and the first stage of the PGA should be used. The following figures show the Integral non linearity for different gain settings over the chip temperature range. Gain 1 -40 C 25 C 85 C 125 C V1.5 (c) 2007 Semtech Corp. 40 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Gain 10 -40 C 25 C 85 C 125 C Gain 100 -40 C 25 C 85 C 125 C V1.5 (c) 2007 Semtech Corp. 41 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Gain 1000 -40 C 25 C 85 C 125 C V1.5 (c) 2007 Semtech Corp. 42 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Differential Non-Linearity The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure 22 shows the differential non-linearity. Figure 22 - Differential Non-Linearity of the ADC Converter V1.5 (c) 2007 Semtech Corp. 43 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Noise Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions for a constant input voltage was performed to derive the equivalent noise levels of PGA1, PGA2, and PGA3. The extracted rms output noise of PGA1, 2, and 3 are given in Table 33: standard output deviation and output rms noise voltage. Figure 23 shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed). Quantization noise is dominant in this case, and, thus, the ADC thermal noise is below 16 bits. The simple noise model of Figure 24 is used to estimate the equivalent input referred rms noise VN,IN of the acquisition chain in the model of Figure 25. This is given by the relationship: VN ,IN 2 VN 1 VN 2 VN 3 GD + GD GD + GD GD GD 1 1 2 1 2 3 = (OSR N ELCONV ) Equation 25 2 2 2 (V rms) 2 where VN1, VN2, and VN3 are the output rms noise figures of Table 33, GD1, GD2, and GD3 are the PGA gains of stages 1 to 3 respectively. As shown in this equation, noise can be reduced by increasing OSR and NELCONV (increases the ADC averaging effect, but reduces noise). Parameter Standard deviation output (LSB) Output rms noise (V) at ADC PGA1 0.85 205 (VN1) PGA2 1.4 340 (VN2) PGA3 1.5 365 (VN3) Table 33 - PGA Noise Measurements (n = 16 bits, OSR = 512, NELCONV = 2, VREF = 5 V) V1.5 (c) 2007 Semtech Corp. 44 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING 80 Occurences [% of total samples] 60 40 20 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 Output Code Deviation From Mean Value [LSB] Figure 23 - ADC Noise (PGA1, 2 & 3 Bypassed, OSR = 512, NELCONV = 2) PGA1 VN1 GD1 PGA2 VN2 GD2 PGA3 VN3 GD3 fs ADC Figure 24 - Simple Noise Model for PGAs and ADC PGA1 VN,IN GD1 VN1 PGA2 VN2 GD2 PGA3 VN3 GD3 fs ADC Figure 25 - Total Input Referred Noise As an example, consider the system where: GD2 = 10 (GD1 = 1; PGA3 bypassed), OSR = 512, NELCONV = 2, VREF = 5 V. In this case, the noise contribution VN1 of PGA1 is dominant over that of PGA2. Using Equation 25, we get: VN,IN = 6.4 V (rms) at the input of the acquisition chain, or, equivalently, 0.85 LSB at the output of the ADC. Considering 0.2 V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB. Noise can also be reduced by implementing a software filter. By making an average on a number of subsequent measurements, the apparent noise is reduced the square root of the number of measurement used to make the average. V1.5 (c) 2007 Semtech Corp. 45 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Gain Error and Offset Error Gain error is defined as the amount of deviation between the ideal transfer function (theoretical Equation 18) and the measured transfer function (with the offset error removed). The actual gain of the different stages can vary depending on the fabrication tolerances of the different elements. Although these tolerances are specified to a maximum of 3%, they will be most of the time around 0.5%. Moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error in the same direction in all stages is very low. Finally, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance. Figure 26 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of FullScale Range (FSR) normalized to 25 C. Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC and the PGA1 stage are completely suppressed if NELCONV > 1. The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 27. The output offset error, expressed in LSB for 16-bit setting, is normalized to 25 Notice that if the ADC is us ed alone, the C. output offset error is below 1 LSB and has no drift. NORMALIZED TO 25 C 0.2 Gain Error [% of FSR] 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100 1 5 20 100 Temperature [C] Figure 26 - Gain Error vs. Temperature for Different PGA Gains NORMALIZED TO 25 C Output Offset Error [LSB] 100 80 60 40 20 0 -20 -40 -50 -25 0 25 50 75 100 1 5 20 100 Temperature [C] Figure 27 - Offset Error vs. Temperature for Different PGA Gains V1.5 (c) 2007 Semtech Corp. 46 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Power Consumption Figure 28 plots the variation of quiescent current consumption with supply voltage VDD, as well as the distribution between the 3 PGA stages and the ADC (see Table 34). As shown in Figure 29, if lower sampling frequency is used, the quiescent current consumption can be lowered by reducing the bias currents of the PGAs and the ADC with registers IB_AMP_PGA [1:0] and IB_AMP_ADC [1:0]. (In Figure 29, IB_AMP_PGA/ADC[1:0] = '11', '10', '00' for fS = 500, 250, 62.5 kHz respectively.) Quiescent current consumption vs. temperature is depicted in Figure 30, showing a relative increase of nearly 40% between -45 and +85C. Figure 28 - Quiescent Current Consumption vs. Supply Voltage Figure 29 - Quiescent Current Consumption vs. Supply Voltage for Different Sampling Frequencies V1.5 (c) 2007 Semtech Corp. 47 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Figure 30 - Absolute Change in Quiescent Current Consumption vs. Temperature Figure 31 - Relative Change in Quiescent Current Consumption vs. Temperature Supply VDD = 5 V VDD = 3.3 V VDD = 2.5 V Back Bone 142 98 99 ADC 127 105 105 PGA1 96 87 87 PGA2 86 73 71 PGA3 97 96 91 TOTAL 548 459 453 Unit A Table 34 - Typical Quiescent Current Distributions in Acquisition Chain (n = 16 bits, fS = 250 kHz) V1.5 (c) 2007 Semtech Corp. 48 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING PCB Layout Considerations PCB layout considerations to be taken when using the SX8723 are relatively simple to get the highest performances out of the ZoomingADC. The most important to achieve good performances out the ZoomingADC is to have a good voltage reference. The SX8723 has already an internal reference that is good enough to get the best performances with a minimal amount of external components, but, in case an external reference is needed this one must be as clean as possible in order to get the desired performance. Separating the digital from the analog lines will be also a good choice to reduce the noise induced by the digital lines. It is also advised to have separated ground planes for digital and analog signals with the shortest return path, as well as making the power supply lines as wider as possible and to have good decoupling capacitors. How to Evaluate The SX8723 is a subset of the SX8724 thus for evaluation purposes the XE8000EV121 evaluation kit can be ordered. This kit connects to any PC using a USB port. The "SX87xx Evaluation Tools" software gives the user the ability to control the SX8724 registers as well as getting the raw data from the ZoomingADC and displaying it on the "Graphical User interface". For more information please look at SEMTECH web site (http://www.semtech.com). V1.5 (c) 2007 Semtech Corp. 49 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Package Outline Drawing: MLPD-W-12 4x4 V1.5 (c) 2007 Semtech Corp. 50 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Land Pattern Drawing: MLPD-W-12 4x4 V1.5 (c) 2007 Semtech Corp. 51 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING Tape and Reel Specification V1.5 (c) 2007 Semtech Corp. 52 www.semtech.com SX8723 ZoomingADCTM for Pressure and Temperature Sensing ADVANCED COMMUNICATIONS & SENSING (c) Semtech 2007 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact Information Semtech Corporation Advanced Communication and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone (805) 498-2111 Fax : (805) 498-3804 V1.5 (c) 2007 Semtech Corp. 53 www.semtech.com |
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