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Product Overview
(R)
Integrated Circuits Group
ID242 Series
Flash Memory Card
(Model Numbers: ID242xxx)
Spec No.: CPS0002-002 Issue Date: May, 1998
SHARP
ID242 SERIES PRODUCT OVERVIEW
l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.
l When using the products covered herein, please observe the conditions written herein and the precautions
outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2). even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * Office electronics * Instrumentation and measuring equipment * Machine tools * Audiovisual equipment * Home appliances * Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * Aerospace equipment * Communications equipment for trunk lines * Control equipment for the nuclear power industry * Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company.
CPSOOOZ-002
8 May.
SHARI=
ID242 SERIES PRODUCT
OVERVIEW
Contents
P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P` P. P. P. P. P. P. P. 3 3 4 5 6 7 7 8 9 9 12 12 12 12 12 14 16 17 17 17 17 17 18 20 20 22 28 29 30 31 31 32
1. Introduction.. 2. 3. 4. 5. 6.
...............................................................................................................
Features ....................................................................................................................... Block Diagram ............................................................................................................ Pin Connections Signal Description ........... ............................................................................................... ......................................................................................................
Functions.. ................................................................................................................... 6. 1 6. 2 6. 3 Common Memory.. Attribute Memory ......................................................................................... ...........................................................................................
Function Table ................................................................................................ Structure (CIS) ...............................................................................
7. 8.
Card Information
Card Control ............................................................................................................... 8. 1 8. 2 8. 3 8. 4 Reset ............................................................................................................. Status Register ................................................................................................ Write Protect Switch.. ..................................................................................... Identifier Codes.. ........ .. ................................................................................... Register (CMR) ................................................................. ............................................................................................... ............................................................................................. Ratings ........................................................................... Conditions.. ...........................................................
9.
Component
Management Definitions.. Specifications
10. Command 11. Electrical
11. 1 Absolute
Maximum
11. 2 Recommended 11. 3 Capacitance
Operating
..................................................................................................... Test Conditions ..................................................................
11. 4 AC Input/Output 12. DC Characteristics 13. AC Characteristics
...................................................................................................... ...................................................................................................... Read Operations.. .............................................................
13. 1 Common Memory 13. 2 Command 13. 3 Attribute 13. 4 Attribute
Write Operations
: Common Memory..
........................................ P. P. P. P. P. P. P.
Memory Read Operations Memory Write Operations
............................................................... ..............................................................
13. 5 Power-Up/Power 14. Specification
Down ..................................................................................
Changes ................................................................................................
15. Other Precautions.. ...................................................................................................... 16. External Diagrams ......................................................................................................
SHARI=
1. Introduction
ID242 SERIES PRODUCT
OVERVIEW
3 --
This datasheet is for SHARP's ID242 series flash memory card. This datasheet provides all AC and DC characteristics (including timing waveforms) and a convenient reference for the device command set and the card's inteof the meth-
grated registers(including
the Flash Memory's
status registers).
This datasheet provides description
ods which are very helpful for customer to use the card.
2. Features
2.1 2.2 Type
Flash Memory
Card
Overview
250ns(@Vcc=3.3v)
Erase Unit 64K word blocks
Program/Erase Cycles
External Dimensions PCMCIA
100,000cycles/Block Type 1 54.0X 85.6X 3.3mm
TlOSO-01
2.3 2.4 2.5 2.6
Interface Function Table
Parallel I/O Interface See Function Table in page. 9 See Pin Connections Conforms to PCMCIA in page. 6 PC Card Standard 95 Card Use Connector JAE or FCN-568J068-G/O Fujitsu)
Pin Connections Type of Connector
(Card connector: JC20-J68S-NB3
2.7 2.8 2.9
Operating
Temperature
0 to 60C
-20
Storage Temperature Not designed for rated radiation
to 65C
hardened.
CPS0002.002BMay,19!
SHARP
3. Block Diagram
ID242 SERIES PRODUCT OVERVIEW
4
D<15:0> A<25:0> REG# CEl# CE2# WE# OE# RDpSYk RESET, , ,
,r
1 1
WP
:A+ '
cl
T Control Logic II,
II,t t' I t4
VPPX vcc Flash Memory Data Add RP#
RY/RY#
VPPl t
vcc t Flash Memory Data Add RP# RYrBY# *I +---(
CE# WE# OE#
* CE# + WE# + OE#
VPP2 t
vcc
vcc t Flash Memory Data + CE# Add + WE# RP# + OE# RYiBY#
VPPl t
c + -+'
= -
.
=rLc
VPPl b b VPP2 . CDl#, CDL%
II. , I :
I I
II
I
VPP2
vcc
i iI
i
vpp1
vcc
I
I
I I
t
:lash Memory Data Add RP# RY/BY# I 4 + -4
RY/BY#
OE#
I
I
__*1
OE#
I I I I * I I I , I * I 9 I I
EEPROM CE# b WE# OE# Data M Add v
, I I I I I I I I I I I I I
Figure 1. Block Giagrarn
SHARI=
4. Pin Connections
Table 1. Pin Connections
ID242 SERIES PRODUCT OVERVIEW
5
;,"
SIGNAL 1
I/O
FUNCTION IGround
ACTIVE
1 35 IGND
139 ID,,
I I/O I Data Bit 13
LOW
I I I
43 IVS,# I 44 IRFU I 45 IRFU 1 46 IA,, 1 1
0
Voltage Sense 1 1Reserved 1Reserved
I I 1Address Bit 17
54 43
55 A74 1 56 IA,, 57 VS,# I 58 IRESET
I I 0
Address Bit 23 Address Bit 24 Voltage Sense 2 HIGH
I I 1Address Bit 25 1 I I Reset
I
I
62 IBVD, 63 BVD,
0
Battery Battery
Boltage Boltage
Detect Detect
2 1
0
DR 65 DQ
66
64
I/O Data Bit 8 I/O Data Bit 9 I/O Data Bit 10 0 Card Detect 2 1Ground
D,Ll
67 ICD,# 68 IGND
CPSOOO2-002
@ May.1 998
SHARP
5. Signal Description
Table 2. Symbol Signal Description l/O
ID242 SERIES PRODUCT
OVERVIEW
Electrical interface
Function ADDRESS INPUTS: These are address bus lines which enable direct addressing of memory on the card. Signal AI) is not used in word access mode. The system should NOT access memory beyond the card's density. because the upper addresses are not decoded. DATA INPUT/OUTPUT: De through Dls constitute the bi-directional significant bit, CARD ENABLE I & 2: CEI# enables Do-D7, CE2# enables Dx-DIG. OUTPUT ENABLE: Active low signal gating read data from the memory card. WRlTE ENABLE: Active low signal gating write data to the memory c`ard. READY/BUSY OUTPUT: indicates status of internally timed erase or write activities. lD242 series has two types of Ready/Busy output mode; PCMClA mode and High-Performance mode. In PCMClA mode, a high output indicates the memory card is ready to accept accesses. A low output indicates that a device in the memory c,ard is busy. In High-Performance mode, the card outputs low when the card is in default state. A high output indicates at least one of flash memory devices in the card comes to be ready to accept accesses. CARD DETECT 1 & 2: These signals provide for card insertion detection. The signals are connected to ground internally on the memory card, and will be forced low whenever a card is placed in the socket. The host socket interface circuitry shall supply 10K or larger pull-up resistors on these signal pins. WRlTE PROTECT: Write Protect reflects the status of the Write Protect switch on the memory card. WP set to high = write protected. WRITE/ERASE GROUND: POWER SUPPLY 1 & 2: CARD POWER SUPPLY: data bus. DIG is the most
Ao-Azs
1
Pull-down (250k Q @ Vcc=Sv)
Du-D15
1/o Pull-down (2'0k ' @VCC=`V) 1 1 1 Pull-up (250k Q @Vcc=Sv) Pull-up (250k Q @ Vcc=Sv) Pull-up (250k 52 @ Vcc=Sv)
CEI#,CEZ# OE#
WE#
RDY/BSY#
0
CDt#, CD2#
0
Pull-down
Ow
WP VPPI, VW2 vcc GND REG# RESET BVDt, BVD2
o
LowPull-down OW High:Pull-up 1OOkw
1 1 0
Pull-up (250kw @Vcc=Sv) Pull-up (250kw @Vcc=Sv) Pull-up 1OOkw VSI#: Pull-down N.C. VSB: N.C. or
REGlSTER SELECT: Provides access to attribute memory when REG# is low. RESET: Active high signal for placing card in Power-On Default State.
BATTERY VOLTAGE DETECT 1 & 2: These signals are pulled high to maintain SRAM card compatibility. VOLTAGE SENSE 1 & 2: Notifies the host socket of the ClS's VCC requirements. VS I# is pulleddown to ground when using the standard ClS, that indicate 3.3V operating is available. And when using the EEPROM for ClS, the VS2# is open. That indicate the available operation voltage is 5V only. RESERVED FOR FUTURE USE
VSI#,
VS2#
0
RFU
CPSOOOZ-002@Mav.1991
SHARP
6. Functions
6.1 Common Memory 6. 1. 1
ID242 SERIES PRODUCT OVERVIEW
7 -
Common Memory Architecture
Figure 2 shows common memory architecture of ID242 series flash memory card. Device pair is consisted of two pieces of flash memory devices. Each device has individually erasable and lockable blocks. All blocks are divided into odd bytes and even bytes. Each device pair and block is selected by address bits. Table 3 shows definitions of address bits.
F100'2.0:
(a) For 2, 4, 8, 1OMB
F10580'
(b) For 16MB, 20MB Figure 2. Common Memory Architecture
Table 3. Address Difinitions Address Pifinitions Select Even / Odd byte in the byte access mode. 1Select address in the block. Select a block. 1Select a device pair. 2MB - IOMB A0 A16-Al I 1 A20-A17 1 A21-A17 1 A25-A21 1 A25-A22
T1051-01 CPS0002-002OMay.1991 3
16MB ,20MB
I 1 1
SHARP
6. 1. 2 Erase
ID242SERIESPRODUCTOVERVIEW
8
Erase is executed one block at a time. Erasable block size is 64K bytes in byte access mode and 128K bytes in word access mode. 6. 1. 3 Address Decoding
The higher address area of ID242 series flash memory card which goes beyond common memory area is not decoded in common memory access. It means that the system will access to random memory address of the memory card even if system will try to access to the memory address which exceeds memory capacity of the card. Please do not access to the memory address which goes beyond memory capacity of the card. As an enhanced function, the memory card enables to output invalid data (either of OOOOh FFFFh) when system or will access to the memory address which exceeds memory capacity of the card. Please contact our sales & marketing support to find concrete way of setting.
6.2
Attribute
Memory
Figure 3 shows attribute memory map of ID242 series flash memory card. Attribute memory is contained within the Card Control Logic. Attribute memory contains the Card Information Structure (CIS) and Component Management Registers (CMRs). The CIS contains tuple information and is located at even byte addresses beginning with address OOOOh (Please refer to section 7). The standard CIS of ID242 series flash memory card is hardwired and is for read only. As an enhanced function, the hardwired CIS area is switchable to EEPROM so that customer can program required CIS. Please contact our sales & marketing support to find concrete way of setting. The CMRs are located at even byte addresses beginning with address 4000h (Please refer to section 9).
r-------------, I I I I r-----I
I
Address I I ' 004200h
I
I I
I I c------
COMPONENT MANAGEMENT REGISTERS
I
_ 004000h
I r------
I 000200h
I
I I I
------ODD
CARD INFORMATION STRUCTURE OOOOOOh EVEN
F1003-01
Figure 3. Attribute Memory Map
CPSOOOZ-002@
May.
1998
SHARI=
6.3
6.3.1
ID242SERIESPRODUCTOVERVIEW
Function
Table
Common Memory Access
Table 4. Common Memory Access
6.3.2 Attribute Memory Access
Table 5. Attribute Memory Access
XXX:Output
data is invalid. is only for CMRs and CIS on EEPROM
The standard CIS is for read only. Write operation
7. Card Information
Structure
(CIS)
the hardwired CIS area is switchable to EEPROM so that customer
The CIS is contained within attribute memory (Please refer to section 6.2). Table 6 shows standard CIS tuples, but it is for read only. As an enhanced function, can program
required CIS. Please contact our sales & marketing
support to find concrete way of setting.
SHARP
ID242 SERIESPRODUCTOVERVIEW
Table
10
-
6. Standard
46h 48h
CIS Value 53h 48h Description S :Product Info H
Address
52h 54h 56h 58h ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h
49h 44h
I D
32h 2 34h 4 53h S 52h R 20h SPACE OOh END TEXT 53h S :Maker Info 48h H 1 41h 52h 1 50h 20h 43h 4Fh IA R IP SPACE C 0
84h 86h 88h
I ooh IEND TEXT FFh End of Tuple 1Ah Configuration Info
Last Index of Configuration Table 92h
I
40h
ICMRS Base Adress(MSB)
I
Configuration Table Entry 1
CPS0002.002@May.i9I
SHARP
1 Address I1 Value A4h 1 OCh 06h A6h A8h , 06h AAh 1 23h I ACh 1 79h
I
ID242 SERIES PRODUCT OVERVIEW
Table 8. Standard CIS (Continued) Description ]Icc Static1.2mA
1 I ICC Average lOOmA ICC Peak lOOmA ~ICCPowerdown 5OmA I [Parameter Selection
I
t
Address 1 Value 1 Description 104h 1Oh Tuple Link iO6h 108h IOAh IOCh I OEh 1lOh 112h Il4h 7Dh 7Dh 1Bh 79h I 8Eh 7Dh 1Bh 35h 35h 52h OOh OOh 1Eh 06h 02h 1 lh 1 Olh I Olh Olh Olh 20h 04h IICC Average 90mA ~ICCPeak 90mA ICC Powerdown 15OmA Parameter Selection lvpp Voltage 12V NC OK Ipp Static 15OmA Ipp Average 30mA Ipp Peak 30mA Ipp Powerdown 50mA Null Null Device Geometry Tuple Link Bus: 2bytes Erase Block: 64Kbvtes Read size: lbyte IWrite size: lbyte Partation: lblock Non-interleaved Manufacturer ID Tuple Link
L
t t t
04h 02h 79h
IIndex Vcc & Vpp IParameter Selection
AEh BOh B2h B4h B6h B8h BAh BCh BEh
I D5h 7Dh 1Bh 75h 75h I I 52h
IVpp Voltage 5V NC OK Ipp Static 15OmA Ipp Average 80mA Ipp Peak 80mA I 11ppPowerdown 50mA
116h
t 118h 1lAh 1lCh 1lEh 120h 122h 124h 126h 128h 12Ah 12Ch 12Eh 130h 132h 134h I 136h 138h 13Ah
1Bh Configuration Table Entry 2 OFh I Tuple Link I I 02h IIndex
I
I
CAh I 06h IICC PeaklOOmA
CCh CEh DOh D2h D4h D6h D8h DAh DCh DEh EOh E2h E4h E6h E8h 23h 79h 8Eh 7Dh 1Bh I 35h 35h 52h 1Bh 1lh 03h 02h 79h B5h 1Eh ICCPowerdown 50mA Parameter Selection Vpp Voltage 12V NCOK Ipp Static 1XhnA 11pp Average 30mA Ipp Peak 30mA Ipp Powerdown 50mA Configuration Table Entry 3 Tuple Link Index Vcc & Vpp Parameter Selection
vcc Voltage
I
13Ch
13Eh 14Oh
3.3v
142h
F4h F6h FAh FCh FEh IOOh 102h
B5h 9Eh 1Bh 75h 75h 52h 1Bh
Vpp Voltage 3.3V Ipp Static 15OmA Ipp Average 80mA Ipp Peak 80mA Ipp Powerdown 5OrnA Configuration Table Entry 4
144h 146h 148h 14Ah 14Ch 14Eh
BOh Manufacturer Code OOh Manufacturer Info: 06h 2MB 07h 4MB 09h 8MB OAh 1OMB ODh 16MB OEh 20MB 33h Manufacturer Info: DVO 21h Function Identification 02h Tuple Link Olh IFunction: MEMORY OOh ISystem Init: None FFh End of CIS
I I
I
I
I.
CPSOOOZ-002 0 May. 199
SHARP
8. Card
8. 1
ID242 SERIES PRODUCT OVERVIEW
12
Control
Reset
The card is in initial state directly after power-up. But we recommend to do reset operation after power-up to make sure to initialize the card. During block erase, byte write, or lock-bit configuration modes, an active RESET will abort the operation. RDYI BSY# remains low until the reset operation completes. Memory contents being altered are no longer valid; the data may be partially erased or written. The host must wait after RESET goes to logic-Low write another command, as determined by
tPHWL.
(Vu) before it can
It is important to assert RESET to the card during a system reset. If a CPU reset occurs without a card reset, the host will not be able to read from the card if that card is in a different mode when the system reset occurs. For example, if an end-user initiates a host reset when the card is in read status register mode, the host will attempt to read code from the card, but will actually read status register data. Sharp's ID242 Series Flash Memory Card allows proper card reset following a system reset through the use of the RESET input. 8. 2 Status Register
Each flash memory device in the card has status register. The status register may be read to determine when a write, block erase, or lock-bits configuration is complete, and whether that operation completed successfully (please refer to Table 10). It may be read at any time by writing the Read Status Register command (70h, 7070h) into the CUI. In word access mode, the status register data of even byte devices are output to D7-0,and the status register data of odd byte devices are output to D15-8.
8. 3
Write Protect Switch
The ID242 Series Flash Memory Card has a write protect switch on the back of the card. When the switch is in the write protect position, the card blocks all writes to the common and attribute memory without Card Management Registers region (see Figure 5). 8. 4 Read identifier Codes / Lock bits Information
Manufacture Code and Device Code are contained within each flash memory device in the memory card. The identifier code operation is initiated by writing the Read Identifier Codes command (90h, 9090h) into the CUI of each memory device. The specific address of each device is necessary to be selected to read these codes (Table 8).
F1005-01 I m
Writeble position I I Write protZ&ition
Note: The write protect switch is shown by the black square.
I
Figure 4. Write Protect Switch
CPS0002.002@May.1998
SHARP
Table 7. bit7 SR.7 WSMS Status Register bit6 SR.6 ESS
ID242 SERIES PRODUCT
OVERVIEW
13
bit5 SR.5 ECLBS STATUS
bit4 SR.4 BWSLBS
bit3 SR.3 VPPS Notes:
bit2 SR.2 BWSS
bit1 SR.l DPS
bit0 SR.0 RFU
SR.7 =WRITE STATE MACHINE I = Ready 0 = Busy
SR.6 =ERASE-SUSPEND STATUS I = Erase Suspended 0 = Erase in Progress/Completed SR.5 =ERASE AND CLEAR LOCK-BlTS STATUS 1 = Error ln Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 =BYTE WRITE AND SET LOCK-BIT 1 = Error in Byte Write or Set Block/Master Lock-Bit 0 = Successful Byte Write or Set Block/Master Lock-Bit SR.3 =VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 =BYTE WRITE SUSPEND STATUS 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR. 1 =DEVICE PROTECT STATUS 1 = Master Lock-bit,Block Lock-bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 =Reserved for Future Enhancements STATUS
Chech RDY/BSY# or SR.7 to determine block erase, word/byte write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7="0". If both SR.5 and SR.4 are " 1 "s after a block erase or lockbit configuration attempt, an improper command sequence was entred. SR.3 does not provide a continuous indication of V,, level. The WSM interrogates and indicates the V,, level only after Block Erase, Word/Byte Write, Set Block/Master Lock-bit, or Clear Lock-bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when V,,=V,,,,,,,,. SR. 1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock-bit, block lock-bit. and RP# only after Block Erase, Word/Byte Write, or Lock-bit configuration command sequences. If informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not 12V. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes commnad indicates master and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register.
Table 8.
Identifier
Codes / Lock bits
Block Lock Configuration
(X: Select Block)
D7-D I: Reserved
NOTE: A0 is ignored in word access mode. and D15-D8 outputs the Odd byte data. DPA: Address as select device pair BLKD: Block Lock Configuration Data MLKD: Master Lock Configuration Data
CPSOOO2-0028
T1052-01
May.
1999
SHARI=
9. Component
Component attribute memory.
ID242 SERIES PRODUCT
OVERVIEW
Management
Registers
Registers
(CMR)
(CMR)
beginning at address 4000h in
Management
are mapped at even byte locations
9. 1
Configuration Option Register (Address4000h)
Address 4000h Bit.7 SRESET SRESET: l=Reset State O=End Reset Cycle Bit.6 Bit.5 Bit.4 Bit.3 Reserved Bit.2 Bit. 1 Bit.0
9. 2
Card Configuration Register (Address:4002h)
Address 4002h PWDN: Bit.7 Bit.6 Bit.5 Reserved Bit.4 Bit.3 Bit.2 PWDN Bit. 1 Reserved are in PowerBit.0
l=Power-Down Device pairs that apointed by Sleep Control Register(4118h-411Ah) Down. O=Power-Up
9. 3
Socket and Copy Register (Address:4006h)
Address 4006h Bit.7 Reserved Bit.6 Bit.5 Copy No. Bit.4 Bit.3 Bit.2 Bit.1 Soket No. Bit.0
Soket No.: Socket Number Copy No.: Copy Number The card may use to distinguish between similar cards installed in a system.
TlO53.01
9. 4
Card Status Register (Address:41 OOh)
Address 41OOh Bit.7 ADM ADM: Bit.6 ADS Bit.5 SRESET Bit.4 CMWP Bit.3 PWDN Bit.2 CISWP Bit. 1 WP Bit.0 RDY/BSY
ORed value of the Ready/Busy Mask Register. 1 = Any device is masked. 0 = All Devices are not Masked. ADS: ORed value of the Sleep Control Register. I = Any device-pair is Controled power-down by bit.2 of the Card Configuration Register. SRESET: Reflects the bit.7 of the Configuration Option Register. CMWP: Reflects the bit.1 of the Write Protection Register. PWDN: Reflects the bit.2 of the Card Configuration Register. CISWP: Reflects the bit.0 of the Write Protection Register. WP: Indicates the Write Protect Switch status. I = Write Protect Switch: ON I = Write Protect Switch: OFF RDY/BSY: Reflects the Ready/Busy Status Register. 1 = All devices are READY. 0 = Any device is BUSY.
CPSOOO2.002 @ May. 1991
SHARI=
9. 5
ID242 SERIES PRODUCT
OVERVIEW
15
Write Protection Register (Address:41 04h)
Address 4104h BLKBN: CMWP: CISWP: NOTE: Bit.7 Bit.6 Bit.5 Reserved Bit.4 Bit.3 Bit.2 BLKBN Bit.1 CMWP Bit.0 CISWP
Block Locking Enable 1 = Enable Block Locking 0 = All Blocks Unlocked Common Memory Write Protect 1 = Common Memory without CIS region in Write Protect Status Common Memory CIS Write Protect I = Common Memory CIS in Write Protect Status bit. Block Locking is always enable.
ID242 series ignores BLKBN
9. 6
Sleep Control Register (Address:41 18h-411 Ah)
Address 4llAh 4118h Reserved DEVlO/ll Bit.7 Bit.6 Bit.5 Bit.4 Reserved DEV8/9 DEV6/7 DEV4/5 DEV2/3 DEVO/l mode
Tl047.01
Bit.3
Bit.2
Bit. 1
Bit.0
1= Select sleep mode device-pair If set to "l", the corresponding device-pairs are putted into deep power-down by PWDN bit of Configuration Status Register.
9. 7
Ready/Busy Mask Register (Address:41 20h-4122h)
Address 412231 4120h DEV7 DEV6 Bit.7 Bit.6 Reserved DEV5 DEV4 Bit.5 Bit.4 Bit.3 DEVll DEV3 Bit.2 DEVlO DEV2 Bit. 1 DEV9 DEVl Bit.0 DEV8 DEVO
1 =Mask the RdylBsy# The corresponding device's Rdy/Bsy# signals to set bit are ignored for card's RDY/BSY# output.
T1040.01
9. 8
Ready/Busy Status Register (Address:41 30h-4132h)
Address 4132h 4130h DEV7 DEV6 Bit.7 Bit.6 Reserved DEV5 DEV4 Bit.5 Bit.4 Bit.3 DEVll DEV3 Bit.2 DEVlO DEV2 Bit. 1 DEV9 DEVl Bit.0 DEV8 DEVO
1 =READY O=BUSY Each bit indicates the corresponding
device's Rdy/Bsy# signal.
Tl041.01
9. 9
Ready/Busy Mode Register (Address:4140h)
Address 4140h RACK: Bit.7 Bit.6 Bit.5 Reserved Bit.4 Bit.3 Bit.2 Bit. 1 RACK Bit.0 MODE
MODE:
Ready Acknowledge Bit Must-clear this bit after receiving ready status to prepare for next device's ready transition. RDY/BSY# Mode 1 = High-Performance Mode 0 = PCMCIA Mode
T1055.01
CPS0002-002@May.l99i
SHARP
IO. Command
Device operations the commands.
ID242SERIESPRODUCTOVERVIEW
Definitions
are determined by writing specific commands to the Command User Interface. Table 9 defines
Table 9. Command
Definitions gate First Bus Cycle Operation Write
Address
Command Read Array / Reset Read Identifier Codes
-r
Data FFh (PFl+) 90h (9090h) 70h (707Oh) 50h (5050h) 40h (4040h) or 1Oh (1010h) 20h (2020h) BOh (BOBOh) Read Read
Second Bus Cycle
Address 1 Data
1
Read Status Register Zlear Status Register
WordlByte
Write
E
DA 1 Write DA DA DA 2 Write Write 3 Write WA
I
( 3peration
Read
WA
1
WD
Block Erase Block Erase and Word/Byte Suspend Block Erase and Word/Byte Resume Set Block Lock-Bit Set Master Lock-Bit Clear Block Lock-Bit Address IA WA BA DA Note: 1. Following the Read Identifier master lock codes. =Identifier =Write =Block =Device code Address Write Write
3 3 3
Write Write Write Write
BA DA DA BA DA DA
Write
DOh (DODOh) 60h (6060h) 60h (6060h) 60h (6060h) Codes Write Write Write
4
Write Write Data ID WD SRD
=Identifier
Address Address Address
=Write Data =Data from Status Register
Codes command,
read operations
access manufacture,
device, block lock, and is complete,
2. Status Register may be read to determine when a write, block erase, or lock bit configuration and whether that operation completed successfully. 3. If the block is locked, block erase or write operations 4. This command is not available. are desabled.
CPSOOOZ-002@
May.1991
SHARP
11. Electrical Specifications
11. 1 Absolute Maximum Ratings
ID242 SERIES PRODUCT OVERVIEW
NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. All specified voltages are with respect to GND. During transitions, this level may undershoot periods 4!0ns or overshoot to Vcc+2.Ov for periods <20ns.
to -2.0~ for
Il. 2 Recommended Operating Conditions
11.3 Capacitance Ta=25"C, f=lMHz PARAMETER Input Capacitance Input/Output Capacitance SYMBOL cm C," MIN TYP 15 25 MAX UNIT PF PF CONDITION v,,=o.ov vO,,=O.Ov
11. 4 AC Input/Output Test Conditions
Vcc=3.3V-+Q.3V;oy)Lp$iq+~
Vcc=5Vk5% vcc=5vs-lo%
3s 1,5 T$q$=XT
Figure 5. Transient Input/Output Reference Waveform
Or
F,008-0,
Figure 8 showsInput/Output level and test level for AC test. Input riseand fall times(10% to 90%) < 10ns.
ws""uz-owdMay.199<
SHARP
12. DC Characteristics
ID242 SERIES PRODUCT OVERVIEW
18
(Ta = 0 to 60C) PARAMETER nput Low Voltage nput High Voltage nput Low Current nput High Current
RI2
iYM BOL
NOTE -i-
TEST CONDITION
I 2 3
3 2 4,5 4 5
jutput Low Voltage
JOLI
VTOHI
jutput High Voltage
dOH2
`cc Stand-by
Current
CCS
\,`cc
Deep Power-Down Chrrent
I CCD
\ `cc v `cc
Read Current
I CCR
or Set
68
Word Write L .ock-Bit Current
I ccw
69
V cc Block Erase or C lear Lock-Bit Current
4 `CE
679
Lock Erase Suspend
4 TWS 4 ?xs \ `LKO
6
:ontinue to next page 1
T1042-01
CPSOOOZ-0028
May.
199.9
SHARI=
DC T/+KAIVIC Characteristics ICK (Continued) , BOL , TE ,
ID242SERIESPRODUCTOVERVIEW
(Ta MIN I MAX , I ;I;., v k;; 1 UNIT 1 = 0 to 60C:
ry
TEST
CONDITION
vrrs vcc
or Read
\ T,,Stmd-by C :urrent
6 4MB 8MB 1OMB 16MB 20MB 1 I 1 I 0.8 1.6 2.0 1.6 2.0 I I I 1.6 2.0 1.6 2.0 mA mA mA VPF>VCC
UA UA ---I
\ Ipp Deep C :urrent
Power-Down
6
\' Word L Zk-Bit
Write Current
or Set
6.9
vrr=5.0v*
10%
\ I,,,, Block Erase or Cblear Lock-Bit Current
6.9
40 32 2MB 4MB 8MB 1OMB 16MB 400 430 500 530 500 1 I 1 1
40 32 400 430 500 530 500
mA mA
IVrr=5.0Vt I Vrr=l2.OVf
10% 5%
UA ---I UA
UA bA 4 UA
uA I
VW5 vcc
v I,+, Word Write or B lock Erase Suspend C `urren t
6
20MB 2MB 4MB 8MB 1OMB 16MB 20MB
I
I
530 0.4
I
I
I
I
530 0.4
I 0.8 I I 1.6 I
2.0 1.6 2.0
1 0.8 I 1.6
2.0 1.6 2.0
VPP>VCC
V Ipp Lockout
Voltage
VrTLK
7,9
I
1
1.5
1
1
1.5
1
v
1 71048-01
NOTE: 1. These 2. 3. 4. 5. 6. 7. 8. These These These These All parameters parameters parameters parameters parameters currents are in are are are are are RMS applied applied applied applied applied unless to all input pins and and Do-D,, all i/put/output in input mode. and RESET. pins in input mode.
to An-AZ5
to CE,#.CEz#,WE#,OE#,REG# to RDY/BSY#. to Do-D,, otherwise in output notes. configurations typical are mode.
Block erase, word/byte the VPP Voltage is VPI'I, Automatic operation. Power
write, and lock-bit VFPZ or VFI.I. reduces
inhibited
when
V,,,
5
VFPLK,
and
guaranteed
in
Savings(APS)
I CCK to 30mA
at Vcc=SV
and
20mA
at Vcc=3.3V
in static
9. Sampled.
CPSOOO2.002@ May. 1998
ID242 SERIES PRODUCT
OVERVIEW
20
13. AC Characteristics
Testing Conditions 1) Input Pulse Level : 1.5 to 3.w (@vcc=5v~5%,vcc=5v+10%)
0 to 3.ov (@Vcc=3.3+0.3V) 2) Input Rise/Fall Time 3) Input/Output Timing Reference Level Ions 2.5V (@Vcc=5V~5%,Vcc=SV~lO%) 1.5v (@Vcc=3.3V+O.3V) 4) Output Load (including scope and jig capacitance) lTTL+lOOpF lTTL+SOpF (@VCC=~V+~%,VCC=~V+IO%) (@Vcc=3.3V+O.3V)
13. 1 Common Memory Read Operations
(Ta = 0 tc 60C) SYMBOL PARAMETER Read Cycle Time Address Access Time CE# Access Time OE# Access Time Output Disable Time from CEl#,CE2# * Output Disable Time from OE# * Output Enable Time from CEI#,CE2# Output Enable Time from OE# Data Valid Time from Address Change +:Time until output become , floating. IEEE t AVAV t AVQV tELQV
JEIDA/ PCMCIA
tcR
vcc=3.3vi MIN 250 1 1 5 1 1
ON MAX 250 250 125 100 100 1 1
Vcc=SV~ MIN 150 5 1 1
5% MAX 150 150 75 75 75 1 I
vcc=w-t MIN 160 5 1 1
10% ~ Unit MAX 160 160 80 80 80 ns
t,(A) t,(CE)
...
kHQz
1t,(OE) ItdidCE) QOE) tc,,( CE)
tGHQZ
tELQNZ
WV
0
-
0
-
0
rio43ai
(The output voltage is not defined.)
CPS0002.002@May.1991
9
SHARP
ID242 SERIES PRODUCT
OVERVIEW
Address
CEl#, CE2#
OE#
Dout
Figure 6. AC Waveforms
for Read Operations
Note)
1. WE# = "HIGH", 2. Either "HIGH"
during a read cycle. or "LOW" in diagonal areas. ta (A), ta (CE) or ta (OE) have concluded.
3. The output data becomes valid when last interval,
CPS0002-002QMay.199
SHARP
ID242 SERIES PRODUCT OVERVIEW
22
13.2 Command Write Operations : Common Memory 13. 2. 1 WE# Controlled Write Operations
(vcc=3.3Vi PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for WE# Data Hold Time OE# Hold Time from WE# CE# Setup Time for WE# Address WE# Setup Time for
0.3VTa=O 60C) to
Write Pulse Width WE# High to RDY/BSY# going Low RESET Recovery Time VPP Setup Time VPP Hold Time Word/Byte Write Time
Block Erase Time
jet Lock-Bit
Time
Zlear Block Lock-Bits rime vw=3.3v k 0.3% Nor-d I byte Suspend Latency rime to Read t\"HRH I
vPP=w+
10.0 9.3 10.4
21.1
PS Ps PS
PS
10%
vw= 12v -t 5%
vpp=3.3vi0.3%
Gase Suspend Latency Time o Read
t WHRHZ
VPP=5Vt
10%
5%
17.2 17.2
l-1 s I-is
T1044.01
vrr=12v*
CPSOOOZ-0028
May.
199
SHARI=
ID242 SERIES PRODUCT OVERVIEW
(Vcc=5Vi
PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for WE# Data Hold Time OE# Hold Time from WE# CE# Setup Time for WE# Address Setup Time for
5%, Vcc=5Vi
lOsTa = 0 I 60C)
Unit ns ns ns ns ns ns ns ns ns ns PS ns ns PS PS
S
WE#
Write Pulse Width WE# High to RDY/BSY# going Low RESET Recovery Time
VPP VPP
Setup Time Hold Time Write Time
Word/Byte
Block Erase Time
S
Set Lock-Bit
Time
PS
Clear Block Lock-Bits Time
Word I byte Suspend Time to Read Erase Suspend to Read Latency Latency
Time
r1049-oi
CPSOOOZ-0026May.199
SHARP
ID242 SERIES PRODUCT
OVERVIEW
1. VIH Address Vn. VIH CE#, CE2# VIL hH OE# VTL
2.
3.
4.
5.
6.
DATA
`VALID ~ sm
tPHWL
hvmL
VOH ,
RDYIB
SY#
VOL VIH
I
I
RESET VIL IT
tQVVL -VPP VPP FL I .ZJ
Figure 7.
AC Waveforms
for Write Operations
(WE# Controlled)
Note) While the data signal is in output mode, do not apply an opposite phase input signal.
CPS0002.0020May.199
SHARP
ID242SERIESPRODUCTOVERVIEW
13. 2. 2 CE# Controlled Write Operations
(Vcc=3.3Vt- 0.3\(Ta = Oto 60C)
PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for CE# Data Hold Time OE# Hold Time from CE# WE# Setup Time for CE# Address CE# Setup Time for
Write Pulse Width CE# High to RDY/BSY# going Low RESET Recovery Time VPP Setup Time
VPP
Hold Time Write Time
Word/Byte
Block Erase Time
Set Lock-Bit
Time
Clear Block Lock-Bits Time
Word I byte Suspend Latency Time to Read
tEHRHI
VPP4V~ vPP=lzv*
10% 5%
9.3 10.4 21.1 17.2 17.2
!JS PS I-1s PS PS
T1045-01
vpp=3.3v-t
Erase Suspend Latency to Read Time
0.3v
10% 5%
tEHRH2
Vpr=5VIk vPP=lzvk
CPS0002.002@May.199
J a
SHARI=
ID242 SERIES PRODUCT
OVERVIEW
26
1
(Vcc=5V& PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for CE# Data Hold Time OE# Hold Time from CE# WE# Setup Time for CE# Address CE# Setup Time for
5%, Vcc=SV&
IO%, Ta=O to 60C
Write Pulse Width CE# High to RDY/BSY# going Low RESET Recovery Time
VPP VPP
Setup Time Hold Time Write Time
Word/Byte
Block Erase Time Set Lock-Bit Time
Clear Block Lock-Bits Time
Word I Byte Suspend Time to Read Erase Suspend to Read Latency
Latency
Time
T1046-01
SHARB=
ID242 SERIES PRODUCT
OVERVIEW
27
1. Address k,(A) wE#
2.
3.
4.
5.
6.
tcw
1 1 tsu(A-CEH)
k&E)/
OE#
CE#,
CE2#
DATA
tEHRHl.2 k'HEL tEHRL VOH
RDYlBSY#
VOL
I
/
vm
RESET RL 1
%%22 VPP FL
1. 2. 3. 4. 5. 6.
v,, tAg~zIzGs9~~//Y V,, POWER-UP AND STANDBY /cl~~~~4tVM~~.17~~~~aj;/~~~~~~M~~.~~~F~P~~q WRITE DATA WRITE OR ERASE SETUP COMMAND 7j;`Lx++J (,Y~P~~~)`bfil;f;)`~~il~~7~~~~~~~ WRITE VALID ADDRESS AND DATA OR ERASE COMFIRM $1/Yi-~~~~~filf$~)A~;C~aa~~ AUTOMATED DATA WRITE OR ERASE DELAY x~-~Jz.b-%7b~~~~~xL READ STATUS REGISTER DATA ~-F-~%~~z+`~W~&A& WRITE READ ARRAY COMMAND
COMMAND
Figure 8.
AC Waveforms
for Write Operations
(CE# Controlled)
Note) While the data signal is in output mode, do not apply an opposite phase input signal.
SHARP
13.3
ID242 SERIES PRODUCT OVERVIEW
Attribute Memory Read Operation (Ta=O-60C) PARAMETER
* : Time
until
becomes
floating.
(The output
voltage
is not defined)
T1056-01
Note) When the CIS constructed by EEPROM,
this card requires 5V voltage for Vcc.
Address \ e \ :El#, CE2# \ ta(CE) w i/ \\\\\\\\A L&E) Dout r q&Y-&T High-Inpedance I t&W t tdOE) ~ f-%%hms Data Output e t&W ' / ' ' ' ' `/ / A ' / / / t,(A) w 1 / h(A) c
OE#
is valid
F1009-0; I
Figure 9.
Attribute
Memory
Read
Operation
CPSOOOZ-00263May.1996
SHARP
13.4
ID242 SERIES PRODUCT OVERVIEW
Attribute Memory Write Operation (Ta=O-60C)
I
PARAMETER
SYMBOL
PCMCIA
I
vcc=3.3v*
0.3v 1
vcc=.wi
10%
1
MAX
I
MIN
I
MAX
I
Unit ns
-
I..
. ..l
".`\-
-
--
-
Write PulseWidth SetupTime for OE# 1 Hold Time for OE# SetupTime for CE# Hold Time for CE#
tWLWH
_....I
`w(WE)
.-\--
300 35 35 0 35
I
150
10 10
ns ns ns ns ns
I
tCHWI twIOE-WE) It 1.lllr.T 1II. , """~I. ,t, (OE-\iW tF1 u/H ILfCF.~ tCHEH t,, W
ll.... I ."' \ -/
0 20
T1057-01
Note) When the CIS constructedby EEPROM, this card requires5V voltage for Vcc.
VIH
\ AIN
Address
CEl#, CE;?#
VIH
OE# t,,(OE-WE)
VIH
WE#
DATA
F1057-01
Figure 10. Attribute Memory Write Operation
SHARP
13.5 Power-Up/Power Down
ID242 SERIES PRODUCT OVERVIEW
PARAMETER CE# Signal Level (O.OV < Vcc < 2.OV) CE# Signal Level (2.OV < Vcc < Vin) CE# Signal Level (Vtu < Vcc) CE# Setup Time RESET Setup Time CE# Recover Time VCC Rising Time VCC Falling Time RESET Width RESET Width RESET Width I
SYMBOL PCMCIA Vi (CE)
NOTES 1 1 1 2 2 I I
MIN 0 vcco.
VIH
MAX
ViMAX
UNITS V V V I ms ms IJS ms ms I us ms ms
I
ViMAX ViMAX
tsu WCC) tauWSET) treeWCC) b tPf tw (RESET) th (Hi-Z RESET) ts (Hi-Z RESET)
I
I
20 20 1.0 0.1 3.0 10 1 0
I
300 300
1
-I
I
-
NOTES: 1. ViMAx means Absolute Maximum Voltage for input in the period of O.OV < Vcc < 2.0 V, Vi (CE#) is only o.oov-ViMAX 2. The tpr and tpr are defined as "linear waveforms" in the period of 10% to 90%, or vice-versa. Even if the waveform is not a "liner waveform," its rising and falling time must meet this specification.
e
tPr
-c-
tsu WCC)
vcc
-)-
tsu (RESET)
=
--
th (Hi-Z RESET)
Hi-Z tw (Hi-Z RESET) -3 + RESET n
:Et#, CEa#
At-
ts (Hi-Z RESET) Hi-Z
FlOlZ-01
Figure 11. Power- Up/Uown
liming
CPSOOO2.002
0 May.
1991
SHARI=
14. Specification Changes
ID242 SERIES PRODUCT OVERVIEW
31
This datasheet is for ID242 series product overview, and final specifications will be submitted for qualification of the memory card. Please note that contents of this datasheet may be revised without announcement beforehand. Please do NOT finalize a system design with this information.
15. Other Precautions
Permanent damage occurs if the memory card is stressed beyond Absolute Maximum Ratings. Operation beyond the Recommended Operating Conditions is not recommended and extended exposure beyond the Recommended Operating Conditions may affect device reliability. Writing to the memory card can be prevented by switching memory card. Avoid allowing the memory card connectors to come in contact with metals and avoid touching the connectors, as the internal circuits can be damaged by static electricity. Avoid storing in direct sunlight, high temperatures (do not place near heaters or radiators), high humidity and dusty areas. Avoid subjecting the memory card to strong physical abuse. Dropping, bending, smashing or throwing the card can result in loss of function. When the memory card is not being used, return it to its protective case. Do not allow the memory card to come in contact with fire. on the write protect switch on the end of the
ID242SERIESPRODUCTOVERVIEW
16. External Diagrams
1
0A
ENLARGEMEHT WRITE-PROTECT
of
THE SWITCH
Protected
-
(Substrdtc
Aped)
FRONT A--P
BACK
rA,PPLICIILL
SCALE
UNIT
l/l
THICKNESS I ,997. 9. 8 TRIEFCI(ECR A,rn.l MATER1 AL
mm
FlNISk
CH- DATE
REVISE MEMORY CARD DIAGRAM Ret. 2. 0
CHARGl
NAt7E
EXTERNAL I wd matngaa P~vI*rt Team oe*v'rc PCMCIA
OATE Bltla* OLlY
TYPE1
\kU~UydtiA SHARP
Ic GROUP CORPORATION
Morn
IMC026-A103
CPSOOO2-002 BY.199

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