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| AP2308GEN Pb Free Plating Product Advanced Power Electronics Corp. Capable of 2.5V gate drive Lower on-resistance 2KV ESD Capability D N-CHANNEL ENHANCEMENT MODE POWER MOSFET BVDSS RDS(ON) ID S SOT-23 G 20V 600m 1.2A Description Advanced Power MOSFETs utilized advanced processing techniques to achieve the lowest possible on-resistance, extremely efficient and cost-effectiveness device. The SOT-23 package is universally used for all commercial-industrial applications. D G S Absolute Maximum Ratings Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Drain-Source Voltage Gate-Source Voltage www..com Parameter Rating 20 6 Units V V A A A W W/ Continuous Drain Current , VGS @ 4.5V Continuous Drain Current , VGS @ 4.5V Pulsed Drain Current 1,2 3 3 1.2 1 5 1.38 0.01 -55 to 150 -55 to 150 Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 90 Unit /W Data and specifications subject to change without notice 200809041 AP2308GEN Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 20 0.5 - Typ. 0.1 1 1.2 0.4 0.3 17 36 76 73 37 17 13 Max. Units 600 850 1.2 1 10 10 2 60 V V/ m m V S uA uA uA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) Static Drain-Source On-Resistance VGS=4.5V, ID=1.2A VGS=2.5V, ID=0.5A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70oC) o VDS=VGS, ID=250uA VDS=5V, ID=1.2A VDS=20V, VGS=0V VDS=16V ,VGS=0V VGS=6V ID=1.2A VDS=16V VGS=4.5V VDS=10V ID=1.2A RG=3.3,VGS=5V RD=10 VGS=0V VDS=10V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 Test Conditions IS=1.2A, VGS=0V Min. - Typ. - Max. Units 1.2 V Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 270/W when mounted on min. copper pad. AP2308GEN 4.5 3.5 4.0 T A = 25 o C 5.0V 4.5V ID , Drain Current (A) 3.0 TA=150 C o 5.0V 4.5V ID , Drain Current (A) 3.5 2.5 3.0 3.5V 2.5 2.0 3.5V 2.0 1.5 1.5 2.5V 2.5V 1.0 1.0 0.5 0.5 V G = 1 .5V 0.0 1.0 2.0 3.0 V G = 1 .5V 0.0 0.0 0.0 1.0 2.0 3.0 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 700 1.6 I D =0.5A T A =25 C 600 o 1.4 I D =1.2A V G =4.5V Normalized R DS(ON) RDSON (m ) 1.2 500 1.0 400 0.8 300 1 2 3 4 5 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 2.0 1.0 0.8 Normalized VGS(th) (V) 1.2 1.5 0.6 IS(A) 1.0 0.4 T j =150 o C 0.2 T j =25 o C 0.5 0.0 0 0.2 0.4 0.6 0.8 1 0.0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage v.s. Junction Temperature AP2308GEN f=1.0MHz 12 100 I D =1.2A VGS , Gate to Source Voltage (V) 10 8 V DS =10V V DS =12V V DS =16V C (pF) C iss 6 4 C oss 2 C rss 0 10 0 0.5 1 1.5 2 2.5 1 3 5 7 9 11 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 10 1 1ms 1 Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 0.1 0.1 ID (A) 10ms 0.05 PDM 0.01 100ms 0.1 t T Single Pulse 0.01 1s T A =25 C Single Pulse 0.01 0.1 1 10 100 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 270/W o DC 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Circuit Fig 12. Gate Charge Circuit |
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