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IRPP3637-06A POWIR+ Chipset Reference Design
6Amp Single Phase Synchronous Buck POWIR+TM Chipset Reference Design using IR3637ASPBF PWM & Driver IC and IRF8910PBF Dual SO-8 MOSFET
By Steve Oknaian, Senior Applications Engineer
Table of Contents
Page Introduction ..........................................................................................2 Design Details ......................................................................................2 Start-Up Procedure ..............................................................................3 Layout Considerations .........................................................................3 Circuit Schematic .................................................................................5 Complete Bill of Materials.....................................................................6 PCB layouts .........................................................................................7-8 Electrical Efficiency & Power Loss .......................................................9 Thermal Performance & Bode Plot.......................................................10 Input & Output Ripple Waveforms........................................................11 Load Step Waveforms..........................................................................12 Power Up & Power Down Waveforms..................................................13 Short Circuit Waveforms ......................................................................14 IRPP3637-xxA Reference Design Selector Table ................................14
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Introduction
The IRPP3637- 06A is an optimized POWIR+TM Chipset reference design, targeted at low cost, low power synchronous buck applications up to 6A output current. The IRPP3637-06A uses International Rectifier's IR3637ASPBF single channel PWM controller in an 8pin SOIC and IRF8910PBF dual SO-8 MOSFET. This reference design has built-in power design expertise regarding component selection and PCB layout, and is representative of a realistic final embedded synchronous buck design, intended to simplify the design in effort without unnecessary design iterations. The design is optimized for 5V input and 1.25V output @ 6A and 600kHz switching frequency, including considerations on layout and passive & magnetic component selection. The IRPP3637-06A delivers the complete 6A design in less than 1.0in2 board area at up to 80% full load electrical efficiency and up to 85% peak efficiency. International Rectifier also offers the POWIR+ Chipset on-line design tool (http://powirplus.irf.com) allowing the customization of the IRPP3637-06A reference design to meet individual requirements. Based on specific inputs, the POWIR+ Chipset on-line design tool will provide a tailored schematic and bill of materials, from which the engineer can run a full suite of on-line design simulations, and then order the fully assembled and tested customized reference design (see details on page 14).
1.25V at a maximum of 6A load current, using the IRF8910PBF dual SO-8 MOSFET. The 600kHz switching frequency allows the selection of reduced size power components. All the essential components that contribute to a low cost compact solution are enclosed by the rectangular box shown on the PCB, showing a total solution size of 1.3" x 0.8" (1.0" sq). The electrical connection diagram is shown in figure 1 and the corresponding circuit schematic is shown in figure 2.
+12V External Vc bias. (Optional) (J5)
+5V (J1)
+5V RTN (J2)
+1.25V Vout RTN (J3) +12V External Vc bias RTN (J6)
+1.25V Vout (J4)
Figure 1: IRPP3637-06A Electrical Connection Diagram
Input/Output Connections J1: J2: J3: J4: J5: Input power connection terminal Input power return preferred connection terminal Output power return preferred connection terminal Output power connection terminal External bias power connection terminal. This terminal is unused for standard reference design configuration. External bias power return preferred connection terminal. This terminal is unused for standard reference design configuration.
J6:
Design Details
The IRPP3637-06A reference design is optimized for an input voltage range of 4.5V to 5.5V and an output voltage of
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Start-Up Procedure
The 5V input power is connected between terminals J1 and J2 and the 1.25V, 6A output power is obtained through terminals J3 and J4. The VCC and VC pins are the low side driver and high side driver power input pins respectively. The VCC pin also includes the housekeeping power of the PWM controller. An under-voltage lockout (UVLO) feature is associated with each of these pins, which is set to 4.2V for VCC and 3.3V for VC. A charge pump circuit comprised of C13, D1, and C14 applies approximately twice the input voltage to the VC pin to allow fast driving capability, hence reducing the switching losses of the control FET (Q1). Upon application of the input power, the output starts ramping up to regulation within 4ms. The ramping time can be adjusted through the soft start capacitor C5. The output voltage of the synchronous buck regulator is set to 1.25V using the internal 0.8V reference voltage. The following equations are used to calculate the MOSFET power loss. Refer to the IRF8910PBF datasheet to select the parametric values of the power loss equations terms. Control FET Losses: Eq (1):
PQ1 = I Q1rms2 .RDQ1 .RDn + ( I o . Qsw1 .Vin + QgQ1 .Vdd + QossQ1 .Vin ).FSW I g1
Total FET losses: Eq (4): PFET _ total = PQ1 + PQ 2 + Ptd Where, IQ1rms and IQ2rms are the rms currents for control and sync FETs respectively, in Amps IO is the output load current in Amps RD is the RDSON in ohms of the FETs and RDn is the normalized RDSON factor vs temperature extracted from the IRF8910PBF datasheet. QSW is the FET switch charge in nC VIN is the input voltage of the sync buck converter Qg is the total gate charge in nC. Vdd is the FET drive voltage, which is 4.5V. Ig is the drive current which is 0.25A. QOSS is the FET output charge in nC. Qrr is the sync FET internal body diode reverse recovery charge in nC VSD is the sync FET internal body diode forward voltage drop in volts. FSW is the switching frequency of the sync buck converter in hertz. td is the dead time caused by the PWM controller IC in seconds. This parameter is specified in IR3637ASPBF datasheet. For design calculations related to programming the output voltage and the soft start time, selection of input/output capacitors and output inductor and control loop compensation, refer to the guidelines outlined in the IR3637ASPBF PWM controller datasheet. IR's online design tool POWIR+ should be used to customize a design for applications outside the standard 4.5V to 5.5V input range and 1.25V output, and for varied design goal objectives.
Synchronous FET Losses: Eq (2):
QossQ2 PQ2 = I Q 2 rms 2 .RDQ2 .RDn + .Vin + QgQ2 .Vdd + QrrQ2 .Vin .FSW 2
Deadtime losses: Eq (3):
Ptd = VSD .I o .t d .Fsw
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Layout Considerations
The IRPP3637-06A reference design PCB layout offers compact design with minimum parasitics at 600kHz switching frequency. The board is designed with 4 layers using 1 oz copper weight per layer. Figures 3a through 3d represent the layout of each layer. To minimize the parasitics, the following was observed: 1. The switch node connection path is made as short as possible by placing the output inductor L1 close to the drain of the synchronous FET inside the dual SO8 package. 2. The input decoupling 10uF ceramic capacitor C3, is placed across the drain of the control FET and the ground pin of the dual SO8 package. The 1200uF electrolytic capacitor C1 represents the input bulk capacitance of the synchronous buck regulator. 3. A solid ground plane is furnished in mid-layer 2. The connection of the signal ground to power ground is done at a single point in the bottom layer as shown in figure 3d. 4. The feedback track from the output VOUT to FB pin of the IC is routed as far away from noise generating traces as possible in mid-layer 2 as shown in figure 3c.
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Figure 2: Schematic Diagram for IRPP3637-06A Reference Design
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QTY 1 1 3 1 3 2 1 1 3 3 4 2 6 1 1 1 1 1 1 1 1 1 1 1 6
REF DESIGNATOR C6 C7 C5, C13, C14 C4 C3, C10, C11 C1, C9 D2 D1 J1, J4, J5 J2, J3, J6 J1, J4, J5, J6 J2, J3 J1, J2, J3, J4, J5, J6 L1 R8 R10 R11 R5 R6 R1 R3 R2 Q1 U1 C2, C8, R4, R7, R9,R12
DESCRIPTION Capacitor, ceramic, 47pF, 50V,COG, 5% Capacitor, ceramic, 3.3nF,50V,X7R,10% Capacitor, ceramic, 0.1F, 50V, X7R, 10% Capacitor, ceramic, 1.0F, 16V, X5R, 20% Capacitor, ceramic, 10uF, 6.3V, X5R, 20% Capacitor, aluminum electrolytic,1200uF,6.3V Schottky Diode, 30V,200mA Schottky Diode, 30V,200mA Red Banana Jacks-Insulated Solder Terminal Black Banana Jacks-Insulated Solder Terminal Pan Head Slotted,screw 1/2" Pan Head Slotted,screw 1/4" Machine Screw Hex Nuts 1.0uH,7.7A,10m Resistor,thick film, 0 Resistor,thick film, 0 Resistor,thick film,0 Resistor,thick film,10, 5% Resistor,thick film,20, 1% Resistor,thick film,15k, 1% Resistor,thick film,11k, 1% Resistor,thick film,6.19k, 1% Dual NFET,20V,Q1/Q2=18.3m,11nC PWM Controller Not installed
SIZE 0603 0603 0603 0603 1206 8mm X 16mm SOT23 SOT23 4.44mm 4.44mm 7.7mm X 7.0mmX3.0mm 0805 0603 1206 1206 0603 0603 0603 0603 SO-8 SO-8
MFR TDK KOA TDK TDK TDK Sanyo IRF IRF Johnson Johnson McMaster-Carr McMaster-Carr McMaster-Carr TOKO ROHM ROHM KOA DALE KOA KOA KOA KOA IR IR
PART NUMBER C1608COG1H470J X7R0603HTTD332K C1608X7R1H104K C1608X5R1C105M C3216X5R0J106M 6ME1200WG BAT54 BAT54S 108-0902-001 108-0903-001 91792A081 91792A077 91841A003 FDV0603-1R0M MCR10EZHJ000 MCR03EZHJ000 RM73Z2B000 CRCW1206-100JRT1 RK73H1JLTD20R0F RK73H1JLTD1502F RK73H1JLTD1102F RK73H1JLTD6191F IRF8910 IR3637ASPbF
Table 1 - Complete Bill of Materials for IRPP3637-06A Reference Design
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Figure 3a: IRPP3637-06A Reference Design top layer placement and layout.
Figure 3b: IRPP3637-06A Reference Design mid-layer1 ground plane
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Figure 3c: IRPP3637-06A Reference Design mid-layer2 layout.
Figure 3d: IRPP3637-06A Reference Design bottom layer layout.
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IRPP3637AS-6A Efficiency
5Vin, 1.25Vout, 600KHz, 250 C, 0LFM
90% 80% 70%
Efficiency
60% 50% 40% 30% 20% 10% 0% 0 1 2 3 4 5 6
Load Current (Amps)
Figure 4a: IRPP3637-06A Reference Design Electrical Efficiency
IRPP3637AS-6A System Power Loss
5Vin, 1.25Vout, 600KHz, 250 C, 0LFM
2.00 1.75
Power Loss (Watts)
1.50 1.25 1.00 0.75 0.50 0.25 0.00 0 1 2 3 4 5 6
Load Current (Amps)
Figure 4b: IRPP3637-06A Reference Design Power Loss Curve
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IRF8910 Dual SO8 package. TC= 770C U1 IC -IR3637AS TC=450C
Vin=5V, Vo=1.25V, Io=6A TA = 250C 0 LFM
Figure 5: IRPP3637-06A Reference Design Thermograph at 6A load
Phase
Gain
Phmargin=670 Fo= 57kHz
Figure 6: IRPP3637-06A Reference Design Bode Plot of the Control Loop at 6A load.
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Figure 7: Input ripple, IO=6A
Figure 8: Output ripple, IO=6A
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Figure 9: Output Voltage undershoot due to 1A to 6A load step, di/dt=2.5A/us
Figure 10: Output Voltage overshoot due to 6A to 1A load step, di/dt=2.5A/us
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Figure 11: Power up. Ch1=VIN, Ch2=VOUT, Ch3=Soft Start
Figure 12: Power down. Ch1=VIN, Ch2=VOUT, Ch3=Soft Start
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Figure 13: Output short circuit protection. Ch1=VOUT, Ch4=IOUT10A/div
VIN
(V)
VOUT
(V)
IOUT
(A)
Max Power
(W)
Efficiency (%), 250C,
0 LFM
VINripple
(mVp-p)
VOUTripple
(mVp-p)
Line Regulation
(%)
Load Regulation
(%)
5V
1.25V
6A
7.5W
80%
280mV
26mV
0.025%
0.1%
Table 2 - IRPP3637-06A Reference Design Performance Summary (all values are typical)
Part Number IRPP3637-06A Input Voltage 5V Output Voltage 1.25V Output Current 6A Switching Frequency 600kHz Power Semi BOM IR3637AS (SO-8), IRF8910 (Dual SO-8) IR3637S (SO-8), IRF7823 (SO-8), IRF7832Z (SO-8) Option to populate S-Can DirectFETs IR3637S (SO-8), IRLR8713 (D-Pak), IRLR7843 (D-Pak) Delivery Time Comments
IRPP3637-12A
12V
1.8V
12A
400kHz
24-48hrs
Standard Reference Designs Fixed BOM
IRPP3637-18A Custom IRPP3637-06A Custom IRPP3637-12A Custom IRPP3637-18A
12V
3.3V
18A
400kHz
Up to 6A 3.0V to 13.2V 0.8V to 5.0V Up to 12A 400kHz or 600kHz Up to 18A Various 1-2wks Customizable Reference Designs via POWIR+ Chipset On-line Design Tool at http://powirplus.irf.com
Table 3 - Complete IRPP3637-xxA Reference Design Selector Table
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