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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1303
www..com
Advance Information
132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1303 Rev 1.7 P 1/56 Copyright 2005 Solomon Systech Limited
May 2005
TABLE OF CONTENTS
1 2 3 4 5 6
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GENERAL INFORMATION ............................................................................................................................5 FEATURES .........................................................................................................................................................5 ORDERING INFORMATION ..........................................................................................................................6 BLOCK DIAGRAM ...........................................................................................................................................7 DIE PAD FLOOR PLAN....................................................................................................................................8 PIN DESCRIPTION .........................................................................................................................................12 FUNCTIONAL BLOCK DESCRIPTIONS....................................................................................................15 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR ..................................................................................15 RESET CIRCUIT ................................................................................................................................................15 COMMAND DECODER AND COMMAND INTERFACE ..........................................................................................15 MPU PARALLEL 6800-SERIES INTERFACE .......................................................................................................16 MPU PARALLEL 8080-SERIES INTERFACE .......................................................................................................16 MPU SERIAL INTERFACE .................................................................................................................................17 GRAPHIC DISPLAY DATA RAM (GDDRAM) ..................................................................................................17 CURRENT CONTROL AND VOLTAGE CONTROL.................................................................................................17 SEGMENT DRIVERS / COMMON DRIVERS .........................................................................................................18 AREA COLOUR DECODER.................................................................................................................................18 DC-DC VOLTAGE CONVERTER .......................................................................................................................19 COMMAND TABLE ........................................................................................................................................21 8.1 DATA READ / WRITE........................................................................................................................................24 COMMAND DESCRIPTIONS........................................................................................................................25 MAXIMUM RATINGS ....................................................................................................................................32 DC CHARACTERISTICS ...............................................................................................................................33 AC CHARACTERISTICS ...............................................................................................................................34 APPLICATION EXAMPLE ............................................................................................................................38 SSD1303T3R1 PACKAGE DETAILS.............................................................................................................39
7
8
9 10 11 12 13 14
SSD1303T3R1 PIN ASSIGNMENT ................................................................................................................................39 15 SSD1303T6R1 PACKAGE DETAILS.............................................................................................................43
SSD1303T6R1 PIN ASSIGNMENT ................................................................................................................................43 SSD1303T6R1 TAB PACKAGE DIMENSIONS ..............................................................................................................45 16 SSD1303T8R1 PACKAGE DETAILS.............................................................................................................47
SSD1303T8R1 PIN ASSIGNMENT ................................................................................................................................47 SSD1303T8R1 TAB PACKAGE DIMENSIONS ..............................................................................................................49 17 SSD1303T9R1 PACKAGE DETAILS.............................................................................................................51
SSD1303T9R1 PIN ASSIGNMENT ................................................................................................................................51 SSD1303T9R1 TAB PACKAGE DIMENSIONS ..............................................................................................................53
Solomon Systech
May 2005
P 2/56
Rev 1.7
SSD1303
18
SSD1303Z PACKAGE DETAILS ...................................................................................................................55
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SSD1303
Rev 1.7
P 3/56
May 2005
Solomon Systech
TABLE OF FIGURES
Figure 1 - Block Diagram.................................................................................................................................. 7 Figure 2 - SSD1303Z Pin Assignment ............................................................................................................. 8 Figure 3 - SSD1303Z Alignment mark dimensions ........................................................................................ 11 Figure 4 - Oscillator Circuit............................................................................................................................. 15 Figure 5 - Display data read back procedure - insertion of dummy read ....................................................... 16 Figure 6 - Display data write procedure in SPI mode.................................................................................... 17 Figure 7 - DC-DC voltage converter circuit .................................................................................................... 19 Figure 8 - Horizontal scroll direction............................................................................................................... 25 Figure 9 - Segment current vs Contrast setting ............................................................................................. 26 Figure 10 - 6800-series MPU parallel interface characteristics ..................................................................... 35 Figure 11 - 8080-series MPU parallel interface characteristics ..................................................................... 36 Figure www..com 12 - Serial interface characteristics ..................................................................................................... 37 Figure 13 - Application Example (Block Diagram of SSD1303T3)................................................................. 38 Figure 14 - SSD1303T3R1 pin assignment (Copper view, Normal TAB design) .......................................... 39 Figure 15 - SSD1303T6R1 pin assignment (Copper view) ............................................................................ 43 Figure 16 - SSD1303T9R1 pin assignment (Copper view) ............................................................................ 51
LIST OF TABLES
Table 1 - Ordering Information ......................................................................................................................... 6 Table 2 - SSD1303Z Die Pad Coordinates ...................................................................................................... 9 Table 3 - Passive component selection: ........................................................................................................ 20 Table 4 - Command table............................................................................................................................... 21 Table 5 - Read command table ...................................................................................................................... 23 Table 6 - Address increment table (Automatic).............................................................................................. 24 Table 7 - Maximum Ratings ........................................................................................................................... 32 Table 8 - DC Characteristics .......................................................................................................................... 33 Table 9 - AC Characteristics .......................................................................................................................... 34 Table 10 - 6800-Series MPU Parallel Interface Timing Characteristics......................................................... 35 Table 11 - 8080-Series MPU Parallel Interface Timing Characteristics......................................................... 36 Table 12 - Serial Interface Timing Characteristics ......................................................................................... 37 Table 13 - SSD1303T3R1 pin assignment..................................................................................................... 40 Table 14 - SSD1303T6R1 pin assignment..................................................................................................... 44 Table 15 - SSD1303T8R1 pin assignment..................................................................................................... 48 Table 16 - SSD1303T9R1 pin assignment..................................................................................................... 52
Solomon Systech
May 2005
P 4/56
Rev 1.7
SSD1303
1
GENERAL INFORMATION
The SSD1303 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. It consists of 132 segments, 64 commons that can support a maximum display resolution of 132x64. Besides, there are 4-colour selections to support monochrome or area colour OLED/PLED. This IC is designed for Common Cathode type OLED panel. The SSD1303 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption. It is suitable for many compact portable applications, such as mobile phone sub-display, calculator and MP3 player, etc.
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2
FEATURES
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Support maximum 132 x 64 dot matrix panel Area colour support with 4 Colour Selection and 64 steps per colour Logic voltage supply: VDD = 2.4V - 3.5V High voltage supply: VCC = 7.0V - 16.0V Maximum segment output current: 320uA Maximum common sink current: 45mA Embedded 132 x 64 bit SRAM display buffer 256-step Contrast Control on monochrome passive OLED panel On-Chip Oscillator Programmable Frame Frequency and Multiplexing Ratio 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface Row Re-mapping and Column Re-mapping Vertical Scrolling Automatic horizontal scrolling function Low power consumption Wide range of operating temperatures: -40 to 90 C
SSD1303
Rev 1.7
P 5/56
May 2005
Solomon Systech
3
ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number SSD1303Z SEG 132 COM 64 Package Form Gold Bump Die Reference Page 8 Remark Die size: 9.22mm x 1.55mm Pad pitch: COM 51.8m SEG 52.2m * * * * * * * * * * * * * * * * * * * * 35mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch 0.12974mm 35mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch 0.11976 35mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch 0.12974mm 35mm film 4 sprocket hole Folding TAB 80 / 68 / SPI interface Output lead pitch 0.12974mm
SSD1303T3R1
96
64
TAB
Page 39
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SSD1303T6R1
132
64
TAB
Page 43
SSD1303T8R1
96
64
TAB
Page 47
SSD1303T9R1
96
64
TAB
Page 51
Solomon Systech
May 2005
P 6/56
Rev 1.7
SSD1303
4
BLOCK DIAGRAM
Common Drivers(odd)
Segment Drivers
D7 D6 D5 D4 D3 D2 D1 D0
Area Colour Decorder
MCU Interface
GDDRAM
RES# CS# www..com D/C E (RD#) R/W (WR#) BS2 BS1 BS0
. . . . . . . . . . .
COM63 COM61 . . . COM3 COM1
VDD VSS
. . . . . . . . . . .
SEG131 SEG130 . . . SEG1 SEG0
Common Drivers (even)
. . . . . . . . . . .
Voltage Control
Current Control
Command Decoder
Display Timing Generator
Oscillator
COM0 COM2 . . . COM60 COM62
VDDB VSSB GDR RESE FB VBREF VCC VCOMH VREF IREF
CL CLS
Figure 1 - Block Diagram
SSD1303
VCL VSL Solomon Systech
Rev 1.7
P 7/56
May 2005
5
DIE PAD FLOOR PLAN
Figure 2 - SSD1303Z Pin Assignment
DUMMY (x2) COM32 COM34 . . COM60 COM62 VSS (x3) VCL (x3) VSS (x2) VSL (x3) VDD VCC (x2) VREF VCOMH (x2) IREF ICAS VDD CLS M/S VSS D7 D6 D5 D4 D3 D2 D1 D0 VDD E/RD R/W VSS D/C RES# CS# VSS DOF# CL M VSS BS2 VDD BS1 VSS BS0 VDD GPIO1 GPIO0 VCC VSS BGGND SENSE VBREF RESE FB VDD (x2) VDDB (x2) GDR (x2) VSSB (x2) VSS TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 VCOMH (x2) VCC (x2) VDD VSL (x3) VSSB (x2) VSS (x2) VCL (x3) VSS (x3) COM63 COM61 . . COM35 COM33 DUMMY (x2)
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DUMMY DUMMY COM30 COM28 COM26 COM24 . . . COM6 COM4 COM2 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 . . . SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM1 COM3 COM5 COM7 . . . COM25 COM27 COM29 COM31 DUMMY DUMMY
Y SSD1303 X
Pad 1,2,3,? >130 Gold Bumps face up
Die size Die height Bump height Bump size Pad 1-18, 113-298 Pad 19-112 Alignment mark T shape + shape Circle Circle (-3132.9, 79.5) (3148.9, 79.5) (3433.9, -274.6) (-3433.9, -274.6) 75um x 75um 75um x 75um R37.5um, inner 18um R37.5um, inner 18um 34um x 84um 54um x 84um 9.22mm x 1.55mm 475 +/- 25um Nominal 18um
PAD 1
Solomon Systech May 2005 P 8/56 Rev 1.7 SSD1303
Table 2 - SSD1303Z Die Pad Coordinates
Pad no. Pad Name 1 NC 2 NC 3 COM33 4 COM35 5 COM37 6 COM39 7 COM41 8 COM43 9 COM45 10 COM47 11 COM49 12 COM51 www..com 13 COM53 14 COM55 15 COM57 16 COM59 17 COM61 18 COM63 19 VSS 20 VSS 21 VSS 22 VCL 23 VCL 24 VCL 25 VSS 26 VSS 27 VSSB 28 VSSB 29 VSL 30 VSL 31 VSL 32 VDD 33 VCC 34 VCC 35 VCOMH 36 VCOMH 37 TR8 38 TR7 39 TR6 40 TR5 41 TR4 42 TR3 43 TR2 44 TR1 45 TR0 46 VSS 47 VSSB 48 VSSB 49 GDR 50 GDR 51 VDDB 52 VDDB 53 VDD 54 VDD 55 FB 56 RESE 57 VBREF 58 SENSE 59 BGGND 60 VSS X-pos -4535.4 -4483.2 -4431.0 -4379.2 -4327.4 -4275.6 -4223.8 -4172.0 -4120.2 -4068.4 -4016.6 -3964.8 -3913.0 -3861.2 -3809.4 -3757.6 -3705.8 -3654.0 -3543.3 -3467.1 -3390.9 -3314.7 -3238.5 -3162.3 -3086.1 -3009.9 -2933.7 -2857.5 -2781.3 -2705.1 -2628.9 -2552.7 -2476.5 -2400.3 -2324.1 -2247.9 -2171.7 -2095.5 -2019.3 -1943.1 -1866.9 -1790.7 -1714.5 -1638.3 -1562.1 -1485.9 -1409.7 -1333.5 -1257.3 -1181.1 -1104.9 -1028.7 -952.5 -876.3 -800.1 -723.9 -647.7 -571.5 -495.3 -419.1 Y-pos -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 Pad no. Pad Name 61 VCC 62 GPIO0 63 GPIO1 64 VDD 65 BS0 66 VSS 67 BS1 68 VDD 69 BS2 70 VSS 71 M 72 CL 73 DOF# 74 VSS 75 CS# 76 RES# 77 D/C 78 VSS 79 R/W 80 E/RD 81 VDD 82 D0 83 D1 84 D2 85 D3 86 D4 87 D5 88 D6 89 D7 90 VSS 91 M/S 92 CLS 93 VDD 94 ICAS 95 IREF 96 VCOMH 97 VCOMH 98 VREF 99 VCC 100 VCC 101 VDD 102 VSL 103 VSL 104 VSL 105 VSS 106 VSS 107 VCL 108 VCL 109 VCL 110 VSS 111 VSS 112 VSS 113 COM62 114 COM60 115 COM58 116 COM56 117 COM54 118 COM52 119 COM50 120 COM48 X-pos -342.9 -267.2 -190.5 -114.3 -38.1 38.1 114.3 190.5 266.7 342.9 419.1 495.3 571.5 647.7 723.9 800.1 876.3 952.5 1028.7 1104.9 1181.1 1257.3 1333.5 1409.7 1485.9 1562.1 1638.3 1714.5 1790.7 1866.9 1943.1 2019.3 2095.5 2171.7 2247.9 2324.1 2400.3 2476.5 2552.7 2628.9 2705.1 2781.3 2857.5 2933.7 3009.9 3086.1 3162.3 3238.5 3314.7 3390.9 3467.1 3543.3 3654.0 3705.8 3757.6 3809.4 3861.2 3913.0 3964.8 4016.6 Y-pos -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 Pad no. Pad Name 121 COM46 122 COM44 123 COM42 124 COM40 125 COM38 126 COM36 127 COM34 128 COM32 129 NC 130 NC 131 NC 132 NC 133 COM30 134 COM28 135 COM26 136 COM24 137 COM22 138 COM20 139 COM18 140 COM16 141 COM14 142 COM12 143 COM10 144 COM8 145 COM6 146 COM4 147 COM2 148 COM0 149 SEG0 150 SEG1 151 SEG2 152 SEG3 153 SEG4 154 SEG5 155 SEG6 156 SEG7 157 SEG8 158 SEG9 159 SEG10 160 SEG11 161 SEG12 162 SEG13 163 SEG14 164 SEG15 165 SEG16 166 SEG17 167 SEG18 168 SEG19 169 SEG20 170 SEG21 171 SEG22 172 SEG23 173 SEG24 174 SEG25 175 SEG26 176 SEG27 177 SEG28 178 SEG29 179 SEG30 180 SEG31 X-pos 4068.4 4120.2 4172.0 4223.8 4275.6 4327.4 4379.2 4431.0 4483.2 4535.4 4535.4 4483.2 4431.0 4379.2 4327.4 4275.6 4223.8 4172.0 4120.2 4068.4 4016.6 3964.8 3913.0 3861.2 3809.4 3757.6 3705.8 3654.0 3445.2 3393.0 3340.8 3288.6 3236.4 3184.2 3132.0 3079.8 3027.6 2975.4 2923.2 2871.0 2818.8 2766.6 2714.4 2662.2 2610.0 2557.8 2505.6 2453.4 2401.2 2349.0 2296.8 2244.6 2192.4 2140.2 2088.0 2035.8 1983.6 1931.4 1879.2 1827.0 Y-pos -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 -679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6
SSD1303
Rev 1.7
P 9/56
May 2005
Solomon Systech
Pad no. Pad Name 181 SEG32 182 SEG33 183 SEG34 184 SEG35 185 SEG36 186 SEG37 187 SEG38 188 SEG39 189 SEG40 190 SEG41 191 SEG42 192 SEG43 193 SEG44 www..com 194 SEG45 195 SEG46 196 SEG47 197 SEG48 198 SEG49 199 SEG50 200 SEG51 201 SEG52 202 SEG53 203 SEG54 204 SEG55 205 SEG56 206 SEG57 207 SEG58 208 SEG59 209 SEG60 210 SEG61 211 SEG62 212 SEG63 213 SEG64 214 SEG65 215 SEG66 216 SEG67 217 SEG68 218 SEG69 219 SEG70 220 SEG71 221 SEG72 222 SEG73 223 SEG74 224 SEG75 225 SEG76 226 SEG77 227 SEG78 228 SEG79 229 SEG80 230 SEG81 231 SEG82 232 SEG83 233 SEG84 234 SEG85 235 SEG86 236 SEG87 237 SEG88 238 SEG89 239 SEG90 240 SEG91
X-pos 1774.8 1722.6 1670.4 1618.2 1566.0 1513.8 1461.6 1409.4 1357.2 1305.0 1252.8 1200.6 1148.4 1096.2 1044.0 991.8 939.6 887.4 835.2 783.0 730.8 678.6 626.4 574.2 522.0 469.8 417.6 365.4 313.2 261.0 208.8 156.6 104.4 52.2 0.0 -52.2 -104.4 -156.6 -208.8 -261.0 -365.4 -417.6 -469.8 -522.0 -574.2 -626.4 -678.6 -730.8 -783.0 -835.2 -887.4 -939.6 -991.8 -1044.0 -1096.2 -1148.4 -1200.6 -1252.8 -1305.0 -1357.2
Y-pos 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6
Pad no. Pad Name 241 SEG92 242 SEG93 243 SEG94 244 SEG95 245 SEG96 246 SEG97 247 SEG98 248 SEG99 249 SEG100 250 SEG101 251 SEG102 252 SEG103 253 SEG104 254 SEG105 255 SEG106 256 SEG107 257 SEG108 258 SEG109 259 SEG110 260 SEG111 261 SEG112 262 SEG113 263 SEG114 264 SEG115 265 SEG116 266 SEG117 267 SEG118 268 SEG119 269 SEG120 270 SEG121 271 SEG122 272 SEG123 273 SEG124 274 SEG125 275 SEG126 276 SEG127 277 SEG128 278 SEG129 279 SEG130 280 SEG131 281 COM1 282 COM3 283 COM5 284 COM7 285 COM9 286 COM11 287 COM13 288 COM15 289 COM17 290 COM19 291 COM21 292 COM23 293 COM25 294 COM27 295 COM29 296 COM31 297 NC 298 NC
X-pos -1409.4 -1461.6 -1513.8 -1566.0 -1618.2 -1670.4 -1722.6 -1774.8 -1827.0 -1879.2 -1931.4 -1983.6 -2035.8 -2088.0 -2140.2 -2192.4 -2244.6 -2296.8 -2349.0 -2401.2 -2453.4 -2505.6 -2557.8 -2610.0 -2662.2 -2714.4 -2766.6 -2818.8 -2871.0 -2923.2 -2975.4 -3027.6 -3079.8 -3132.0 -3184.2 -3236.4 -3288.6 -3340.8 -3393.0 -3445.2 -3654.0 -3705.8 -3757.6 -3809.4 -3861.2 -3913.0 -3964.8 -4016.6 -4068.4 -4120.2 -4172.0 -4223.8 -4275.6 -4327.4 -4379.2 -4431.0 -4483.2 -4535.4
Y-pos 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6 679.6
Solomon Systech
May 2005
P 10/56
Rev 1.7
SSD1303
Figure 3 - SSD1303Z Alignment mark dimensions
T shape
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+ shape
Circle
Unit in um
SSD1303
Rev 1.7
P 11/56
May 2005
Solomon Systech
6
PIN DESCRIPTION
CL This pin is the system clock input. When internal clock is enabled, this pin should be left open. The internal clock is output from this pin. When internal oscillator is disabled, this pin receives display clock signal from external clock source. CLS This is the internal clock enable pin. When it is pulled HIGH, internal clock is enabled. When it is pulled LOW, the internal clock is disabled, an external clock source must be connected to the CL pin for normal operation.
www..com BS1, BS0,
BS2 These are MCU interface input selection pins. See the following table for selecting different interfaces: 6800-parallel interface 0 0 1 8080-parallel interface 0 1 1 Serial interface 0 0 0
BS0 BS1 BS2
CS# This pin is the chip select input. The chip is enabled for MCU communication only when CS# had been pulled low. RES# This is a reset signal input pin. When it is pulled LOW, initialization of the chip is executed. D/C This is the Data/Command control pin. When it is pulled HIGH, the input at D7-D0 is treated as display data. When it is pulled LOW, the input at D7-D0 is transferred to the command registers. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. R/W (WR#) This is a MCU interface input pin. When 6800-series Parallel Interface mode is selected, this pin is used as Read/Write (R/W) selection input. Pull this pin to HIGH for read mode and pull it to LOW for write mode. When 8080-series Parallel Interface mode is selected, this pin is used as Write (WR#) selection input. Pull this pin to LOW for write mode. Data write operation is initiated when this pin is pulled LOW and the CS# is pulled LOW. E (RD#) This is a MCU interface input pin. When 6800-series Parallel Interface is selected, this pin is used as Enable (E) signal. Read/Write operation is initiated when this pin is pulled HIGH and the CS# pin is pulled LOW. When 8080-series Parallel Interface is selected, this pin is used to receive the Read Data (RD#) signal. Data read operation is initiated when this pin is pulled LOW and CS# pin is pulled LOW. D7-D0 These are 8-bit bi-directional data bus to be connected to the microprocessor's data bus. When serial interface mode is selected, D1 will be the serial data input, SDIN, D0 will be the serial clock input, SCLK, and D2 should be left opened.
Solomon Systech
May 2005
P 12/56
Rev 1.7
SSD1303
VDD This is a voltage supply pin. It must be connected to external source. VSS This is a ground pin. It also acts as a reference for the logic pins and the OLED driving voltages. It must be connected to external ground. BGGND This is a ground pin for analog circuits. It must be connected to external ground VCC This is the most positive voltage supply pin of the chip. It should be supplied externally.
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VREF This is a voltage reference pin for pre-charge voltage in driving OLED device. Voltage should be set to match with the OLED driving voltage in current drive phase. It can either be supplied externally or by connecting to VCC. IREF This is a segment current reference pin. A resistor should be connected between this pin and VSS. Set the current at 10uA. VCOMH This is an input pin for the voltage output high level for COM signals. A capacitor should be connected between this pin and VSS. VDDB This is a power supply pin for the internal buffer of the DC-DC voltage converter. It must be connected to VDD when the converter is used. VSSB This is a ground pin for the internal buffer of the DC-DC voltage converter. It must be connected to VSS when the converter is used. GDR This is an output pin drives the gate of the external NMOS of the booster circuit. RESE This is a source current pin of the external NMOS of the booster circuit. VBREF This is an internal voltage reference pin for booster circuit. A stabilization capacitor, typ. 1uF, should be connected to Vss. FB This is a feedback resistor input pin for the booster circuit. It is used to adjust the booster output voltage level, Vcc. COM0-COM63 These are pins provided the Common switch signals to the OLED panel. They are in high impedance state when display is OFF.
SSD1303
Rev 1.7
P 13/56
May 2005
Solomon Systech
SEG0-SEG131 These are pins provided the Segment switch signals to the OLED panal. They are in high impedance stage when display is OFF. TR0-TR8, GPIO0, GPIO1, ICAS, M and DOF# These are reserved pins. No connection necessary and should be left open individually. VSL This is a segment voltage reference pin. This pin should be connected to VSS externally. VCL This is a common voltage reference pin. This pin should be connected to VSS externally. M/S This pin must be connected to VDD to enable the chip.
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NC Dummy pad. Do not group or short NC pins together.
Solomon Systech
May 2005
P 14/56
Rev 1.7
SSD1303
7
FUNCTIONAL BLOCK DESCRIPTIONS
7.1 Oscillator Circuit and Display Time Generator
Internal Oscillator
CL
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M U X
CLK
Divider
DCLK
Internal Display Clock
Figure 4 - Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the Display Timing Generator.
7.2 Reset Circuit
When RES# pin is pulled LOW, the chip is initialized with the following status: 1. Display is OFF 2. 132 x 64 Display Mode 3. Normal segment and display data column address and row address mapping (SEG0 is mapped to column address 00H and COM0 is mapped to row address 00H) 4. Shift register data clear in serial interface 5. Display start line is set at display RAM address 0 6. Column address counter is set at 0 7. Normal scan direction of the COM outputs 8. Contrast control register is set at 80H 9. DC/DC enable
7.3 Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. When the D/C# pin is pulled HIGH, the inputs at D7-D0 are interpreted as data and be written to Graphic Display Data RAM (GDDRAM). When it is pulled LOW, the inputs at D7-D0 are interpreted as command, they will be decoded and be written to the corresponding command registers.
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Rev 1.7
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May 2005
Solomon Systech
7.4 MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D7-D0), R/W (WR#), E (RD#), D/C, CS#. When the R/W (WR#) pin is pulled HIGH, Read operation from the Graphic Display Data RAM (GDDRAM) or the status register occurs. When the R/W (WR#) pin is pulled LOW, Write operation to Display Data RAM or Internal Command Registers occurs, depending on the status of D/C input. The E (RD#) input serves as data latch signal (clock) when HIGH provided that CS# is LOW. Refer to Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed, which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 5 below.
www..com R/W#
(W/R#) E (RD#)
Data bus N
Write column address Dummy read
n
Data read1
n+1
Data read2
n+2
Data read3
Figure 5 - Display data read back procedure - insertion of dummy read
7.5 MPU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D7-D0), R/W (WR#), E (RD#), D/C, CS#. The E (RD#) input serves as data read latch signal (clock) when it is LOW provided that CS# is LOW. Display data or status register read is controlled by D/C signal. R/W (WR#) input serves as data write latch signal (clock) when it is HIGH and provided that CS# is LOW. Display data or command register write is controlled by D/C. Refer to Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
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May 2005
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SSD1303
7.6 MPU Serial Interface
The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. D3 to D7, E and R/W pins can be connected to external ground. SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. During data writing, an additional NOP command should be inserted before the CS# goes high (Refer to Figure 6.
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Figure 6 - Display data write procedure in SPI mode
CS#
D/C
SDIN/ SCLK
DB1
DB2
DBn
NOP COMMAND
SCLK(D0)
SDIN(D1)
D7
D6
D5
D4
D3
D2
D1
D0
7.7 Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 64 bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display.
7.8 Current Control and Voltage Control
This block is used to derive the incoming power sources into different levels of internal use voltage and current. VCC and VDD are external power supplies. VREF is reference voltage, which is used to derive the driving voltage for segments and commons. IREF is a reference current source for segment current drivers.
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Rev 1.7
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May 2005
Solomon Systech
7.9 Segment Drivers / Common Drivers
Segment drivers deliver 132 current sources to drive OLED panel. The driving current can be adjusted from 0 to 300uA with 256 steps. Common drivers generate voltage scanning pulses.
7.10 Area Colour Decoder
Page 0 and Page 1 of the display are divided into 32 banks. Bank16 and Bank32 comprise of a display area of 12 x 8 pixels. Other banks (0~15 & 17~31) have matrices of 8 x 8 pixels. Each bank can be programmed to any one of the four colours (colour A, B, C, D). Detailed operation can be referred to the Command Table.
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Page 0, bank 1
Page 0, bank 16
Page 1, bank 17
Page 1, bank 32
Bank 0 (background) Page 2 - Page 7
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May 2005
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SSD1303
7.11DC-DC Voltage Converter
It is a switching voltage generator circuit, designed for handheld applications. In SSD1303, internal DC-DC voltage converter accompanying with an external application circuit (shown in below figure) can generate a high voltage supply VCC from a low voltage supply input VDD. VCC is the voltage supply to the OLED driver block. Below application circuit is an example for the input voltage of 3V VDD to generate VCC of 12V @0mA ~ 20mA application. Figure 7 - DC-DC voltage converter circuit L1
D1
VCC
VDD
+
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C5
AGND
Q1
VDDB GDR
+
R1
+
+
+
C6
VBREF
+
RESE
C7 R3
C2
C3
C1
VSSB
AGND
FB
+
AGND
C4
R2
DGND
Remark: 1. 2. 3. 4.
VSSB is tied to VSS on SSD1303T3 package. L1, D1, Q1, C5 should be grouped closed together on PCB layout. R1, R2, C1, C4 should be grouped closed together on PCB layout. The VCC output voltage level can be adjusted by R1and R2, the reference formula is: VCC = 1.2 x (R1+R2) / R2 The value of (R1+R2) should be between 500k to 1M Ohm.
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Rev 1.7
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May 2005
Solomon Systech
Table 3 - Passive component selection: Components Typical Value L1 Inductor, 10H D1 Schottky diode Q1 R1, R2 R3 C1 C2 C3 C4 www..com C5 C6 C7 MOSFET Resistor Resistor, 1.2 Capacitor, 1F Capacitor, 6.8F Capacitor, 1F Capacitor, 10nF Capacitor, 1 ~ 10 F Capacitor, 0.1 ~ 1F Capacitor, 15nF
Remark 1A 1A, 25V e.g. 1N5822, BAT54 [Philips Semiconductors] N-FET with low RDS(on) and low Vth voltage. e.g. MGSF1N02LT1 [ON SEMI] 1%,1/10W 1%, 1/2W 16V Low ESR, 25V 16V 16V 16V 16V 16V
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May 2005
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SSD1303
8
COMMAND TABLE
Table 4 - Command table (D/C =0, R/W (WR#)=0, E (RD#)=1) Note: commands marked with "**" are compatible to SSD1301
D/C Hex
0 00~0F
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 X3 X2 X1 X0
Command
Set Lower Column Address **
Description
Set the lower nibble of the column address register using X3X2X1X0 as data bits. The initial display line register is reset to 0000b after POR. Set the higher nibble of the column address register using X3X2X1X0 as data bits. The initial display line register is reset to 0000b after POR.
0
10~1F
0
0
0
1
X3
X2
X1
X0
Set Higher Column Address **
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0 0 0 0 0
26 A[2:0] B[2:0] C[1:0] D[2:0]
0 * * * *
0 * * * *
1 * * * *
0 * * * *
0 * * * *
1 A2 B2 * D2
1 A1 B1 C1 D1
0 A0 B0 C0 D0
Horizontal scroll setup
A[2:0] Set the number of column scroll per step Valid value: 001b, 010b, 011b, 100b B[2:0] Define start page address C[1:0] Set time interval between each scroll step in terms of frame frequency 00b - 12 frame 01b - 64 frames 10b - 128 frames 11b - 256 frames D[2:0] Define end page address Set the value of D[2:0] larger or equal to B[2:0]
0 0
2F 2E
0 0
0 0
1 1
0 0
1 1
1 1
1 1
1 0
Activate horizontal scroll Start horizontal scrolling Deactivate horizontal scroll Set Display Start Line Stop horizontal scrolling
0
40-7F
0
1
X5
X4
X3
X2
X1
X0
Set display TAM display start line register from 0-63 using X5X3X2X1X0. Display start line register is reset to 000000 during POR
0 0 0 0
81 A[7:0] 82 A[7:0]
1 A7 1 A7
0 A6 0 A6
0 A5 0 A5
0 A4 0 A4
0 A3 0 A3
0 A2 0 A2
0 A1 1 A1
1 A0 0 A0
Set Contrast Control Register ** Brightness for color banks
Double byte command to select 1 out of 256 contrast steps. Contrast increases as the value increases. (POR = 80h) Double byte command to select 1 out of 256 brightness steps. Brightness increases as the value increases. (POR = 80h)
0 0 0 0 0
91 X[5:0] A[5:0] B[5:0] C[5:0]
1 * * * *
0 * * * *
0 X5 A5 B5 C5
1 X4 A4 B4 C4
0 X3 A3 B3 C3
0 X2 A2 B2 C2
0 X1 A1 B1 C1
1 X0 A0 B0 C0
Set Look Up Table (LUT) for area colour
Set current drive pulse width of Bank 0, Colour A, B and C. Bank 0: X[5:0] = 0... 63; for pulse width set to 1 ~ 64 clocks (POR = 110001b) Colour A: A[5:0] same as above (POR = 111111b) Colour B: B[5:0] same as above (POR = 111111b) Colour C: C[5:0] same as above (POR = 111111b)
Note: colour D pulse width is fixed at 64 clocks pulse .
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Rev 1.7
P 21/56
May 2005
Solomon Systech
D/C Hex
0 0 0 0 0 92 A[7:0] B[7:0] C[7:0] D[7:0]
D7 D6 D5 D4 D3 D2 D1 D0
1 A7 B7 C7 D7 0 A6 B6 C6 D6 0 A5 B5 C5 D5 1 A4 B4 C4 D4 0 A3 B3 C3 D3 0 A2 B2 C2 D2 1 A1 B1 C1 D1 0 A0 B0 C0 D0
Command
Set bank colour of for bank 1-16 (Page 0)
Description
A[1:0] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 1 A[3:2] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 2 : : D[7:6]: 00, 01, 10, or 11 for Colour = A, B, C or D of bank 16
0
93
1 A7 B7 C7 D7
0 A6 B6 C6 D6
0 A5 B5 C5 D5
1 A4 B4 C4 D4
0 A3 B3 C3 D3
0 A2 B2 C2 D2
1 A1 B1 C1 D1
1 A0 B0 C0 D0
Set bank colour of for bank 17-32 (Page 1)
A[1:0] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 17 A[3:2] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 18 : : D[7:6]: 00, 01, 10, or 11 for Colour = A, B, C or D of bank 32
0 www..comA[7:0] 0 0 0 B[7:0] C[7:0] D[7:0]
0
A0~ A1
1
0
1
0
0
0
0
X0 Set Segment Re-map ** X0=0: column address 0 is mapped to SEG0 (POR) X0=1: column address 131 is mapped to SEG0
0
A4~A5
1
0
1
0
0
1
0
X0
Set Entire Display ON/OFF **
X0=0: normal display (POR) X0=1: entire display ON X0=0: normal display (POR) X0=1: inverse display The next command, A[5:0] determines multiplex ratio N from 16MUX-64MUX, POR= 64MUX Reserved, do not use Reserved, do not use
0 0 0 0 0
A6~A7 A8 A[5:0] AA AB
1 1 * 1 1
0 0 * 0 0
1 1 A5 1 1
0 0 A4 0 0
0 1 A3 1 1
1 0 A2 0 0
1 0 A1 1 1
X0 0 A0 0 1
Set Normal/Inverse Display ** Set Multiplex Ratio ** NOP NOP
0 0
0 0 0
AD
1 1
1 1 1
0 0
0 0 1
1 0
1 1 0
0 0
0 1 0
1 1
1 X3 X3
1 0
1 X2 *
0 1
1 X1 *
1 Set DC-DC on/off X0
X0 X0 * Set Display ON/OFF ** Set Page Address ** Set COM Output Scan Direction **
AE~AF B0~BF C0/C8
X0 : 1 DC-DC will be turned on when display on (POR) 0 DC-DC is disable X0=0: turns OFF OLED panel (POR) X0=1: turns ON OLED panel Set GDDRAM Page Address (0~7) for read/write using X3X2X1X0 X3=0: normal mode (POR) Scan from COM 0 to COM [N -1] X3=1: remapped mode. Scan from COM [N-1] to COM0
0
D0-D1
1
1
0
1
0
0
0
X0
Reserved
Where N is the Multiplex ratio. Reserved, do not use
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May 2005
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SSD1303
D/C Hex
0 0 D3 A[5:0]
D7 D6 D5 D4 D3 D2 D1 D0
1 * 1 * 0 A5 1 A4 0 A3 0 A2 1 A1 1 A0
Command
Set Display Offset **
Description
Set vertical scroll by COM from 0-63. The value is reset to 00H after POR.
0
D5
1
1
0
1
0
1
0
1
Set Display Clock Divide Ratio/Oscillator Frequency
A[3:0] Define the divide ratio of the display clocks (DCLK): Divide ratio= A[3:0] + 1, POR is 0000b (divide ratio = 1)
0 A[7:0] www..com
A7
A6
A5
A4
A3
A2
A1
A0
A[7:4] Set the Oscillator Frequency. Oscillator Frequency increases with the value of A[7:4] and vice versa. POR is 0111b
0 0
D8
1 0
1 0
0 X5
1 X4
1 0
0 X2
0 0
0 X0
0 0 0 0
D9 A[7:0] DA
1 A7 1 0
1 A6 1 0
0 A5 0 0
1 A4 1 X4
1 A3 1 0
0 A2 0 0
0 A1 1 1
1 A0 0 0
X5X4= 11 Area Colour enable X2=0 and X0=0: Normal (POR) power mode X2=1 and X0=1: Set low power save mode Set Pre-charge period** A[3:0] Phase 1 period of up to 15 dclk clocks [POR=2h]; 0 is invalid entry A[7:4] Phase 2 period of up to 15 dclk clocks [POR=2h]; 0 is invalid entry Set COM pins hardware X4=0, Sequential COM pin configuration configuration (i.e. COM31, 30, 29....0 ; SEG0-132; COM31,32....62,63) X4=1(POR), Alternative COM pin configuration (i.e. COM62,60,58,...2,0; SEG0-132; COM1,3,5...61,63)
Set area colour mode on/off & low power display mode
X5X4= 00 (POR) : mono mode
0 0
DB A[6:0]
1 *
1 A6
0 A5
1 A4
1 A3
0 A2
1 A1
1 A0
Set VCOM Deselect Level
A[6:0] 0000000 low VCOM deselect level (~ 0.43 Vref) 0110101 normal VCOM deselect level (~ 0.77*Vref (POR)) 1111111 high VCOM deselect level (equal Vref)
0 0 0
E2 E3 F*
1 1 1
1 1 1
1 1 1
0 0 1
0 0 *
0 0 *
1 1 *
0 1 *
Reserved NOP ** Reserved
Reserved Command for No Operation Reserved, do not use
Note: Remark "*" stands for "Don't Care"
Table 5 - Read command table
SSD1303 Rev 1.7 P 23/56 May 2005 Solomon Systech
(D/C=0, R/W (WR#)=1, E (RD#)=1 for 6800 or E (RD#)=0 for 8080)
Bit Pattern
D7D6D5D4D3D2D1D0
Command
Status Register Read * D7 : D6 : D5 : D4 : D3 : D2 : D1 : D0 :
Description
Reserve "1" for display OFF / "0" for display ON Reserve Reserve Reserve Reserve Reserve Reserve
Note: Patterns other than that given in Command Table are prohibited to enter to the chip as a command; otherwise, unexpected result will occur.
8.1 www..com
Data Read / Write
To read data from the GDDRAM, input HIGH to R/W (WR#) pin and D/C pin for 6800-series parallel mode, LOW to E (RD#) pin and HIGH to D/C# pin for 8080-series parallel mode. No data read is provided in serial mode operation. In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a dummy read is required before the first data read. See Figure 5 in Functional Block Description. To write data to the GDDRAM, input LOW to R/W (WR#) pin and HIGH to D/C pin for 6800-series parallel mode AND 8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each data write.
Table 6 - Address increment table (Automatic)
D/C 0 0 1 1 R/W (WR#) 0 1 0 1 Comment Write Command Read Status Write Data Read Data Address Increment No No Yes Yes*1
*1. If read-data command is issued in read-modify-write mode, address increase is not applied.
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May 2005
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9
COMMAND DESCRIPTIONS
Set Lower Column Address This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU. Set Higher Column Address This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU.
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Activate Horizontal Scroll Start motion of horizontal scrolling. This command should only be issued after Horizontal scroll setup parameters are defined. The following actions are prohibited after the horizontal scroll is activated 1. RAM access (Data write or read) 2. Changing horizontal scroll setup parameters The SSD1303 horizontal scroll is designed for 128 columns scrolling only. reserved for computation and should be left open. 4 remaining columns are
With column address 0 mapped to SEG0 (Segment remap setting = A0h), the 4 unused columns will be SEG128, SEG129, SEG130, SEG131. With column address 0 mapped to SEG131 (Segment remap setting = A1h), the 4 unused columns will be SEG0, SEG1, SEG2, SEG3. Figure 8 - Horizontal scroll direction SEG126 SEG127 SEG128 SEG129 SEG130 B SEG131 A
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
REMAP SETTING
...
... ! "
A0 A1
A
B
C
D
E Z
F Y
! "
! "
...
Y F
Z E D
Invalid data C
Invalid data
Scroll direction
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Rev 1.7
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May 2005
Solomon Systech
Deactivate Horizontal Scroll Stop motion of horizontal scrolling. Horizontal Scroll Setup This command consists of 5 consecutive bytes to set up the horizontal scroll parameters. It determined the scrolling start page, end page and the scrolling speed. Before issuing this command, the horizontal scroll must be deactivated (2Eh). Otherwise, ram content may be corrupted. Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63 are assigned to www..com Page 0 to 7.
Set Contrast Control Register This command is to set Contrast Setting of the display. The chip has 256 contrast steps from 00 to FF. The segment output current increases as the contrast step value increases. See Figure 9. Figure 9 - Segment current vs Contrast setting
Segm ent current vs Contrast setting
350
300
250 Current (uA) 200
Segment output current setting: Iseg = Cr/256 * Iref * scale factor Where: Cr is contrast step Iref is reference current equals 10uA Scale factor =32
150
100
50
0 00 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF
Contrast setting
Set Brightness for Color Banks This command is to set Brightness Setting of the display for area colors banks (except bank 0). The chip has 256 brightness steps from 00 to FF. The segment output current increases as the brightness step value increases
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May 2005
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Rev 1.7
SSD1303
Set Look Up Table (LUT) for area colour SSD1303 provides 4 colour (pulse width) settings - Colour A, B, C and D. The colour intensity (or grey scale) is defined by the current drive pulse width. The pulse width of colour A, B, C can be programmable from 1 to 64 DCLK* duration. The colour D is fixed at 64 DCLK pulse width. This colour setting has to be stored in the Look Up Table (LUT). For the background colour, the colour intensity is defined by a variable X[5:0]. Set LUT command: 10010001 X[5:0] A[5:0] B[5:0] C[5:0] Description
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Set background colour Set Pulse Width A Set Pulse Width B Set Pulse Width C Pulse width D is fixed to 64 DCLK DCLK: Internal Display Clock Set bank colour of bank 1-16 (Page 0) and bank colour of bank 17-32 (Page 1) Next step is to define the colour of each display area. The 132x64 display matrix is divided into 8 pages of 8 commons per pages. The first two pages, page 0 and page 1, are divided into 32 banks: Bank16 and Bank32 comprise of a display area of 12x8 pixels. Other banks (0~15 & 17~31) have matrices of 8x8 pixels. Each bank can be programmable to any 1 of the 4 colour (A, B, C, D). User can use 92h and 93h command for the bank colour setting. Note: Only applicable in area colour mode. Set Segment Re-map This command changes the mapping between the display data column address and segment driver. It allows flexibility in OLED module design. Refer to Command Table. Set Entire Display ON/OFF This command forces the entire display to be "ON" regardless of the contents of the display data RAM. This command has priority over normal/reverse display. This command will be used with "Set Display ON/OFF" command to form a compound command for entering power save mode. Set Normal/Inverse Display This command sets the display to be either normal/inverse. In normal display, a RAM data of 1 indicates an "ON" pixel while in inverse display; a RAM data of 0 indicates an "ON" pixel. Set Multiplex Ratio This command switches default 63 multiplex mode to any multiplex ratio from 2 to 63. The output pads COM0-COM63 will be switched to corresponding COM signal. Set DC-DC on/off This command is to control the DC-DC voltage converter. The converter will be turned on by issuing this command then DISPLAY ON command. The panel display must be off while issuing this command. POR the DC-DC will be turned on.
Bank 0 Colour A Colour B Colour C Colour D
Number of DCLKs X[5:0] A[5:0] B[5:0] C[5:0] 64 (fixed)
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Rev 1.7
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May 2005
Solomon Systech
Set Display ON/OFF This command turns the display ON or OFF. When the display is OFF, the segment and common output are in high impedance state. Set Page Address This command positions the page address from 0 to 7 in GDDRAM. Refer to Command Table. Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in OLED module design. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will be vertically flipped. Set Display Offset This is a double byte command. The next command specifies the mapping of display start line to one of www..com COM0-63 (it is assumed that COM0 is the display start line, display start line register equals to 0). For example, to move the COM16 towards the COM0 direction for 16 lines, the 6-bit data in the second byte should be given by 010000. To move in the opposite direction by 16 lines, the 6-bit data should be given by (64 - 16) and so the second byte should be 100000.
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May 2005
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Rev 1.7
SSD1303
Hardware pin name COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 www..com COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63
64 Normal 0 0 Row0 RAM0 Row1 RAM1 Row2 RAM2 Row3 RAM3 Row4 RAM4 Row5 RAM5 Row6 RAM6 Row7 RAM7 Row8 RAM8 Row9 RAM9 Row10 RAM10 Row11 RAM11 Row12 RAM12 Row13 RAM13 Row14 RAM14 Row15 RAM15 Row16 RAM16 Row17 RAM17 Row18 RAM18 Row19 RAM19 Row20 RAM20 Row21 RAM21 Row22 RAM22 Row23 RAM23 Row24 RAM24 Row25 RAM25 Row26 RAM26 Row27 RAM27 Row28 RAM28 Row29 RAM29 Row30 RAM30 Row31 RAM31 Row32 RAM32 Row33 RAM33 Row34 RAM34 Row35 RAM35 Row36 RAM36 Row37 RAM37 Row38 RAM38 Row39 RAM39 Row40 RAM40 Row41 RAM41 Row42 RAM42 Row43 RAM43 Row44 RAM44 Row45 RAM45 Row46 RAM46 Row47 RAM47 Row48 RAM48 Row49 RAM49 Row50 RAM50 Row51 RAM51 Row52 RAM52 Row53 RAM53 Row54 RAM54 Row55 RAM55 Row56 RAM56 Row57 RAM57 Row58 RAM58 Row59 RAM59 Row60 RAM60 Row61 RAM61 Row62 RAM62 Row63 RAM63
64 Normal 8 0 Row8 RAM8 Row9 RAM9 Row10 RAM10 Row11 RAM11 Row12 RAM12 Row13 RAM13 Row14 RAM14 Row15 RAM15 Row16 RAM16 Row17 RAM17 Row18 RAM18 Row19 RAM19 Row20 RAM20 Row21 RAM21 Row22 RAM22 Row23 RAM23 Row24 RAM24 Row25 RAM25 Row26 RAM26 Row27 RAM27 Row28 RAM28 Row29 RAM29 Row30 RAM30 Row31 RAM31 Row32 RAM32 Row33 RAM33 Row34 RAM34 Row35 RAM35 Row36 RAM36 Row37 RAM37 Row38 RAM38 Row39 RAM39 Row40 RAM40 Row41 RAM41 Row42 RAM42 Row43 RAM43 Row44 RAM44 Row45 RAM45 Row46 RAM46 Row47 RAM47 Row48 RAM48 Row49 RAM49 Row50 RAM50 Row51 RAM51 Row52 RAM52 Row53 RAM53 Row54 RAM54 Row55 RAM55 Row56 RAM56 Row57 RAM57 Row58 RAM58 Row59 RAM59 Row60 RAM60 Row61 RAM61 Row62 RAM62 Row63 RAM63 Row0 RAM0 Row1 RAM1 Row2 RAM2 Row3 RAM3 Row4 RAM4 Row5 RAM5 Row6 RAM6 Row7 RAM7
Output 64 56 Normal Normal 0 0 8 0 Row0 RAM8 Row0 RAM0 Row1 RAM9 Row1 RAM1 Row2 RAM10 Row2 RAM2 Row3 RAM11 Row3 RAM3 Row4 RAM12 Row4 RAM4 Row5 RAM13 Row5 RAM5 Row6 RAM14 Row6 RAM6 Row7 RAM15 Row7 RAM7 Row8 RAM16 Row8 RAM8 Row9 RAM17 Row9 RAM9 Row10 RAM18 Row10 RAM10 Row11 RAM19 Row11 RAM11 Row12 RAM20 Row12 RAM12 Row13 RAM21 Row13 RAM13 Row14 RAM22 Row14 RAM14 Row15 RAM23 Row15 RAM15 Row16 RAM24 Row16 RAM16 Row17 RAM25 Row17 RAM17 Row18 RAM26 Row18 RAM18 Row19 RAM27 Row19 RAM19 Row20 RAM28 Row20 RAM20 Row21 RAM29 Row21 RAM21 Row22 RAM30 Row22 RAM22 Row23 RAM31 Row23 RAM23 Row24 RAM32 Row24 RAM24 Row25 RAM33 Row25 RAM25 Row26 RAM34 Row26 RAM26 Row27 RAM35 Row27 RAM27 Row28 RAM36 Row28 RAM28 Row29 RAM37 Row29 RAM29 Row30 RAM38 Row30 RAM30 Row31 RAM39 Row31 RAM31 Row32 RAM40 Row32 RAM32 Row33 RAM41 Row33 RAM33 Row34 RAM42 Row34 RAM34 Row35 RAM43 Row35 RAM35 Row36 RAM44 Row36 RAM36 Row37 RAM45 Row37 RAM37 Row38 RAM46 Row38 RAM38 Row39 RAM47 Row39 RAM39 Row40 RAM48 Row40 RAM40 Row41 RAM49 Row41 RAM41 Row42 RAM50 Row42 RAM42 Row43 RAM51 Row43 RAM43 Row44 RAM52 Row44 RAM44 Row45 RAM53 Row45 RAM45 Row46 RAM54 Row46 RAM46 Row47 RAM55 Row47 RAM47 Row48 RAM56 Row48 RAM48 Row49 RAM57 Row49 RAM49 Row50 RAM58 Row50 RAM50 Row51 RAM59 Row51 RAM51 Row52 RAM60 Row52 RAM52 Row53 RAM61 Row53 RAM53 Row54 RAM62 Row54 RAM54 Row55 RAM63 Row55 RAM55 Row56 RAM0 Row57 RAM1 Row58 RAM2 Row59 RAM3 Row60 RAM4 Row61 RAM5 Row62 RAM6 Row63 RAM7 -
56 Normal 8 0 Row8 RAM8 Row9 RAM9 Row10 RAM10 Row11 RAM11 Row12 RAM12 Row13 RAM13 Row14 RAM14 Row15 RAM15 Row16 RAM16 Row17 RAM17 Row18 RAM18 Row19 RAM19 Row20 RAM20 Row21 RAM21 Row22 RAM22 Row23 RAM23 Row24 RAM24 Row25 RAM25 Row26 RAM26 Row27 RAM27 Row28 RAM28 Row29 RAM29 Row30 RAM30 Row31 RAM31 Row32 RAM32 Row33 RAM33 Row34 RAM34 Row35 RAM35 Row36 RAM36 Row37 RAM37 Row38 RAM38 Row39 RAM39 Row40 RAM40 Row41 RAM41 Row42 RAM42 Row43 RAM43 Row44 RAM44 Row45 RAM45 Row46 RAM46 Row47 RAM47 Row48 RAM48 Row49 RAM49 Row50 RAM50 Row51 RAM51 Row52 RAM52 Row53 RAM53 Row54 RAM54 Row55 RAM55 Row0 RAM0 Row1 RAM1 Row2 RAM2 Row3 RAM3 Row4 RAM4 Row5 RAM5 Row6 RAM6 Row7 RAM7
56 Normal 0 8 Row0 RAM8 Row1 RAM9 Row2 RAM10 Row3 RAM11 Row4 RAM12 Row5 RAM13 Row6 RAM14 Row7 RAM15 Row8 RAM16 Row9 RAM17 Row10 RAM18 Row11 RAM19 Row12 RAM20 Row13 RAM21 Row14 RAM22 Row15 RAM23 Row16 RAM24 Row17 RAM25 Row18 RAM26 Row19 RAM27 Row20 RAM28 Row21 RAM29 Row22 RAM30 Row23 RAM31 Row24 RAM32 Row25 RAM33 Row26 RAM34 Row27 RAM35 Row28 RAM36 Row29 RAM37 Row30 RAM38 Row31 RAM39 Row32 RAM40 Row33 RAM41 Row34 RAM42 Row35 RAM43 Row36 RAM44 Row37 RAM45 Row38 RAM46 Row39 RAM47 Row40 RAM48 Row41 RAM49 Row42 RAM50 Row43 RAM51 Row44 RAM52 Row45 RAM53 Row46 RAM54 Row47 RAM55 Row48 RAM56 Row49 RAM57 Row50 RAM58 Row51 RAM59 Row52 RAM60 Row53 RAM61 Row54 RAM62 Row55 RAM63 -
Set MUX ratio(A8) COM Normal / Remapped (C0 / C8) Display offset (D3) Display start line (40 - 7F)
SSD1303
Rev 1.7
P 29/56
May 2005
Solomon Systech
Output 64 Remap Hardware pin name COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 www..com COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 Row63 Row62 Row61 Row60 Row59 Row58 Row57 Row56 Row55 Row54 Row53 Row52 Row51 Row50 Row49 Row48 Row47 Row46 Row45 Row44 Row43 Row42 Row41 Row40 Row39 Row38 Row37 Row36 Row35 Row34 Row33 Row32 Row31 Row30 Row29 Row28 Row27 Row26 Row25 Row24 Row23 Row22 Row21 Row20 Row19 Row18 Row17 Row16 Row15 Row14 Row13 Row12 Row11 Row10 Row9 Row8 Row7 Row6 Row5 Row4 Row3 Row2 Row1 Row0 0 0 RAM63 RAM62 RAM61 RAM60 RAM59 RAM58 RAM57 RAM56 RAM55 RAM54 RAM53 RAM52 RAM51 RAM50 RAM49 RAM48 RAM47 RAM46 RAM45 RAM44 RAM43 RAM42 RAM41 RAM40 RAM39 RAM38 RAM37 RAM36 RAM35 RAM34 RAM33 RAM32 RAM31 RAM30 RAM29 RAM28 RAM27 RAM26 RAM25 RAM24 RAM23 RAM22 RAM21 RAM20 RAM19 RAM18 RAM17 RAM16 RAM15 RAM14 RAM13 RAM12 RAM11 RAM10 RAM9 RAM8 RAM7 RAM6 RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 Row7 Row6 Row5 Row4 Row3 Row2 Row1 Row0 Row63 Row62 Row61 Row60 Row59 Row58 Row57 Row56 Row55 Row54 Row53 Row52 Row51 Row50 Row49 Row48 Row47 Row46 Row45 Row44 Row43 Row42 Row41 Row40 Row39 Row38 Row37 Row36 Row35 Row34 Row33 Row32 Row31 Row30 Row29 Row28 Row27 Row26 Row25 Row24 Row23 Row22 Row21 Row20 Row19 Row18 Row17 Row16 Row15 Row14 Row13 Row12 Row11 Row10 Row9 Row8 64 Remap 8 0 RAM7 RAM6 RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 RAM63 RAM62 RAM61 RAM60 RAM59 RAM58 RAM57 RAM56 RAM55 RAM54 RAM53 RAM52 RAM51 RAM50 RAM49 RAM48 RAM47 RAM46 RAM45 RAM44 RAM43 RAM42 RAM41 RAM40 RAM39 RAM38 RAM37 RAM36 RAM35 RAM34 RAM33 RAM32 RAM31 RAM30 RAM29 RAM28 RAM27 RAM26 RAM25 RAM24 RAM23 RAM22 RAM21 RAM20 RAM19 RAM18 RAM17 RAM16 RAM15 RAM14 RAM13 RAM12 RAM11 RAM10 RAM9 RAM8 Row63 Row62 Row61 Row60 Row59 Row58 Row57 Row56 Row55 Row54 Row53 Row52 Row51 Row50 Row49 Row48 Row47 Row46 Row45 Row44 Row43 Row42 Row41 Row40 Row39 Row38 Row37 Row36 Row35 Row34 Row33 Row32 Row31 Row30 Row29 Row28 Row27 Row26 Row25 Row24 Row23 Row22 Row21 Row20 Row19 Row18 Row17 Row16 Row15 Row14 Row13 Row12 Row11 Row10 Row9 Row8 Row7 Row6 Row5 Row4 Row3 Row2 Row1 Row0 64 Remap 0 8 RAM7 RAM6 RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 RAM63 RAM62 RAM61 RAM60 RAM59 RAM58 RAM57 RAM56 RAM55 RAM54 RAM53 RAM52 RAM51 RAM50 RAM49 RAM48 RAM47 RAM46 RAM45 RAM44 RAM43 RAM42 RAM41 RAM40 RAM39 RAM38 RAM37 RAM36 RAM35 RAM34 RAM33 RAM32 RAM31 RAM30 RAM29 RAM28 RAM27 RAM26 RAM25 RAM24 RAM23 RAM22 RAM21 RAM20 RAM19 RAM18 RAM17 RAM16 RAM15 RAM14 RAM13 RAM12 RAM11 RAM10 RAM9 RAM8 Row47 Row46 Row45 Row44 Row43 Row42 Row41 Row40 Row39 Row38 Row37 Row36 Row35 Row34 Row33 Row32 Row31 Row30 Row29 Row28 Row27 Row26 Row25 Row24 Row23 Row22 Row21 Row20 Row19 Row18 Row17 Row16 Row15 Row14 Row13 Row12 Row11 Row10 Row9 Row8 Row7 Row6 Row5 Row4 Row3 Row2 Row1 Row0 48 Remap 0 0 RAM47 RAM46 RAM45 RAM44 RAM43 RAM42 RAM41 RAM40 RAM39 RAM38 RAM37 RAM36 RAM35 RAM34 RAM33 RAM32 RAM31 RAM30 RAM29 RAM28 RAM27 RAM26 RAM25 RAM24 RAM23 RAM22 RAM21 RAM20 RAM19 RAM18 RAM17 RAM16 RAM15 RAM14 RAM13 RAM12 RAM11 RAM10 RAM9 RAM8 RAM7 RAM6 RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 Row47 Row46 Row45 Row44 Row43 Row42 Row41 Row40 Row39 Row38 Row37 Row36 Row35 Row34 Row33 Row32 Row31 Row30 Row29 Row28 Row27 Row26 Row25 Row24 Row23 Row22 Row21 Row20 Row19 Row18 Row17 Row16 Row15 Row14 Row13 Row12 Row11 Row10 Row9 Row8 Row7 Row6 Row5 Row4 Row3 Row2 Row1 Row0 48 Remap 8 0 RAM47 RAM46 RAM45 RAM44 RAM43 RAM42 RAM41 RAM40 RAM39 RAM38 RAM37 RAM36 RAM35 RAM34 RAM33 RAM32 RAM31 RAM30 RAM29 RAM28 RAM27 RAM26 RAM25 RAM24 RAM23 RAM22 RAM21 RAM20 RAM19 RAM18 RAM17 RAM16 RAM15 RAM14 RAM13 RAM12 RAM11 RAM10 RAM9 RAM8 RAM7 RAM6 RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 Row47 Row46 Row45 Row44 Row43 Row42 Row41 Row40 Row39 Row38 Row37 Row36 Row35 Row34 Row33 Row32 Row31 Row30 Row29 Row28 Row27 Row26 Row25 Row24 Row23 Row22 Row21 Row20 Row19 Row18 Row17 Row16 Row15 Row14 Row13 Row12 Row11 Row10 Row9 Row8 Row7 Row6 Row5 Row4 Row3 Row2 Row1 Row0 48 Remap 0 8 RAM41 RAM40 RAM41 RAM42 RAM43 RAM44 RAM45 RAM46 RAM47 RAM46 RAM45 RAM44 RAM43 RAM42 RAM41 RAM40 RAM39 RAM38 RAM37 RAM36 RAM35 RAM34 RAM33 RAM32 RAM31 RAM30 RAM29 RAM28 RAM27 RAM26 RAM25 RAM24 RAM23 RAM22 RAM21 RAM20 RAM19 RAM18 RAM17 RAM16 RAM15 RAM14 RAM13 RAM12 RAM11 RAM10 RAM9 RAM8 Row47 Row46 Row45 Row44 Row43 Row42 Row41 Row40 Row39 Row38 Row37 Row36 Row35 Row34 Row33 Row32 Row31 Row30 Row29 Row28 Row27 Row26 Row25 Row24 Row23 Row22 Row21 Row20 Row19 Row18 Row17 Row16 Row15 Row14 Row13 Row12 Row11 Row10 Row9 Row8 Row7 Row6 Row5 Row4 Row3 Row2 Row1 Row0 48 Remap 8 16 RAM63 RAM62 RAM61 RAM60 RAM59 RAM58 RAM57 RAM56 RAM55 RAM54 RAM53 RAM52 RAM51 RAM50 RAM49 RAM48 RAM47 RAM46 RAM45 RAM44 RAM43 RAM42 RAM41 RAM40 RAM39 RAM38 RAM37 RAM36 RAM35 RAM34 RAM33 RAM32 RAM31 RAM30 RAM29 RAM28 RAM27 RAM26 RAM25 RAM24 RAM23 RAM22 RAM21 RAM20 RAM19 RAM18 RAM17 RAM16 Set MUX ratio(A8) COM Normal / Remapped (C0 / C8) Display offset (D3) Display start line (40 - 7F)
Set Display Clock Divide Ratio/ Oscillator Frequency This command is used to set the frequency of the internal display clocks, DCLKs. It is defined as the divide ratio (Value from 1 to 16) used to divide the oscillator frequency. POR is 1. Frame frequency is determined by divide ratio, number of display clocks per row, MUX ratio and oscillator frequency. Set Area Colour Mode ON/OFF This command is used to enable area colour mode. POR is mono mode.
Solomon Systech
May 2005
P 30/56
Rev 1.7
SSD1303
Set Low Power Display Mode This is a double byte command. This command is set to reduce power consumption during IC operation. Set Pre-charge period This command is used to set the duration of the pre-charge period. The interval is counted in number of DCLK. POR is 2 DCLK. Set COM pins hardware configuration This command is to set the COM signals pin configuration (sequential or alternative) to match the OLED panel hardware layout Sequential COM pin configuration:
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COM31, 30, 29...0
SEG0, 1, 2... 131
COM32, 33, 34...63
Alternative COM pin configuration (POR): COM62, 60, 58...0 SEG0, 1, 2... 131 COM1, 3, 5...63
Set VCOM deselect level This command is to set the COM pin output voltage level at deselect stage. NOP No Operation Command Status register Read This command is issued by setting D/C# LOW during a data read (refer to Figure 10 and Figure 11 for parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode.
SSD1303
Rev 1.7
P 31/56
May 2005
Solomon Systech
10 MAXIMUM RATINGS
Table 7 - Maximum Ratings (Voltage Reference to VSS)
Symbol VDD VCC VREF VCOMH Vin TA Tstg Parameter Supply Voltage Supply Voltage/Output voltage SEG/COM output voltage Input voltage Operating Temperature Storage Temperature Range Value -0.3 to +4.0 0.0 to 18.0 0.0 to 18.0 0.0 to 18.0 0.0 to 18.0 Vss-0.3 to Vdd+0.3 -40 to +90 -65 to +150 Unit V V V V V V C C
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Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description.
Solomon Systech
May 2005
P 32/56
Rev 1.7
SSD1303
11 DC CHARACTERISTICS
Table 8 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C)
Symbol VCC VDD VDD VOH
www..comOL V
Parameter Operating Voltage Logic Supply Voltage Logic Supply Voltage (internal DC/DC enable) High Logic Output Level Low Logic Output Level High Logic Input Level Low Logic Input Level Sleep mode Current Sleep mode Current VCC Supply Current VDD = 2.7V, VCC = 12V, IREF = 10uA No loading, Display ON, All ON
Test Condition IOUT = 100uA, 3.3MHz IOUT = 100uA, 3.3MHz IOUT = 100uA, 3.3MHz IOUT = 100uA, 3.3MHz VDD=2.7V, display OFF, No panel attached VDD=2.7V, display OFF, No panel attached
Min 7 2.4 3.0 0.9*VDD 0 0.8*VDD 0 -10 -10
Typ 12 -
Max 16 3.5 3.5 VDD 0.1*VDD VDD 0.2*VDD +10 +10
Unit V V V V V V V uA uA
VIH VIL ICC, SLEEP IDD, SLEEP
ICC
Contrast = FF
-
550
-
uA
IDD
VDD Supply Current VDD = 2.7V, VCC = 12V, IREF = 10uA No loading, Display ON, All ON Segment Output Current
Contrast = FF
-
190
-
uA
Contrast=FF Contrast=AF Contrast=5F Contrast=0F Dev = (ISEG - IMID)/IMID IMID = (IMAX + IMIN)/2 ISEG[0:131] = Segment current at contrast = FF Adj Dev = (I[n]-I[n+1]) / (I[n]+I[n+1]) VDD input=3V, L=22uH; R1=450Kohm; R2=50Kohm; Icc = 20mA(loading)
285 -
320 220 120 20 2.0
355 3 % uA
ISEG
VDD=2.7V, VCC=12V, IREF=10uA, Display ON, Segment pin under test is connected with a 20K resistive load to VSS Segment output current uniformity Adjacent pin output current uniformity (contrast = FF)
Dev
Adj. Dev
-
%
11.0
12.0
13.0 V
Vcc
DC-DC converter output voltage -
7
-
16
Pwr
DC-DC converter output power
VDD input=3V, L=22uH; Vcc = 12V
-
-
400
mW
SSD1303
Rev 1.7
P 33/56
May 2005
Solomon Systech
12 AC CHARACTERISTICS
Table 9 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C.) Parameter Test Condition Min Typ Symbol
FOSC Oscillation Frequency of Display Timing Generator Frame Frequency for 64 MUX Mode Vdd = 2.7V 315 360 Max 420 Unit kHz
FFRM
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132x64 Graphic Display Mode, Display ON, Internal Oscillator Enabled
-
FOSC X 1/(D*K*64)
-
Hz
Reset low pulse width RES# Reset complete time
-
3
us
-
2
us
D: divide ratio (default value = 1) K: number of display clocks (default value = 54) Refer to command table (set display clock divide ratio/oscillator freq) for detail description
Solomon Systech
May 2005
P 34/56
Rev 1.7
SSD1303
Table 10 - 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = 25C)
Symbol
tcycle tAS tAH tDSW tDHW tDHR www..com tOH tACC PW CSL PW CSH tR tF Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Parameter
Min
300 0 0 40 7 20 120 60 60 60 -
Typ
-
Max
70 140 15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
D/C
tAS tAH
R/W
E
tcycle PW CSL PW CSH
CS#
tF tDSW D0~D7(WRITE)
tR tDHW
Valid Data
tACC tDHR
D0~D7(READ)
Valid Data
tOH
Figure 10 - 6800-series MPU parallel interface characteristics
SSD1303
Rev 1.7
P 35/56
May 2005
Solomon Systech
Table 11 - 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = 25C)
Symbol
tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH www..com tR tF
Parameter
Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Min
300 0 0 40 7 20 120 60 60 60 -
Typ
-
Max
70 140 15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
D/C tAS CS# tF PW CSL RD# tcycle tR PW CSH t AH
WR#
tDSW D0-D7 (Write data to driver)
tDHW
Valid Data
D0-D7 (Read data from driver)
tACC Valid Data
tDHR
t Figure 11 - 8080-series MPU parallel interface characteristics
Solomon Systech
May 2005
P 36/56
Rev 1.7
SSD1303
Table 12 - Serial Interface Timing Characteristics
(VDD - VSS = 2.4 to 3.5V, TA = 25C)
Symbol
tcycle tAS tAH tCSS tCSH tDSW tDHW www..com tCLKL tCLKH tR tF Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time
Parameter
Min
250 150 150 120 60 100 100 100 100 -
Typ
-
Max
15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns
D/C
tAS tAH tCSH tcycle
CS#
tCSS
tCLKL SCLK(D0) tF tDSW SDIN(D1)
tCLKH
tR tDHW
Valid Data
CS#
SCLK(D0)
SDIN(D1)
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12 - Serial interface characteristics
SSD1303
Rev 1.7
P 37/56
May 2005
Solomon Systech
13 APPLICATION EXAMPLE
Figure 13 - Application Example (Block Diagram of SSD1303T3)
The configuration for 6800-parallel interface mode, externally VCC is shown in the following diagram: (VDD=2.7V, VCC=VREF=12V, IREF=10uA)
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DISPLAY PANEL SIZE 96 x 64
COM62 COM60 . . COM2 COM0
SSD1303T3
VCC VCOMH IREF D7~D0 E (RD#) R/W# (W/R#) D/C# RES# CS# BS1 BS2 VDD VDDB GDR RESE FB VBREF VSS
C3
R1
C2
D0~D7 E (RD#) R/W# (W/R#) VSS [GND] D/C# RES# CS# BS1 BS2 VDD VSS
Vcc
Pin connected to MCU interface: D0~D7, E, R/W#, D/C#, CS#, RES# Pin externally connected to VSS: BS0, VSSB Pin internally connected to VCC: VREF GDR, RESE, VBREF, FB should be left open individually; C1~ C3: 4.7uF R1: 910k, R1=(Voltage at IREF pin-VSS)/IREF Voltage at IREF pin = VCC-3V
Solomon Systech
COM1 COM3 . . COM61 COM63 C1
SEG0 . . . . . . . . . . . . SEG95
May 2005
P 38/56
Rev 1.7
SSD1303
14 SSD1303T3R1 PACKAGE DETAILS
SSD1303T3R1 Pin Assignment
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Figure 14 - SSD1303T3R1 pin assignment (Copper view, Normal TAB design) Remark: Use internal clock VREF is connected to VCC Support MCU interface: 8-bit 6800/8080 parallel interface and SPI VSSB, BGGND are connected to VSS BS0 is connected to VSS
SSD1303
Rev 1.7
P 39/56
May 2005
Solomon Systech
Table 13 - SSD1303T3R1 pin assignment
Pin no.
1 2 3 4 5 6 7 8 9 10 11 12 13 www..com 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pin name
NC VSS GDR VDDB FB RESE VBREF GP0 GP1 NC VDD1 BS1 BS2 NC CS# RES# D/C R/W E/RD D0 D1 D2 D3 D4 D5 D6 D7 IREF VCOMH VCC NC NC NC COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10
Pin no.
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pin name
COM8 COM6 COM4 COM2 COM0 NC NC NC NC NC NC NC NC
Pin no.
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46
Pin name SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95
NC NC NC NC NC NC NC NC COM1 COM3 COM5
Pin no.
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211
Pin name
COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 NC NC
Solomon Systech
May 2005
P 40/56
Rev 1.7
SSD1303
SSD1303T3R1 TAB PACKAGE DIMENSIONS
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SSD1303
SSD1303T3
SOLOMON
Rev 1.7
P 41/56
May 2005
Solomon Systech
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Solomon Systech
May 2005
P 42/56
Rev 1.7
SSD1303
15 SSD1303T6R1 PACKAGE DETAILS
SSD1303T6R1 Pin Assignment
Figure 15 - SSD1303T6R1 pin assignment (Copper view)
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Remark: Use internal clock VREF is connected to VCC Support MCU interface: 8-bit 6800/8080 parallel interface and SPI VSSB, BGGND are connected to VSS BS0 is connected to VSS
SSD1303
Rev 1.7
P 43/56
May 2005
Solomon Systech
Table 14 - SSD1303T6R1 pin assignment
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 www..com 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name NC VCC VCOMH IREF D7 D6 D5 D4 D3 D2 D1 D0 E/RD R/W D/C RES# CS# NC BS2 BS1 VDD NC NC NC VBREF RESE FB VDDB GDR VSS NC NC NC COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 Pin no. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin name COM9 COM7 COM5 COM3 COM1 NC NC NC NC NC NC NC SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 Pin no. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin name SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 Pin no. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin name SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 NC NC NC NC NC NC NC NC NC NC NC COM0 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 Pin no. 241 242 243 244 245 246 247 248 249 Pin name COM50 COM52 COM54 COM56 COM58 COM60 COM62 NC NC
Solomon Systech
May 2005
P 44/56
Rev 1.7
SSD1303
SSD1303T6R1 TAB Package Dimensions
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T6 03 13 SD S
SSD1303
Rev 1.7
P 45/56
May 2005
Solomon Systech
www..com
Solomon Systech
May 2005
P 46/56
Rev 1.7
SSD1303
16 SSD1303T8R1 PACKAGE DETAILS
SSD1303T8R1 Pin Assignment
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Remark: Use internal clock VREF is connected to VCC Support MCU interface: 8-bit 6800/8080 parallel interface and SPI VSSB, BGGND are connected to VSS BS0 is connected to VSS
SSD1303
Rev 1.7
P 47/56
May 2005
Solomon Systech
Table 15 - SSD1303T8R1 pin assignment
Pin no.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 www..com 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pin name
NC VSS GDR VDDB FB RESE VBREF GP0 GP1 NC VDD1 BS1 BS2 NC CS# RES# D/C R/W E/RD D0 D1 D2 D3 D4 D5 D6 D7 IREF VCOMH VCC NC NC NC COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10
Pin no.
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pin name
COM8 COM6 COM4 COM2 COM0 NC NC NC NC NC NC NC NC
Pin no.
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46
Pin name SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95
NC NC NC NC NC NC NC NC COM1 COM3 COM5
Pin no.
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211
Pin name
COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 NC NC
Solomon Systech
May 2005
P 48/56
Rev 1.7
SSD1303
SSD1303T8R1 TAB Package Dimensions
www..com
SSD1303
Rev 1.7
P 49/56
May 2005
Solomon Systech
www..com
Solomon Systech
May 2005
P 50/56
Rev 1.7
SSD1303
17 SSD1303T9R1 PACKAGE DETAILS
SSD1303T9R1 Pin Assignment
Figure 16 - SSD1303T9R1 pin assignment (Copper view)
www..com
Remark: Use internal clock VREF is connected to VCC Support MCU interface: 8-bit 6800/8080 parallel interface and SPI VSSB, BGGND are connected to VSS BS0 is connected to VSS
SSD1303
Rev 1.7
P 51/56
May 2005
Solomon Systech
Table 16 - SSD1303T9R1 pin assignment
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 www..com 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name NC VCC VCOMH IREF D7 D6 D5 D4 D3 D2 D1 D0 E R/W D/C RES CS# NC BS2 BS1 VDD1 NC GPIO1 GPIO0 VBREF RESE FB VDDB GDR VSS NC NC NC COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin name COM9 COM7 COM5 COM3 COM1 NC NC NC NC NC NC NC NC SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin name SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 NC NC NC NC NC NC NC NC COM0 COM2 COM4 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 Pin name COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 NC NC
Solomon Systech
May 2005
P 52/56
Rev 1.7
SSD1303
SSD1303T9R1 TAB Package Dimensions
www..com
S
3 30 D1 S
T9
SSD1303
Rev 1.7
P 53/56
May 2005
Solomon Systech
www..com
Solomon Systech
May 2005
P 54/56
Rev 1.7
SSD1303
18 SSD1303Z PACKAGE DETAILS
DIE TRAY DIMENSIONS
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SSD1303
Rev 1.7
P 55/56
May 2005
Solomon Systech
www..com
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
http://www.solomon-systech.com
Solomon Systech
May 2005
P 56/56
Rev 1.7
SSD1303

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