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SPRC205A/SPRC206A
5-Function Remote Control Encoder/Decoder
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Preliminary
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written approval of Sunplus.
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of patent or other rights
and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to obtain the of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support devices/ systems or
aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express
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1. GENERAL DESCRIPTION
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SPRC205A/SPRC206A
FIVE FUNCTIONS REMOTE CONTROL ENCODER/DECODER PAIRS
2. FEATURES
Operating voltage 2.2V - 5.5V operation Built-in R-oscillator (a 5% resistor required) Low standby and operating current ISTBY,SPRC205A < 1.0A, R-oscillator stops IOPERATE,SPRC205A < 15mA, R-oscillator free run, crystal & PA on IOPERATE,SPRC206A < 100A, R-oscillator free run Built-in power on reset Built-in Crystal & PA in SPRC205A 5-function I/O pins 2^5 = 32 encoding in SPRC205A The SPRC206A is a remote control decoder, which decodes the serial bit-stream data received from the SPRC205A and interprets the 5-line information as 5-bit output data to control the corresponding external component. received. With SUNPLUS state-of-the-art technology and strong support, SPRC205A and SPRC206A are the simplest and most suitable products for your RC products. The SPRC206A will be activated only when two consecutive and equal frames are Variable frame rates controlled by external resistor
encoder/decoder in remote control (RC) applications. The SPRC205A, a RC encoder, is able to encode five lines of binary information into a serial bit-stream data. When any of the 5-line information is activated, built-in crystal oscillator and power amplifier will be enabled to deliver the encoded bit-stream data. After the 5-line information becomes inactive, the SPRC205A will transmit additional fifteen data frames to increase transmission reliability.
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These two devices are especially designed is use as paired
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3. BLOCK DIAGRAM
SPRC205A VDD
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R-OSC
Divide/64
Divider/4
ROSC
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DI0 . . . DI4
. . .
Data Latch
Pattern Gen
Crystal & PA
OSCI OSCO RFO DOUT
VSS
SPRC206A
ROSOUT
VDD DO0 DO4
ROSC IN1 OUT1 DIN IN2 OUT2
R-OSC
Clock Recovery
Error Processing
De-glitch
OverSampling
Frame Extractor
Power-on reset
8bit CKRC_CNT
4bit SYM_CNT
7bit BITCNT
VSS
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4.1.1. SPRC205A
Mnemonic DI0 DI1 DI2 DI3 DI4 DOUT OSCI OSCO RFO ROSC VDD VSS Type I PIN No. 2 8 9 11 12 7 3 4 5 10 1 6 Serial bit-stream data output; connected a capacitor of 10nF to VSS to reduce RF spurious. Crystal oscillator input pin Crystal oscillator output pin Power Amplifier output pin. The waveform do not exceed 9Vpp. R-oscillator input, connected to VDD through a resistor. Power voltage input Power ground input 5-function parallel data input Description
4.1.2. SPRC206A
Mnemonic DO0 DO1 DO2 DO3 DO4 DIN ROSC ROSCOUT IN1 IN2 OUT1 OUT2 VDD VSS I I O I I O O P P Type I PIN No. 5 6 8 9 10 4 2 3 11 12 13 14 7 1 Power voltage input Power ground input Inverter output pins Serial bit-stream data input R-oscillator input, connected to VDD through a resistor. R-oscillator clock output Inverter input pins 5-function parallel data output Description
Legend: I = Input, O = Output, P = Power
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SPRC205A/SPRC206A
4. SIGNAL DESCRIPTIONS
4.1. PIN Description
O I
O O I P P
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4.2.2. SPRC206A - PDIP 14
4.2. PIN Configuration
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4.2.1. SPRC205A - PDIP 14
VDD DI0
1 2 3 4 5 6 7
14 13 12 11 10 9 8
DI4 DI3 ROSC DI2 DI1 DOUT NC
VSS ROSC ROSCOUT DIN DO0 DO1 VDD
1 2 3 4 5 6 7
14 13 12 11 10 9 8
OUT2 IN2 OUT1 IN1 DO4 DO3 DO2
OSCO RFO
NC
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OSCI VSS
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5. FUNCTIONAL DESCRIPTIONS
5.1. Frame Format
Preamble P P P P PO A/I E A/I D0 A/I D1 A/I D2 A/I D3 A/I D4 A/I
P
P
Preamble field: 6 preamble fields PO field: Even parity check field E field: Frame polarity indication field; frames are transmitted in positive/negative sequence. Data field: 5 data fields P pattern: encoded as 101 I pattern: encoded as 110
5.2. Operation
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A pattern: encoded as 100
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The SPRC205A encodes 5-function information into 2 series of bit-stream data and transmits the encoded data stream via RFO when any of the 5-function I/Os is activated. The cycle will repeat until all 5-function I/Os become inactive. After these 5-function I/Os
5
become inactive, SPRC205A will transmit another 15 all-zero frames to inform SPRC206A returning to disabled state. transmitting timing is shown as follows: The
DI[4:0]
1F
05
1F
DOUT
...
... 15 Frames
The SPRC206A is able to receive serial bit-stream data transmitted from SPRC205A and decode the data fields as 5-bits data output. Any signal on DIN pin will activate SPRC206A to decode the incoming data. When SPRC206A receives two consecutive,
correct and equal frames, DO[4:0] is able to control the external component. The DO[1,0] and DO[3:2] are exclusive to each other; that is, DO[1:0] and DO[3:2] cannot be activated at the same time. The receiving timing is shown below:
DIN
...
...
DI[4:0]
00
0A
15
1F
DI[4:0]
00
0A
15
10
2 Frames
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5.3. Decoder Flow Chart
Power On
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STANDBY
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Preamble Check
YES
NO
Count error frame
Error frame >=3 ?
YES
NO
Symbol Check
YES
NO
Disable Data output & VT
Store 5bits data
NO
Match Previous stored data ?
YES
Latch data output
After power on, it is reset at STANDBY state. When the signal on DIN is received by SPRC206A, it will check the incoming data frame structure. If preamble or data field errors occur, it will back to STANDBY state to check the next frame. If the receiving frame structure passes the preamble and symbol checks, the 5-bit data is stored and then compared to the previous stored 5-bits data. If the present data matches the previous data, DO[4:0] is active and it is back to STANDBY and ready to check the next frame.
In addition, the SPRC206A built-in a Clock Recovery block to automatically adjust the ratio of data rate to clock rate. The only limitation is using a 5% accuracy resistor is required in SPRC205A and SPRC206A.
5.5. Super Regeneration Amplifier
The SPRC206A features two inverter inputs and outputs as pins. The two inverters can be used for amplifier of the Super-Regeneration RF receiver data output. Users can change
5.4. R-oscillator
Both SPRC205A and SPRC206A have built in R-oscillator. Users need only one resistor (or a capacitor if needed) to implement the clock input and to change the frame rate by replacing different resistor. Frame rate = FOSC / 64 / 33
the two inverters' gain by adjusting external resistor and capacitor.
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Symbol V+ VIN TA TSTO Ratings < 7.0V -0.5V to V+ + 0.5V -20 to +60 -50 to +150
DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics.
6.2. DC Characteristics of SPRC205A (VDD = 3.0V, TA = 25)
Characteristics Operating Voltage RFO Maximum Waveform Operating Current Standby Current Input High level Input Low level Output High Current Output Sink Current DI[4:0] pull high resistor OSC Frequency Symbol VDD VRFO IOP ISTBY,SPRC205A VIH VIL IOH IOL RDI FOSC Limit Min. 2.2 2.0 Typ. -6.0 6.0 200 128 Max. 5.5 9 15 1.0 0.8 Unit V Vpp mA A V V mA mA K KHz Test Condition R-OSC resistor = 200K VDD = 4.5V, Inductor load. R-OSC resistor = 200K Crystal & PA on (6.0dBm) R-OSC disable VDD = 3.0V VDD = 3.0V VDD = 3.0V, VOH = 2.4V VDD = 3.0V, VOL = 0.4V VDD = 3.0V ROSC = 200K @ VDD from 2.0V - 5.5V
6.3. DC Characteristics of SPRC206A (VDD = 3.0V, TA = 25)
Characteristics Operating Voltage Operating Current Input High level Input Low level Output High Current (DO) Output Sink Current (DO) DIN pull low resistor OSC Frequency Maximum tolerance data rate Minimum tolerance data rate Maximum rejection data rate Minimum rejection data rate Symbol VDD IOP VIH VIL IOH IOL RDIN FOSC FTOR,MAX FTOR,MIN FREJ,MAX FREJ,MIN Limit Min. 2.0 2.0 2.4 2.8 Typ. -6.0 6.0 200 128 Max. 5.5 100 0.8 1.6 1.3 Unit V A V V mA mA K KHz KHz KHz KHz KHz Test Condition R-OSC resistor = 200K R-OSC resistor = 200K VDD = 3.0V VDD = 3.0V VDD = 3.0V, VOH = 2.4V VDD = 3.0V, VOL = 0.4V VDD = 3.0V ROSC = 200K @ VDD from 2.0V - 5.5V FOSC = 128KHz FOSC = 128KHz FOSC = 128KHz FOSC = 128KHz
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6.6. The Relationships of the VDD and the Output Power
Output Power dBm
6.4. The Relationships of the ROSC and the FOSC
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6.4.1. VDD = 3.0V, TA = 25
Frosc vs. Rosc
2500 2000 1500 1000
20 15 10 5
Frequency = 27.145 MHz RF Load = 50 Ohm
Frosc (KHz)
500 0
0
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200
400 Rosc (Kohm)
600
800
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0 -5 -10
6.5. The Relationships of the VDD and the FOSC
Frosc vs. VDD 500 400 Frosc(KHz) 300 200 100 0 0 1 2 3 VDD(V) 4 5 6 7
2
2.5
3
3.5
4
VDD, V
4.5
5
5.5
6
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7. APPLICATION CIRCUITS
7.1. SPRC205A Application Circuit
VDD VDD VDD
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F L
B
DI0 DI1 DI2 DI3 DI4
ROSC
DOUT RFO OSCI
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R
Ground
OSCO
SPRC205A
SPRC205A Encoder application circuit
7.2. SPRC206A Application Circuit
VDD
9V ROSCOUT ROSC F-B Motor DO0 DO1 RFI DO DIN DO2 DO3 DO4 RF module IN1 SPRC206A OUT1 IN2 OUT2 9V M
9V L-R Motor
M 9V
SPRC206A Decoder application circuit
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7.3. SPRC206A Application Circuit (with Super Regeneration RF)
VDD
RFI
Super-regeneration RF module DO
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VBAT F-B Motor DO0 DO1 DO2 IN1 SPRC206A DO3 DO4 OUT1 M
VBAT L-R Motor
ROSCOUT
ROSC
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R1
C1
M
R2
C2
IN2
OUT2
DIN
R3
R4
R5
C3
Ground SPRC206A Decoder application circuit
7.4. Reference Design
For general application, "DI0" is defined as "Forward". "DI1" is "Backward"', "DI2" as `Left', "DI3" as "Right", and "DI4" for "Turbo" or other functions.
7.5. 27MHz Transmitter
The standby current is estimated less than 1.0A if no button pressed. When a button is pressed, the SPRC205A wakes up and transmits the encoded RF signal.
VDD S1 R1 18
Forward
3.0V DC J1
1 2
VDD C2 27.195MHz
1
C1 U1 S2
VDD DI4 12
104 Turbo S3 Right R3 VDD 200k R5 S4 270 Left Backward
R2 22p C3 10M
X1
2
DIO
DI3
11
3
47p C4 0.1u 18 C5 0.1u
OSCI
ROSC
10
L1 L2
1uH
4 OSCO DI2 9
R4 VDD ANTENNA
S5
5
1
D1 LED
1uH
6
VSS
DOUT
7
C7 100p 3.9uH 50 Ohm Antenna J2
1 2
C8 10n SPRC205 COB
L3 470nH C9 200p C10 100p
TP1 TxData
Matching to 50 Ohm load
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1
2
C11 47p
RFO
DI1
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7.7. RF Output Matching Example
27MHz Matching Circuit
50 Ohm Antenna J2
1 2
7.6. Crystal Oscillator Example
For over tone type crystal, a LC tank circuit is necessary to prevent base tone oscillating.
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L3 470nH C9 200p C10 100p
Fx
1
, Fx crystal frequency, L L1, C C3
2 LC
Matching to 50 Ohm load
27MHz Oscillator Circuit
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C2
27.195MHz
OSCI Over Tone Crystal OSCO
C2
27.195MHz
OSCI
22p C3 47p C4 0.1u
R2 10M
X1
22p C3 22p
R2
X1
10M
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Fundamental Crystal OSCO
40MHz Matching Circuit
50 Ohm Antenna J2
1 2
L3 220nH C9 180p C10 100p
L1 1uH
Matching to 50 Ohm load
40MHz Oscillator Circuit
C2 C2 40.68MHz 40.68MHz
OSCI Over Tone Crystal OSCO
OSCI Fundamental Crystal OSCO
22p C3 33p C4 0.1u
R2 10M
X1
22p C3 22p
R2 10M
X1
49MHz Matching Circuit
50 Ohm Antenna J2
1 2
L3 220nH C9 120p C10 68p
L1 560nH
Matching to 50 Ohm load
49MHz Oscillator Circuit
C2 49.86MHz
OSCI Over Tone Crystal OSCO
12p C3 27p C4 0.1u L1
R2 10M
X1
470nH
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VDD S1 Forward VDD BT1 3V C2 27.195MHz
1
7.8. RF Harmonic and Bandwidth
R1 0
C1 U1 S2
VDD DI4 12
104 Switch S3 Right R3 200k
22p C3 47p C4 0.1u C5 0.1u
R2 1M
X1
2
DIO
DI3
11
ANTENNA
3
OSCI
ROSC
10
L1 L2
1uH
4 OSCO DI2 9
S4 Left S5
5 RFO DI1 8
R4 0
470nH
VDD C101 68p
Backward
6
VSS
DOUT
7
4.7uH
L3
470nH C10 200p
47p TP1 TxData
T
C9 100p
1) Ch 1:
2 Volt 10 ns
The RF fundamental power is related to supply voltage, and the harmonic power is, too. R4 and R1 can reduce harmonic if it works at higher voltage (ex 5.5V). C8 is used to reduce the RF bandwidth (for 27MHz, 40MHz, 49MHz to meet band edge limitation). The following table shows RFO (pin5 of SPRC205A) waveform by various conditions Note: the antenna loading is 50 Ohm Test condition VDD=3.0V, R4=0, R1=0 Perfect wavefrom. RFO waveform
1
C7
SPRC205A
C8 10n
T
1) Ch 1:
2 Volt 10 ns
2v/, 10ns/
VDD=4.0V, R4=0, R1=0 Higher the supply voltage, higher the fundamental and harmonic power
T
1) Ch 1:
2 Volt 10 ns
2v/, 10ns/
VDD=4.0V, R4=0, R1=330 Ohm Add R1 to lower supply voltage to reduce harmonic
T
1) Ch 1:
2 Volt 10 ns
2v/, 10ns/
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Test condition RFO waveform
VDD=5.5V, R4=0, R1=0 Ohm If the peak voltage of RFO exceeds 9V, RFO breaks down. It gets lower fundamental and higher harmonic.
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1) Ch 1:
2 Volt 10 ns
2v/, 10ns/
VDD=5.5V, R4=100 Ohm, R1=330 Ohm Use R4 to limit the RFO waveform.
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1) Ch 1:
2 Volt 10 ns
2v/, 10ns/
7.9. 27MHz Super Regenerative Receiver
1
R1 3.3k
2
U1
1 VSS OUT2 14
1
R2 3.9M
2
2
1
R4 C4 100p Forward Backward 200k
C2
INDUCTOR L1 104
2 1 3
1
3
ROSCout OUT1
12
1
C3 12p R6
2
ROSC
IN2
13
R3 100k
1
E1 ANTENNA
2
C5
4 DIN IN1 11
R5 3.9M
100p
2
2
5
DO0
DO4
10
6
DO1
DO3
9
Turbo Right Left
8.2k
220k
3
Q1 C945
3.3k
104
R7
2
1
C6 R8
C7 45p
2
6V SPRC206 COB
C9 103
C10 103
C11 4.7u
2
1
7
VDD
DO2
8
11
C8 56p
1
L2 3.3u
1
2
100 C13 100u
2
C12 3.3n 47u R11 430
2
R9
1
VDD
2
R10
1
1
2
D1 3.3V
2
100u
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Please contact Sunplus sales representatives for more information.
8.2. Ordering Information
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8. PACKAGE/PAD LOCATIONS
8.1. PAD Assignment and Locations
Product Number
Package Type Chip form Chip form Package form - PDIP 14 Package form - PDIP 14
SPRC205A - C SPRC206A - C SPRC205A - PD02 SPRC206A - PD02
8.3. Package Information
8.3.1. SPRC205A - PDIP 14
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D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-14-300
e Body Size D1 E1 A2
b Lead Size b c
182
L1
e
75010 2504 1305 1305
10Typ 100Typ
All units are in mil. 1mil = 25.4m
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8.3.2. SPRC206A - PDIP 14
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D1
A2
c
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L1
e Body Size D1 E1 A2
b Lead Size b c
182
L1
e
75010 2504 1305 1305
10Typ 100Typ
D1 E1 A2 L1 b c e
Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-14-300
All units are in mil. 1mil = 25.4m
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Package PDIP
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8.4. Storage Condition and Period for Package
Moisture sensitivity level LEVEL 3 (Reference) Max. Reflow temperature 220 +5/-0 (Reference) Floor life storage condition N/A Dry pack No
Note1: Please refer to IPC/JEDEC standard J-STD-020A and EIA JEDEC stand JFSD22-A112 Note2: or refer to the "CAUTION Note" on dry pack bag.
8.5. Recommended SMT Temperature Profile
This "Recommended" temperature profile is a rough guideline for SMT process reference. Most of SUNPLUS leadframe base product choice Matte Tin and Sn/Bi for plating recipe. For PPF(Pre-Plated Frame) product with 63/37 solder paste, we recommend 240~245 for peak temperature.
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The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this
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document are for reference purposes only.
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9. DISCLAIMER
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10. REVISION HISTORY
Date Revision # 0.3 Description 1. Modify Frame rate: from Fosc/64/54 to Fosc/64/33 in section 5.4 2. Add package storage in sections 8.4 and 8.5 0.2 1. Add RFO limit, Bandwidth, Harmonic characteristic. 2. Remove "8. PACKAGE/PAD LOCATIONS" Original 19 Page 8 18
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DEC. 03, 2003
SEP. 18, 2002
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