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PAS5101PE Specification
PAS5101PE CMOS 1.3MEGA DIGITAL IMAGE SESNSOR
General Description
The PAS5101PE is a highly integrated CMOS active-pixel image sensor that has resolution of 1280( H ) x 1024 ( V ). To have an excellent image quality, the PAS5101PE output 10-bits RGB raw data though a parallel data bus. It is available in 48-pin LCC. The PAS5101PE can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset correction DAC, programmable gain control, 10-bits ADC, 10-bits output companding, interpolated subsampling and defect compensation.
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Features
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Key Specification Supply Voltage Resolution Array Diagonal Pixel Size Max. Frame Rate Max. System Clock Max. Pixel Clock Color Filter Exposure Time Scan Mode Sensitivity S/N Ratio Chief Ray Angle Package Type 2.5v ~ 3.3v 1280 ( H ) x 1024 ( V ) 5.9mm ( ~1/3" Optic ) 3.6m x 3.6m ~15 fps @ 1.3Mega Up to 48MHz Up to 24MHz RGB Bayer Pattern ~ Frame time to Line time Progressive TBD TBD 20 ~ 24 48-pin LCC
1.3Mega resolution, ~1/3" Lens. Bayer RGB color filter array. 10-bits parallel RGB raw data output. On-Chip 10-bits pipeline A/D converter. On-Chip programmable gain amplifier 4-bits color gain amplifier. 4-bits global gain amplifier. Digital gain stage. Continuous variable frame time. Continuous variable exposure time. I2CTM interface. 20mA power dissipation ( 15fps / 2.5v ). < 10uA low power-down dissipation. Window-of-Interest (WOI). Sub-sampling. Defect compensation. Lens shading compensation.
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PAS5101PE Specification
1. Pin Assignment
SYSCLK VDDMD PXCLK RESET VSSD PX7 NC NC VSYNC PX9 NC
8
18
17
16
15
14
13
12
11
10
9
NC
7
NC NC NC PX8 VDDD
19 20 21 22 23 24
6 5 4 3
NC NC HSYNC NC NC VDDMA NC VREF VDDA PWDN NC NC
PAS5101PE
-- Top View --
2 1 48 47 46 45 44 43
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PX6 PX0 PX5 PX1 NC NC NC
25
26 27 28 29 30
31
32
33
34
35
36
37
38
39
40
41
42
VSSA
SDA
PX4
PX3
SCL
PX2
NC
NC
NC
NC
Figure 1.1 Shows the PAS5101PE pin diagram
NC
NC
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PAS5101PE Specification
Pin No. 1 2-3 4 5-8 9 10 11 12
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Name VDDMA NC HSYNC NC VSYNC VDDMD PXCLK RESET SYSCLK PX9 VSSD PX7 NC PX8 VDDD PX6 PX0 PX5 PX1 NC PX4 PX3 PX2 SCL SDA NC VSSA NC PWDN VDDA VREF NC
Type PWR
Description Analog main power, 2.5V.
OUT
Horizontal synchronization signal.
OUT PWR OUT IN IN OUT PWR OUT
Vertical synchronization signal. Digital main power, 2.5~3.3V. Pixel clock output. Resets all registers to default values ( chip reset if high .) Master clock input. Digital data out. Digital ground. Digital data out.
14 15 16 17-21 22 23 24 25 26 27 28-32 33 34 35 36 37 38 39 40-44 45 46 47 48
OUT PWR OUT OUT OUT OUT
Digital data out. Nc, Internal Regulator 1.8V Digital data out. Digital data out. Digital data out. Digital data out.
OUT OUT OUT IN I/O
Digital data out. Digital data out. Digital data out. I2C clock. I2C data. Internal pull high resister is 10K.
GND
Analog ground.
IN PWR ANA
Power Down (chip power down if high ). Analog power, 2.5V. Internal voltage reference.
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PAS5101PE Specification
2. Sensor Array Format & Output Timing
2.1. Physical Sensor Array Format
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Figure 2.1 Physical Sensor Array Format
2.2. Output Timing
1.3Mega mode ( 1288 x 1032 ) pixel readout: H_Start[9:0] = 0, LPF[7:0] = 1035, V_Start[8:0] = 0, Nov_Size_By4[7:0] = 63, H_Size[9:0] = 1287, V_Size[8:0]= 1035,
Figure 2.2 Inter-line timing
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PAS5101PE Specification
Figure 2.3 Inter-frame timing
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Figure 2.4 Inter-frame timing @ Dark masked
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PAS5101PE Specification
3. Block Diagram & Function Description
3.1. Block Diagram
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Figure 3.1 Shows the PAS5101PE sensor block diagram The PAS5101PE is a 1/3" CMOS imaging sensor with 1280 ( H ) x 1024 ( V ) physical pixels. The active region of sensor array is 1288 ( H ) x 1032 ( V ) as shown in Figure 3.1. The sensor array is cover with Bayer pattern color filters and -lens. The first pixel location ( 0,0 ) is programmable in 2 direction ( X and Y ) and the default value is at the left-down side of sensor array. After a programmable exposure time, the image is sampled first with CDS ( Correlated Double Sampling ) block to improve S/N ration and reduce fixed pattern noise. Three analog gain stages are implemented before signal transferred by the 10-bits A/D converter. The front gain stage ( FG ) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The programmable color gain stage ( CG ) is used to balance the luminance response difference between B/G/R. The global gain stage ( GG ) is programmed to adapt the gain to the image luminance. The fine gained signal will be digitized by the on-chip 10-bits A/D converter. After the image data has been digitized, further alteration to the signal can be applied before the data is output.
3.2. Defect Compensation
The defect compensation block can detect the possible defect pixel and replace it with average output of like-colored pixels on either side of defective pixel. There is no limitation in the capability of defect number. This function is also Enable / Disable by user.
3.3. Companding Curves
The companding function is used to simulate the gamma curve and do non-linear transformation before the data is output. There are 4 curves selected by setting register Compand_Sel as shown in Figure 3.2 and this function is also Enable / Disable by user.
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PAS5101PE Specification
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Figure 3.2 Companding curves program by Compand_EnH and Compand_Sel
3.4. Power Down Mode
The PAS5101PE can be power down by setting register "SW_PwrDn" or by enable PWDN pin. PAS5101PE supports two power down modes : Software Power Down : Set register "SW_PwrDn" = 0x01 to power down all the internal block except I2CTM. Hardware Power Down : Pull PWDN pin to high to power down the chip. The chip will go into standby mode.
3.5. Reset Mode
The PAS5101PE can be reset by setting "SW_Reset" or by enable Reset pin. PAS5101PE supports two reset modes : Software Reset : Set register "SW_Reset" = 0x01 to reset all the I2CTM registers. It's only reset the register value not reset full chip. HardwareReset : Pull Reset pin to high to reset the full chip.
3.6. Window-of-Interest ( WOI )
Users are allowed to define window size as well as window location in PAS5101PE. The location of window can be anywhere in the pixel array. Window size and window location is defined by register "H_Start", "V_Start", "V_Size" and "H_Size"; The "H_Start" defines the starting column while "V_Start" defines the starting rom of the window; The "H_Size" define the column width of the window and "V_Size" defines the row depth of the window.
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PAS5101PE Specification
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Figure 3.3
3.7.1. Output timing of WOI
Hardware windowing VGA ( 640x480 ) pixels readout ( With 4 dark lines ): H_Start[9:0] = 0, LPF[7:0] = 483, V_Start[8:0] = 0, Nov_Size_By4[7:0] = 63, H_Size[9:0] = 639, V_Size[8:0]= 483,
Figure 3.4 Inter-line timing of W.O.I
Figure 3.5 Inter-frame timing of W.O.I
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PAS5101PE Specification
3.7. Sub-Sampling
PAS5101PE can be programmed to output image in VGA QVGA and QQVGA size. In the VGA subsampling mode, both vertical and horizontal pixels are sub-sampling at 1/2; In QVGA sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/4; While in QQVGA sub-sampling mode, subsampling at 1/8. By programming Skip_Analog and Skip_Digital, The maximum sub-sampling rate is 1/32 ( Skip_Analog + Skip_Digital ).
3.7.1. Skip_Analog
Sub-sampling ( Skip_Analog ) to VGA ( 640x480 ) pixels readout ( With 4 dark lines ): H_Start[9:0] = 0,
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V_Start[8:0] = 0,
H_Size[9:0] = 1287,
V_Size[8:0]= 1035,
LPF[7:0] = 519,
Nov_Size_By4[7:0] = 63, Skip_Analog = 1 ( sub-sampling 1/2 )
Figure 3.6 Valid pixel = ( H_Size + 1 ) / Skip_Analog = 1288 / 2 = 644 Valid line = (((( V_Siez + 1 ) - 4 ) / Skip_Analog ) + 4) = (((( 1035 + 1 ) - 4 ) / 2 ) + 4 ) = 520
Figure 3.7 Inter-line timing of W.O.I
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PAS5101PE Specification
Figure 3.8 Inter-frame timing of W.O.I
3.7.2. www..comSkip_Digital
Sub-sampling ( Skip_Digital ) to VGA ( 640x480 ) pixels readout ( With 4 dark lines ): H_Start[9:0] = 0, LPF[7:0] = 1036, V_Start[8:0] = 0, H_Size[9:0] = 1287, V_Size[8:0]= 1035, Nov_Size_By4[7:0] = 63, Skip_Digital = 1
Valid pixel = ( H_Size + 1 ) / Skip_Digital = 1288 / 2 = 644 Valid line = ( V_Siez + 1 ) / Skip_Digital = ( 1035 + 1 ) / 2 = 518
Figure 3.9 Inter-line timing
Figure 3.10 Inter-frame timing
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PAS5101PE Specification
4. I2CTM Bus
PAS5101PE supports I2C bus transfer protocol and is acting as slave device. The 7 bits unique slave address is "1000000" and supports receiving / transmitting speed up to 400KHz.
4.1. I2C Bus Overview
Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. Only the master can initiates a transfer ( start ), generates clock signals, and terminates a transfer ( stop ).
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Start and stop condition : A high to low transition of the SDA line while SCA is high defines a start condition. A low to high transition of the SDA line while SCA is high defines a stop condition. Please refer to Figure 4.1. Valid data : The data on the SDA line must be stable during the high period of the SCA clock. Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the first byte. Please refer to Figure 4.2. Both the master and slave can transmit and receive data from the bus. Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle.
Figure 4.1 Start and Stop conditions
Figure 4.2 Valid Data
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PAS5101PE Specification
4.2. Data Transfer Format 4.2.1. Master transmits data to salve ( write cycle )
S : Start. A : Acknowledge by salve. P : Stop. RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 - Read cycle, RW = 0 - Write cycle.
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SUBADDRESS : The address values of PAS5101PE internal control registers. ( Please refer to PAS5101PE register description )
During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS5101PE ) issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the PAS5101PE acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS5101PE control register ( address was assigned by 2nd byte ). After PAS5101PE issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS5101PE sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAS5101PE can be programming via this way.
4.2.2. Slave transmits data to master ( read cycle )
The sub-address was taken from previous write cycle. The sub-address is automatically increment after each byte read. Am : Acknowledge by master. Note there is no acknowledgment from master after last byte read.
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PAS5101PE Specification
During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS5101PE. The 8 bits data was read from PAS5101PE internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS5101PE place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS5101PE ) must releases SDA line to master to generate STOP condition.
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4.3. I2CTM Bus Timing
4.4. I2CTM Bus Timing Specification
Parameter SCL clock frequency. Hold time ( repeated ) Start condition. After this period, the first clock pulse is generated. Low period of the SCL clock. High period of the SCL clock. Set-up time for a repeated START condition. Symbol fscl tHD:STA tLOW tHIGH tSU;STA Standard Mode Min. 10 4.0 4.7 0.75 4.7 Max 400 Unit KHz s s s s 13
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PAS5101PE Specification
Data hold time. For I2C-bus device. Data set-up time. Rise time of both SDA and SCL signals. Fall time of both SDA and SCL signals. Set-up time for STOP condition. Bus free time between a STOP and START. Capacitive load for each bus line.
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tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL VnH
0 250 30 30 4.0 4.7 1
0.1 VDD
3.45 N.D. N.D. 15 -
s ns ns ( notel ) ns ( notel ) s s pF V V
at LOW level for each connected device. ( Including hysteresis ) Noise margin at HIGH level for each connected device. ( including hysteresis )
0.2 VDD
Note : It depends on the "high" period time of SCL.
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PAS5101PE Specification
5. Specifications
Absolute Maximum Ratings Ambient Storage Temperature VDDD Supply Voltage ( with respect to ground ) VDDA VDDMD VDDMA
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-40 ~ +125 3V 3V 4V 4V -0.3V to VDDMD + 1V +230 2000V
Input / Output Voltage ( with respect to ground ) Lead temperature, Surface-mount process ESD rating, Human Body model
DC Electrical Characteristics ( Ta = 0 ~ 70 ) Symbol VDDA VDDD VDDMD IDD IPWDN Parameter Type : POWER DC supply voltage - Analog DC supply voltage - Digital DC supply voltage - I/O Operating Current ( ~ 15fps / 2.5v ) Power Down Current Type : IN & I/O Reset and System Clock VIH VIL CIN Input Voltage HIGH Input Voltage LOW Input Capacitor 0.7 x VDDMD 0.3 x VDDMD 10 V V pF 2.4 20 10 2.4 2.5 1.8 3.3 2.6 V V V mA A Min. Typ. Max. Unit
Type : OUT & I/O for PX 0 : 7, PXCLK, H/VSYNC & SDA, load 10pF, 1.2K, 2.5V VOH VOL Output Voltage HIGH Output Voltage LOW 0.9 x VDDMD 0.1 x VDDMD V V
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PAS5101PE Specification
AC Operating Condition Symbol Sysclk Pxclk Parameter Master clock frequency Pixel clock output frequency Min. Typ. Max. 48 24 Unit MHz MHz
Sensor Characteristics Parameter
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Typ. TBD TBD TBD Operation Stable Image -10 ~ +70 0 ~ +50
Unit V/Lux-sec dB dB
Sensitivity Signal to Noise Ratio Dynamic Range
Temperature Range
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6.
C2
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VREF 0.1uF C4 VDDMA 8 7 U1 6 5 AGND 4 3 2 1 48 47 46 45 PWDN 44 43 DGND VDDMA VREF VDDMA AGND HSY NC JP1 0.1uF
DGND
PXCLK
PX7
PX9
SYSCLK
RESET
18
17
16
15
14
13
12
11
10 9 NC
NC
NC
PX7
VSSD
PXCLK
RESET
29 NC NC NC NC NC
NC
30 PX4 PX3 PX2 SCL SDA NC VSSA
NC
NC
31
32
NC
33
34
35
36
37
38
40
41
42
PX4
PX3
PX2
SCL
SDA
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VDDMD VSYNC PX9 NC NC NC HSY NC NC NC SYSCLK VDDMD VSYNC
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AGND 39
VDDMD PX9 SY SCLK PX8 DGND PX7 PXCLK PX6 PX2 PX5 PX3 PX4 PX1 PX0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AGND SDA VDDMA SCL RESET VSY NC PWDN HSY NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PAS5101PE Specification
v1.0 2005/4/27
Notes: VDDMD is 2.5V ~ 3.3V sensor IO power. VDDMA is 2.5V sensor analog power. C1 should close to sensor VDDA and AGND. C2 should close to sensor VREF and AGND.
CONN FLEX 24/SM
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19
NC
20
NC
21
NC
Reference Circuit Schematic
PX8
22
PX8
23
VDDD
PX6
24
PX6 NC VREF VDDA PWDN
PAS5101PE
VDDMA
PX0
25
PX0
PX5
26
PX5
PX1
27
PX1
28
NC
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PAS5101PE Specification
7. Package Information
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PAS5101PE Specification
8. Reflow Profile for Non Lead-Free
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PAS5101PE Specification
9. Lens & Holder
9.1. LarGan 40-900L 9.2. LarGan 40-519C 9.3. MaxEmil SS-4828GA 9.4. PEH-0116-03AA
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