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GS74108TP/J SOJ, TSOP Commercial Temp Industrial Temp Features
* Fast access time: 8, 10, 12, 15ns * CMOS low power operation: 150/125/110/90 mA at min. cycle time. * Single 3.3V 0.3V power supply * All inputs and outputs are TTL compatible * Fully static operation * Industrial Temperature Option: -40 to 85C * Package line up J: 400mil, 36 pin SOJ package TP: 400mil, 44 pin TSOP Type II package
512K x 8 4Mb Asynchronous SRAM
SOJ 512K x 8 Pin Configuration
A4 A3 A2 A1 A0 CE DQ1 DQ2 VDD VSS DQ3 DQ4 WE A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
8, 10, 12, 15ns 3.3V VDD Center VDD & VSS
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
NC A5 A6 A7 A8 OE DQ8 DQ7 VSS VDD DQ6 DQ5 A9 A10 A11 A12 A18 NC
36 pin 400mil SOJ
Description
The GS74108 is a high speed CMOS static RAM organized as 524,288-words by 8-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3V power supply and all inputs and outputs are TTL compatible. The GS74108 is available in 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions Symbol
A0 to A18 DQ1 to DQ8 CE WE OE VDD VSS NC
Description
Address input Data input/output Chip enable input Write enable input Output enable input +3.3V power supply Ground No connect
A13
Rev: 1.06 7/2000
1/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
TSOP-II 512K x 8 Pin Configuration
NC NC A4 A3 A2 A1 A0 CE DQ1 DQ2 VDD VSS DQ3 DQ4 WE A17 A16 A15 A14 A13 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE DQ8 DQ7 VSS VDD DQ6 DQ5 A9 A10 A11 A12 A18 NC NC NC
44 pin 400mil TSOP II
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A18 CE WE OE
Column Decoder
Control
I/O Buffer
DQ1
DQ8
Rev: 1.06 7/2000
2/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
Truth Table CE
H L L L Note: X: "H" or "L"
OE
X L X H
WE
X H L H
DQ1 to DQ8
Not Selected Read Write High Z
VDD Current
ISB1, ISB2
IDD
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
VDD VIN VOUT PD TSTG
Rating
-0.5 to +4.6 -0.5 to VDD+0.5 ( 4.6V max.) -0.5 to VDD+0.5 ( 4.6V max.) 0.7 -55 to 150
Unit
V V V W
oC
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.06 7/2000
3/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J Recommended Operating Conditions
Parameter
Supply Voltage for -10/12/15 Supply Voltage for -8 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range
Symbol
VDD VDD VIH VIL TAc TAI
Min
3.0 3.135 2.0 -0.3 0 -40
Typ
3.3 3.3 -
Max
3.6 3.6 VDD+0.3 0.8 70 85
Unit
V V V V
o
C C
o
Note: 1. Input overshoot voltage should be less than VDD+2V and not exceed 20ns. 2. Input undershoot voltage should be greater than -2V and not exceed 20ns.
Capacitance
Parameter
Input Capacitance Output Capacitance
Symbol
CIN COUT
Test Condition
VIN=0V VOUT=0V
Max
5 7
Unit
pF pF
Notes: 1. Tested at TA=25C, f=1MHz 2. These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL ILO VOH VOL
Test Conditions
VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = - 4mA ILO = + 4mA
Min
-1uA -1uA 2.4
Max
1uA 1uA
0.4V
Rev: 1.06 7/2000
4/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
Power Supply Currents Parameter Symbol Test Conditions
CE VIL All other inputs VIH or VIL Min. cycle time IOUT = 0 mA CE VIH All other inputs VIH or VIL Min. cycle time CE VDD - 0.2V All other inputs VDD - 0.2V or 0.2V
0 to 70C 8ns 10ns 12ns 15ns 10ns
-40 to 85C 12ns 15ns
Operating Supply Current
IDD
150mA
125mA
110mA
90mA
135mA
120mA
100mA
Standby Current
ISB1
70mA
65mA
60mA
55mA
75mA
70mA
65mA
Standby Current
ISB2
30mA
40mA
AC Test Conditions
Parameter
Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load
Conditions
VIH=2.4V VIL=0.4V tr=1V/ns tf=1V/ns 1.4V 1.4V Fig. 1& 2
Output Load 1
DQ 50 VT=1.4V 30pF1
Output Load 2
3.3V DQ 5pF1 589 434
Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Rev: 1.06 7/2000
5/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J AC Characteristics
Read Cycle Parameter
Read cycle time Address access time Chip enable access time (CE) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Chip disable to output in High Z (CE) Output disable to output in High Z (OE)
Symbol
tRC tAA tAC tOE tOH tLZ* tOLZ* tHZ* tOHZ*
-8 Min
8 ------3 3 0 -----
-10 Max
--8 8 3.5 ------4 3.5
-12 Min
12 ------3 3 0 -----
-15 Min
15 ------3 3 0 -----
Min
10 ------3 3 0 -----
Max
--10 10 4 ------5 4
Max
--12 12 5 ------6 5
Max
--15 15 6 ------7 6
Unit
ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested
Read Cycle 1: CE = OE = VIL, WE = VIH
tRC Address tAA tOH Data Out Previous Data Data valid
Rev: 1.06 7/2000
6/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
Read Cycle 2: WE = VIH
tRC Address tAA CE tAC tLZ OE tOE Data Out tOLZ High impedance
DATA VALID
tHZ
tOHZ
Write Cycle Parameter
Write cycle time Address valid to end of write Chip enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z
Symbol
tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ*
-8 Min
8 5.5 5.5 4 0 5.5 0 0 0 3 ---
-10 Max
--------------------3.5
-12 Min
12 8 8 6 0 8 0 0 0 3 ---
-15 Min
15 10 10 7 0 10 0 0 0 3 ---
Min
10 7 7 5 0 7 0 0 0 3 ---
Max
--------------------4
Max
--------------------5
Max
--------------------6
Unit
ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested
Rev: 1.06 7/2000
7/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
Write Cycle 1: WE control
tWC Address tAW OE tCW CE tAS WE tDW Data In tWHZ Data Out
HIGH IMPEDANCE DATA VALID
tWR
tWP tDH
tWLZ
Write Cycle 2: CE control
tWC Address tAW OE tAS CE tWP WE tDW Data In Data Out
DATA VALID
tWR1
tCW
tDH
HIGH IMPEDANCE
Rev: 1.06 7/2000
8/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
36 Pin SOJ, 400 mil
Dimension in inch Symbol D L c E HE GE A A1 A2 B B1 c e
A
Dimension in mm min 0.66 2.67 0.33 0.61 0.15 nom 2.80 0.43 0.71 0.20 max 3.70 2.92 0.53 0.81 0.30
min 0.026
nom -
max 0.146 -
0.105 0.110 0.115 0.013 0.017 0.021 0.024 0.028 0.032 0.006 0.008 0.012
1
D E e
0.920 0.924 0.929 23.37 23.47 23.60 0.395 0.400 0.405 10.04 10.16 10.28 0.05 9.00 2.08 0o 1.27 9.30 9.60 0.10 10o 0.430 0.435 0.440 10.93 11.05 11.17 0.354 0.366 0.378 0.082 0o 0.004 10o
A
A2
A1
y
B B1
HE Detail A Q GE L y Q
Note: 1. Dimension D& E do not include interlead flash 2. Dimension B1 does not include dambar protrusion / intrusion 3. Controlling dimension: inches
Rev: 1.06 7/2000
9/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
44 Pin, 400 mil TSOP-II Dimension in inch Dimension in mm Symbol min nom max min nom max
A A1 HE
A
44
D
23
c
0.002 0.01 -
-
0.047 -
0.05 0.95 0.25 -
1.00 0.35 0.15
1.20 1.05 0.45 -
E
A2 B c D E e HE L
0.037 0.039 0.041 0.014 0.018 0.006 -
1 A2
e
22 B
0.721 0.725 0.729 18.31 18.41 18.51 0.396 0.400 0.404 10.06 10.16 10.26 0.031 0.40 0
o
0.80 0.50 0.80 -
0.60 0.10 5o
A
0.455 0.463 0.471 11.56 11.76 11.96 0.016 0.020 0.024 0
o
A1
y L1 L
L1 y Q
0.031 -
0.004 5
o
Detail A
Q
Note: 1. Dimension D& E do not include interlead flash 2. Dimension B does not include dambar protrusion / intrusion 3. Controlling dimension: mm
Rev: 1.06 7/2000
10/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J
Ordering Information Part Number*
GS74108TP-8 GS74108TP-10 GS74108TP-12 GS74108TP-15 GS74108TP-8I GS74108TP-10I GS74108TP-12I GS74108TP-15I GS74108J-8 GS74108J-10 GS74108J-12 GS74108J-15 GS74108J-8I GS74108J-10I GS74108J-12I GS74108J-15I
Package
400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ
Access Time
8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns
Temp. Range
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Status
* Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. For example:
GS74108TP-8T
Rev: 1.06 7/2000
11/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108TP/J Revision History
Rev. Code: Old; New
741081.04d 5/1999/741081.05 1/ 2000 GS74108Rev1.05 10/19991/ 2000K;Rev 5 2/2000L
Types of Changes Page #/Revisions/Reason Format or Content
1. Content 1. 2. Page 2/Pins 16 - 20 and 26 - 30 on 44 pin TSOP II Pin Configuration/ Correction. GSI Logo
Format/Content
Rev: 1.06 7/2000
12/12
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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