View SI4133G-X2_192536.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SI4133G-X2
D U A L -B A N D R F S Y N T H E S I Z E R WI T H I N T E G R A T E D V C O S F O R G S M A N D G P R S WI R E L E S S C O M M U N I C A T I O N S
Features
" "
RF1: 900 MHz to 1.8 GHz RF2: 750 MHz to 1.5 GHz 1070.4, 1080, and 1089.6 MHz
! ! ! ! ! ! !
! ! !
IF Synthesizer
"
Integrated VCOs, Loop Filters, Varactors, and Resonators Minimal External Components Required
Applications
!
GSM900, DCS1800, and PCS1900 Cellular Telephones
! !
GPRS Data Terminals HSCSD Data Terminals
S i4 13 3G
!
Dual-Band RF Synthesizers
!
Optimized for Use with Hitachi Bright2+ Transceiver Settling Time < 150 s Low Phase Noise Programmable Power Down Modes 1 A Standby Current 18 mA Typical Supply Current 2.7 V to 3.6 V Operation Packages: 24-Pin TSSOP and 28-Pin MLP
Ordering Information See page 27.
-X T 2
Pin Assignments
Si4133G-XT2
SCLK SDATA
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SENB VDDI IFOUT GNDI IFLB IFLA GNDD VDDD GNDD XIN PWDNB AUXOUT
Description
The SI4133G-X2 is a monolithic integrated circuit that performs both IF and dual-band RF synthesis for GSM and GPRS wireless communications applications. The SI4133G-X2 includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and power down settings are programmable through a three-wire serial interface.
GNDR RFLD RFLC GNDR RFLB RFLA GNDR
Functional Block Diagram
Reference Amplifier Power Down Control
GNDR RFOUT VDDR
XIN
/65
Phase Detector
RFLA RFLB
PWDNB
SDATA
IFOUT
23
GNDR
SENB
SCLK
SDATA SCLK SENB
Serial Interface 22-bit Data Register
Phase Detector
RFLC RFLD
GNDR RFLD RFLC
1 2 3 4 5 6 7
28
27
26
25
24
GNDI
22 21 20 19 18 17 16 15
/N
RF1 RFOUT
Si4133G-XM2
VDDI
GNDI IFLB IFLA GNDD VDDD GNDD XIN
/N
Phase Detector
RF2
AUXOUT
Test Mux
IFOUT IF
GNDR RFLB
/N
IFLA IFLB
RFLA GNDR
8
9
10
11
12
13
14
GNDR
GNDR
AUXOUT
RFOUT
Patents pending
Rev. 0.9 8/00 Copyright (c) 2000 by Silicon Laboratories Si4133GX2-DS09
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
PWDNB
GNDD
VDDR
S i4 13 3G -X 2
2
Rev. 0.9
SI4133G-X2 TA B L E O F CON T E N T S
Section Page
4 15 15 15 16 17 17 17 18 18 18 20 25 26 27 28 29 32
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4133G-XT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4133G-XM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: Si4133G-XT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: Si4133G-XM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 0.9
3
S i4 13 3G -X 2
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Symbol TA VDD V (VDDR - VDDD), (VDDI - VDDD) Test Condition Min -20 2.7 -0.3 Typ 25 3.0 -- Max 85 3.6 0.3 Unit C V V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at 3.0 V and an operating temperature of 25C unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter DC Supply Voltage Input Current3 Input Voltage3 Storage Temperature Range Symbol VDD IIN VIN TSTG Value -0.5 to 4.0 10 -0.3 to VDD+0.3 -55 to 150 Unit V mA V
o
C
Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SENB, PWDNB and XIN.
4
Rev. 0.9
SI4133G-X2
Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = -20 to 85C
Parameter Total Supply Current
1
Symbol
Test Condition RF1 and IF operating
Min -- -- -- --
Typ 18 13 12 10 1 -- -- -- -- -- --
Max 31 17 17 14 -- -- 0.3 VDD 10 10 -- 0.4
Unit mA mA mA mA A V V A A V V
RF1 Mode Supply Current1 RF2 Mode Supply Current1 IF Mode Supply Current1 Standby Current High Level Input Voltage2 Low Level Input Voltage2 High Level Input Current2 Low Level Input Current2 High Level Output Voltage3 Low Level Output Voltage3 VIH VIL IIH IIL VOH VOL VIH = 3.6 V, VDD = 3.6 V VIL = 0 V, VDD= 3.6 V IOH = -500 A IOH = 500 A PWDNB = 0, XPDM = 0
-- 0.7 VDD -- -10 -10 VDD-0.4 --
Notes: 1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 1080 MHz, RFPWR = 1 2. For signals SCLK, SDATA, SENB, and PWDNB. 3. For signal AUXOUT.
Rev. 0.9
5
S i4 13 3G -X 2
Table 4. Serial Interface Timing
(VDD = 2.7 to 3.6 V, TA = -20 to 85C)
Parameter1 SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDATA Setup Time to SCLK2 SDATA Hold Time from SCLK2 SENB to SCLK Delay Time
2
Symbol tclk tr tf th tl tsu thold ten1 ten2 ten3 tw
Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2
Min 40 -- -- 10 10 5 0 10 12 12 10
Typ -- -- -- -- -- -- -- -- -- -- --
Max -- 50 50 -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns
SCLK to SENB Delay Time2 SENB to SCLK Delay Time2 SENB Pulse Width
Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of waveform. See Figure 2.
tr
80%
tf
SCLK
50% 20%
th
tclk
tl
Figure 1. SCLK Timing Diagram
6
Rev. 0.9
SI4133G-X2
D 17
D 16
D 15
A 1
A 0
Figure 2. Serial Interface Timing Diagram
First bit clocked in
Last bit clocked in
DDDDDDDDDDDDDDDDDDAAAA 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0
data field
address field
Figure 3. Serial Word Format
Rev. 0.9
7
S i4 13 3G -X 2
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = -20 to 85C)
Parameter1 XIN Input Frequency Reference Amplifier Sensitivity Internal Phase Detector Frequency RF1 VCO Center Frequency Range RF2 VCO Center Frequency Range IFOUT Center Frequency Tuning Range from fCEN RF1 VCO Pushing RF2 VCO Pushing IF VCO Pushing RF1 VCO Pulling RF2 VCO Pulling IF VCO Pulling RF1 Phase Noise
Symbol fREF VREF f fCEN fCEN fCEN
Test Condition
Min -- 0.5
Typ 13 -- 200
Max -- VDD +0.3
Unit MHz VP-P KHz
f = fREF/R 947 789 -- Note: LEXT 10% Open loop -5 -- -- -- VSWR = 2:1, all phases, open loop -- -- -- 1 MHz offset 3 MHz offset -- -- -- -- -- -- -- -- -- ZL = 50
ZL = 50
-- -- 1080 -- 0.5 0.4 0.3 0.4 0.1 0.1 -132 -142 -134 -144 -117 0.9 -26 -26 -26 -2 -6
1720 1429 -- +5 -- -- -- -- -- -- -- -- -- -- -- --
MHz MHz MHz % MHz/V MHz/V MHz/V MHzp-p MHzp-p MHzp-p dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz deg rms dBc dBc dBc
RF2 Phase Noise
1 MHz offset 3 MHz offset
IF Phase Noise RF1 Integrated Phase Error RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Power Level IFOUT Power Level
100 kHz offset 100 Hz to 100 kHz Second Harmonic
-7 -10
1 -3
dBm dBm
Notes: 1. RF1 = 1.55 GHz, RF2 = 1.4 GHz, IF = 1080 MHz., RFPWR=0 for all parameters unless otherwise noted. 2. From power up request (PWDNB or SENB during a write of 1 to bits PDAB, PDIB, and PDRB in register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 s. 3. From power down request (PWDNB, or SENB during a write of 0 to bits PDAB, PDIB, and PDRB in register 2) to supply current equal to IPWDN.
8
Rev. 0.9
SI4133G-X2
Table 5. RF and IF Synthesizer Characteristics (Continued)
(VDD = 2.7 to 3.6 V, TA = -20 to 85C)
Parameter1 RF1 Reference Spurs
Symbol
Test Condition Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz
Min -- -- -- -- -- -- -- --
Typ -70 -75 -80 -75 -80 -80 140 --
Max -- -- -- -- -- -- -- 100
Unit dBc dBc dBc dBc dBc dBc s ns
RF2 Reference Spurs
Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz
Power Up Request to Synthesizer Ready Time, RF1, RF2, IF2 Power Down Request to Synthesizer Off Time3
tpup tpdn
Figures 4, 5 Figures 4, 5
Notes: 1. RF1 = 1.55 GHz, RF2 = 1.4 GHz, IF = 1080 MHz., RFPWR=0 for all parameters unless otherwise noted. 2. From power up request (PWDNB or SENB during a write of 1 to bits PDAB, PDIB, and PDRB in register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 s. 3. From power down request (PWDNB, or SENB during a write of 0 to bits PDAB, PDIB, and PDRB in register 2) to supply current equal to IPWDN.
Figure 4. Hardware Power Management Timing Diagram
Figure 5. Software Power Management Timing Diagram
Rev. 0.9
9
S i4 13 3G -X 2
TRACE A: Ch1 FM Gate Time A Offset 800 Hz
133.59375 us
-461.24
kHz
Real
160 Hz /div
-800 Hz Start: 0 s Stop: 299.21875 us
Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency
10
Rev. 0.9
SI4133G-X2
Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency
Figure 8. Typical RF1 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency
Rev. 0.9
11
S i4 13 3G -X 2
Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency
Figure 10. Typical RF2 Spurious Response at 1.2 GHz with 200 kHz Phase Detector Update Frequency
12
Rev. 0.9
SI4133G-X2
Figure 11. Typical IF Phase Noise at 1080 MHz with 200 kHz Phase Detector Update Frequency
Figure 12. IF Spurious Response at 1080 MHz with 200 kHz Phase Detector Update Frequency
Rev. 0.9
13
S i4 13 3G -X 2
From System Controller
Si4133G-XT2
1 2 3 4 5
SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR
SENB VDDI IFOUT GNDI IFLB IFLA GNDD VDDD GNDD XIN PWDNB AUXOUT
24 23 22 21 20 19 18 17 16 15 14 13
Vdd
0.022m F 10nH 560pF IFOUT
Printed Trace Inductors
6 7 8 9 10
Printed Trace Inductor or Chip Inductor
Vdd
0.022m F
560pF External Clock PDWNB AUXOUT
560pF RFOUT
2nH 0.022m F Vdd
11 12
Figure 13. Typical Application Circuit: Si4133G-XT2
Vdd From System Controller
28 27 26 25 24 23 22
0.022m F
10nH 560pF IFOUT
SCLK
SENB
VDDI
GNDR
SDATA
IFOUT
GNDI
1 2 3
GNDR RFLD RFLC GNDR RFLB RFLA
GNDI IFLB IFLA
21 20 19 18 17 16 15
Printed Trace Inductor or Chip Inductor
Printed Trace Inductors
4 5 6 7
Si4133G-XM2
GNDD VDDD GNDD
Vdd
0.022m F 560pF External Clock
AUXOUT
PWDNB
RFOUT
GNDR
GNDR GNDR
XIN
GNDD
14
8
9
10
11
VDDR
12
13
Vdd 0.022m F AUXOUT PWDNB 2nH 560pF RFOUT
Figure 14. Typical Application Circuit: Si4133G-XM2
14
Rev. 0.9
SI4133G-X2
Functional Description
The SI4133G-X2 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for many wireless applications such as GSM900, DCS1800, and PCS1900. Its fast transient response also makes the SI4133G-X2 especially well suited to GPRS and HSCSD multislot applications where channel switching and settling times are critical. This integrated circuit (IC), with a minimum number of external components, is all that is necessary to implement the frequency synthesis function. The SI4133G-X2 has three complete phase-locked loops (PLLs) with integrated voltage-controlled oscillators (VCOs). The low phase noise of the VCOs makes the SI4133G-X2 suitable for use in demanding cellular applications. Also integrated are phase detectors, loop filters, and reference dividers. The IC is programmed through a three-wire serial interface. One PLL is provided for IF synthesis, and two PLLs are provided for dual-band RF synthesis. One RF VCO is optimized to have its center frequency set between 947 MHz and 1720 MHz, while the second RF VCO is optimized to have its center frequency set between 789 MHz and 1429 MHz. Each RF PLL can adjust its output frequency by 5% relative to its VCO's center frequency. The IF VCO is optimized to have its center frequency set to 1080 MHz. Three settings are provided for IF output frequencies of 1070.4 MHz, 1080 MHz and 1089.6 MHz. The center frequency of each of the three VCOs is set by connection of an external inductance. Inaccuracies in the value of the inductance are compensated for by the SI4133G-X2's proprietary self-tuning algorithm. This algorithm is initiated each time the PLL is powered-up (by either the PWDNB pin or by software) and/or each time a new output frequency is programmed. The two RF PLLs share a common output pin, so only one PLL is active at a given time. Because the two VCOs can be set to have widely separated center frequencies, the RF output can be programmed to service different frequency bands, thus making the SI4133G-X2 ideal for use in dual-band cellular handsets. The unique PLL architecture used in the SI4133G-X2 produces a transient response that is superior in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs.
Serial Interface
The SI4133G-X2 is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. Figure 3 on page 7 shows the format of the serial interface. A timing diagram for the serial word is shown in Figure 2 on page 7. When the serial interface is enabled (i.e., when SENB is low) data and address bits on the SDATA pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SENB into the internal data register addressed in the address field. The serial word is disabled when SENB is high. Table 9 on page 20 summarizes the data register functions and addresses. It is not necessary (although it is permissible) to clock into the internal shift register any leading bits that are "don't cares".
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies 5% with respect to their VCO center frequencies. Each center frequency is established by the value of an external inductance connected to the respective VCO. Manufacturing tolerances of 10% for the external inductances are acceptable. The SI4133G-X2 will compensate for inaccuracies in each inductance by executing a self-tuning algorithm following power-up or following a change in the programmed output frequency. Because the total tank inductance is in the low nH range, the inductance of the package needs to be considered in determining the correct external inductance. The total inductance (LTOT) presented to each VCO is the sum of the external inductance (LEXT) and the package inductance (LPKG). Each VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as follows:
1 F CEN = ------------------------------------------2 L TOT C NOM
or
1 F CEN = -------------------------------------------------------------------2 ( L PKG + L EXT ) C NOM
Rev. 0.9
15
S i4 13 3G -X 2
Tables 6 and 7 summarize these characteristics for each VCO. between RFLC and RFLD as shown in Figure 15. This, in addition to 2.3 nH of package inductance, will present the correct total inductance to the VCO. In manufacturing, the external inductance can vary 10% of its nominal value and the SI4133G-X2 will correct for the variation with the self-tuning algorithm. In most cases the requisite value of the external inductance is small enough to allow a PC board trace to be utilized. During initial board layout, a length of trace approximating the desired inductance can be used. For more information, please refer to Application Note 31.
Table 6. Si4133G-XT2 VCO Characteristics
VCO fCEN Range (MHz) Min Max Cnom (pF) Lpkg (nH) Lext Range (nH) Min Max
RF1 RF2 IF
947 789
1720 1429
4.3 4.8 6.5
2.0 2.3 2.1
0.0 0.3 1.2
4.6 6.2
Self-Tuning Algorithm
1080 The self-tuning algorithm is initiated immediately following power-up of a PLL or, if the PLL is already powered, following a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its free-running frequency is near the desired output frequency. In so doing, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the VCO. It will also reduce the frequency error for which the PLL must correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations. The SI4133G-X2's self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur AFTER self-tuning is limited. For external inductances with temperature coefficients around 150 ppm/oC, the PLL will be able to maintain lock for changes in temperature of approximately 30oC. Applications where the PLL is regularly powered down or switched between channels minimize or eliminate the potential effects of temperature drift because the VCO is re-tuned when it is powered up or when a new frequency is programmed. In applications where the ambient temperature can drift substantially after selftuning, it may be necessary to monitor the LDETB (lockdetect bar) signal on the AUXOUT pin to determine the locking state of the PLL. (See the AUXILIARY OUTPUT section below for how to select LDETB.) The LDETB signal will be low after self-tuning has completed but will rise when either the IF or RF PLL
Table 7. Si4133G-XM2 VCO Characteristics
VCO fCEN Range (MHz) Min Max Cnom (pF) Lpkg (nH) Lext Range (nH) Min Max
RF1 RF2 IF
947 789
1720 1429
4.3 4.8 6.5
1.5 1.5 1.6
0.5 1.1 1.7
5.1 7.0
1080
Si4133G-XM2 LPKG 2 LEXT
LPKG 2
Figure 15. External Inductance Connection
As a design example, suppose it is desired to synthesize frequencies in a 25 MHz band between 1120 MHz and 1145 MHz. The center frequency should be defined as midway between the two extremes, or 1132.5 MHz. The PLL will be able to adjust the VCO output frequency 5% of the center frequency, or 56.6 MHz of 1132.5 MHz (i.e., from approximately 1076 MHz to 1189 MHz, more than enough for this example). The RF2 VCO has a CNOM of 4.8 pF, and a 4.1 nH inductance (correct to two digits) in parallel with this capacitance will yield the desired center frequency. An external inductance of 1.8 nH should be connected
16
Rev. 0.9
SI4133G-X2
nears the limit of its compensation range (LDETB will also be high when either PLL is executing the selftuning algorithm). The output frequency will still be locked when LDETB goes high, but the PLL will eventually lose lock if the temperature continues to drift in the same direction. Therefore, if LDETB goes high both the IF and RF PLLs should promptly be re-tuned by initiating the self-tuning algorithm. update periods, the SI4133G-X2 executes the selftuning algorithm. Thereafter the PLL controls the output frequency. Because of the unique architecture of the SI4133G-X2 PLLs, the time required to settle the output frequency to 0.1 ppm error is approximately 21 update periods. Thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled (including time for self-tuning) is around 28 update periods or 140 S.
Output Frequencies
The IF and RF output frequencies are set by programming the N Divider registers. Each RF PLL has its own N register and can be programmed independently. All three PLL R dividers are fixed at R=65 to yield a 200 kHz phase detector update rate from a 13 MHz reference frequency. Programming the N divider register for either RF1 or RF2 automatically selects the associated output. The reference frequency on the XIN pin is divided by R and this signal is input to the PLL's phase detector. The other input to the phase detector is the PLL's VCO output frequency divided by N. The PLL acts to make these frequencies equal. That is, after an initial transient
RF and IF Outputs
The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF VCOs and IF VCO, respectively. The RF output amplifier receives its input from either the RF1 or RF2 VCO, depending upon which N divider register was last written to. For example, programming the N divider register for RF1 automatically selects the RF1 VCO output. The RFOUT pin must be coupled to its load through an ac coupling capacitor. A matching network is required to maximize power delivered into a 50 load. The network consists of a 2 nH series inductance, which may be realized with a PC board trace, connected between the RFOUT pin and the ac coupling capacitor. The network is made to provide an adequate match to an external 50 load for both the RF1 and RF2 frequency bands. The matching network also filters the output signal to reduce harmonic distortion. A 50 load is not required for proper operation of the SI4133G-X2. Depending on transceiver requirements, the matching network may not be needed. See Figure 16 below.
2 nH RFOUT 50 560 pF
F OUT FREF ------------- = -----------N 65
or
NF OUT = ----- F REF 65
For XIN = 13 MHz this simplifies to
F OUT = N 200 kHz
The integer N is set by programming the RF1 N Divider register (register 3), the RF2 N Divider register (register 4), and the IF N Divider register (register 5). Each N divider is implemented as a conventional high speed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. However, the calculation of these values is done automatically. Only the appropriate N value needs to be programmed
Figure 16. RFOUT 50 Test Circuit
The RF output power is controlled with the RFPWR bit in register 0. Setting this bit increases the supply current by approximately 1.2 mA. To minimize output power variation over temperature, the RFPWR bit can be set as a function of temperature. For example, set RFPWR=1 for temperatures greater than 50oC, otherwise set RFPWR=0. The IFOUT pin must also be coupled to its load through an ac coupling capacitor. A matching network is also required in order to drive a 50 load. See Figure 17 below.
PLL Loop Dynamics
The transient response for each PLL has been optimized for a GSM application. VCO gain, phase detector gain, and loop filter characteristics are not programmable. The settling time for each PLL is directly proportional to its phase detector update period T (T equals 1/f). For a GSM application with a 13 MHz reference frequency, the RF and IF PLLs T = 5 S. During the first 6.5
Rev. 0.9
17
S i4 13 3G -X 2
18 nH IFOUT 50W 560 pF
Auxiliary Output (AUXOUT)
The AUXOUT pin can be used to monitor a variety of signals. The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (register 0). The possible outputs are listed in the description of the Main Configuration register. Some of these signals may only be useful for evaluation purposes (in particular, the PLL R-divider and N-divider outputs). Two signals, have more general use. The first is the LDETB signal, which can be selected by setting the AUXSEL bits to 011. As discussed previously, this signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambient temperature drift and should be re-tuned. The second is the Reference Clock output. This is a buffered version of the signal on the XIN pin, with the exception that it will be held low when the reference frequency amplifier is powered down.
Figure 17. IFOUT 50 Matching Network
Reference Frequency Amplifier
The SI4133G-X2 provides a reference frequency amplifier. If the driving signal has CMOS levels it can be connected directly to the XIN pin. Otherwise, the reference frequency signal should be ac coupled to the XIN pin through a 100 pF capacitor.
Power Down Modes
Table 8 summarizes the power down functionality. The SI4133G-X2 can be powered down by taking the PWDNB pin low or by setting bits in the Power Down register (register 2). When the PWDNB pin is low, the SI4133G-X2 will be powered down regardless of the Power Down register settings. When the PWDNB pin is high, power management is under control of the Power Down register bits. It may be desirable to defeat power down of the reference frequency amplifier. In such a case the XPDM (XTAL Power Down Mode) bit in the Main Configuration register (register 0) should be set to 1. The reference frequency amplifier will then remain powered up even when the PWDNB pin is asserted (i.e., low), excepting when all three of the Power Down register bits (PDAB, PDIB, and PDRB) are low. This exception exists so that, even in this mode, the reference amplifier can be forced to power down if sufficient time occurs for a power down and power up sequence. Alternatively, the reference amplifier power down defeat mode can be exited by setting XPDM to 0. With the PWDNB pin high, the XPDM bit has no effect. The reference frequency amplifier, IF, and RF sections of the SI4133G-X2 circuitry can be individually powered down by setting the Power Down register bits PDAB, PDIB, and PDRB low, respectively. Note that the reference frequency amplifier will also be powered up if either the PDRB and PDIB bits are high, even if the PDAB bit is low. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (register 0) is equivalent to setting all three of the bits in the Power Down register to 1. The serial interface remains available and can be written in all power down modes.
18
Rev. 0.9
SI4133G-X2
Table 8. Power Down Configuration
PWDNB Pin AUTOPDB PDIB PDRB Reference Frequency Amplifier IF Circuitry RF Circuitry
PWDNB = 0
X 0 0 0 0 0 1
X 0 0 1 1 0 x
X 0 1 0 1 0 x
OFF OFF ON ON ON ON ON
OFF OFF OFF ON ON OFF ON
OFF OFF ON OFF ON OFF ON
PWDNB = 1
Note: The XPDM bit has no effect when the PWDNB pin is high.
Rev. 0.9
19
S i4 13 3G -X 2
Control Registers
Table 9. Register Summary Register Name 0 1 2 3 4 5 6 7 . . . 15 Reserved Main Configuration Reserved Power Down RF1 N Divider RF2 N Divider IF N Divider Reserved Reserved X X X X X X X X X X X X X NRF1 NRF2 NIF X X X X X 0
PDIB PDRB
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 17 16 15 14 13 12 11 10 9 8 7 65 4 X X X AUXSEL 0 0 0 0 0 0 0 0
Bit 3
AUTO PDB
Bit 2 0
Bit 1 1
Bit 0 0
Note: X = Don't Care. Registers 1 and 6-15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed here is reserved and should not be written.
20
Rev. 0.9
SI4133G-X2
Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 X X X AUXSEL 0 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3
AUTO PDB
D2 0
D1 1
D0 0
Bit 17:15 14:12
Name Reserved AUXSEL Don't care.
Function
Auxiliary Output Pin Definition. 000 = Reserved. 001 = Force output low. 010 = CMOS level of fREF. 011 = Lock Detect--LDETB. 100 = CMOS level of fR of active RF synthesizer. 101 = CMOS level of fR of IF synthesizer. 110 = CMOS level of fN of active RF synthesizer. 111 = CMOS level of fN of IF synthesizer. Program to zero. Program to zero. Auto Power Down 0 = Software powerdown is controlled by register 2. 1 = Equivalent to setting all bits in register 2 = 1. Program to zero. Program to one. Program to zero.
11:5 4 3
Reserved Reserved AUTOPDB
2 1 0
Reserved Reserved Reserved
Rev. 0.9
21
S i4 13 3G -X 2
Register 2. Power Down Address Field (A[3:0]) = 0010 Bit Name Bit 17:2 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 X X X X Name Reserved PDIB Don't care. Power Down IF Synthesizer. 0 = IF synthesizer powered down. 1 = IF synthesizer on. Power Down RF Synthesizer. 0 = RF synthesizer powered down. 1 = RF synthesizer on. X X X X X D8 X D7 X D6 X D5 X D4 X D3 X D2 X D1 D0
PDIB PDRB
Function
0
PDRB
Register 3. RF1 N Divider Address Field (A[3:0]) = 0011 Bit Name Bit 17:0 Name NRF1 N Divider for RF1 Synthesizer. D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF1 Function
Register 4. RF2 N Divider Address Field = A[3:0] = 0100 Bit Name Bit 17 16:0 D17 D16 D15 D14 D13 D12 D11 D10 X Name Reserved NRF2 Don't care. N Divider for RF2 Synthesizer. D9 D8 NRF2 Function D7 D6 D5 D4 D3 D2 D1 D0
22
Rev. 0.9
SI4133G-X2
Register 5. IF N Divider Address Field (A[3:0]) = 0101 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 X X Name 17:16 15:0 Reserved NIF Don't care. N Divider for IF Synthesizer. Only the following values are allowed (frequencies assume XIN is 13 MHz): 7150 = 1070.4 MHz 7215 = 1080.0 MHz 7280 = 1089.6 MHz D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NIF Function
Rev. 0.9
23
S i4 13 3G -X 2
<15 ns
Figure 18. AUXOUT Timing Diagram
24
Rev. 0.9
SI4133G-X2
Pin Descriptions: Si4133G-XT2
SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SENB VDDI IFOUT GNDI IFLB IFLA GNDD VDDD GNDD XIN PWDNB AUXOUT
Name AUXOUT GNDD GNDI GNDR IFLA, IFLB IFOUT PWDNB RFLA, RFLB RFLC, RFLD RFOUT SCLK SDATA SENB VDDD VDDI VDDR XIN
Pin Number(s) Description 13 16, 18 21 3, 6, 9, 10 19, 20 22 14 7, 8 4, 5 11 1 2 24 17 23 12 15 Auxiliary output Common ground for digital circuitry Common ground for IF analog circuitry Common ground for RF analog circuitry Pins for inductor connection to IF VCO Intermediate frequency (IF) output of the IF VCO Power down input pin Pins for inductor connection to RF1 VCO Pins for inductor connection to RF2 VCO Radio frequency (RF) output of the selected RF VCO Serial clock input Serial data input Enable serial port input Supply voltage for digital circuitry Supply voltage for IF analog circuitry Supply voltage for the RF analog circuitry Reference frequency amplifier input
Rev. 0.9
25
S i4 13 3G -X 2
Pin Descriptions: Si4133G-XM2
SDATA IFOUT
23
GNDR
SENB
SCLK
28
27
26
25
24
GNDR RFLD RFLC GNDR RFLB RFLA GNDR
1 2 3 4 5 6 7 8 9 10 11 12 13 14
GNDI
22 21 20 19 18 17 16 15
VDDI
GNDI IFLB IFLA GNDD VDDD GNDD XIN
GNDR
GNDR
AUXOUT
RFOUT
Name AUXOUT GNDD GNDI GNDR IFLA, IFLB IFOUT PWDNB RFLA, RFLB RFLC, RFLD RFOUT SCLK SDATA SENB VDDD VDDI VDDR XIN
Pin Number(s) Description 12 14, 16, 18 21, 22 1, 4, 7-9, 28 19, 20 23 13 5,6 2, 3 10 26 27 25 17 24 11 15 Auxiliary output Common ground for digital circuitry Common ground for IF analog circuitry Common ground for RF analog circuitry Pins for inductor connection to IF VCO Intermediate frequency (IF) output of the IF VCO Power down input pin Pins for inductor connection to RF1 VCO Pins for inductor connection to RF2 VCO Radio frequency (RF) output of the selected RF VCO Serial clock input Serial data input Enable serial port input Supply voltage for digital circuitry Supply voltage for IF analog circuitry Supply voltage for the RF analog circuitry Reference frequency amplifier input
26
Rev. 0.9
PWDNB
GNDD
VDDR
SI4133G-X2
Ordering Guide
Ordering Part Number Si4133G-XM2 Si4133G-XT2 Description RF1 / RF2 / IF OUT RF1 / RF2 / IF OUT Package 28-Pin MLP 24-Pin TSSOP Temperature -20 to 85oC -20 to 85oC
Rev. 0.9
27
S i4 13 3G -X 2
Package Outline: Si4133G-XT2
E
H L
B D A e
A1
C
Figure 19. 24-Pin Thin Shrink Small Outline Package (TSSOP)
Table 10. Package Dimensions
Symbol Min A A1 B C D E e H L -- 0.002 0.007 0.004 0.303 0.169 Inches Max 0.047 0.006 0.012 0.008 0.311 0.177 Millimeters Min -- 0.05 0.19 0.09 7.70 4.30 Max 1.1 0.15 0.30 0.20 7.90 4.50
0.026 BSC 0.252 BSC 0.018 0 0.030 8
0.65 BSC 6.40 BSC 0.45 0 0.75 8
28
Rev. 0.9
SI4133G-X2
Package Outline: Si4133G-XM2
Figure 20. 28-Pin Micro Leadframe Package (MLP) Table 11. Package Dimensions
Controlling Dimension: mm Symbol Min A A1 b D D1 E E1 N Nd Ne e L 0.50 -- 0.00 0.18 Millimeters Nom 0.90 0.01 0.23 5.00 BSC 4.75 BSC 5.00 BSC 4.75 BSC 28 7 7 0.50 BSC 0.60 0.75
12
Max 1.00 0.05 0.30
Rev. 0.9
29
S i4 13 3G -X 2 NOT E S :
30
Rev. 0.9
SI4133G-X2 NOT E S :
Rev. 0.9
31
S i4 13 3G -X 2
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free:1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
32
Rev. 0.9

▲Up To Search▲

Price & Availability of SI4133G-X2

	To Download SI4133G-X2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .