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aS2-Quadrant Multiplying 8-Bit DACs * 8 Independent at Input Data and Address Port (3-Wire * Serial Digital .D Standard) plus Internal Chip Address Decoder(c) w * Dual Supplies (+5 V typ.) w Speed: * w High 12.5 MHz Digital Clock Rate -
FEATURES
* * * * * VREF to VOUT Settling Time: 150ns to 8-bit (typ) - Voltage Reference Input Bandwidth: 10 MHz (typ) Low Power: 150mW (typ) Low AC Voltage Reference Feedthrough Excellent Channel-to-Channel Isolation DNL = +0.8 LSB, INL = +1 LSB (typ) DACs Matched to +0.5% (typ) -
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MP7651
8-Channel, Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Data Port and Chip Select Decoder
* Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz * VREF/2 Output Preset Level * Latch-Up Proof * Greater than 2000 V ESD Protection
APPLICATIONS
GENERAL DESCRIPTION
The MP7651 is ideal for direct gain control of video, composite video, CCD and other high frequency analog signals. The device includes 8-channels of high speed, high bandwidth, two quadrant, multiplying, 8-bit accurate digital-to-analog converter. It includes an output drive buffer per channel capable of driving +1mA (typ) to a load. DNL of better than +0.8 LSB is achieved with a channel-to-channel matching of better than 0.5%. Stability, matching, and precision of the DACs is achieved by using EXAR's thin film technology. Also, excellent channel-to-channel isolation is achieved with EXAR's BiCMOS process which cannot be achieved using a typical CMOS technology.
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* ATE * Process Control (Low Noise) * Convergence Adjustment for High Resolution Monitors (Work Stations) * Digital Gain/Attenuation/Offset Control * Trimmer Replacement
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fast output settling time, and VREF feedthrough isolation of -65dB or better. In addition, low distortion in the order of 0.25% with a 1 V p-p, 1 MHz signal. A specified and constant input impedance of each VREF+ input gives flexibility for optimal system design. The serial data 3-wire standard -processor logic interface reduces pin count, package size (28 pin), and board wire (space). Additionally, the internal chip select decoder allows for easy daisy chaining without the addition of separate control logic.
An open loop architecture (patent pending) provides wide small signal bandwidth from VREF to output up to 10 MHz (typ),
MP7651 is fabricated on a junction isolated, high speed, dual metal, linear compatible BiCMOS (BiCMOS IVTM) thin film resistors. This process enables precision high speed analog/digital (mixed-mode) circuits to be fabricated on the same chip.
Rev. 2.00 1
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MP7651
SIMPLIFIED BLOCK DIAGRAM(c)
VCC
RST 8 8-Bit Latch DAC 0 +1
VR0 VO0 VR1 8 8-Bit Latch DAC 1 +1 VO1
VR7 8 8-Bit Latch DAC 7 +1 VO7
8 8 8 LD CLK LD SDI 1-Bit Latch 1-Bit Latch 8 4-8 DEC 4 4-Bit CH Address COMP 4 4-Bit CS Address 3-State Buffer LD LD CS0P to CS3P
4
DB0 to DB7
SDO
16-Bit Shift Register
VEE
GND
ORDERING INFORMATION
Package Type
SOIC Plastic Dip
Temperature Range
-40 to +85C -40 to +85C
Part No.
MP7651AS MP7651AN
INL (LSB)
+1 +1
DNL (LSB)
+0.8 +0.8
Gain Error (% FSR)
+1.5 +1.5
Rev. 2.00 2
MP7651
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
VR1 VO1 VO2 VR2 VR3 VO3 VCC VEE GND VO4 VR4 VR5 VO5 VO6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
VR0 VO0 CS3P CS2P RST LD CLK SDO SDI CS1P CSOP VO7 VR7 VR6
VR1 VO1 VO2 VR2 VR3 VO3 VCC VEE GND VO4 VR4 VR5 VO5 VO6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VR0 VO0 CS3P CS2P RST LD CLK SDO SDI CS1P CSOP VO7 VR7 VR6
28 Pin PDIP (0.300") NN28
28 Pin SOIC (EIAJ, 0.335") R28
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NAME VR1 VO1 VO2 VR2 VR3 VO3 VCC VEE GND VO4 VR4 VR5 VO5 VO6 VR6
DESCRIPTION DAC 1 Reference Input DAC 1 Output DAC 2 Output DAC 2 Reference Input DAC 3 Reference Input DAC 3 Output Positive Supply Negative Supply Ground DAC 4 Output DAC 4 Reference Input DAC 5 Reference Input DAC 5 Output DAC 6 Output DAC 6 Reference Input
PIN NO. 16 17 18 19 20 21 22 23 24 25 26 27 28
NAME VR7 VO7 CSOP CS1P SDI SDO CLK LD RST CS2P CS3P VO0 VR0
DESCRIPTION DAC 7 Reference Input DAC 7 Output Chip Select Bit 0 (LSB) Chip Select Bit 1 Serial Data/Address Input Serial Data Output Shift Register Clock Load Signal; Load Data to Selected DACs Reset Signal; Reset all DACs to VREF/2 Chip Select Bit 2 Chip Select Bit 3 (MSB) DAC 0 Output DAC 0 Reference Input
Rev. 2.00 3
MP7651
ELECTRICAL CHARACTERISTICS TABLE
Unless Otherwise Noted: VCC = +5 V, VEE = -5 V and -3 V, VREF = 3 V and -3 V, T = 25C, Output Load = Open
Parameter DC CHARACTERISTICS Resolution (All Grades) Differential Non-Linearity Integral Non-Linearity Monotonicity Gain Error Zero Scale Offset Output Drive Capability REFERENCE INPUTS Impedance of VREF Voltage Range DYNAMIC CHARACTERISTICS2 Input to Output Bandwidth Input to Output Settling Time5 Small Signal Voltage Reference Input to Output Bandwidth Small Signal Voltage Reference Input to Output Bandwidth Voltage Settling from VREF to VDAC Out Voltage Settling from Digital Code to VDAC Out VREF Feedthrough Group Delay Harmonic Distortion Channel-to-Channel Crosstalk Digital Feedthrough Power Supply Rejection Ratio POWER CONSUMPTION Positive Supply Current Negative Supply Current Power Dissipation DIGITAL INPUT CHACTERISTICS Logic High3 Logic Low3 Input Current Input Capacitance2 VIH VIL IL CL 2.4 0.8 +10 8 2.4 0.8 +10 8 V V A pF ICC IEE PDISS 15 15 150 25 25 250 30 30 300 mA mA mW VREF = 0 V VREF = 0 V VREF = 0 V, Codes = all 1 10 150 10 5 8 275 275 -65 20 0.5 -75 1 0.02 300 300 325 325 MHz ns MHz MHz ns ns dB ns % dB nVs %/% REF VR 6 VEE +1.5 12 18 VCC-1.8 6 18 V k VREF N DNL INL GE ZOFS IO +20 +1 8 +0.8 +1 Guaranteed +1.5 +75 8 +1 +1 Guaranteed +1.5 +75 Bits LSB LSB % FSR mV mA FSR = Full Scale Range (1) Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
Max Swing is AGND +3 V
RL = 5 k, CL = 20 pF VR = 1.6 V p-p, RL = 5k to VEE VR = 1.6 V p-p, RL = 5k to VEE VOUT=50mV p-p above code 16 VOUT=50mV p-p for all codes VR=0 to VR = 3V Step (6) to 1 LSB ZS to FS to 1 LSB Codes=0 @ 1 MHz VREF=1MHz Sine 3V p-p @ 1 MHz, single channel CLK to VOUT V = +5%
tr tr tsr tsd FDT GD THD CT Q PSRR
Rev. 2.00 4
MP7651
ELECTRICAL CHARACTERISTICS TABLE
Description DIGITAL TIMING SPECIFICATIONS2, 4 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Reset Pulse Width Clock Edge to Load Rising Edge Clock Edge to Load Falling Edge Load Falling Edge to SDO 3-state Enable Load Rising Edge to SDO 3-state Disable Load Falling Edge to CLK Disable Load Rising Edge to CLK Enable LD Set-up Time with Respect to CLK CS0-CS3 Set-Up Time with Respect to LD tCH, tCL tDS tDH tPD tLD tRST tCKLD1 tCKLD2 tHZ1 tHZ2 tLDCK1 tLDCK2 tLDSU tCSLD 40 10 15 40 100 50 100 0 50 35 25 35 15 25 100 60 100 0 60 50 40 50 20 35 50 10 15 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Conditions
NOTES: 1 Full Scale Range (FSR) is 3V. 2 Guaranteed but not production tested. 3 Digital Input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See Figures 2 and 3. 5 For reference input pulse: tR = tF > 100 ns. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VEE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6.5 V VRi to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to VEE VOi to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to VEE Digital Input & Output Voltage to GND . . . . . . . . . . . . . . . . . . . . GND -0.5 to VCC +0.5 V Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300C Package Power Dissipation Rating @ 75C PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . . 6mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s.
APPLICATIONS INFORMATION Refer to Section 8 for Applications Information
Rev. 2.00 5
MP7651
SDI (Data In) CLK LD
1 0 1 0 1 0
CS3S CS2S CS1S CS0S
A3
A2
A1
A0
D7
D6
D0
VOUT
DAC Register Loaded
Figure 1. Serial Data Timing and Loading
tDS SDI
1 0 1 0
tDH
tHZ1
tHZ2 HIGH Z
SDO
tPD CSOP-CS3P
1 0
tCSLD
tCH
1
tLDSU tCL tCKLD2 tCKLD1 tLDCK1
tLDCK2
CLK LD
0 1 0
tLD
+5 V
VOUT
0V
tSD + 1/2 LSB BAND
Figure 2. Detail Serial Data Input Timing (RST = "1")
RST
1 0
tRST
tSD VO = VREF VO = VREF/2 + 1/2 LSB ERROR BAND
Figure 3. RESET Operation
Rev. 2.00 6
MP7651
THEORY OF OPERATION
MP7651 is equipped with a serial data 3-wire standard processor logic interface to reduce pin count, package size (28 pin), and board wire (space). This interface consists of LD which controls the transfer of data to the selected DAC channel, SDI (serial data/address input), CLK (shift register clock) and SDO (serial data output). When the LD signal is high, CLK signal loads the digital input bits (SDI) into the 16-bit shift register (8 bits data D7 to D0, plus 4 bits address A3 to A0, and 4 bits of Chip Select data CS0S to CS3S). If the CS0S to CS3S in the shift register match the parallel chip-select address (CS0P to CS3P) for the selected chip, then the LD signal going low loads the data Function Shift Data In and Out Stop Shifting Data In and Out Load DACs DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 A3 A2 A1 A0 X X X X X X X X LD 1 0 into the selected DAC of that chip. The LD signal going low also disables the serial data input (SDI), output (SDO 3-stated) and the CLK input. This design tremendously reduces digital noise, and glitch transients into the DACs due to free running CLK and SDI. Also, 3-stating the SDO output with LD signal would allow read back of pre-stored digital data of the selected package using one SDO wire for all DAC ICs on the board. Note also that the reset signal (RST) resets all analog outputs to 1/2 of VREF, regardless of any digital inputs. Also note that the input VRi is referenced to GND.
CS0S CS1S CS2S CS3S X X X X X X X X
CLK 01
Repeat
RST 1 1
SDI Data Input X
SDO Data Output Hi-Z
X
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
No Operation 10 10 10 10 10 10 10 10 No Operation No Operation No Operation X
Matched with 4 parallel chip select data CS0P to CS3P
1 1 Reset all DACs X to VREF/2
1 1 X
1 1 X
0 1 X
X X X X X X X X X X X X X X
1 1 1 1 1 1 1 1
X X X X X X X X
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 1 0
X X X
Hi-Z Hi-Z X
X
X
X
X
Table 1. Digital Function Truth Table Serial In/Serial Out
D7 MSB
0 0
D6
D5
D4
D3
D2
D1
D0 DAC Output Voltage D LSB VOi = AGND + (VRi - AGND) ( 256 )
0 1 AGND 1 (VRi - AGND) ( 256 ) + AGND
0 0
0 0
0 0
0 0
0 0
0 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
254 (VRi - AGND) ( 256 ) + AGND 255 (VRi - AGND) ( 256 ) + AGND
Table 2. DAC Transfer Function Analog Output vs. Digital Code
Rev. 2.00 7
MP7651
8
ENABLE DAC
NOT USED 8 8
LD
4 To 16 Decoder
CS3P CS2P CS1P CS0P 3-STATE SDI LAT DQ EN LD D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3
CS0S CS1S CS2S CS3S
SDO E
CLK
LAT DQ EN
LD
Figure 4. Internal Chip Address Decoder Plus Logic Interface
Rev. 2.00 8
MP7651
ADDRESS BUS
A0 to A23
AS
CS
ADDRESS DECODER
4
VMA
MC68000
CLK VPA 1/4 7HC125 VDS DB0 FROM SYSTEM RESET DB0 to DB15 16 16 SDI LD CS0P to CS3P
MP7651
RST
DATA BUS
Figure 5. MC68000 Interface (Simplified Diagram)
A0 to A15
16 3
16
ADDRESS BUS
E1
A0 to A2
MC6800
02 R/W E3 E2
74LS138 ADDRESS DECODER
8
4
DB0 to DB7
8
DATA BUS
LD DB7 SDI
CLK CS0P to CS3P
MP7651
RST
FROM SYSTEM RESET
NOTES: 1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each WRITE presents the next bit 2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE location 2000, R/W, and 02. A WRITE to address 4000 transfers data from the input shift register to the DAC register.
Figure 6. MC6800 Interface (Simplified Diagram)
Rev. 2.00 9
MP7651
APPLICATION NOTES
VRI1 8 8
VOI1
VRI2 8 8
VOI2
VRI16 8 8
VOI16
MP7651
MP7651 IC (2)
CS1P SDI 4 LD SDO 4 SDI
MP7651 IC (16)
CS1P LD SDO 4
PC
SDI
IC (1)
CS1P LD SDO
DATA CS0P-CS3P LD CLK 4
Figure 7. Simplified Diagram Configuration A
VRI1 8 8
VOI1
VRI2 8 8
VOI2
VRIn 8 8
VOIn
MP7651 IC (1)
CSIP
MP7651 IC (2)
CSIP SDI 4 LD SDO 4 4 SDI SDO
MP7651 IC (n)
CSIP LD SDO 4
PC
DATA OUT DATA CS0P-CS3P CS OR LD CLK 4 n
SDI
LD
#1
#2
#n
Figure 8. Simplified Diagram Configuration B
Rev. 2.00 10
MP7651
SDO0 ROW ADDRESS n ADDRESS DECODER 2n 3 2 1 WR SDO1 SDOE SDOF SDI CLK
7651
4 0 SDO LD SDI 4 1 SDO
7651
4 LD SDI E SDO
7651
4 LD SDI F SDO
7651
LD SDI
7651
4 0 SDO LD SDI 4 1 SDO
7651
4 LD SDI E SDO
7651
4 LD SDI F SDO
7651
LD SDI
7651
4 0 SDO LD SDI 4 1 SDO
7651
4 LD SDI E SDO
7651
4 LD SDI F SDO
7651
LD SDI
Figure 9. Simplified Diagram Configuration C
Rev. 2.00 11
MP7651
8
ADDRESS BUS
8 3 A0 to A2
8085
ALE
8212
+5 V
E1 E3
WR 8
E2
74LS138 ADDRESS DECODER
DATA BUS
SOD LD CLK CS0P to CS3P SDI
MP7651
RST
NOTES: FROM SYSTEM RESET 1. Clock generated by WR and decoding address 8000 2. Data is clocked into the DAC shift register by executing memory write instructions. The clock input is generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction to address 4000. 3. Serial data must be present in the right justified format in registers H & L of the microprocessor.
Figure 10. 8085 Interface (Simplified Diagram)
MP7651 EVALUATION BOARD
1.6 Vp-p Measurement Buffer 5 pF 1k Test Load
DUT
VR0 VO0 VR1 VO1 VR2 VO2 VR3 VO3 VR4 VO4 VR5 VO5 VR6 VO6 VR7 VO7 N/C SDI SDO CLK LD RST N/C DGND 20 pF 5k
VOUT
MP7651
All resistors = 50 unless otherwise specified Gain of all DACs set to 1 (no attenuation)
Figure 1. Crosstalk Measurement Set-Up
Rev. 2.00 12
MP7651
PERFORMANCE CHARACTERISTICS Channel-to-Channel Crosstalk (Gain vs. Frequency; All DACs set to full scale; VREF=1.6 Vp-p)
Output DACs shown below are: DAC 7, 1, 2, 5, 6, 3 and 4 Output DACs shown below are: DAC 2, 0, 3, 4, 7, 5 and 6
dB
DAC 7
dB
DAC 2
DAC 0 Driven
MHz
DAC 1 Driven
MHz
Graph 1.
Graph 2.
Output DACs shown below are: DAC 1, 3, 4, 5, 0, 6 and 7
Output DACs shown below are: DAC 4, 2, 1, 7, 0, 5 and 6
dB
DAC 1
dB
DAC 4
DAC 2 Driven
MHz
DAC 3 Driven
MHz
Graph 3.
Output DACs shown below are: DAC 5, 3, 6, 7, 0, 1 and 2
Graph 4.
Output DACs shown below are: DAC 6, 4, 7, 0, 3, 1 and 2
DAC 6
dB
DAC 5
dB
DAC 4 Driven
MHz
DAC 5 Driven
MHz
Graph 5.
Output DACs shown below are: DAC 5, 7, 0, 4, 3, 1 and 2
Graph 6.
Output DACs shown below are: DAC 0, 6, 5, 4, 3, 1 and 2
dB
DAC 5
dB
DAC 0
DAC 6 Driven
MHz
DAC 7 Driven
MHz
Graph 7.
Rev. 2.00 13
Graph 8.
MP7651
Digital Input Code
Digital Input Code
Graph 9. Linearity Error vs. Digital Input Code DACs 0 to 3
Graph 10. Linearity Error vs. Digital Input Code DACs 4 to 7
Graph 11. Preset Voltage vs. Temperature
Graph 12. PSRR vs. Frequency
VR = 500 mV p-p
Gain
Phase
VR = 1.6 V p-p
Graph 13. Gain & Phase vs. Frequency
Rev. 2.00 14
Graph 14. Feedthrough vs. Frequency
MP7651
VR = 6 V p-p 3 V p-p
1.5 V p-p 1 V p-p 0.5 V p-p
Graph 15. Gain (VO/VR) vs. Frequency Open Loop/Unloaded Output*
Graph 16. THD vs. Frequency
Graph 17. ICC vs. Temperature
Graph 18. IEE vs. Temperature
A GE = +1.5% FSR
VRR Positive
All DACs driven, measured DAC @ zero scale and other DACs @ full scale B
VRR Negative
All DACs except monitored driven, all DACs @ full scale
-V
Graph 19. Reference Input Voltage Range vs. Supply Voltages
* A 2K or 5K resistor across output and VEE will remove peaking (See graph 26).
Graph 20. All Channel Crosstalk vs. Frequency
Rev. 2.00 15
MP7651
LD (5 V/DIV) VR = 3 V Digital Code = 2550255 VO (2 V/DIV) VR (2 V/DIV)
Digital Code = All Ones
VO (2 V/DIV)
2s/DIV
2s/DIV
Graph 21. Digital Settling
Graph 22. Pulse Response (tR = tF = 100 ns for VR)
VR (2 V/DIV)
LD (5 V/DIV)
VO (2 V/DIV)
VO (10mV/DIV)
2s/DIV
2s/DIV
Graph 23. 128 kHz Sawtooth Waveform Response
Graph 24. Clock and SDI Feedthrough
LD (5 V/DIV)
Gain (5 dB/DIV)
VO (10mV/DIV)
Group Delay (20 ns/DIV)
2s/DIV
MHz
Graph 25. Clock/SDI Feedthrough
Graph 26. Typical Gain and Group Delay vs. Frequency (with 5K resistor across output to VEE)
Rev. 2.00 16
MP7651
28 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) NN28
S
28 1 Q1 D
15 14 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN 0.130 0.015 0.014 0.038 0.008 1.340 0.290 0.240 MAX 0.230 -- 0.023 0.065 0.015 1.485 0.325 0.310
MILLIMETERS MIN 3.30 0.381 0.356 0.965 0.203 34.04 7.37 6.10 MAX 5.84 -- 0.584 1.65 0.381 37.72 8.26 7.87
0.100 BSC 0.115 0 0.055 0.020 (1) 0.150 15 0.070 0.100
2.54 BSC 2.92 0 1.40 0.508 3.81 15 1.78 2.54
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 2.00 17
MP7651
28 LEAD SMALL OUTLINE (335 MIL EIAJ SOIC) R28
D
28
15
E
1 14
H
C Seating Plane e B A1 L A
MILLIMETERS SYMBOL A A1 B C D E e H L MIN 2.60 MAX 2.80
INCHES MIN 0.102 MAX 0.110
0.2 (typ.) 0.3 0.10 17.6 8.3 0.5 0.20 18.0 8.5
0.008 (typ.) 0.012 0.004 0.693 0.327 0.020 0.008 0.709 0.335
1.27 (typ.) 11.5 0.8 12.1 1.2
0.050 (typ.) 0.453 0.031 0.477 0.047
Rev. 2.00 18
MP7651 Notes
Rev. 2.00 19
MP7651
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 20

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