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KM4132G271B
CMOS SGRAM
8Mbit SGRAM
128K x 32bit x 2 Banks Synchronous Graphic RAM LVTTL
Revision 2.4 May 1998
Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 2.4 (May 1998)
KM4132G271B
Revision History
Revision 2.4 (May 1998)
* Added KM4132G271B-7 product(143MHz @ CL =3).
CMOS SGRAM
Revision 2.3 (March 1998)
* Added Reverse Type Package in ODERING INFORMATION and PIN CONFIGURATION. * Removed KM4132G271B-H/12 product(-H : 100MHz @ CL =2, -12 : 83MHz @ CL=3). * Changed the Current values of ICC1, ICC3N, ICC4, ICC5, ICC6, ICC7 in DC CHARACTERISTICS. * Changed tSAC from 6 to 6.5 @ 125MHz, tSS from 2 to 2.5 @ 125MHz in AC PARAMETER . * Delete a page including FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
Revision 2.1 (November 1997)
* Changed the Height of TQFP Package from 1.4mmMAX to 1.2mmMax in
PACKAGE DIMENSIONS.
Revision 2.0 (October 1997)
* Added -H binning(100MHz @ CL =2 ). * Changed some values in DC CHARACTERISTICS. * Changed some values in AC PARAMETER (tSAC / tOH / tSHZ / tRP / tRC / tBPL / tBWC etc.). * Removed a AC Parameter, tBAL(Block write data-in to Active command period) in * Added the Package Type description(PQFP, TQFP) in
AC PARAMETER .
* Changed some values in FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
PACKAGE DIMENSIONS.
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Rev. 2.4 (May 1998)
KM4132G271B
128K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
* * * * JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual bank / Pulse RAS MRS cycle with address key programs -. CAS Latency (2, 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM 0-3 for byte masking Auto & self refresh 16ms refresh period (1K cycle) 100 Pin PQFP, TQFP (14 x 20 mm) Reverse Type Package offers the best signal routing
CMOS SGRAM
GENERAL DESCRIPTION
The KM4132G271B is 8,388,608 bits synchronous high data rate Dynamic RAM organized as 2 x 131,072 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Write per bit and 8 columns block write improves performance in graphics systems.
* * * * * * *
ORDERING INFORMATION
Part NO. KM4132G271BQ(R)-7 KM4132G271BQ(R)-8 KM4132G271BQ(R)-10 KM4132G271BTQ(R)-7 KM4132G271BTQ(R)-8 KM4132G271BTQ(R)-10 Max Freq. 143MHz 125MHz 100MHz 143MHz 125MHz 100MHz LVTTL 100 TQFP LVTTL 100 PQFP Interface Package
Graphics Features
* SMRS cycle. -. Load mask register -. Load color register * Write Per Bit(Old Mask) * Block Write(8 Columns)
* ~G271BQR# / ~G271BTQR# : Reverse Type Package
FUNCTIONAL BLOCK DIAGRAM
DQMi BLOCK WRITE CONTROL LOGIC CLK CKE CS MASK WRITE MASK REGISTER COLOR REGISTER INPUT BUFFER
CONTROL
LOGIC
MUX
*
COLUMN MASK DQMi DQi (i=0~31)
TIMING REGISTER
RAS CAS WE DSF DQMi
*
128Kx32 CELL ARRAY
128Kx32 CELL ARRAY
ROW DECORDER BANK SELECTION
*
SERIAL COUNTER COLUMN ADDRESS BUFFER ROW ADDRESS BUFFER REFRESH COUNTER
ADDRESS REGISTER CLOCK ADDRESS(A0~A9)
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OUTPUT BUFFER
LATENCY & BURST LENGTH
PROGRAMING REGISTER
COLUMN DECORDER
SENSE AMPLIFIER
Rev. 2.4 (May 1998)
Forward Type
Reverse Type
KM4132G271B
PIN CONFIGURATION (TOP VIEW)
DQ2 VSSQ DQ1 DQ0 VDD N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VSS DQ31 DQ30 VSSQ DQ29 DQ29 VSSQ DQ30 DQ31 VSS N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VDD DQ0 DQ1 VSSQ DQ2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 Pin QFP Reverse Type 20 x 14 0.65(R) pin Pitch
100 Pin QFP Forward Type 20 x 14 0.65(R) pin Pitch
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DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C DQM3 DQM1 CLK CKE DSF N.C A8 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS BA(A9) N.C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS BA(A9) N.C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C DQM3 DQM1 CLK CKE DSF N.C A8
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A7 A6 A5 A4 VSS N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VDD A3 A2 A1 A0
A0 A1 A2 A3 VDD N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VSS A4 A5 A6 A7
Rev. 2.4 (May 1998)
CMOS SGRAM
KM4132G271B
PIN CONFIGURATION DESCRIPTION
PIN CLK CS NAME System Clock Chip Select INPUT FUNCTION Active on the positive going edge to sample all inputs.
CMOS SGRAM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMi Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one clock +tSS prior to new command. Disable input buffers for power down in standby. Row / Column addresses are multiplexed on the same pins. Row address : RA0 ~ RA8, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and Row precharge. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active.(Byte Masking) Data inputs/outputs are multiplexed on the same pins. Enables write per bit, block write and special mode register set. Power Supply : +3.3V0.3V/Ground Provide isolated Power/Ground to DQs for improved noise immunity.
CKE
Clock Enable
A0 ~ A8 A9(BA) RAS CAS WE DQMi DQi DSF VDD/VSS VDDQ /VSSQ N.C
Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Define Special Function Power Supply /Ground Data Output Power /Ground No Connection
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Rev. 2.4 (May 1998)
KM4132G271B
ABSOLUTE MAXIMUM RATINGS (Voltage referenced to VSS)
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
CMOS SGRAM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V = 0V) SS Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Output Loading Condition Symbol VDD, VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 5 5 see figure 1 Unit V V V V V uA uA Note 1 IOH = -2mA IOL = 2mA Note 2 Note 3 Note
Note : 1. VIL (min) = -1.5V AC(pulse width 5ns). 2. Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 3. Dout is disabled, 0V VOUT VDD.
CAPACITANCE
(VDD/VDDQ = 3.3V, TA = 25C, f = 1MHz) Symbol CIN1 CIN2 COUT Min Max 4 4 5 Unit pF pF pF
Parameter Input capacitance (A0 ~ A9) Input capacitance (CLK, CKE, CS, RAS, CAS, WE, DSF & DQM) Data input/output capacitance (DQ0 ~ DQ31)
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF
Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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Rev. 2.4 (May 1998)
KM4132G271B
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T = 0 to 70C VIH(min) /VIL(max) =2.0V/0.8V) A Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol Test Condition CAS Latency
CMOS SGRAM
Speed -7 180 -8 160 2 2 35 -10 150
Unit
Note
ICC1 ICC2 P ICC2 PS ICC2 N
Burst Length =1 tRC tRC(min), tCC tCC(min), IOL = 0 mA CKE VIL(max), tCC = 15ns CKE VIL(max), CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns CKE VIL(max), CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0 mA, Page Burst All bank Activated, tCCD = tCCD (min) tRC tRC(min) CKE 0.2V tCC tCC(min), IOL=0mA, tBWC (min) 3 2
mA
1
mA
Precharge Standby Current in non power-down mode ICC2 NS Active Standby Current in power-down mode ICC3 P ICC3 PS ICC3 N
mA 15 3 3 50 mA 25 300 180 90 280 180 90 2 210 190 150 210 160 90 mA mA mA 2
mA
Active Standby Current in non power-down mode (One Bank Active)
ICC3 NS
Operating Current (Burst Mode) Refresh Current Self Refresh Current Operating Current (One Bank Block Write)
ICC4 ICC5 ICC6 ICC7
mA
1
Note : 1. Measured with outputs open. Addresses are changed only one time during tcc(min). 2. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
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Rev. 2.4 (May 1998)
KM4132G271B
AC OPERATING TEST CONDITIONS
Parameter AC input levels Input timing measurement reference level Input rise and fall time(See note 3) Output timing measurement reference level Output load condition
3.3V
CMOS SGRAM
(VDD = 3.3V0.3V, TA = 0 to 70C) Value Vih/Vil = 2.4V / 0.4V 1.4V
tR/tF=1ns/ 1ns
1.4V See Fig. 2 Vtt = 1.4V
1200 Output 870 * * * 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0=50 *
50
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
AC CHARACTERISTICS
Parameter
(AC operating conditions unless otherwise noted) Symbol Min 7 12 tSAC tOH tCH tCL tSS tSH tSLZ 2.5 2.5 2.5 2 1 1 6 8 6 8 -7 Max 1000 Min 8 12 2.5 3 3 2.5 1 1 6.5 8 6.5 8 -8 Max 1000 Min 10 13 2.5 3.5 3.5 2.5 1 1 7 9 7 9 ns ns ns ns ns ns ns 2 3 3 3 3 2 ns 1, 2 -10 Max 1000 ns 1 Unit Note
CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z
CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2
tCC
CAS latency=3 CAS latency=2
tSHZ
* All AC parameters are measured from half to half. Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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Rev. 2.4 (May 1998)
KM4132G271B
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to new col. address delay Last data in to row precharge Last data in to burst stop Col. address to col. address delay Block write data-in to PRE command delay Block write cycle time Number of valid output data Symbol -7 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) tBPL(min) tBWC(min) CAS latency=3 CAS latency=2 70 14 16 21 49 Version -8 16 16 20 48 100 70 1 1 1 1 1 1 2 1 70 -10 20 20 20 50
CMOS SGRAM
Unit ns ns ns ns us ns CLK CLK CLK CLK CLK CLK CLK
Note 1 1 1 1
1 2 2 2 3
1, 3 4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. This parameter means minimum CAS to CAS delay at block write cycle only. 4. In case of row precharge interrupt, auto precharge and read burst stop.
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Rev. 2.4 (May 1998)
KM4132G271B
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Special Mode Register Set Refresh Auto Refresh Entry Self Refresh Bank Active & Row Addr. Exit L H H L H L H Write Per Bit Disable Write Per Bit Enable H X L H L H H X L H X L H X H H X H L H L X X X X L L L H CKEn-1 CKEn H X CS L RAS CAS L L WE L
CMOS SGRAM
DSF DQM A9 L H L X X X A8 A7~ A0 Note 1, 2 1,2,7 3 3 X 3 3 V Row Address L H H X L H L L L X V L H H H X X X L L L L H Exit Entry L H H L X L H Exit L H H X L H H X H L H H H L H X X H X V X X H X H X X L H H H X X H X V X L L L H X X H X V X V X V X X X 8 X X X X X X H L L X X X V X Entry H L X X X L H V L H X X Column Address Column Address Column Address 4, 5 4,5,9 V 4 4, 6 4, 5 4,5,6,9 4, 5 4,5,6,9 7
OP CODE
Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable Block Write & Column Addr. Burst Stop Precharge Bank Selection Both Banks Clock Suspend or Active Power Down Auto Precharge Disable Auto Precharge Enable
H
Precharge Power Down Mode
DQM No Operation Command
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A9 : Program keys. (@MRS) A5, A6 : LMR or LCR select. (@SMRS) Color register exists only one per DQi which both banks share. So dose Mask Register. Color or mask is loaded into chip through DQ pin. 2. MRS can be issued only at both banks precharge state. SMRS can be issued only if DQs are idle. A new command can be issued at the next clock of MRS/SMRS.
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Rev. 2.4 (May 1998)
KM4132G271B
SIMPLIFIED TRUTH TABLE
3. Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without Row precharge command is meant by "Auto". Auto/Self refresh can be issued only at both precharge state. 4. A9 : Bank select address. If "Low" at read, (block) write, Row active and precharge, bank A is selected. If "High" at read, (block) write, Row active and precharge, bank B is selected. If A8 is "High" at Row precharge, A9 is ignored and both banks are selected. 5. It is determined at Row active cycle. whether Normal/Block write operates in write per bit mode or not. For A bank write, at A bank Row active, for B bank write, at B bank Row active. Terminology : Write per bit =I/O mask (Block) Write with write per bit mode=Masked(Block) Write
CMOS SGRAM
6. During burst read or write with auto precharge, new read/(block) write command cannot be issued. Another bank read/(block) write command can be issued at tRP after the end of burst. 7. Burst stop command is valid only at full page burst length. 8. DQM sampled at positive going edge of a CLK. masks the data-in at the very CLK(Write DQM latency is 0) but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2) 9. Graphic features added to SDRAMs original features. If DSF is tied to low, graphic functions are disabled and chip operates as a 8M SDRAM with 32 DQ s.
SGRAM vs SDRAM
Function DSF SGRAM Function L MRS H L Bank Active with Write per bit Disable Bank Active H Bank Active with Write per bit Enable L Normal Write Write H Block Write
MRS
SMRS
If DSF is low, SGRAM functionality is identical to SDRAM functionality . SGRAM can be used as an unified memory by the appropriate DSF control --> SGRAM=Graphic Memory + Main Memory
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Rev. 2.4 (May 1998)
KM4132G271B
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS Address Function A9 W.B.L
(Note 1)
CMOS SGRAM
A8 TM
A7
A6
A5 CAS Latency
A4
A3 BT
A2
A1 Burst Length
A0
Test Mode A8 0 0 1 1 A7 0 1 0 1 Write Burst Length A9 0 1 Length Burst Single Bit Type Mode Register Set Vendor Use Only A6 0 0 0 0 1 1 1 1
CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 2 3 Reserved Reserved Reserved Reserved A3 0 1
Burst Type Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
Burst Length BT=0 1 2 4 8 Reserved Reserved Reserved 256(Full) BT=1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved
(Note 2)
Special Mode Register Programmed with SMRS Address Function A9 A8 X A7 A6 LC A5 LM A4 A3 A2 X A1 A0
Load Color A6 0 1 Function Disable Enable
Load Mask A5 0 1 Function Disable Enable
(Note 3)
POWER UP SEQUENCE
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. The full column burst(256bit) is available only at Sequential mode of burst type. 3. If LC and LM both high(1), data of mask and color register will be unknown.
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Rev. 2.4 (May 1998)
KM4132G271B
BURST SEQUENCE (BURST LENGTH = 4)
Initial address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 Sequential
CMOS SGRAM
Interleave 2 3 0 1 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Sequential Interleave
PIXEL to DQ MAPPING(at BLOCK WRITE)
Column address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 3 Byte I/O31 - I/O24 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 2 Byte I/O23 - I/O16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 1 Byte I/O15 - I/O8 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 0 Byte I/O7 - I/O0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
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Rev. 2.4 (May 1998)
KM4132G271B
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock for proper functionality and ICC specifications.
CMOS SGRAM
POWER-UP
The following sequence is recommended for POWER UP 1. Power must be applied to either CKE and DQM inputs to pull them high and other pins are NOP condition at the inputs before or along with VDD(and VDDQ ) supply. The clock signal must also be asserted at the same time. 2. After VDD reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in NOP condition. 3. Both banks must be precharged now. 4. Perform a minimum of 2 Auto refresh cycles to stabilize the internal circuitry. 5. Perform a MODE REGISTER SET cycle to program the CAS latency, burst length and burst type as the default value of mode register is undefined. At the end of one clock cycle from the mode register set cycle, the device is ready for operation. When the above sequence is used for Power-up, all the outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. cf.) Sequence of 4 & 5 may be changed.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SGRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SGRAM enters the power down mode from the next clock cycle. The SGRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "tSS + 1CLOCK " before the high going edge of the clock, then the SGRAM becomes active from the same clock edge accepting all the input commands.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various operating modes of SGRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SGRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SGRAM. The mode register is written by asserting low on CS, RAS, CAS, WE and DSF (The SGRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A8 and A9 in the same cycle as CS, RAS, CAS, WE and DSF going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0 ~ A2, burst type uses A3, addressing mode uses A4 ~ A6, A7 ~ A8 are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7 ~ A8 must be set to low for normal SGRAM operation. Refer to table for specific codes for various burst length, addressing modes and CAS latencies.
BANK SELECT (A9)
This SGRAM is organized as two independent banks of 131,072 words x 32 bits memory arrays. The A9 inputs is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. When A9 is asserted low, bank A is selected. When A9 is asserted high, bank B is selected. The bank select A9 is latched at bank activate, read, write mode register set and precharge operations.
ADDRESS INPUT (A0 ~ A8)
The 17 address bits required to decode the 131,072 word locations are multiplexed into 9 address input pins(A0~A8). The 9 bit row address is latched along with RAS and A9 during bank activate command. The 8 bit column address is latched along with CAS, WE and A9 during read or write command.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SGRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE, DSF and all the address inputs are ignored.
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Rev. 2.4 (May 1998)
KM4132G271B
DEVICE OPERATIONS
BANK ACTIVATE
The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of tRCD (min) from the time of bank activation. tRCD (min) is an internal timing parameter of SGRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding off the result to the next higher integer. The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SGRAM is high requiring some time for power supplies to recover before the other bank can be sensed reliably. tRRD (min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max). The number of cycles for both tRAS (min) and tRAS (max) can be calculated similar to tRCD specification.
CMOS SGRAM
cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrapped around. The write burst can also be terminated by using DQM for blocking data and precharging the bank " tRDL " after the last data input to be written into the active row. See DQM OPERATION also.
DQM OPERATION
The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SGRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. DQM is also used for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. DQM masks the DQs by a byte regardless that the corresponding DQs are in a state of WPB masking or Pixel masking. Please refer to DQM timing diagram also.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD (min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid only at full page burst length where the output does not go into high impedance at the end of burst and the burst is wrapped around..
PRECHARGE
The precharge operation is performed on an active bank by asserting low on CS, RAS, WE and A8 with valid A9 of the bank to be precharged. The precharge command can be asserted anytime after tRAS (min) is satisfied from the bank activate command in the desired bank. "tRP" is defined as the minimum time required to precharge a bank. The minimum number of clock cycles required to complete row precharge is calculated by dividing "tRP" with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS (max). Therefore, each bank has to be precharged within tRAS (max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again.
BURST WRITE
The burst write command is similar to burst read command, and is used to write data into the SGRAM on consecutive clock
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DEVICE OPERATIONS (Continued)
Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc. is possible only when both banks are in idle state.
CMOS SGRAM
SELF REFRESH
The self refresh is another refresh mode available in the SGRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SGRAM. In self refresh mode, the SGRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOPs for a minimum time of "tRC" before the SGRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 1024 auto refresh cycles immediately after exiting self refresh.
AUTO PRECHARGE
The precharge operation can also be performed by using auto precharge. The SGRAM internally generates the timing to satisfy tRAS (min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A8. If burst read or burst write command is issued with low on A8, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with high on A8 after both banks have satisfied tRAS (min) requirement, performs precharge on both banks. At the end of tRP after performing precharge all, both banks are in idle state.
DEFINE SPECIAL FUNCTION(DSF)
The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM functions as 128K x 32 x2 Bank SDRAM. SGRAM can be used as an unified memory by the appropriate DSF command. All the graphic function modes can be entered only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands. SDRAM functions such as RAS Active, Write, and WCBR change to SGRAM functions such as RAS Active with WPB, Block Write and SWCBR respectively. See the section below for the graphic functions that DSF controls.
AUTO REFRESH
The storage cells of SGRAM need to be refreshed every 16ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS,RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by "tRC(min)". The minimum number of clock cycles required can be calculated by driving "tRC" with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOPs until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 1024 auto refresh cycles once in 16ms.
SPECIAL MODE REGISTER SET(SMRS)
There are two kinds of special mode registers in SGRAM.One is color register and the other is mask register. Those usage will be explained in the "WRITE PER BIT" and "BLOCK WRITE" sections. When A5 and DSF goes high in the same cycle as CS, RAS, CAS and WE going low, Load Mask Register(LMR) process is executed and the mask registers are filled with the masks for associated DQs through DQ pins. And when A6 and DSF goes high in the same cycle as CS, RAS, CAS and WE going low, Load Color Register(LCR) process is executed and the color register is filled with color data for associated DQs through the DQ pins. If both A5 and A6 are high at SMRS, data of mask and color cycle are required to complete the write in the mask register and the color register at LMR and LCR respectively. A new command can be issued in the next clock of LMR or LCR. SMRS, compared with MRS, can be issued at the active state under the condition that DQs are idle. As in write operation, SMRS accepts the data needed through DQ pins. Therefore bus contention must be avoided. The more detailed materials can be obtained by referring corresponding timing diagram.
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DEVICE OPERATIONS (Continued)
WRITE PER BIT
Write per bit(i.e. I/O mask mode) for SGRAM is a function that selectively masks bits of data being written to the devices. The mask is stored in an internal register and applied to each bit of data written when the mask is enabled. Bank active command with DSF=High enables write per bit for associated bank. Bank active command with DSF=Low disables write per bit for the associated bank. The mask used for write per bit operations is stored in the mask register accessed by SWCBR(Special Mode Register Set Command). When a mask bit=1, the associated data bit is written when a write command is executed and write per bit has been enabled for the bank being written. When a mask bit=0, the associated data bit is unaltered when a write command is executed and the write per bit has been enabled for the bank being written. No additional timing conditions are required for write per bit operations. Write per bit writes can be either single write, burst writes or block writes. DQM masking is the same for write per bit and non-WPB write.
CMOS SGRAM
Timing Diagram to lllustrate tBWC
0 CLOCK CKE CS RAS CAS WE DSF 1 CLK BW HIGH 1 2
BLOCK WRITE
Block write is a feature allowing the simultaneous writing of consecutive 8 columns of data within a RAM device during a single access cycle. During block write the data to be written comes from an internal "color" register and DQ I/O pins are used for independent column selection. The block of column to be written is aligned on 8 column boundaries and is defined by the column address with the 3 LSBs ignored. Write command with DSF=1 enables block write for the associated bank. A write command with DSF=0 enables normal write for the associated bank. The block width is 8 column where column="n" bits for by "n" part. The color register is the same width as the data port of the chip.It is written via a SWCBR where data present on the DQ pin is to be coupled into the internal color register. The color register provides the data masked by the DQ column select, WPB mask(If enabled), and DQM byte mask. Column data masking(Pixel masking) is provided on an individual column basis for each byte of data. The column mask is driven on the DQ pins during a block write command. The DQ column mask function is segmented on a per bit basis(i.e. DQ[0:7] provides the column mask for data bits[0:7], DQ[8:15] provides the column mask for data bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9 masks column [1] for data bits [8:15], etc). Block writes are always non-burst, independent of the burst length that has been programmed into the mode register. Back to back block writes are allowed provided that the specified block write cycle time(tBWC ) is satisfied. If write per bit was enabled by the bank active command with DSF=1, then write per bit masking of the color register data is enabled. If write per bit was disabled by a bank active command with DSF=0, the write per bit masking of the color register data is disabled. DQM masking provides independent data byte masking during block write exactly the same as it does during normal write operations, except that the control is extended to the consecutive 8 columns of the block write.
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SUMMARY OF 1M Byte SGRAM BASIC FEATURES AND BENEFITS
Features 128K x 32 x 2 SGRAM Benefits
CMOS SGRAM
Interface
Synchronous
Better interaction between memory and system without wait-state of asynchronous DRAM. High speed vertical and horizontal drawing. High operating frequency allows performance gain for SCROLL, FILL, and BitBLT. Pseudo-infinite row length by on-chip interleaving operation. Hidden row activation and precharge. High speed vertical and horizontal drawing. High speed vertical and horizontal drawing. Programmable burst of 1, 2, ,4, 8 and full page transfer per column addresses. Programmable burst of 1, 2, ,4, 8 and full page transfer per column addresses. Switch to burst length of 1 at write without MRS. Compatible with Intel and Motorola CPU based system. Programmable CAS latency. High speed FILL, CLEAR, Text with color registers. Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and byte masking functions. A and B bank share. Write-per-bit capability(bit plane masking). A and B banks share. Byte masking(pixel masking for 8bpp system) for data-out/in Each bit of the mask register directly controls a corresponding bit plane. Byte masking(pixel masking for 8bpp system) for color by DQi
Bank Page Depth / 1 Row Total Page Depth Burst Length(Read)
2 ea 256 bit 1024 bytes 1, 2, 4, 8 Full Page
1, 2, 4, 8 Full Page Burst Length(Write) BRSW Burst Type CAS Latency Block Write Sequential & Interleave 2, 3 8 Columns
Color Register Mask Register Mask function
1 ea. 1 ea. DQM0-3 Write per bit Pixel Mask at Block Write
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BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1) Clock Suspended During Write (BL=4) CLK CMD CKE
Masked by CKE
CMOS SGRAM
2) Clock Suspended During Read (BL=4)
WR
RD
Masked by CKE
Internal CLK
DQ(CL2) DQ(CL3)
D0 D0
D1 D1
D2 D2 Not Written
D3 D3
Q0
D0 Q1 Q0
Q2 Q1
Q3 Q2 Q3
Suspended Dout
Note : CKE to CLK disable/enable=1 clock
2. DQM Operation
1) Write Mask (BL=4) CLK CMD DQMi
Note 1
2) Read Mask (BL=4)
WR
RD
Masked by DQM
DQ(CL2) DQ(CL3)
D0 D0
D1 D1
D3 D3
Q0
Masked by DQM Hi-Z
Q2 Q1
Q3 Q2 Q3
Hi-Z
DQM to Data-in Mask = 0CLK
DQM to Data-out Mask = 2CLK
3) DQM with Clock Suspended (Full Page Read) CLK CMD CKE DQM DQ(CL2) DQ(CL3) Q0
Hi-Z Hi-Z
Note 2
RD
Q2 Q1
Hi-Z Hi-Z
Q4 Q3
Hi-Z Hi-Z
Q6 Q5
Q7 Q6
Q8 Q7
*Note : 1. There are 4 DQMi(i=0~3). Each DQMi masks 8 DQis.(1 Byte, 1 Pixel for 8 bpp) 2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE " L".
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3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4) Note 1 CLK CMD ADD DQ(CL2) DQ(CL3) RD A RD B QA0 QB0 QA0 QB1 QB0 QB2 QB1 QB3 QB2 QB3
CMOS SGRAM
tCCD
Note 2
2) Write interrupted by(Block) Write (BL=2) CLK CMD WR WR
Note 2
3) Write interrupted by Read (BL=2)
WR
BW
Note 2
WR
RD
Note 2
tCCD
ADD DQ A B
tCCD
C D
tCCD
A B
Note 4
DA0
DB0
DB1
DC0
Pixel
DQ(CL2) DQ(CL3)
DA0 DA0
QB0
QB1 QB0 QB1
tCDL
Note 3
tCDL
Note 3
tCDL
Note 3
4) Block Write to Block Write CLK CMD ADD BW A BW B
Note 4
DQ
Pixel Pixel
tBWC
Note 5
*Note : 1. By " Interrupt ", It is possible to stop burst read/write by external command before the end of burst. By "CAS Interrupt" , to stop burst read/write by CAS access ; read, write and block write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) 4. Pixel :Pixel mask. 5. tBWC : Block write minimum cycle time.
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4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(1) CL=2, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ Q0
Hi-Z
Note 1
CMOS SGRAM
RD
WR
D0 RD
D1 WR
D2
D3
Hi-Z
D0
D1 WR
D2
D3
RD
Hi-Z
D0
D1 WR
D2
D3
RD
D0
D1
D2
D3
(2) CL=3, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ v) CMD DQM DQ Q0
Hi-Z
Note 2
RD
WR
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
Hi-Z
D0
D1 WR
D2
D3
RD
D0
D1
D2
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. 2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
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5. Write Interrupted by Precharge & DQM
CLK
Note 2
CMOS SGRAM
CMD DQM DQ
WR
PRE
Note 1
D0
D1
D2
D3
Masked by DQM
*Note : 1. To inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3 PRE 2) Block Write CLK CMD DQ BW Pixel PRE
tRDL
Note 1
tBPL
Note 1
3) Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0 PRE Q2 Q1 Q3 Q2
1 Note 2
Q3
2
7. Auto Precharge
1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3
Note 3 Auto Precharge Starts
2) Block Write CLK CMD DQ (CL 2, 3) BW Pixel
tBPL
tRP
3) Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0
Note 3 Auto Precharge Starts
Q2 Q1
Q3 Q2 Q3
Note 3 Auto Precharge Starts
*Note : 1. tBPL : Block write data-in to PRE command delay 2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively. 3. The row active command of the precharge bank can be issued after t RP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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8. Burst Stop & Precharge Interrupt
1) Write Interrupted by Precharge (BL=4) CLK CMD DQM DQ D0 D1 D2 D3
Note 1
CMOS SGRAM
2) Write Burst Stop (Full Page Only) CLK
WR
PRE
CMD
WR
STOP
DQ
D0
D1
D2
tRDL
tBDL
3) Read Interrupted by Precharge (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD PRE
Note 3 1
4) Read Burst Stop (Full Page Only) CLK CMD Q1 Q0 Q1
2
RD
STOP
Note 3
Q0
DQ(CL2) DQ(CL3)
Q0
Q1 Q0
1
2
Q1
9. MRS & SMRS
1) Mode Register Set CLK
Note 4
2) Special Mode Register Set CLK
CMD
PRE
MRS ACT
CMD
SMRS ACT SMRS SMRS BW
1CLK 1CLK 1CLK 1CLK
tRP
1CLK
*Note : 1. tRDL : 1 CLK, Last Data in to Row Precharge. 2. tBDL : 1 CLK, Last Data in to Burst Stop Delay. 3. Number of valid output data after Row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely. 4. PRE : Both banks precharge if necessary. MRS can be issued only at all bank precharge state.
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10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal CLK CMD
Note 1
CMOS SGRAM
2) Power Down (=Precharge Power Down) Exit CLK
tSS
CKE Internal CLK RD CMD
Note 2
tSS
NOP ACT
11. Auto Refresh & Self Refresh
1) Auto Refresh Note 3 CLK
Note 4 o Note 5
CMD CKE
PRE
AR
o o o
CMD
tRP
2) Self Refresh Note 6
tRC
o
CLK
Note 4
o
CMD CKE
PRE
SR
o o o o
CMD
tRP
*Note : 1. Active power down : one or more bank active state. 2. Precharge power down : both bank precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after Auto Refresh command.
tRC
During tRC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, both banks must be idle state. 5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are perfomed internally. After self refresh entry, self refresh mode is kept while CKE is LOW. During self refresh mode, all inputs expect CKE will be don t cared, and outputs will be in Hi-Z state. During tRC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (1K cycles) is recommended.
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12. About Burst Type Control
Sequential Counting Basic MODE Interleave Counting
CMOS SGRAM
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8) BL=1, 2, 4, 8 and full page wrap around. At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting At MRS A3 = "1".(See to Interleave Counting Mode) Starting Address LSB 3 bits A0-2 should be "000" or "111".@BL=8. -- if LSB="000" : Increment Counting. -- if LSB="111" : Decrement Counting. For Example,(Assume Addresses except LSB 3 bits are all 0, BL=8) -- @ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7 -- @ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0 At BL=4, same applications are possible. As above example, at Interleave Counting mode, by confining starting address to some values, Pseudo-Decrement Counting Mode can be realized. See the BURST SEQUENCE TABLE carefully. At MRS A3 = "0".(See to Sequential Counting Mode) A0-2 = "111".(See to Full Page Mode) Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized. -- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3(BL=8) -- @ Pseudo-Binary Counting, Accessed Column in order 3-4-5-6-7-8-9-10(Burst Stop command) Note. The next column address of 256 is 0. Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
PseudoDecrement Sequential Counting PseudoMODE
PseudoBinary Counting
Random MODE
Random column Access tCCD = 1 CLK
13. About Burst Length Control
1 2
Basic MODE At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "001". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "010". At MRS A2,1,0 = "011". At MRS A2,1,0 = "111". Wrap around mode(Infinite burst length)should be stopped by burst stop, RAS interrupt or CAS interrupt. At MRS A9 = "1". Read burst =1, 2, 4, 8, full page/write Burst =1 At auto precharge of write, tRAS should not be violated. 8 Column Block Write. LSB A0-2 are ignored. Burst length=1. tBWC should not be violated. At auto precharge, tRAS should not be violated. tBDL = 1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively Using burst stop command, it is possible only at full page burst length. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL = 1 with DQM, valid DQ after burst stop is 1, 2 for CL= 2, 3 respectively During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, CAS interrupt can not be issued.
4 8
Full Page
BRSW Special MODE
Block Write
Random MODE
Burst Stop
RAS Interrupt (Interrupted by Precharge) Interrupt MODE CAS Interrupt
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14. Mask Functions
1) Normal Write I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. If bit plane 0, 3, 7, 9, 15, 22, 24, and 31 keep the original value. i) STEP c SMRS(LMR) :Load mask[31-0]="0111, 1110, 1011, 1111, 0111, 1101, 0111, 0110" e Row Active with DSF "H" :Write Per Bit Mode Enable e Perform Normal Write. i) ILLUSTRATION I/O(=DQ) External Data-in DQMi Mask Register Before Write After Write 31 DQM3=0 01111110 00000000 01111110 24 23 DQM2=0 10111111 00000000 10111111 16 15 DQM1=0 01111101 11111111 10000010 8 7
CMOS SGRAM
0 DQM0=1
11111111
11111111
00000000
00000000 01110110 11111111 11111111
Note 1
2) Block Write Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING TABLE. If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color. Assume 8bpp, White = "0000,0000", Red="1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011" i) STEP c SMRS(LCR) :Load color(for 8bpp, through x32 DQ color0-3 are loaded into color registers) Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red) = "1100,0011, 1110, 0001, 0000, 1111, 1010, 0011" e Row Active with DSF "L" : I/O Mask by Write Per Bit Mode Disable e Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110" i) ILLUSTRATION I/O(=DQ) DQMi Color Register 000 Before Block Write & DQ (Pixel data) 001 010 011 100 101 110 111 000 001 After Block Write 010 011 100 101 110 111
Note 2
31 DQM3=0
24
23 DQM2=0
16
15 DQM1=0
8
7 DQM0=1
0
Color3=Blue White DQ24=H White DQ25=H White DQ26=H White DQ27=L White DQ28=H White DQ29=H White DQ30=H White DQ31=L Blue Blue Blue White Blue Blue Blue White
Color2=Green White DQ16=H White DQ17=H White DQ18=L White DQ19=H White DQ20=H White DQ21=H White DQ22=L White DQ23=H Green Green White Green Green Green White Green
Color1=Yellow White DQ8=H White DQ9=L White DQ10=H White DQ11=H White DQ12=H White DQ13=L White DQ14=H White DQ15=H Yellow White Yellow Yellow Yellow White Yellow Yellow
Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White White
*Note :1. DQM byte masking. 2. At normal write, ONE column is selected among columns decorded by A 2-0 (000-111). At block write, instead of ignored address A 2-0 , DQ0-31 control each pixel.
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(Continued)
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING TABLE. Assume 8bpp, White = "0000,0000", Red="1010,0011", Green ="1110,0001", Yellow ="0000,1111", Blue ="1100,0011"
CMOS SGRAM
i) STEP c SMRS(LCR) : Load color(for 8bpp, through x 32 DQ color0-3 are loaded into color registers) Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red) = "1100,0011,1110,0001,0000,1111,1010,0011" e SMRS(LMR ): Load mask. Mask[31-0] ="1111,1111,1101,1101, 0100,0010,0111,0110" --> Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Maskin g e Row Active with DSF "H" : I/O Mask by Write Per Bit Mode Enable e Block Write with DQ[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110" (Pixel Mask) i) ILLUSTRATION I/O(=DQ) Color Register DQMi Mask Register Before Write 31 24 23 16 15 8 7 0
Blue 11000011 DQM3=0 11111111 Yellow 00001111 Blue 11000011
Green 11100001 DQM2=0 11011101 Yellow 00001111 Blue 11000011
Yellow 00001111 DQM1=0 01000010 Green 11100001 Red 10100011
Red 10100011 DQM0=1 01110110 White 00000000 White 00000000
Note 1
After Write
I/O(=DQ) DQMi Color Register 000 Before Block Write & DQ (Pixel data) 001 010 011 100 101 110 111 000 001 After Block Write 010 011 100 101 110 111
Note 2
31 DQM3=0
24
23 DQM2=0
16
15 DQM1=0
8
7 DQM0=1
0
Color3=Blue Yellow DQ24=H Yellow DQ25=H Yellow DQ26=H Yellow DQ27=L Yellow DQ28=H Yellow DQ29=H Yellow DQ30=H Yellow DQ31=L Blue Blue Blue Yellow Blue Blue Blue Yellow
Color2=Green Yellow DQ16=H Yellow DQ17=H Yellow DQ18=H Yellow DQ19=H Yellow DQ20=H Yellow DQ21=H Yellow DQ22=H Yellow DQ23=H Blue Blue Blue Blue Blue Blue Blue Blue
Color1=Yellow Green DQ8=H Green DQ9=L Green DQ10 =H Green DQ11=L Green DQ12 =H Green DQ13=L Green DQ14 =H Green DQ15=L Red Green Red Green Red Green Red Green
Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White White
Note 1
PIXEL MASK
I/O MASK
PIXEL & I/O MASK
BYTE MASK
*Note :1. DQM byte masking. 2. At normal write, ONE column is selected among columns decorded by A 2-0 (000-111). At block write, instead of ignored address A 2-0 , DQ0-31 control each pixel.
- 27
Rev. 2.4 (May 1998)
KM4132G271B
Power On Sequence & Auto Refresh
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CKE CS
High level is necessary o o
tRP
tRC o o o
RAS
o
o
o o
CAS
o
ADDR
o o
o o KEY
Ra
A9/BA
o o
o o
KEY
BS
A8/AP
o o
o o
KEY
Ra
o
o o
WE
o
DSF
o o
o o
DQM
o High level is necessary
o
High-Z
DQ
o
o
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (Write per Bit Enable or Disable)
: Dont care
- 28
Rev. 2.4 (May 1998)
KM4132G271B
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
tCC
CKE
*Note 1
tCL
HIGH
tRAS tRC tSH tRP
CS
tRCD tSH
RAS
tSS
tSS
CAS
tCCD tSH
tSH
ADDR
Ra
tSS
Ca
tSS
Cb Cc Rb
tSS
*Note 2 *Note 2,3
tSH
*Note 2,3 *Note 2,3 *Note 4 *Note 2
A9
BS
BS
BS
BS
BS
BS
*Note 3
*Note 3
*Note 3
*Note 4
A8
Ra
Rb
tSH
WE
tSS
*Note 5 *Note 6 *Note 3 *Note 5
DSF
tSS
DQM
tSH tSS tSH
tRAC
DQ
tSAC
Qa Db
tSH
Qc
tSLZ
tOH tSHZ
tSS
Row Active (Write per Bit Enable or Disable)
Read
Write or Block Write
Read Precharge
Row Active (Write per Bit Enable or Disable)
: Dont care
- 29
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
*Note : 1. All input can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by A 9.
A9 0 1
Active & Read/Write Bank A Bank B
3. Enable and disable auto precharge function are controlled by A 8 in read/write command.
A8 0
A9 0 1
Operation Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst.
1
0 1
4. A8 and A9 control bank precharge when precharge command is asserted.
A8 0 0 1
A9 0 1 X
Precharge Bank A Bank B Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
A9 0
DSF L H
Operation Bank A row active, disable write per bit function for bank A Bank A row active, enable write per bit function for bank A Bank B row active, disable write per bit function for bank B Bank B row active, enable write per bit function for bank B
1
L H
6. Block write/normal write is controlled by DSF.
DSF L H
Operation
Minimum cycle time
Normal write Block write
tCCD tBWC
- 30
Rev. 2.4 (May 1998)
KM4132G271B
Read & Write Cycle at Same Bank @Burst Length=4
0 CLOCK CKE HIGH
*Note 1
CMOS SGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRC
CS
tRCD
RAS
*Note 2
CAS ADDR A9 A8
Ra Rb Ra Ca0 Rb Cb0
WE
DSF
DQM
tOH
DQ (CL=2)
Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
tRAC
*Note 3
tSAC tOH
tSHZ
*Note 4
tRDL
DQ (CL=3)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
tRAC
*Note 3
tSAC
tSHZ
*Note 4
tRDL
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
: Dont care *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row enters precharge. Last valid output will be Hi-Z after
tSHZ
from the clcok.
3. Access time from Row address. tCC *(tRCD + CAS latency - 1) + 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8) At Full page bit burst, burst is wrap-around.
tSAC
- 31
Rev. 2.4 (May 1998)
KM4132G271B
Page Read & Write Cycle at Same Bank @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CS
tRCD
RAS CAS ADDR A9
Ra Ca0 Cb0 Cc0 Cd0
A8
Ra
tCDL
WE
*Note 2
tRDL
DSF
*Note 1
*Note 3
DQM
DQ (CL=2)
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
DQ (CL=3)
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
: Dont care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
- 32
Rev. 2.4 (May 1998)
KM4132G271B
Block Write cycle(with Auto Precharge)
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CS
RAS CAS
*Note 2
ADDR A9 A8
RAa
CAa
CAb
RBa
CBa
CBb
RAa
RBa
WE
DSF
tBWC
DQM
*Note 1
DQ
Pixel Mask
Pixel Mask
Pixel Mask
Pixel Mask
Row Active with Write-per-Bit Enable (A-Bank)
Masked Block Write (A-Bank) Masked Block Write with Auto Precharge (A-Bank)
Row Active (B-Bank)
Block Write with Auto Precharge (B-Bank) Block Write (B-Bank)
: Dont care
*Note : 1. Column Mask(DQi=L : Mask, DQi=H :Non Mask) 2. At Block Write, CA0~2 are ignored.
- 33
Rev. 2.4 (May 1998)
KM4132G271B
SMRS and Block/Normal Write @ Burst Length=4
0 CLOCK CKE CS RAS CAS
*Note 1
CMOS SGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
A0-2 A3,4,7 A5 A6 A8
RAa
RBa
CBa
RAa
CAa
RBa
CBa
RAa
CAa
RBa
CBa
RAa
CAa
RBa
CBa
RAa
RBa
A9 WE DSF
DQM DQ
Color I/O Mask Pixel Mask I/O Mask Color
DBa0 DBa1 DBa2 DBa3
Load Color Register
Load Mask Register Masked Block Write (A-Bank)
Row Active with WPB* Enable (A-Bank)
Row Active with WPB* Enable (B-Bank)
Load Color Register Masked Write with Auto Precharge (B-Bank) WPB* : Write-Per-Bit
Load Mask Register
: Dont care
*Note :
1. At the next clock of special mode set command, new command is possible.
- 34
Rev. 2.4 (May 1998)
KM4132G271B
Page Read Cycle at Different Bank @Burst Length=4
0 CLOCK CKE
*Note 1
CMOS SGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
CS RAS
*Note 2
CAS ADDR A9 A8 WE DSF LOW
RAa CAa RBb CBb CAc CBd CAe
RAa
RBb
DQM
DQ (CL=2)
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1 QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
DQ (CL=3)
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1 QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
Row Active (A-Bank)
Row Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
: Dont care
*Note :
1. CS can be dont care when RAS, CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
- 35
Rev. 2.4 (May 1998)
KM4132G271B
Page Write Cycle at Different Bank @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CS
RAS
CAS
ADDR
RAa
Key
CAa
RBb
CBb
CAc
CBd
A9
A8
RAa
RBb
tCDL
WE DSF
DQM
DQ
Mask
DAa0
DAa1
DAa2
DAa3
DBb0
DBb1
DBb2
DBb3
DAc0
DAc1
DAc2
DAc3
DBd0
DBd1
DBd2
DBd3
Load Mask Register Row Active with Write-Per-Bit enable (A-Bank)
Row Active (B-Bank) Masked Write (A-Bank)
Write (B-Bank)
Masked Write with auto precharge (A-Bank)
Write with auto Precharge (B-Bank)
: Dont care
- 36
Rev. 2.4 (May 1998)
KM4132G271B
Read & Write Cycle at Different Bank @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CS RAS CAS ADDR A9 A8 WE DSF DQM
RAc RAa CAa RBb CBb RAc CAc
RAa
RBb
tCDL
*Note 1
DQ (CL=2)
QAa0
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
QAc0
QAc1
QAc2
DQ (CL=3)
QAa0
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
QAc0
QAc1
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (B-Bank)
Write (B-Bank) Row Active (A-Bank)
Read (A-Bank)
: Dont care
*Note :
1. tCDL should be met to complete write.
- 37
Rev. 2.4 (May 1998)
KM4132G271B
Read & Write Cycle with Auto Precharge I @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CS RAS CAS ADDR A9 A8 WE DSF
RAa RBb RAa RBb CAa CBb
DQMi
DQ (CL=2)
QAa0
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
DQ (CL=3)
QAa0
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
: Dont care
*Note : 1.
tRCD
should be controlled to meet minimum
tRAS
before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode and Block write)
- 38
Rev. 2.4 (May 1998)
KM4132G271B
Read & Write Cycle with Auto Precharge II @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CS
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
Ra
Ca
A9
A8
Ra
Rb
Ra
WE
DSF
DQM
DQ (CL=2)
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Da0
Da1
DQ (CL=3)
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Da0
Da1
Row Active (A-Bank)
Read with Auto Pre charge (A-Bank) Row Active (B-Bank)
Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank) *Note 1
Precharge (B-Bank)
Row Active (A-Bank)
Write with Auto Precharge (A-Bank)
: Dont care *Note: 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at B Bank read command input point . - any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
- 39
Rev. 2.4 (May 1998)
KM4132G271B
Read & Write Cycle with Auto Precharge III @Burst Length=4
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
A9
A8
Ra
Rb
WE
DSF
DQM
DQ (CL=2)
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
DQ (CL=3)
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
*Note 1
Row Active (A-Bank)
Read with Auto Precharge (A-Bank)
Auto Precharge Start Point (A-Bank) Row Active (B-Bank)
Read with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
: Dont care *Note : 1. Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point
- 40
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full page Only)
0 CLOCK CKE HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CS RAS CAS ADDR A9
*Note 1 *Note 1
RAa
CAa
CAb
A8 WE DSF
RAa
DQM
1 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 1 QAb5
*Note 2
DQ (CL=2)
QAa0
QAa1
QAa2
QAa3
2
2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
DQ (CL=3)
QAa0
QAa1
QAa2
QAa3
QAa4
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
: Dont care
*Note :
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at full page mode.
- 41
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only)
0 CLOCK HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE CS
RAS
CAS
ADDR
RAa
CAa
CAb
A9
*Note 1 *Note 1
A8
RAa tBDL
tRDL
WE
DSF
*Note 3
DQM
*Note 2
DQ
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
: Dont care
*Note :
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell. It is defined by AC parameter of It is defined by AC parameter of
tBDL(=1CLK). tRDL (=1CLK). tRDL
of 1CLK.
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
DQM at write interrupted by precharge command is needed to ensure Input data after Row precharge cycle will be masked internally. 4. Burst stop is valid only at full page burst length.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
- 42
Rev. 2.4 (May 1998)
KM4132G271B
Burst Read Single bit Write Cycle @Burst Length=2, BRSW
0 CLOCK
*Note 1
CMOS SGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
HIGH
CS RAS
*Note 2
CAS ADDR A9 A8 WE DSF DQM
RAa RBb RAc RAa CAa RBb CAb RAc CBc CAd
DQ (CL=2)
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DQ (CL=3)
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
Row Active (A-Bank)
Row Active (B-Bank) Write (A-Bank)
Row Active (A-Bank) Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
Read with Auto Precharge (A-Bank)
: Dont care
*Note :
1. BRSW mode is enabled by setting A 9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that the next cycle starts the precharge. 3. WPB function is also possible at BRSW mode.
tRAS
should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
- 43
Rev. 2.4 (May 1998)
KM4132G271B
Clock suspension & DQM operation cycle @CAS Latency=2, Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMOS SGRAM
16
17
18
19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
A9
A8
Ra
WE
DSF
*Note 1
DQM
DQ
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Dc0
Dc2
tSHZ
tSHZ
Row Active
Read
Clock Suspension
Read
Read DQM Write
Write DQM Clock Suspension : Dont care
*Note :
1. DQM needed to prevent bus contention.
- 44
Rev. 2.4 (May 1998)
KM4132G271B
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
0 CLOCK 1 2 3
o o
*Note 2
CMOS SGRAM
4
5
6
7
8
9
o
10
11
12
13
14
15
16
17
18
19
tSS
CKE
*Note 1
tSS tSS tSS
o
*Note 3
o
o
CS
o
o
o o
RAS
o
o
o o
CAS
o
ADDR
o o
Ra
o o
Ca
A9
o o
o o
A8
o o
Ra
o o
WE
o o
o o
DSF
o o
o o
DQM
o o
o o
DQ
o
o
Qa0
Qa1
Qa2
Precharge Power-down Entry
Precharge Power-down Exit Row Active Active Power-down Entry
Read
Precharge
Active Power-down Exit
: Dont care
*Note :
1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least "1CLK +
tSS"
prior to Row active command.
3. Cannot violate minimum refresh specification. (16ms)
- 45
Rev. 2.4 (May 1998)
KM4132G271B
Self Refresh Entry & Exit Cycle
0 CLOCK
*Note 2 *Note 1
CMOS SGRAM
1
2
3
4
5
6
o o
7
8
9
10
11
12
13
o
14
15
16
17
18
19
*Note 4
tRCmin. tSS
*Note 3
o
*Note 6
CKE
o
tSS
o o
*Note 5
CS
o
o
o o
*Note 7
RAS
*Note 7
o
o
o o
CAS
o
ADDR
o o
o o
A9
o o
o o
A8
o o
o o
WE
o o
o o o o
DSF
o o
DQM
o o
o o
DQ
Hi-Z
o
Hi-Z
Self Refresh Exit
o
Self Refresh Entry *Note : TO ENTER SELF REFRESH MODE
Auto Refresh : Dont care
1. CS, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 1K cycle of burst auto refresh is required before self refresh entry and after self refresh exit
- 46
Rev. 2.4 (May 1998)
KM4132G271B
Mode Register Set Cycle
0 CLOCK CKE CS
*Note 2
CMOS SGRAM
Auto Refresh Cycle
6 7 8 9 10 11 12 13 14 15
o
1
2
3
4
5
16
17
18
19
HIGH
HIGH
o
o
tRC
RAS
*Note 1
o o o
CAS
o o
*Note 3
ADDR
o o
Key
Ra
o
WE
o
o
DSF
o
DQM
o o
DQ
Hi-Z
Hi-Z
o
MRS New Command
Auto Refresh
New Command
: Dont care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, & WE activation and DSF of low at the same clock cycle with address key will set internal mode register. 2. Minimum 1 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table.
- 47
Rev. 2.4 (May 1998)
KM4132G271B
FUNCTION TRUTH TABLE(TABLE 1)
Current State CS H L L L L IDLE L L L L L L L H L L L L Row Active L L L L L L L L H L L L L Read L L L L L L L H L L Write L L L L L RAS X H H H L L L L L L L L X H H H H H H L L L L L L X H H H H H H H L L L L X H H H H H H H CAS X H H L H H H H L L L L X H H L L L L H H H L L L X H H H L L L L H H H L X H H H L L L L WE X H L X H H L L H H L L X H L H H L L H L L H L L X H L L H H L L H L L X X H L L H H L L DSF X X X X L H L H L H L H X X X L H L H X L H X L H X X L H L H L H X L H X X X L H L H L H BA (A9) X X X BA BA BA BA X X X ADDR X X X CA RA RA PA X X X NOP NOP ILLEGAL ILLEGAL ACTION
CMOS SGRAM
NOTE
2 2
Row Active ; Latch Row Address ; Non-IO Mask Row Active ; Latch Row Address ; IO Mask NOP ILLEGAL Auto Refresh or Self Refresh ILLEGAL Mode Register Access Special Mode Register Access NOP NOP ILLEGAL Begin Read ; Latch CA ; Determine AP ILLEGAL Begin Write ;Latch CA ; Determine AP Block Write ;Latch CA ; Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL ILLEGAL Special Mode Register Access NOP(Continue Burst to End --> Row Active) NOP(Continue Burst to End --> Row Active) Term burst --> Row active ILLEGAL Term burst ; Begin Read ; Latch CA ; Determine AP ILLEGAL Term burst ; Begin Write ; Latch CA ; Determine AP Term burst ; Block Write ; Latch CA ; Determine AP ILLEGAL Term Burst ; Precharge timing for Reads ILLEGAL ILLEGAL NOP(Continue Burst to End --> Row Active) NOP(Continue Burst to End --> Row Active) Term burst --> Row active ILLEGAL Term burst ; Begin Read ; Latch CA ; Determine AP ILLEGAL Term burst ; Begin Write ; Latch CA ; Determine AP Term burst ; Block Write ; Latch CA ; Determine AP 3 3 3 3 3 2 3 3 6 2 2 5 6 5 4
OP Code OP Code X X X BA X BA BA BA BA X X X X X X X BA X BA BA BA BA X X X X X X BA X BA BA X X X CA,AP X CA,AP CA,AP RA PA X X X X X X X CA,AP X CA,AP CA.AP RA PA X X X X X X CA,AP X CA,AP CA,AP
OP Code
- 48
Rev. 2.4 (May 1998)
KM4132G271B
FUNCTION TRUTH TABLE(TABLE 1, Continued)
Current State CS L Write L L L H L Read with Auto Precharge L L L L L H L Write with Auto Precharge L L L L L H L L Precharging L L L L H L Block Write Recovering L L L L L H L Row Activating L L L L L H L Refreshing L L L RAS L L L L X H H H H L L X H H H H L L X H H H L L L X H H H L L L X H H H L L L X H H L L CAS H H H L X H H L L H L X H H L L H L X H H L H H L X H H L H H L X H H L H H L X H L H L WE H L L X X H L H L X X X H L H L X X X H L X H L X X H L X H L X X H L X H L X X X X X X DSF X L H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BA (A9) BA BA X X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X X X ADDR RA PA X X X X X CA,AP CA,AP RA,PA X X X X CA,AP CA,AP RA,PA X X X X CA,AP RA PA X X X X CA,AP RA PA X X X X CA,AP RA PA X X X X X X ILLEGAL ACTION
CMOS SGRAM
NOTE 2 3
Term Burst : Precharge timing for Writes ILLEGAL ILLEGAL NOP(Continue Burst to End --> Precharge) NOP(Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Continue Burst to End --> Precharge) NOP(Continue Burst to End --> Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after ILLEGAL NOP --> Row Active after NOP --> Row Active after ILLEGAL ILLEGAL ILLEGAL Term Block Write : Precharge timing for Block Write ILLEGAL NOP --> Row Active after NOP --> Row Active after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL
2 2 2
2 2 2
tRP NOP --> Idle after tRP
2 2
tRP tBWC tBWC
2 4
2 2 2 2
tRCD tRCD
2 2 2 2
tRC tRC
- 49
Rev. 2.4 (May 1998)
KM4132G271B
FUNCTION TRUTH TABLE (TABLE 1, Continued)
ABBREVIATIONS RA = Row Address(A0~A9) NOP = No Operation Command BA = Bank Address(A10 ) CA = Column Address(A0~A7) PA = Precharge All(A9) AP = Auto Precharge(A9)
CMOS SGRAM
*Note : 1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle. 2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA). 5. Illegal if any banks is not idle. 6. Legal only if all banks are in idle or row active state.
FUNCTION TRUTH TABLE for CKE(TABLE 2)
Current State CKE n-1 H L Self Refresh L L L L L H Both Bank Precharge Power Down L L L L L L H H H All Banks Idle H H H H H H L Any State other than Listed Above H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L L H L H L CS X H L L L L X X H L L L L X X H L L L L L L L X X X X X RAS X X H H H L X X X H H H L X X X H H H L L L L X X X X X CAS X X H H L X X X X H H L X X X X H H L H L L L X X X X X WE X X H L X X X X X H L X X X X X H L X H H L L X X X X X DSF X X X X X X X X X X X X X X X X X X X L L L H X X X X X ADDR X X X X X X X X X X X X X X X X X X X RA X OP Code OP Code X X X X X INVALID Exit Self Refresh --> ABI after tRC Exit Self Refresh --> ABI after tRC ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power Down Mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL Row (& Bank) Active Enter Self Refresh Mode Register Access Special Mode Register Access NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend 10 10 9 9 9 8 8 7 7 ACTION NOTE
ABBREVIATIONS : ABI = All Banks Idle *Note : 7. After CKEs low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKEs low to high transition to issue a new command. 8. CKE low to high transition is asynchronous as if restarts internal clock. A minimum setup time "tSS + one clock" must be satisfied before any command other than exit. 9. Power-down and self refresh can be entered only from the all banks idle state. 10. Must be a legal command.
- 50
Rev. 2.4 (May 1998)
KM4132G271B
PACKAGE DIMENSIONS (TQFP)
CMOS SGRAM
Dimensions in Millimeters
0 ~ 7 17.20 14.00 #100 #1
0.20 0.10
23.20 20.00
0.20
0.10
0.575
0.825
0.30
0.08
0.65
0.09~0.20
0.13 MAX
1.00
0.10
1.20 MAX *
0.10 MAX 0.80
0.05 MIN
0.20
* All Package Dimensions of PQFP & TQFP are same except Height. - PQFP (Height = 3.0mmMAX) - TQFP (Height = 1.2mmMAX)
- 51
Rev. 2.4 (May 1998)

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