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| www..com CSC0100P CSC0100P USB and PS/2 Combo Peripheral OTP Controller Version: 1.00 .com DataShee ISSUED August 18 Info DCC July 2004 Chesen Electronics Corp. Taipei, Taiwan .com DataSheet 4 U .com www..com CHESEN CSC0100P 65C02 with USB and PS/2 Interface OTP Controller @Copyright 2001~2004 CHESEN ELECTRONICS CORP. All Rights Reserved. Manual Rev. 1.00: July 28, 2004 with document number M_CSC0100P_100 The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Revision History Revision No. 0.10 0.20 0.30 1.00 History Preliminary issue .com Revise EEPROM programming Fixed IRQII & IRQEII register address error - Amend program user guide - Initial release Date July 22, 2003 Jan. 18, 2004 July 20, 2004 July 28, 2004 Remark t4U.com DataShee .com 2004/July V1.00 2 DataSheet 4 U .com www..com CHESEN Features CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Low cost solution for low speed USB or PS/2 peripheral, such as keyboard, mice, joystick and others Built-in 65C02 8 Bit CPU - 6MHz external ceramic resonator - 3MHz internal CPU clock - 256 bytes RAM - 8K x 8 EPROM - Auto configure to operate as USB or PS/2 interface USB specification compliance: - Conforms to USB specification, version 1.1 - Conforms to USB HID specification, version 1.1 - Supports 1 low speed device address and 3 endpoints - 8 bytes FIFO for each endpoint - Integrated USB transceiver - Build in 3.3V regulator IO ports t4U.com - 31 general purpose I/O pins .com DataShee - Port0, 1, 2 are 8 bit I/O with each pin supports high impedance or 20K ohm internal pull up - Maskable interrupt on Port2 pins with option programmable pull low - Port3 is 7 bit I/O with each pin supports high impedance or 20K ohm internal pull up, 4 of which support programmable interrupt function - 4 dedicated LED pins for direct LED driving capability - D+ D- can be used as general purpose I/O with programmable interrupt function, 5K ohm pull up while disable USB Built-in power-on reset. One 8 bits timer 8 channels 12 bits analog-to-digital converter switch with Port1 Available package LQFP-44 .com 2004/July V1.00 3 DataSheet 4 U .com www..com CHESEN Product Overview CSC0100P 65C02 with USB and PS/2 Interface OTP Controller The CSC0100P is an 8-bit 65C02 core CPU based USB microcontroller with electrically one-time programmable (OTP) read only memory (EPROM). It features 31 general purpose I/O (GPIO) pins to support USB, PS/2 interface and other applications. These I/O are grouped into 4 ports (Port0 to 3) with high impedance, internal pull up, interrupt mechanism and Schmitt trigger features for various peripheral application requirements. And the 4 dedicated LED output direct connect the LED components with high current drive capability. Block Diagram Tim er Reset RAM ADC Progra m ROM Interrupt 3.3V Reg ula tor USB Eng ine USB PS/2 Xc vr D+ SCLK DSDAT A 65C02 CPU Core t4U.com .com DataShee LED Port1 Port2 Port0 Port3 LED0~ 3 P1.0~ 1.7 P2.0~ 2.7 P0.0~ 0.7 P3.0~ 3.6 .com 2004/July V1.00 4 DataSheet 4 U .com www..com CHESEN Pin Assignment CSC0100P 65C02 with USB and PS/2 Interface OTP Controller t4U.com CSC0100P-L44 L44 Pin # NAME IN/OUT DESCRIPTION 1 P31 I/O Port 3 Bit 1 2 P32/INT0 I/O Port 3 Bit 2 / External interrupt 0 3 P33/INT1 I/O Port 3 Bit 3 / External interrupt 1 4 P34/INT2 I/O Port 3 Bit 4 / External interrupt 2 5 P35/INT3 I/O Port 3 Bit 5 / External interrupt 3 6 P36 I/O Port 3 Bit 6 Input Programming voltage supply; ground for normal operation 7 VPP P 8 P00 I/O Port 0 Bit 0 9 P01 I/O Port 0 Bit 1 10 P02 I/O Port 0 Bit 2 11 P03 I/O Port 0 Bit 3 12 P04 I/O Port 0 Bit 4 13 P05 I/O Port 0 Bit 5 14 P06 I/O Port 0 Bit 6 15 P07 I/O Port 0 Bit 7 16 P10 / AD0 I/O*1 Port 1 Bit 0 / ADC channel 0 17 P11 / AD1 I/O*1 Port 1 Bit 1 / ADC channel 1 18 P12 / AD2 I/O*1 Port 1 Bit 2 / ADC channel 2 19 P13 / AD3 I/O*1 Port 1 Bit 3 / ADC channel 3 20 P14 / AD4 I/O*1 Port 1 Bit 4 / ADC channel 4 .com 21 P15 / AD5 I/O*1 Port 1 Bit 5 / ADC channel 5 *1 22 P16 / AD6 I/O Port 1 Bit 6 / ADC channel 6 23 P17 / AD7 I/O*1 Port 1 Bit 7 / ADC channel 7 24 P20 I/O Port 2 Bit 0 25 P21 I/O Port 2 Bit 1 26 P22 I/O Port 2 Bit 2 27 P23 I/O Port 2 Bit 3 28 P24 I/O Port 2 Bit 4 29 P25 I/O Port 2 Bit 5 30 P26 I/O Port 2 Bit 6 31 P27 I/O Port 2 Bit 7 32 LED0 OUT LED Output Bit 0 33 LED1 OUT LED Output Bit 1 34 LED2 OUT LED Output Bit 2 35 LED3 OUT LED Output Bit 3 36 SELPAD IN GPIO Schmitt Trigger input mode select 37 P5V P Power supply 38 OSCO OUT Crystal/Ceramic resonator out 39 OSCI IN Crystal/Ceramic resonator in 40 PADGND P Ground 41 USB3V3 P Power 3.3V 42 D+ / SCLK I/O USB data+ / PS/2 SCLK data 43 D- / SDATA I/O USB data- / PS/2 SDATA 44 P30 I/O Port 3 Bit 0 + Schmitt trigger Input *1 : Input mode while used as ADC channel (for 8K ROM version only) DataShee .com 2004/July V1.00 5 DataSheet 4 U .com www..com CHESEN CPU and Memory CSC0100P 65C02 with USB and PS/2 Interface OTP Controller CPU The CPU core of CSC0100P is an 8-bit 65C02 running with 3MHz frequency. ROM CSC0100P builds in 8K bytes program memory EPROM with address from E000H to FFFFH. The FFFAH and FFFBH are non-mask interrupt (NMI) vector address, the FFFCH and FFFDH are CPU reset vector address, and FFFEH and FFFFH are maskable interrupt vector address RAM CSC0100P builds in 256 bytes RAM for user data and stack. The address of SRAM is from 80H to 17FH. The stack register has to set to 7FH in the beginning of user program, and then the stack pointer will point to address 17FH. Memory Map $0000 $0033 t4U.com System Register Unused .com DataShee $0080 $00FF $0100 $017F $E000 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF RAM RAM Unused EPROM NMI-L NMI-H RESET-L RESET-H IRQ-L IRQ-H NMI Vector RESET Vector IRQ Vector .com 2004/July V1.00 6 DataSheet 4 U .com www..com CHESEN System Register ADDR $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 t4U.com Function IRQ Status I CSC0100P 65C02 with USB and PS/2 Interface OTP Controller $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 RESET R/W R 00H IRQI W Function IRQ Clear I R 00H IRQCLRI W R IRQ Enable I 00H IRQEI W R IRQ USB Status 00H IRQUSB W IRQ USB Clear R 00H IRQUSBCLR W IRQ USB Enable R 00H IRQUSBE W Timer Register R 00H TIMER W Timer Control R 01H TCON W Timer Mode R 00H TMOD W R Port 0 Data FFH PORT0 W R Port 1 Data FFH PORT1 W R Port 2 Data FFH PORT2 W R Port 3 Data 1FH PORT3 W R LED FFH W Clear Watch Dog R 00H CLRWDT W Mode Flag R 02H MODE_FG W USB Address R 00H UADD W Device Feature R 21H Control DFC W R TXDAT0 XXH W R TXCNT0 XXH W R TXFLG0 00H W R RXDAT0 XXH W R RXCNT0 XXH W R RXFLG0 00H W R TXDAT1 XXH W REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INT3 INT2 P2INT 4ms INT1 INT0 TMR CINT3 EWDT SUSP EINT3 STUP CINT2 CP2INT EINT2 EP2INT C4ms E4ms IN2 CINT1 EINT1 IN1 CINT0 EINT0 OT0 CTMR ETMR IN0 CSUSP CSTUP ESUSP ESTUP CIN2 EIN2 CIN1 EIN1 COT0 EOT0 CIN0 EIN0 TM7 TEST TM6 TESTQ TM5 TM4 TM3 TM2 TM1 TM0 ETIMER TMD2 P07 P17 P27 P06 P16 P05 P15 P04 P14 P24 P34 P03 P13 P23 P33 LED3 P02 P12 P22 P32 LED 2 TMD1 P01 P11 P21 P31 LED 1 TMD0 P00 P10 P20 P30 LED0 .com P26 P36 P25 P35 DataShee 0 1 0 1 0 1 0 POF 1 SUSF UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 x x PS2EN x RESUME 0 X VCPI T0B7 T0B6 T0B5 T0B4 T0B3 T0B2 T0B1 T0B0 C0B3 C0B2 C0B1 C0B0 T0SEQC STL0 T0FULL R0B7 R0B6 R0B5 R0B4 R0B3 R0B2 R0B1 R0B0 X0B3 X0B2 X0B1 X0B0 RSTL0 R0FULL T1B7 T1B6 T1B5 T1B4 T1B3 T1B2 T1B1 T1B0 .com 2004/July V1.00 7 DataSheet 4 U .com www..com CHESEN $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 t4U.com CSC0100P 65C02 with USB and PS/2 Interface OTP Controller TXCNT1 TXFLG1 TXDAT2 TXCNT2 TXFLG2 SUSLO SUSHI ADC Status/Control ADSCR ADC Data ADDRH ADC Data ADDRL Port1 Control P1CON INT_CFGI INT_CFGII INT_CFGIII Function IRQ Status II XXH 00H XXH XXH 00H 00H 00H 20H 00H 00H 00H 00H 00H 00H $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 IRQII IRQ Enable II IRQEII Function IRQ Clear II 00H 00H 00H 00H 00H 30H 08H 00H 00H 00H 00H 00H IRQCLRII Port0 Control P0CON Port2 Control P2CON Port3 Control P3CON USB Control USBCON Port2 Pull_Low Control ANAPOWER WakeTimer Port1 ADC Control DPLUS I/O Control DMINUS I/O Control R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W C1B3 C1B2 C1B1 C1B0 T1EPE T1SEQC STL1 T1FULL T2B7 T2B6 T2B5 T2B4 T2B3 T2B2 T2B1 T2B0 C2B3 C2B2 C2B1 C2B0 T2EPE T2SEQC STL2 0 1 CH1 T2FULL 0 1 ADACT 1 0 ADON 0 1 1 0 0 1 1 0 1 0 CH0 ADDR4 CKS2 CKS1 CKS0 CH2 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR3 ADDR2 ADDR1 ADDR0 P1CON7 P1CON6 P1CON5 P1CON4 P1CON3 P1CON2 P1CON1 P1CON0 I1EDGE I1_POL1 I1_POL0 I0EDGE I0_POL1 I2EDGE I2_POL1 PEDGE P_POL1 I0_POL0 I2_POL0 P_POL0 .com I3EDGE I3_POL1 I3_POL0 DataShee NEDGE N_POL1 N_POL0 USBN USBP EUSBN EUSBP CUSBN CUSBP P0CON7 P0CON6 P0CON5 P0CON4 P0CON3 P0CON2 P0CON1 P0CON0 P2CON7 P2CON6 P2CON5 P2CON4 P2CON3 P2CON2 P2CON1 P2CON0 P3CON7 P3CON6 P3CON5 P3CON4 P3CON3 P3CON2 P3CON1 P3CON0 NCON PCON vrefsel EN waketm 0 0 0 adclevel X S1 P1_A1 X S0 P1_A0 DPIO DMIO 0 P1_A2 P1_A7 P1_A6 P1_A5 P1_A4 P1_A3 .com 2004/July V1.00 8 DataSheet 4 U .com www..com CHESEN Power On Reset CSC0100P 65C02 with USB and PS/2 Interface OTP Controller CSC0100P builds in power on reset circuitry which will de-assert a 5ms pulse for resetting the system. User also can connect reset signal from the RESETB pin for external resetting control. Clock and Timer The system clock is coming from the external crystal or ceramic resonator with 6MHz frequency. This frequency will divide internal by 2 to generate 3MHz for CPU. The system has an 8 bits timer. The clock source is system clock divided by Timer Mode Register value. Every time when the timer is enable and the Timer Register value down count to zero, it will generate a timer interrupt to the system when ETMR=1. ADDR $06 REGISTER Timer Register TIMER RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 00H TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0 W TM7 ~ TM0: Timer value 00000000: 0 t4U.com 00000001: 1 00000010: 2 11111110: 254 11111111: 255 ADDR $07 REGISTER Timer Control TCON .com DataShee RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R X X 01H ETIMER W ETIMER: Enable timer 0: Enable 1: Disable .com 2004/July V1.00 9 4U D a t a S h e e t. c o m www..com CHESEN ADDR $08 REGISTER Timer Mode TMOD CSC0100P 65C02 with USB and PS/2 Interface OTP Controller RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R TMD2 TMD1 TMD0 00H W TMD2, TMD1, TMD0: Timer clock source TMD2 TMD1 TMD0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Clock Source System / 16 System / 32 System / 64 System / 128 System / 256 System / 512 System / 1024 System / 2048 Min. Count 2.66us 5.32 us 10.64 us 21.28 us 42.56 us 85.12 us 170.24 us 340.48 us Max.. Count 682.66 us 1.36ms 2.72 ms 5.44 ms 10.89 ms 21.79 ms 43.58 ms 87.16 ms t4U.com .com DataShee .com 2004/July V1.00 10 DataSheet 4 U .com www..com CHESEN Interrupt CSC0100P 65C02 with USB and PS/2 Interface OTP Controller The CSC0100P has the following interrupt sources. 1. External IO interrupt Programmable level, edge or bi-edge trigger interrupt from P3.2 (INT0), P3.3 (INT1), P3.4 (INT2), P3.5 (INT3), D+ (USBP) or D- (USBN). 2. Timer interrupt Interrupt source comes from the timer overflow. 3. 4ms interrupt Interrupt source comes from every 4ms. 4. Port2 interrupt Interrupt will generate when any bit of Port2 is "0". 5. OT0 interrupt Interrupt source when USB endpoint 0 received data. 6. IN0, IN1, IN2 interrupt Interrupt source when Host ready to receive USB data 7. STUP interrupt Interrupt source when USB endpoint 0 received SETUP TOKEN. 8. SUSP interrupt Interrupt source when USB bus idles for more than 3ms. t4U.com .com DataShee ADDR $00 $01 Function IRQ Status I RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INT3 INT2 P2INT 4ms INT1 INT0 TMR R 00H IRQI W Function IRQ Clear I R 00H IRQCLRI CINT3 CINT2 CP2INT C4ms CINT1 CINT0 CTMR W REGISTER TMR: Timer interrupt status 0: No timer interrupt 1: 1 timer interrupt is pending INT0: External P3.2 interrupt status 0: No external I/O interrupt 1: 1 external I/O interrupt is pending INT1: External P3.3 interrupt status 0: No external interrupt 1: 1 external interrupt is pending 4ms: 4ms interrupt status 0: 4ms not coming 1: Reach 4ms and interrupt is pending P2INT: Port2 interrupt status 0: None of the bit in Port2 is "0" 1: At least one bit in Port2 is "0" .com 2004/July V1.00 11 DataSheet 4 U .com www..com CHESEN INT2: External P3.4 interrupt status 0: No external I/O interrupt 1: 1 external I/O interrupt is pending INT3: External P3.5 interrupt status 0: No external interrupt 1: 1 external interrupt is pending CTMR: Clear timer interrupt 0: No function 1: Clear timer interrupt CINT0: Clear external P3.2 interrupt 0: No function 1: Clear external P3.2 interrupt CINT1: Clear external P3.3 interrupt 0: No function 1: Clear external P3.3 interrupt C4ms: Clear 4ms interrupt 0: No function 1: Clear 4ms interrupt CP2INT: Clear Port2 interrupt 0: No function 1: Clear Port2 interrupt CINT2: Clear external P3.4 interrupt 0: No function 1: Clear external P3.4 interrupt CINT3: Clear external P3.5 interrupt 0: No function 1: Clear external P3.5 interrupt CSC0100P 65C02 with USB and PS/2 Interface OTP Controller t4U.com .com DataShee .com 2004/July V1.00 12 DataSheet 4 U .com www..com CHESEN ADDR $27 $29 REGISTER Function IRQ Status II CSC0100P 65C02 with USB and PS/2 Interface OTP Controller RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 USBN USBP R 00H IRQII W Function IRQ Clear II R 00H IRQCLRII CUSBN CUSBP W USBP: External D+ interrupt status 0: No external I/O interrupt 1: 1 external I/O interrupt is pending USBN: External D- interrupt status 0: No external I/O interrupt 1: 1 external I/O interrupt is pending CUSBP: Clear external D+ interrupt 0: No function 1: Clear external D+ interrupt CUSBN: Clear external D- interrupt 0: No function 1: Clear external D- interrupt t4U.com .com DataShee ADDR $02 REGISTER IRQ Enable I IRQEI RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R EWDT EINT3 EINT2 EP2INT E4ms EINT1 EINT0 ETMR 00H W ETMR: Enable timer interrupt 0: No function 1: Enable timer interrupt EINT0: Enable external P3.2 interrupt 0: No function 1: Enable external P3.2 interrupt EINT1: Enable external P3.3 interrupt 0: No function 1: Enable external P3.3 interrupt E4ms: Enable 4ms interrupt 0: No function 1: Enable 4ms interrupt EP2INT: Enable Port2 interrupt 0: No function 1: Enable Port2 interrupt .com 2004/July V1.00 13 DataSheet 4 U .com www..com CHESEN EINT2: Enable external P3.4 interrupt 0: No function 1: Enable external P3.4 interrupt EINT3: Enable external P3.5 interrupt 0: No function 1: Enable external P3.5 interrupt EWDT: Enable watchdog function 0: Enable watchdog function 1: Disable CSC0100P 65C02 with USB and PS/2 Interface OTP Controller REGISTER RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IRQ Enable II R EUSBN EUSBP $28 00H IRQEII W *Function available disable USB device (USBEN="0") EUSBP: Enable external D+ interrupt 0: No function 1: Enable external D+ interrupt EUSBN: Enable external D- interrupt 0: No function 1: Enable external D- interrupt ADDR $03 REGISTER IRQ USB Status IRQUSB ADDR t4U.com .com DataShee RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IN2 IN1 OT0 IN0 R SUSP STUP 00H W IN0: USB endpoint 0 host receiving ready interrupt status 0: No USB IN0 interrupt 1: One IN0 interrupt is pending OT0: USB endpoint 0 receiving data interrupt status 0: No USB OT0 interrupt 1: 1 OT0 interrupt is pending IN1: USB endpoint 1 host receiving ready interrupt status 0: No USB IN0 interrupt 1: One IN0 interrupt is pending IN2: USB endpoint 2 host receiving ready interrupt status 0: No USB IN2 interrupt 1: One IN2 interrupt is pending .com 2004/July V1.00 14 DataSheet 4 U .com www..com CHESEN CSC0100P 65C02 with USB and PS/2 Interface OTP Controller STUP: USB endpoint 0 host receiving SETUP TOKEN interrupt status 0: No USB SETUP TOKEN interrupt 1: One USB SETUP TOKEN interrupt is pending SUSP: USB SUSPEND interrupt status 0: No USB SUSPEND interrupt 1: One USB SUSPEND interrupt is pending ADDR $04 REGISTER IRQ USB Clear IRQUSBCLR RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 00H CIN2 CIN1 COT0 CIN0 W CSUSP CSTUP CIN0: Clear USB endpoint 0 host receiving ready interrupt 0: No function 1: One IN0 interrupt is pending COT0: Clear USB endpoint 0 receiving data interrupt 0: No function 1: 1 OT0 interrupt is pending CIN1: Clear USB endpoint 1 host receiving ready interrupt 0: No function .com t4U.com 1: One IN0 interrupt is pending CIN2: Clear USB endpoint 2 host receiving ready interrupt 0: No function 1: One IN2 interrupt is pending CSTUP: Clear USB endpoint 0 host receiving SETUP TOKEN interrupt 0: No function 1: One USB SETUP TOKEN interrupt is pending CSUSP: Clear USB SUSPEND interrupt 0: No function 1: One USB SUSPEND interrupt is pending ADDR $05 REGISTER IRQ USB Enable IRQUSBE RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R ESUSP ESTUP EIN2 EIN1 EOT0 EIN0 00H W DataShee EIN0: Enable USB endpoint 0 host receiving ready interrupt 0: No function 1: Enable IN0 interrupt EOT0: Enable USB endpoint 0 receiving data interrupt 0: No function 1: Enable OT0 interrupt .com 2004/July V1.00 15 DataSheet 4 U .com www..com CHESEN CSC0100P 65C02 with USB and PS/2 Interface OTP Controller EIN1: Enable USB endpoint 1 host receiving ready interrupt 0: No function 1: Enable IN0 interrupt EIN2: Enable USB endpoint 2 host receiving ready interrupt 0: No function 1: Enable IN2 interrupt ESTUP: Enable USB endpoint 0 host receiving SETUP TOKEN interrupt 0: No function 1: Enable USB SETUP TOKEN interrupt ESUSP: Enable USB SUSPEND interrupt 0: No function 1: Enable USB SUSPEND interrupt ADDR $24 REGISTER INT_CFGI RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R I1EDGE I1_POL1 I1_POL0 I0EDGE I0_POL1 I0_POL0 00H W t4U.com I0EDGE, I0_POL1, I0_POL0: External interrupt level and polarity for INT0 .com I0EDGE I0_POL1 I0_POL0 Level 0 0 0 Edge trigger 0 0 1 Edge trigger 1 0 0 Level trigger 1 0 1 Level trigger 0 1 0 Edge trigger I1EDGE, I1_POL1, I1_POL0: External interrupt level and polarity for INT1 I1EDGE I1_POL1 I1_POL0 Level 0 0 0 Edge trigger 0 0 1 Edge trigger 1 0 0 Level trigger 1 0 1 Level trigger 0 1 0 Edge trigger ADDR $25 REGISTER INT_CFGII Polarity Falling Rising High Low Bi-edge DataShee Polarity Falling Rising High Low Bi-edge RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R I3EDGE I3_POL1 I3_POL0 I2EDGE I2_POL1 I2_POL0 00H W I2EDGE, I2_POL1, I2_POL0: External interrupt level and polarity for INT2 I2EDGE I2_POL1 I2_POL0 Level 0 0 0 Edge trigger 0 0 1 Edge trigger 1 0 0 Level trigger 1 0 1 Level trigger Polarity Falling Rising High Low .com 2004/July V1.00 16 DataSheet 4 U .com www..com CHESEN CSC0100P 65C02 with USB and PS/2 Interface OTP Controller I3EDGE, I3_POL1, I3_POL0: External interrupt level and polarity for INT3 I3EDGE I3_POL1 I3_POL0 Level 0 0 0 Edge trigger 0 0 1 Edge trigger 1 0 0 Level trigger 1 0 1 Level trigger Polarity Falling Rising High Low ADDR $26 REGISTER INT_CFGIII RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R NEDGE N_POL1 N_POL0 PEDGE P_POL1 P_POL0 00H W PEDGE, P_POL1, P_POL0: External interrupt level and polarity for D+ PEDGE P_POL1 P_POL0 Level 0 0 0 Edge trigger 0 0 1 Edge trigger 1 0 0 Level trigger 1 0 1 Level trigger 0 1 0 Edge trigger NEDGE, N_POL1, N_POL0: External interrupt level and polarity for DNEDGE N_POL1 N_POL0 Level 0 0 0 Edge trigger .com t4U.com 0 0 1 Edge trigger 1 0 0 Level trigger 1 0 1 Level trigger 0 1 0 Edge trigger Polarity Falling Rising High Low Bi-edge Polarity Falling Rising High Low Bi-edge DataShee .com 2004/July V1.00 17 DataSheet 4 U .com www..com CHESEN I/O Port CSC0100P 65C02 with USB and PS/2 Interface OTP Controller The CSC0100P has 31 general purpose I/O pins distributed on Port0, Port1, Port2 and Port3. When using the I/O pin as output, just write the corresponding bit to the register. While writing "1" to the corresponding bit first as using this pin as input. The four LED pins is output only with high current driving capability. P0,1,2,3,USBCON VCC 1 1 2 2 3 R=20K PMOS IO Data Bus 1 20 NMOS t4U.com Block Diagram of Port0, 1, 2, 3 .com ADDR $09 $0A $0B $0C $0D $32 $33 REGISTER Port 0 Data PORT0 Port 1 Data PORT1 Port 2 Data PORT2 Port 3 Data PORT3 LED DPLUS I/O Control DMINUS I/O Control RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R P07 P06 P05 P04 P03 P02 P01 P00 FFH W R P17 P16 P15 P14 P13 P12 P11 P10 FFH W R P27 P26 P25 P24 P23 P22 P21 P20 FFH W R P36 P35 P34 P33 P32 P31 P30 1FH W R LED3 LED 2 LED 1 LED0 FFH W R DPIO 00H W R DMIO 00H W DataShee Pmn: Corresponding bit for Port0~Port3, where m represents for Port number and n represents for bit number. LEDn: Corresponding LED output bit DPIO: D+ status while disable USB function DMIO: D- status while disable USB function .com 2004/July V1.00 18 DataSheet 4 U .com www..com CHESEN ADDR $23 $2A $2B $2C $2D $2E REGISTER Port1 Control P1CON Port0 Control P0CON Port2 Control P2CON Port3 Control P3CON USB Control USBCON Port2 Pull_Low Control CSC0100P 65C02 with USB and PS/2 Interface OTP Controller RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R P1CON7 P1CON6 P1CON5 P1CON4 P1CON3 P1CON2 P1CON1 P1CON0 00H W R P0CON7 P0CON6 P0CON5 P0CON4 P0CON3 P0CON2 P0CON1 P0CON0 00H W R P2CON7 P2CON6 P2CON5 P2CON4 P2CON3 P2CON2 P2CON1 P2CON0 00H W R P3CON7 P3CON6 P3CON5 P3CON4 P3CON3 P3CON2 P3CON1 P3CON0 00H W R NCON PCON 30H W R 08H W P1CONn: Pull up control 0: Internal pull up with 20K ohm resistor 1: No internal pull up When using the Port1 as analog to digital converter channel, the P1CONn has to set to "1". VCC R=20K t4U.com DATA BUS 1 .com 2 PMOS IO DataShee NMOS 1 20 AD P0CONn: Pull up control 0: Internal pull up with 20K ohm resistor 1: No internal pull up P2CONn: Pull up control 0: Internal pull up with 20K ohm resistor 1: No internal pull up P3CONn: Pull up control 0: Internal pull up with 20K ohm resistor 1: No internal pull up .com 2004/July V1.00 19 DataSheet 4 U .com www..com CHESEN CSC0100P 65C02 with USB and PS/2 Interface OTP Controller PCON: D+ Pull up control 0: Internal pull up with 5K ohm resistor 1: No internal pull up NCON: D- Pull up control 0: Internal pull up with 5K ohm resistor 1: No internal pull up t4U.com .com DataShee .com 2004/July V1.00 20 DataSheet 4 U .com www..com CHESEN D- D+ and PS/2 Operation CSC0100P 65C02 with USB and PS/2 Interface OTP Controller The CSC0100P is optimized to combine USB or PS/2 interface device with following features: 1. The USB D+ and D- line can be used for general purpose I/O or SCLK and SDATA for PS/2. 2. When USB disabled (VCPI="1"), D+ D- pins will be placed in high impedance with pull up disable. 3. The 5K ohm internal pull up on the D+ (SCLK) and D- (SDATA) pins when enable (PCON="0" NCON="0") 4. The state of D+ (SCLK) and D- (SDATA) pins can be read from the DPLUS DMINUS register Mode of D+ and DUSB PS/2 IO with high impedance IO with 5K ohm pull up t4U.com Procedure 1. Enable USB (PS2EN="1" && VCPI="0") 2. Drive 3.3V voltage output with internal regulator (VCPI="0"), 1.5K ohm internal pull up on regulator output and D- pin 1. Disable USB (PS2EN="0" && VCPI="1") 2. Drive floating state on internal regulator (VCPI="1") 3. Enable PS/2 5K ohm pull up on SCLK, SDATA (PS2EN="0") 4. Enable interrupt and read/write status 1. Disable USB (PS2EN="0" && VCPI="1") 2. Drive floating state on internal regulator (VCPI="1") 3. Disable PS/2 5K ohm pull up on D+, D- (PCON,NCON ="1") 4. Read/Write I/O status with DPLUS DMINUS register 1. Disable USB (PS2EN="0" && VCPI="1") 2. Drive floating state on internal regulator (VCPI="1") 3. Enable PS/2 5K ohm pull up on D+, D- (PCON, NCON ="0") .com DataShee 4. Read/Write I/O status with DPLUS DMINUS register .com 2004/July V1.00 21 DataSheet 4 U .com www..com CHESEN Watch-Dog Timer CSC0100P 65C02 with USB and PS/2 Interface OTP Controller The watch-dog resets the system whenever the 150ms internal watch-dog timer run over. Writing 55H to the Clear Watch Dog register at address 0x0E will clear the timer. This is used to prevent the dead lock of program. ADDR $0E REGISTER Clear Watch Dog CLRWDT RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 00H W 0 1 0 1 0 1 0 1 Wake Up Timer The wake up time can be programmed by configuring the WakeTimer 30H. ADDR $30 REGISTER WakeTimer S0 0 0 1 1 waketm: State of the wake up timer 0: One wake up state under processing 1: No wake up under processing EN: Enable wake up timer 0: Disable 1: Enable RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R EN waketm 0 0 0 0 S1 S0 00H W S1 0 1 .com 0 1 Wake up time 1ms 2ms 4ms 8ms t4U.com DataShee .com 2004/July V1.00 22 DataSheet 4 U .com www..com CHESEN Suspend Mode CSC0100P 65C02 with USB and PS/2 Interface OTP Controller The CSC0100P supports low power suspend mode. When there is no signal on the USB bus, there is a USB suspend interrupt (SUSP) request occurred. The suspend high / low register (SUSLO SUSHI) are used to place the CSC0100P into the suspend mode. The CSC0100P is placed into the low power state by writing #55H to SUSLO first, writes #AAH to SUSHI after then. The SUSF bit of the mode flag register (MODE_FG) will be set when enters suspend mode. When the program is running, whether it is active from power on reset or resume reset by distinguishing the POF and SUSF in the mode flag register. ADDR $0F $1E $1F REGISTER Mode Flag MODE_FG SUSLO SUSHI RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 02H POF SUSF W R 00H W 0 1 0 1 0 1 0 1 R 00H W 1 0 1 0 1 0 1 0 SUSF: Suspend mode flag 0: Non-suspend mode 1: Suspend mode t4U.com .com POF: Power on reset flag 0: Not power on reset 1: Power on reset DataShee .com 2004/July V1.00 23 DataSheet 4 U .com www..com CHESEN USB Device CSC0100P 65C02 with USB and PS/2 Interface OTP Controller USB Address Register (UADD): address of USB device ADDR $10 REGISTER USB Address UADD RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 00H W UADD6 ~ UADD0: USB address from 1 to 127 Device Feature Control Register (DFC): ADDR $11 REGISTER Device Feature Control DFC RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R RESUM 0 X X X PS2EN X VCPI 21H W E VCPI: VCPI 0 1 VCP Output DPull_up 1.5K to VCP D- No .com Pull_up 1.5K to VCP t4U.com DataShee RESUME: When CSC0100P leaves the suspend mode, write this bit to wake up the system by sending a 10 ~ 15ms signal to host. PS2EN: Disable PS/2 mode manually 0: PS/2 mode 1: USB mode .com 2004/July V1.00 24 DataSheet 4 U .com www..com CHESEN ADDR $12 $18 $1B REGISTER TXDAT0 TXDAT1 TXDAT2 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Transmit Data Register (TXDAT0, TXDAT1, TXDAT2): USB Transmit FIFO Data Register For Endpoint 0/1/2 RESET R/W R XXH W R XXH W R XXH W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T0B7 T0B6 T0B5 T0B4 T0B3 T0B2 T0B1 T1B7 T1B6 T1B5 T1B4 T1B3 T1B2 T1B1 T2B7 T2B6 T2B5 T2B4 T2B3 T2B2 T2B1 T0B0 T1B0 T2B0 Transmit Byte Count Register (TXCNT0, TXCNT1, TXCNT2): USB FIFO Transmit Byte Count Register For Endpoint 0/1/2 ADDR $13 $19 $1C REGISTER TXCNT0 TXCNT1 TXCNT2 RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R XXH W C0B3 R XXH W C1B3 R XXH W C2B3 BIT 2 BIT 1 BIT 0 C0B2 C0B1 C0B0 C1B2 C1B1 C1B0 C2B2 C2B1 C2B0 CnB3, CnB2, CnB1, CnB0: Transmit byte count from 0 to 8. The transmit byte count register will increase automatically when every data writes to the transmit data register. t4U.com Write 0 to this register force device to send out .com empty data. Transmit Flag Register (TXFLG0, TXFLG1, TXFLG2): USB Transmit Flag Register For Endpoint 0/1/2 ADDR $14 $1A $1D REGISTER TXFLG0 TXFLG1 TXFLG2 RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 T0SEQ R 00H C W R T1SEQ T1EPE 00H C W R T2SEQ T2EPE 00H C W BIT 1 BIT 0 STL0 STL1 STL2 T0FULL T1FULL T2FULL DataShee TnFULL (R): Transmit FIFO full 0: FIFO not full 1: FIFO full TnFULL (W): Write "1" to start transmission STLn: Write "1" to tell system the transmit error TnSEQC: 0: Data transmit from DATA0 1: Data transmit from DATA1 .com 2004/July V1.00 25 DataSheet 4 U .com www..com CHESEN T1EPE: Enable endpoint 1 0: Disable 1: Enable T2EPE: Enable endpoint 2 0: Disable 1: Enable CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Receive Data Register (RXDAT0): USB Receive FIFO Data Register For Endpoint 0 ADDR $15 REGISTER RXDAT0 RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R R0B7 R0B6 R0B5 R0B4 R0B3 R0B2 R0B1 R0B0 XXH W Receive Byte Count Register: USB FIFO Receive Byte Count Register For Endpoint 0 ADDR $16 REGISTER RXCNT0 RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R X0B3 X0B2 X0B1 X0B0 XXH W X0B3, X0B2, X0B1, X0B0: Receive byte count from 0 to 8. The receive byte count register will increase automatically when every data writes to the receive data register. .com t4U.com Receive Flag Register (RXFLG0): USB Receive Flag Register For Endpoint 0 ADDR $17 REGISTER RXFLG0 RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R RSTL0 R0FULL 00H W DataShee R0FULL: Receive FIFO Full 0: Receive FIFO not full 1: Receive FIFO full RSTL0: Write "1" to tell system the receive error .com 2004/July V1.00 26 DataSheet 4 U .com www..com CHESEN Analog to Digital Converter CSC0100P 65C02 with USB and PS/2 Interface OTP Controller The CSC0100P (8K EPROM only) has 8 channels 12 bits analog to digital converter, the 8-ch analog converting input signals are from P1.0 ~ P1.7. When using P1 as analog input channel, the pull up of the relative bit should be disabled and Port 1 ADC control should enable. ADDR $23 $31 REGISTER Port1 Control P1CON Port1 ADC Control RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R P1CON7 P1CON6 P1CON5 P1CON4 P1CON3 P1CON2 P1CON1 P1CON0 00H W R P1_A7 P1_A6 P1_A5 P1_A4 P1_A3 P1_A2 P1_A1 P1_A0 00H W P1CONn: Pull up control 0: Internal pull up with 20K ohm resistor 1: No internal pull up When using the Port1 as analog to digital converter channel, the P1CONn has to set to "1". P1_An: Enable port 1 ADC control 0: Disable ADC function 1: Enable ADC function t4U.com ADC Status/Control Register (ADSCR): ADDR $20 .com DataShee REGISTER RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADC Status/Control R ADACT 20H CKS2 CKS1 CKS0 CH2 CH1 CH0 ADON ADSCR W CH2, CH1, CH0: AD input channel selection CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 AD0 (P1.0) AD1 (P1.1) AD2 (P1.2) AD3 (P1.3) AD4 (P1.4) AD5 (P1.5) AD6 (P1.6) AD7 (P1.7) .com 2004/July V1.00 27 DataSheet 4 U .com www..com CHESEN CKS2 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 1 1 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller CKS2, CKS1, CKS0: ADC conversion time CKS0 0 1 0 1 0 1 0 1 ADC_CONVERT_TIME 1us 2us 4us 8us 16us 32us 64us 128us ADON (W): Enable ADC 0: Disable ADC, the P1.0 ~ P1.7 act as general purpose I/O 1: Enable ADC, the P1.0 ~ P1.7 act as analog input channels ADACT (R): ADC conversion 0: No conversion or conversion not ready 1: Conversion done ADC Data Register (ADDR): t4U.com ADDR $21 $22 $2F REGISTER ADC Data ADDRH ADC Data ADDRL ANAPOWER RESET R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 .com R ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 00H W ADDR3 ADDR2 ADDR1 ADDR0 R 00H W R vrefsel adclevel x 00H x W DataShee ADDRn (R): 12 bits ADC conversion data adclevel: Internal reference voltage selection (if vrefsel=0) 0: 3.3V 1: 5.0V vrefsel: Reference voltage selection 0: Internal 1: External reference voltage from P3.6 .com 2004/July V1.00 28 DataSheet 4 U .com www..com CHESEN Programming of EPROM CSC0100P 65C02 with USB and PS/2 Interface OTP Controller When the CSC0100P is delivered, the chip has all 64K bits in the HIGH state. "ZEROs" are loaded into the CSC0100P relevant bit through the procedure of programming. The programming mode is entered when 12.75V is applied to the VPP pin and 6.25V applied on VCC pin. The rising edge of SCLK shifts a data bit of SDATA to the data latch, data in the data latch can be programmed in 8-bit format to the EPROM directly through the parallel data bus. De vic e ID SDa ta SC LK SC E# SOE# SPGM# SVPP SVCC Operation Modes Serial I/F (SIF) SCE# SOE# SDATA X X Hi-Z VIL VIL VIH VIH VIL VIL Shift In Shift Out Shift Out Parallel I/F (PIF) OE# PGM# VIL X VIH VIL -VIL tPW VIH -- Ad dress Counter Dec od er Da ta Latc h Ad d re ss Da ta T EPROM o CE# OE# PGM# VPP VCC CE# OE# PGM# & T st e Co ntro l Lo g ic .com t4U.com DataShee Mode SVPP/VPP SVCC/VCC Normal VCC VCC (N) Program 12.75V 6.25V (P) Program 12.75V 6.25V Verify (PV) ID Verify 12.75V 6.25V (IDV) CE# VIL VIL VIL -- DATA Hi-Z Data Out Data In -- .com 2004/July V1.00 29 DataSheet 4 U .com www..com CHESEN Programming Specifications CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Sta rt 1. SVPP/VPP= 12.75V 2. SVCC/VCC= 6.25V Fa il Che c k De vic e ID De vic e Erro r Pa ss Fa il Bla nk Che c k De vic e Fa ilure t4U.com .com Pa ss DataShee Yes 8 b it d a ta word to b e p ro g ra m = FFH No X= 0 Inc re m e nt Ad d ress Pro g ra m Inc re m e nt X No No Fa il Pro g ra m Byte Verify Pa ss La st Ad d re ss X= 24 Yes Ba c k to No rm a l Mod e De vic e Pa sse d .com 2004/July V1.00 30 DataSheet 4 U .com www..com CHESEN ID Verify CSC0100P 65C02 with USB and PS/2 Interface OTP Controller ID Verify (VPP=12.75V VCC=6.25V) P00/SCLK P01/SDATA 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 1 P10/SCE P20/SOE P21/SPGM OTP_ROM Interface VPP t4U.com VP P10/SCE P20/SOE P21/SPGM Address Data .com DataShee .com 2004/July V1.00 31 DataSheet 4 U .com www..com CHESEN Blank Check CSC0100P 65C02 with USB and PS/2 Interface OTP Controller First Byte Program Verify Mod e Inc rem ent Address Counter Shift 8 bit out and Verify Fail Pass t4U.com .com DataShee No Last Word Y es Blank Chec k Passed Blank Chec k Failed .com 2004/July V1.00 32 DataSheet 4 U .com www..com CHESEN Program Program (VPP=12.75V VCC=6.25V) CSC0100P 65C02 with USB and PS/2 Interface OTP Controller VPP VCC P00/SCLK P01/SDATA P10/SCE P20/SOE P21/SPGM A15 A14 A13 A0 D7 D6 D5 D4 D3 D2 D1 D0 OTP_ROM t4U.com Interface .com VPP VCC P10/SCE P20/SOE P21/SPGM Address DataShee Address Latch Data Data Latch .com 2004/July V1.00 33 DataSheet 4 U .com www..com CHESEN Program Verify CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Prog ra m Verify Mod e Shift 8 bit o ut and Verify Fail Pa ss t4U.com .com Pro gra m Pa ssed Progra m Fa ilure DataShee .com 2004/July V1.00 34 DataSheet 4 U .com www..com CHESEN CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Program Verify (VPP=12.75V VCC=6.25V) VPP VCC P00/SCLK P01/SDATA P10/SCE P20/SOE P21/SPGM A15 A14 A13 A0 D7 D6 D5 D4 D3 D2 D1 D0 OTP_ROM t4U.com Interface .com VPP VCC P10/SCE P20/SOE P21/SPGM Address DataShee Address Latch Data Output Data .com 2004/July V1.00 35 DataSheet 4 U .com www..com CHESEN Instruction Set List CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Instruction Description Instruction ADC Add with Carry LDY AND Logical AND LSR ASL Arith. Shift Left LSRA ASLA Arith. Shift Left NOP BBRb Branch if Bit Reset ORA BBSb Branch if Bit Set PHA BCC Branch if Carry Clear PHP BCS Branch if Carry Set PHX BEQ Branch if Equal PHY BIT Bit Test PLA BMI Branch if Minus PLP BNE Branch if Not Equal PLX BPL Branch if Plus PLY BRA Branch Always RMBb BRK Break(-[S]={PC+2,P}) ROL BVC Branch if Overflw Clr ROLA BVS Branch if Overflw Set ROR CLC Clear Carry flag RORA CLD Clear Decimal mode RTI CLI Clear Int. disable RTS CLV Clear Overflow flag SBC CMP Compare SEC .com t4U.com CPX Compare index reg. SED CPY Compare index reg. SEI DEC Decrement SMBb DEC A Decrement Acc. STA DEX Decrement index reg. STX DEY Decrement index reg. STY EOR Logical Exclusive OR STZ INC Increment TAX INC A Increment Acc. TAY INX Increment index reg. TRB INY Increment index reg. TSB JMP Jump TSX JSR Jump to Subroutine TXA LDA Load Accumulator TXS LDX Load index register TYA *More detailed specification please refer to 65C02 programming data book. Description Load index register Logical Shift Right Logical Shift Right No Operation Logical Inclusive OR Push Accumulator Push status register Push index register Push index register Pull Accumulator Pull status register Pull index register Pull index register Reset Memory Bit Rotate Left Rotate Left Acc. Rotate Right Rotate Right Acc. Return from Interrupt Return from Subr. Subtract with Carry Set Carry flag Set Decimal mode Set Interrupt disable Set Memory Bit Store Accumulator Store index register Store index register Store Zero Transfer Accumulator Transfer Accumulator Test and Reset Bits Test and Set Bits Transfer Stack ptr Transfer index reg. Transfer index reg. Transfer index reg. DataShee .com 2004/July V1.00 36 DataSheet 4 U .com www..com CHESEN Firmware Programming Guide Suspend/Resume/Wakeup CSC0100P 65C02 with USB and PS/2 Interface OTP Controller SUSP = 1 Write ' 1 ' to clear CSUSP bit Write `55' to SUSLO Write `AA' to SUSHI Enter power down mode Wait for resume or wakeup Port2 Wakeup t4U.com Resume .com Write ' 0 ' to clear SUSF bit Check remote wakeup event like keyboard button pressed DataShee Suspend process complete Write `0' to clear SUSF bit Wakeup process complete .com 2004/July V1.00 37 DataSheet 4 U .com www..com CHESEN Receive Packet via Setup CSC0100P 65C02 with USB and PS/2 Interface OTP Controller STUP = 1 Write ' 1 ' to clear CSTUP bit Get received byte count from RXCNT 0 Read received data continuous from RXDAT0 ( total RXCNT0 bytes ) t4U.com .com DataShee Clear R0FULL bit SETUP data packet received complete .com 2004/July V1.00 38 DataSheet 4 U .com www..com CHESEN Receive Packet via Endpoint 0 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller OT0 = 1 Write ' 1 ' to clear COT0 bit Get received byte count from RXCNT0 t4U.com Read received data continuous from RXDAT0 .com ( total RXCNT0 bytes ) DataShee Clear R0FULL bit OUT data packet received complete .com 2004/July V1.00 39 DataSheet 4 U .com www..com CHESEN Transmit Packet via Endpoint 0 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Start to transmit function Write `0' TXCNT0 to reset FIFO Push all transmitting data into TXDAT0 ( maximum 8 bytes ) t4U.com Set correct data toggle Sequence via .com T0SEQC DataShee Set T0FULL bit SIE will transmit the packet while it receives a IN token .com 2004/July V1.00 40 DataSheet 4 U .com www..com CHESEN Transmit Packet via Endpoint 1 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Start to transmit function Write `0' to TXCNT1 to reset FIFO Push all transmitting data into TXDAT1 ( maximum 8 bytes ) t4U.com Set correct data toggle Sequence via .com T1SEQC DataShee Set T1FULL bit SIE will transmit the packet while it receives a IN token .com 2004/July V1.00 41 DataSheet 4 U .com www..com CHESEN Transmit Packet via Endpoint 2 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller Start to transmit function Write `0' to TXCNT2 to reset FIFO Push all transmitting data into TXDAT2 ( maximum 8 bytes ) t4U.com Set correct data toggle Sequence via .com T2SEQC DataShee Set T2FULL bit SIE will transmit the packet while it receives a IN token .com 2004/July V1.00 42 DataSheet 4 U .com www..com CHESEN Electrical Characteristics CSC0100P 65C02 with USB and PS/2 Interface OTP Controller VDD=5V, GND=0V, TA=25, Fosc=6MHz Parameters Symbol Operating Voltage Vdd Operating Current Iop Suspend Current Isp Input High Voltage Vih Input Low Voltage Vil Output High Voltage Voh Output Low Voltage Vol LED Sink Current I led Pull-up Resistance Rup Schmitt Tigger Input High Voltage Vstih Schmitt Tigger Input Low Voltage Vstil Min 4.4 2 Typ 5 Max 5.25 20 500 0.8 2.4 6 0.8 10 20K 1.7 1.1 0.4 14 2 Unit V mA uA V V V V mA V V Conditions No load Product Matrix Part Number t4U.com Memory EPROM Size RAM Size 8K Bytes CSC0100P-L44 I/Os GPIO ADC 31 256 Bytes 8 .com 4 LEDs Package Type LQFP-44 Operating Range Commercial DataShee Part Number CSC0100P-PG Description CSC0100P Programmer .com 2004/July V1.00 43 DataSheet 4 U .com www..com CHESEN Package Outline LQFP-44 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller t4U.com .com DataShee .com 2004/July V1.00 44 DataSheet 4 U .com www..com CHESEN Appendix CSC0100P 65C02 with USB and PS/2 Interface OTP Controller CSC0100P-PG CSC0100P Programmer Guide Hardware Description t4U.com .com DataShee 1. VCC input voltage = 13V ~ 15 V 2. Programmer support 40-pin DIP; 20-pin DIP; 18-pin DIP; 44-pin LQFT and 48-pin LQFP (via the adaptor) IC package type 3. Support flat cable for target board in system programming (The pin definition as indicated in the circuit) .com 2004/July V1.00 45 DataSheet 4 U .com www..com CHESEN Software Installation and User Guide CSC0100P 65C02 with USB and PS/2 Interface OTP Controller 1. Boot from Win98 or DOS boot disk (included OTP.exe programmer program) 2. PC BIOS print port sets as EPP mode 3. Execute OTP.EXE, the functions are as below: [A] Auto < I&B&P&C> Proceed ID verify Blank verify Program Compare ID verify error or Blank verify error will not proceed Program [B] Blank verify Check all the EPROM data clear to 0xFF or not [C] Compare & display error Compare programmed data with the buffer data, will indicated if the data is not the same. [D] Display buffer Display the buffer data [I] ID verify Verify the ID data is 0x43H 0x59H or not. [L] Load BIN file to buffer Load the program .bin file to buffer **The program file data is located at 0xE000 ~ 0XFFFF, the .bin file needs to move 0x0000 ~ 0x1FFFF to 0xE000 ~ 0XFFFF [P] Program Hardware code in buffer burn into IC .com t4U.com DataShee [R] Read Read the IC data to buffer memory [W] Save buffer to disk Save the buffer data to disk [S] Security As executed, the code on ROM can not read out of it [Q] Quit Exit the programmer program .com 2004/July V1.00 46 DataSheet 4 U .com www..com CHESEN Programmer Schematic J1 1 2 3 4 CON4 CSC0100P 65C02 with USB and PS/2 Interface OTP Controller VCC_IN R1 C1 10U J2 1 U1 Vin 7812 GND Vout 3 C2 4.7U V12V C3 0.1U 1 U2 Vin 7805 GND Vout 3 C4 4.7U VCC C5 0.1U GND SIP\2P GND D1 1N4148 1 U4 Vin 7805 Vout GND 1 2 OTP-12V OTP-CLK OTP-DATA OTP-CE 3 C6 4.7U V6.25V C7 0.1U U5 1 2 3 4 5 6 7 8 9 U3 DIP18 SOCKET 18 17 16 15 14 13 12 11 10 GND OTP-6.25V OTP-PGM OTP-OE 2 2 6 5 4 3 2 1 44 43 42 41 40 J3 1 2 3 4 SIP\4P GND D2 1N4148 J4 1 2 SIP\2P D3 1N4148 OTP-12V OTP-CLK OTP-DATA 7 8 9 10 11 12 13 14 15 16 17 VPP P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P36 P35 P34 P33 P32 P31 P30 DMINUS DPLUS USB3V3 PADGND GND J5 1 2 JACK D4 1N4148 VCC_IN GND LQFP44 OTP-CE OSC1 OSC2 VCC SELPAD LED3 LED2 LED1 LED0 P27 P26 P25 39 38 37 36 35 34 33 32 31 30 29 GND OTP-6.25V OTP-12V OTP-CLK OTP-DATA OTP-CE 1 2 3 4 5 6 7 8 9 10 U6 DIP20 20 19 18 17 16 15 14 13 12 11 GND OTP-6.25V 2 OTP-PGM OTP-OE GND OTP-OE OTP-PGM OTP-12V OTP-CLK OTP-DATA V6.25V 1 10K R2 C VCC 1 VCC R4 10K SCLK SCE SPGM SOE 2 3 4 5 6 7 8 9 10 19 1 OTP-CE J6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SIP\16P OTP-12V OTP-CLK OTP-DATA OTP-CE OTP-OE OTP-PGM GND OTP-6.25V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 U7 DIP40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND OTP-6.25V 18 19 20 21 22 23 24 25 26 27 28 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 OTP-PGM OTP-OE R3 10K P1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 CON\DB25HM CLK CE DATA0 PGM OE A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 GND G DIR VCC P36 P35 P34 P33 P32 P31 P30 DMINUS DPLUS USB3V3 PADGND 18 17 16 15 14 13 12 11 20 U8 VCC 6 5 4 3 2 1 44 43 42 41 40 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 GND JP1 1 OTP-CLK OTP-CE OTP-PGM OTP-OE C C 2 3 4 5 6 7 8 9 74LS641 JP2 2 3 4 5 6 7 8 9 10 19 1 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 GND G DIR VCC 18 17 16 15 14 13 12 11 20 OTP-DATA OTP-12V OTP-CLK OTP-DATA OTP-CE 7 8 9 10 11 12 13 14 15 16 17 VPP P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 LQFP44 OSC1 OSC2 VCC SELPAD LED3 LED2 LED1 LED0 P27 P26 P25 39 38 37 36 35 34 33 32 31 30 29 GND OTP-6.25V t4U.com R5 R6 R7 R8 R9 100 100 100 100 100 74LS641 U10A 1 2 3 1 VCC VEE VSS 16 7 8 R10 10K U11A 2 CD4052 Title |