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| www..com DRAM MODULE M53230800DW0/DB0 & M53230810DW0/DB0 EDO Mode 8M x 32 DRAM SIMM using 4Mx4, 4K/2K Refresh, 5V GENERAL DESCRIPTION The Samsung M5323080(1)0D is a 8Mx32bits Dynamic RAM high density memory module. The Samsung M5323080(1)0D consists of sixteen CMOS 4Mx4bits DRAMs in 24-pin SOJ package mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M5323080(1)0D is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. M53230800DW0/DB0 M53230810DW0/DB0 FEATURES * Part Identification - M53230800DW0-C(4096 cycles/64ms Ref, SOJ, Solder) - M53230800DB0-C(4096 cycles/64ms Ref, SOJ, Gold) - M53230810DW0-C(2048 cycles/32ms Ref, SOJ, Solder) - M53230810DB0-C(2048 cycles/32ms Ref, SOJ, Gold) * Extended Data Out * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * TTL compatible inputs and outputs * Single +5V10% power supply PERFORMANCE RANGE Speed -50 -60 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns tHPC 25ns 30ns * 1st Gen. JEDEC standard PDPin & pinout * PCB : Height(1000mil), double sided component PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 A11 Vcc A8 A9 RAS1 RAS0 NC NC Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol NC NC Vss CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC Vss PIN NAMES Pin Name A0 - A11 Function Address Inputs(4K Ref) Address Inputs(2K Ref) Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection DataShee .com W A0 - A10 DQ0 - DQ31 RAS0, RAS1 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC PRESENCE DETECT PINS (Optional) Pin PD1 PD2 PD3 PD4 50NS NC Vss Vss Vss 60NS NC Vss NC NC * Pin connection changing available SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. * NOTE : A11 is used for only M53230800DW0/DB0 (4K ref.) .com DataSheet4 U .com www..com DRAM MODULE FUNCTIONAL BLOCK DIAGRAM CAS0 CAS RAS OE DQ1 U0 DQ2 DQ3 A0A11(A10) DQ4 DQ1 U1 DQ2 DQ3 A0A11(A10) DQ4 DQ0-DQ3 DQ1 DQ2 U8 DQ3 A0DQ4 A11(A10) DQ1 U9 DQ2 DQ3 A0DQ4 A11(A10) M53230800DW0/DB0 M53230810DW0/DB0 RAS0 W W CAS RAS OE RAS1 DQ4-DQ7 CAS RAS OE W W CAS RAS OE CAS1 CAS RAS OE DQ1 U2 DQ2 DQ3 A0A11(A10) DQ4 DQ1 U3 DQ2 DQ3 A0A11(A10) DQ4 DQ8-DQ11 W DQ1 U10 DQ2 DQ3 A0DQ4 A11(A10) W DQ1 U11 DQ2 DQ3 A0DQ4 A11(A10) W CAS RAS OE DQ12-DQ15 CAS RAS OE W CAS RAS OE t4U.com CAS2 CAS RAS OE DQ16-DQ19 .com DQ1 U4 DQ2 DQ3 A0A11(A10) DQ4 DQ1 U5 DQ2 DQ3 A0A11(A10) DQ4 DQ20-DQ23 DQ1 U12 DQ2 DQ3 A0DQ4 A11(A10) W DQ1 U13 DQ2 DQ3 A0DQ4 A11(A10) W CAS RAS OE DataShee W CAS RAS OE W CAS RAS OE CAS3 CAS RAS OE DQ1 U6 DQ2 DQ3 A0A11(A10) DQ4 DQ1 U7 DQ2 DQ3 A0A11(A10) DQ4 DQ24-DQ27 W DQ1 U14 DQ2 DQ3 A0DQ4 A11(A10) W DQ1 U15 DQ2 DQ3 A0DQ4 A11(A10) W CAS RAS OE DQ28-DQ31 CAS RAS OE W A0-A11(A10) Vcc CAS RAS OE W .1 or .22uF Capacitor for each DRAM Vss To all DRAMs .com DataSheet4 U .com www..com DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS M53230800DW0/DB0 M53230810DW0/DB0 Rating -1 to +7.0 -1 to +7.0 -55 to +150 16 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage *1 : VCC+2.0V/20ns, Pulse width is measured at VCC. *2 : -2.0V/20ns, Pulse width is measured at VSS. Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC+1*1 0.8 Unit V V V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol Speed -50 -60 Dont care -50 -60 -50 -60 Dont care -50 -60 Dont care Dont care M53230800DW0/DB0 Min - M53230810DW0/DB0 Min - Max 736 656 Max 896 816 32 896 816 736 656 16 896 816 80 10 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V t4U.com ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL DataShee -80 -10 2.4 - .com 32 736 656 656 576 16 736 656 80 10 0.4 - - -80 -10 2.4 - ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL : Operating Current * (RAS, CAS, Address cycling @tRC=min) : Standby Current (RAS=CAS=W=VIH) : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) : EDO Mode Current * (RAS=VIL, CAS Address cycling : tHPC=min) : Standby Current (RAS=CAS=W=Vcc-0.2V) : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) : Output High Voltage Level (IOH = -5mA) : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle, tHPC. .com DataSheet4 U .com www..com DRAM MODULE CAPACITANCE (TA = 25E , VCC=5V, f = 1MHz) Item Input capacitance[A0-A11(A10)] Input capacitance[W] Input capacitance[RAS0, RAS1] Input capacitance[CAS0 - CAS3] Input/Output capacitance[DQ0-31] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - M53230800DW0/DB0 M53230810DW0/DB0 Max 100 130 70 30 20 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in set-up time Data-in hold time Refresh period (4K Ref) Refresh period (2K Ref) Write command set-up time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Symbol -50 Min Max Min 110 60 15 30 3 3 2 40 60 15 45 10 20 15 5 0 10 0 10 30 0 0 0 10 10 15 10 0 10 64 32 0 5 10 5 10K 45 30 10K 15 50 -60 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns 7 9 9 8 8 13 4 10 3,4,10 3,4,5 3,10 3 6,11,12 2 Note t4U.comCAS hold time 90 tRC 50 tRAC 13 tCAC 25 tAA 3 tCLZ 3 13 tCEZ 2 50 tT 30 tRP 50 10K tRAS 13 tRSH 38 tCSH 8 tCAS .com 10K 20 37 tRCD 15 25 tRAD 5 tCRP 0 tASR 10 tRAH 0 tASC 8 tCAH 25 tRAL 0 tRCS 0 tRCH 0 tRRH 10 tWCH 10 tWP 13 tRWL 8 tCWL 0 tDS 8 tDH 64 tREF 32 tREF 0 tWCS 5 tCSR 10 tCHR 5 tRPC DataShee .com DataSheet4 U .com www..com DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter CAS precharge time (C-B-R counter test cycle) Access time from CAS precharge Hyper page mode cycle time CAS precharge time(Hyper page cycle) RAS pulse width(Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay W pulse width (Hyper Page Cycle) Symbol -50 Min 20 30 25 8 50 30 10 10 5 3 3 15 5 13 13 200K Max M53230800DW0/DB0 M53230810DW0/DB0 -60 Min 20 35 30 10 60 35 10 10 5 3 3 15 5 15 15 200K Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note tCPT tCPA tHPC tCP tRASP tRHCP tWRP tWRH tDOH tREZ tWEZ tWED tWPE 3 13 7,11,12 7,11 NOTES t4U.com 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 8. Either tRCH or tRRH must be satisfied for a read cycle. DataShee 9. These .com parameter are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 12. If RAS goes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condtion of the output is achieved by RAS high going. 13. tASCtCP min .com DataSheet 4 U .com www..com DRAM MODULE READ CYCLE M53230800DW0/DB0 M53230810DW0/DB0 tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH t4U.com tAA tCEZ tCAC .com tCLZ tRAC OPEN tREZ DATA-OUT tWEZ DataShee DQ VOH VOL - Dont care Undefined .com DataSheet4 U .com www..com DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN M53230800DW0/DB0 M53230810DW0/DB0 tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP t4U.com DataShee .com tDS tDH DQ VIH VIL DATA-IN Dont care Undefined .com DataSheet4 U .com www..com DRAM MODULE HYPER PAGE READ CYCLE M53230800DW0/DB0 M53230810DW0/DB0 tRASP RAS VIH VIL o tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA t4U.com tCAC tAA .com tCPA tAA tCAC tRAC tDOH VALID DATA-OUT tCAC tAA tCPA tDOH DataShee tDOH VALID DATA-OUT VALID DATA-OUT DQ VOH VOL - VALID DATA-OUT tCLZ Dont care Undefined .com DataSheet 4 U .com www..com DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN M53230800DW0/DB0 M53230810DW0/DB0 tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS o tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCAH tASC tCAH o o tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL o tWCS tWCH tWP tCWL tRWL tWP tCWL t4U.com DataShee .com tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH o VALID DATA-IN tDS tDH VALID DATA-IN o Dont care Undefined .com DataSheet4 U .com www..com DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don't care DOUT = OPEN tRC RAS VIH VIL - M53230800DW0/DB0 M53230810DW0/DB0 tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don't care t4U.com tRP RAS VIH VIL - DataShee .com tRAS tRC tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. .com DataSheet 4 U .com www..com DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) M53230800DW0/DB0 M53230810DW0/DB0 tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP t4U.com tAA tCAC tCLZ .com tRAC DQ VOH VOL - tCEZ tREZ tWEZ DATA-OUT DataShee OPEN Dont care Undefined .com DataSheet 4 U .com www..com DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN M53230800DW0/DB0 M53230810DW0/DB0 tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tWCS W VIH VIL - tWRP tWCH tWP t4U.com DQ VIH VIL - tDS tDH DataShee .com DATA-IN Dont care Undefined .com DataSheet 4 U .com www..com DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE M53230800DW0/DB0 M53230810DW0/DB0 tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL - tWRP tWRH tAA tRCS tCAC tRRH tRCH tWEZ tCLZ DATA-OUT tCEZ tREZ DQ VOH VOL - t4U.com WRITE CYCLE W VIH VIL - tWRP tWRH tRWL DataShee .com tWCS tCWL tWCH tWP tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. .com DataSheet 4 U .com www..com DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care M53230800DW0/DB0 M53230810DW0/DB0 tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCHS tCSR tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH t4U.com DataShee TEST MODE IN CYCLE NOTE : OE , A = Dont care .com tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Dont care Undefined .com DataSheet 4 U .com www..com DRAM MODULE PACKAGE DIMENSIONS M53230800DW0/DB0 M53230810DW0/DB0 Units : Inches (millimeters) 4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA.002(3.18.051) .400(10.16) 1.00(25.40) .250(6.35) .080(2.03) .250(6.35) .250(6.35) 3.750(95.25) R.062.004(R1.57.10) .125(3.17) MIN ( Front view ) t4U.com .com ( Back view ) Gold & Solder Plating Lead .350(8.89) MAX .010(.25)MAX .100(2.54) MIN .225(5.71) MIN .050(1.27) .041.004(1.04.10) .054(1.37) .047(1.19) Tolerances : .005(.13) unless otherwise specified NOTE : The used device are 4Mx4 EDO DRAM (SOJ & 300mil) DRAM Part No. : M53230800DW0/DB0 -- K4E170411D-B (300 mil) M53230810DW0/DB0 -- K4E160411D-B (300 mil) Revision History Rev 0.0 : Oct. 1999 .com DataSheet 4 U .com |
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