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SPECIFICATIONS FOR LCD MODULE
CUSTOMER CUSTOMER PART NO. AMPIRE PART NO. APPROVED DATE
Approved For Specifications Approved For Specifications & Sample AMPIRE CO., LTD. 2F., No.88, Sec. 1, Sintai 5th Rd., Sijhih City, Taipei County 221, Taiwan (R.O.C.) 88 2 ( D ) TEL:886-2-26967269 , FAX:886-2-26967196 or 26967270 APPROVED BY CHECKED BY ORGANIZED BY
AM-320240NSTNQW-TW0H
BY
Date : 2009/10/21
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RECORD
Revision Date Page 2009/10/21 --
OF
REVISION
Contents Editor John
New Release
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1 Features
5.7 inch Amorphous-TFT-LCD (Thin Film Transistor Liquid Crystal Display) module. This module is composed of a 5.7" TFT-LCD panel, LCD controller, power driver circuit, touch panel and backlight unit. 1.1 TFT Panel Feature : (1) Construction: 5.7" a-Si color TFT-LCD, White LED Backlight, touch panel and PCB. (2) Resolution (pixel): 320(R.G.B) X240 (3) Number of the Colors : 262K colors ( R , G , B 6 bit digital each) (4) LCD type : Transmissive Color TFT LCD ( normally White) (5) Interface: 33 pin pitch 0.5 FFC (6) Power Supply Voltage: Single power input. Built-in power supply circuit. (7) Viewing Direction:12 O'clock (The direction it's hard to be discolored ): 1.2 LCD Controller Feature: (1) MCU interface 8/9/16/18 bit 80&68 series MCU interface. (2) Display RAM size : 640x240x3x6 bits. Ex:320x240 two frame buffer with 262K colors. (3) Arbitrary display memory start position selection. (4) MCU interface : 16 bit 80 MPU interface. (5) 8 bit / 16 bit interface support 65K ( R5G6B5) /262K(R6G6B6) colors data format. (6) 9 bit / 18 bit interface support 262K(R6G6B6) colors data format only.
2 Physical specifications
Item Display resolution Active area Screen size Pixel size Color configuration Overall dimension Backlight unit Specifications 960 (W) x 240(H) 115.2 (W) x 86.4 (H) 5.7(Diagonal) 120 (W) x 360 (H) R.G.B stripe 144.0(W)x104.6(H)x14.57(D) LED Unit dot mm inch um mm
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3 Default Setting & Option
Interface : The user can select the MCU interface by change the Jumper & Resister Array. Setting JP1 RA1 RA2 RA3 RA4 Remark Interface Type 80-18Bit interface 80-16Bit interface 80-9Bit interface 80-8Bit interface 68-18Bit interface 68-16Bit interface 68-9Bit interface 68-8Bit interface Connector 33Pin Pin Header ( Pitch 0.5 x 33 pin) 1,2 short 2,3 open 1,2 short 2,3 open 1,2 short 2,3 open 1,2 short 2,3 open 1,2 open 2,3 short 1,2 open 2,3 short 1,2 open 2,3 short 1,2 open 2,3 short 2K OPEN OPEN OPEN ohm OPEN 2K OPEN OPEN ohm OPEN OPEN 2K OPEN ohm OPEN OPEN OPEN 2K ohm 2K OPEN OPEN OPEN ohm OPEN 2K OPEN OPEN ohm OPEN OPEN 2K OPEN ohm OPEN OPEN OPEN 2K ohm 80/68 8/9/16/18 bit interface
Default
Default
4 Electrical specification
4.1 Absolute max. ratings 4.1.1 Electrical Absolute max. ratings Item Power voltage
Input voltege
Symbol Condition VDD VBin
B
Min. -0.3 -0.3
Max. 5.5 VDD+0.3
Unit V V
Remark
VSS=0
Note 1
Note1: /CS,/WR,/RD,RS,DB0~DB7
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4.1.2 Environmental Absolute max. ratings OPERATING STORAGE Item MIN MAX MIN MAX Temperature Humidity Corrosive Gas -20 Note1 Not Acceptable 70 -30 Note1 Not Acceptable 80
Remark Note1,2,3,4,5,6
Note1 : Ta <= 40 : 85% RH max Ta > 40 : Absolute humidity must be lower than the humidity of 85%RH at 40 Note2 : Background color changes slightly depending on ambient temperature. This phenomenon is reversible. Note3 : The response time will be slower at low temperature. Note4 : Only operation is guarantied at operating temperature. Contrast , response time, another display quality are evaluated at +25 Note5 : This is panel surface temperature, not ambient temperature. Note6 : When LCM be operated over than 40 , the life time of the LED back-light will be reduced.
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4.1.3 LED back-light Unit Absolute max. ratings Item Peak forward Current Reverse Voltage Symbol IF VR Ratings 360 12 Unit mA V Remark
4.2 Electrical characteristics 4.2.1 DC Electrical characteristic of the LCD Typical operating conditions (VSS=0V) Item Symbol Min. Typ. Power supply Input Voltage for logic Output Voltage for Logic H Level L Level H Level L Level VDD VBIH VBIL
B
Max. 5.2 5.5 0.8 VDD 0.4
Unit Remark V V V V V mA Note 1
3.1 2.0 VSS
5.0 -
B
VBOH VBOL
B
2.4 VSS -
Note 2 Note 3
B
Power Supply current
IDD
150
-
Note1: With 5V Tolerance Input , /CS, /WR,/RD,RS,DB0~DB17 Note2: DB0~DB17 Note3: fV =60Hz , Ta=25 , VDD=3.3V , DCLK=10MHz, PLL frequency=40MHz, Display pattern : All Black 4.2.2 Electrical characteristic of LED Back-light Parameter Symbol Min. Typ. Max. Unit LED voltage VBAK -10.5 -V
B
Condition Just for reference Ta=25 Ta=60
LED forward current
IBLED IBLED
B
---
320 210
---
mA mA
B
The constant current source is needed for white LED back-light driving. When LCM is operated over 60 ambient temperature, the IBLED of the LED
B
back-light should be adjusted to 210mA max
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4.3 AC Timing characteristic of the Graphic TFT LCD controller 4.3.1 80 series Timing
Symbol tcycle
PWHW PWLW tAS tAH tDSW tHWR tcsb-s tcsb-h
Parameter Enable cycle time
Enable high-level pulse width Enable low-level pulse width RS setup time RS hold time Write data setup time Write data hold time CSB setup time CSB hold time
Min 100
66 33 16 16 50 50 16 16
Typ 200
70 130 25 45 50 40 20 30
Max
Unit Remark ns ns ns ns ns ns ns ns ns
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4.3.2 68eries Timing
Symbol tcycle PWEH PWEL tASE tAHE tDSWE tHE tcsb-s tcsbh
Parameter Enable cycle time Enable high-level pulse width Enable low level pulse width RS setup time RS hold time Write data setup time Write data hold time CSB setup time CSB hold time
Min 100 66 33 16 16 50 50 16 16
Typ 200 70 130 25 45 50 40 20 30
Max
Unit Remark ns ns ns ns ns ns ns ns ns
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5
Optical specification 5.1 Optical characteristic :
Item Symbol Condition Min. Typ. Max. Unit Remark
Response Time
Rise Fall
TBr TBf
B
=0
At optimized viewing angle
B
200 55 45 55 55 --0.262 0.279
15 35 350 60 50 60 60 500 70 0.312 0.329
30 50 --0.362 0.379
ms ms
Note 1,2,3,5 Note 1,2,4,5
Contrast ratio Top
Bottom
CR
Viewing Angle
Left Right
CR10
IBLED=320mA
deg. cd/mP2
P
Note1,2,5,6 Note1.2 Note 8
Brightness of LCM Uniformity White chromaticity XW YW
Ta=25
IBLED=320mA
Ta=25
%
( )For reference only. These data should be update according the prototype. Note 1: Ambient temperature=25,and lamp current I LED o be measured in the dark room. Note 2:To be measured on the center area of panel with a viewing cone of 1by Topcon luminance meter BM-7,after 10 minutes operation. Note 3.Definition of response time: The output signals of photo detector are measured when the input signals are changed from "black" to "white"(falling time) and from "white" to "black" (rising time), respectively. The response time is defined as the time interval between the 10% and 90% of amplitudes. Refer to figure as below.
B B=320mA.T
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Note 4.Definition of contrast ratio: Contrast ratio is calculated with the following formula. Contrast ratio(CR)=
Photo detector output when LCD is at "White" state Photo detector Output when LCD is at "Black" state
Note 5.Definition of viewing angle, Refer to figure as below.
Note 6.Measured at the center area of the panel when all the input terminals of LCD panel are electrically opened. Ring light
LCD module
Brightness gauge BM-7 (Topcon)
Metal halide lamp Glass fiber LIGHT:OFF, LIGHT:ON
LCD Optical Detector
Brightness gauge BM-7 (Topcon)
LED
LIGHT:ON, LIGHT:OFF
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Note8: Measurement of the following 9 places on the display.
The Uniformity definition (Min Brightness / Max Brightness) x 100%
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6
Interface specifications
6.1Driving signals for the TFT panel Pin no Symbol I/O Description Remark 1 /RESET I Reset Signal 80 Series: Write Signal 2 /WR I 68 Series: R/W Signal 3 /CS I Chip Select Signal 4 RS I Data type selection 80 Series: Read signal 5 RD II 68 Series: Enable signal(E) 6 D0 I/O 7 D1 I/O 8 D2 I/O 9 D3 I/O Data input/output 10 D4 I/O 11 D5 I/O 12 D6 I/O 13 D7 I/O 14 DGND I Ground 15 D8 I/O 16 D9 I/O 17 D10 I/O 18 D11 I/O 19 D12 I/O 20 D13 I/O 21 D14 I/O 22 D15 I/O Data input/output 23 D16 I/O 24 D17 I/O 25 VDD P Power Supply for Logic 26 VDD P 27 DGND P Ground 28 DGND P When use 8 or 16 bit MPU interface. The 65k/262k data format can be select. Lo:65K Hi:262K colors 29 65K/262K I When use 9 or 18bit MPU interface. The 262K data can be used only. The 65K/262K pin must set to Hi 30 DGND P Ground 31 NC Not use 32 NC Not use 33 NC Not use
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BLOCK DIAGRAM
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8
Interface Protocol
8.1.1 16Bit-80/68- Write to Command Register
8.1.2 16Bit-80/68-Write to Display RAM
/CS 80 mode 68 mode /RD /WR E R/W RS DB[15:0]
Note1
Display RAM Write Enable 0x000C1
Note2
Send Data1
Note3
Send Data2
Note4
Send DataN
Note5
Display RAM Write Disable 0x00080
Note1: DB[15:0] send 0x000C1 to Enable the Display RAM write. Note2: DB[15:0] represent the writing Data1 to Display RAM Note3: DB[15:0] represent the writing Data2 to Display RAM Note4: DB[15:0] represent the writing DataN to Display RAM Note5: DB[15:0] send 0x00080 to Disable the Display RAM write.
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8.2
Data transfer order Setting 8.2.1 16 bit interface 65K color (Pin29 65K/262K =Low) 15 14 13 12 11 10 9 8 7 6 5 4
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4
DB
3
B3
2
B2
1
B1
0
B0
8.2.2 16 bit interface 262K color (Pin29 65K/262K =High) DB 15 14 13 12 11 10 9 8 7 6 5 4 3 1Pst data XXXXXXXXXXXXX
P
2P
nd
2 X
B2
1
R5 B1
0
R4 B0
P
data
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
8
Register Depiction
Default (Hex) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark
Register Address (Hex) 00 Description Register Address (Hex) 01 Description Register Address (Hex) 02 Description Register Address (Hex) 03 Description Register Address (Hex) 04 Description Register Address (Hex) 05
Description
MSB of X-axis start position 00 set the horizontals start position of display active region
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis start position 00 set the horizontals start position of display active region
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis end position 01 set the horizontals end position of display active region
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis end position 3F set the horizontals end position of display active region
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis start position 00 set the vertical start position of display active region
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of Y-axis start position 00 Set the vertical start position of display active region
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Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) MSB of Y-axis end position 06 00 Description set the vertical end position of display active region Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) LSB of Y-axis end position 07 EF Description Set the vertical end position of display active region
Remark
Remark
To simplify the address control of display RAM access, the window area address function allows for writing data only within a window area of display RAM specified by registers REG[00]~REG[07] . After writing data to the display RAM, the Address counter will be increased within setting window address-range which is specified by MIN X address (REG[0] & REG[1]) MAX X address (REG[2] & REG[3]) MIN Y address (REG[4] & REG[5]) MAX Y address (REG[6] & REG[7]) Therefore, data can be written consecutively without thinking the data address.
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Register Address (Hex) 08
Default DB7 DB6 DB5 DB4 (Hex) 01 X X X X
DB3 X
DB2 X
DB1
DB0
Remark
_PanelXSize H_Byte[1:0]
Description Set the panel X size Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 (Hex) (Hex) 09 40 _PanelXSize L_Byte[7:0] Description Set the panel X size
DB0
Remark
The register REG[08] and REG[09] is use to calculate the RAM address. If you want to use the TFT as Landscape mode (320x240), the REG[08] & RGE[09 must set to 320. If you want to use the TFT as Portrait mode (240x320), the REG[08] & RGE[09] must set to 240. Register Address (Hex) 0A Default (Hex) 00
DB7 DB6 DB5 DB4 X X X X
DB3 X
DB2 DB1
DB0
Remark
[17:16] bits of memory write start address
Description Memory write start address Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) [15:8] bits of memory write start address 0B 00 Description Memory write start address Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) [7:0] bits of memory write start address 0C 00 Description Memory write start address
Remark
Remark
BUS_SEL Blanking P/S_SEL CLK_SEL 0x0D Bit_SWAP OUT_TEST "0x10_Clk_sel[1:0]" : The TFT controller built-in 40Mhz PLL clock. These bits Description are for select the TFT panel dot clock frequency. 00 : 20Mhz 01: 10Mhz 02: 5 Mhz "0x10_ps_sel[2]" : The TFT controller support parallel and serial RGB interface. These bits are for select the output timing. 0 : serial Panel 1: Parallel panel
Register Address (Hex) 0x10
Default (Hex)
DB7
DB6
DB5 DB4
DB3
DB2
DB1 DB0 Remark
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"0x10_blanking_tmp[3]" 0 : OFF (blanking) 1: ON ( normal operation) "0x10_bus_sel[5:4]" : It only for serial Panel 00=R , 01=G , 10=B "0x10_out_test[6]" : Self test 0 : normal operation 1: for test (don't use for normal operation) When set the bit to "1" , the Rout=(Reg 2a[6:0]) Gout=(Reg 2b[6:0]) Bout=(Reg 2c[6:0]) "0x10_bit_swap[7]" : 0-normal The default setting is suitable for AM320240N1. Don't need to modify it. Register Address (Hex) 0x11 Default (Hex) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark
Description
X X EVEN _ODD 00 " Even line of serial panel data out sequence or data bus order of parallel panel 000: RGB 001: RBG 010: GRB 011: GBR 100: BRG 101: BGR Others: reserved
Odd line of serial panel data out sequence 000: RGB 001: RBG 010: GRB 011: GBR 100: BRG 101: BGR Others: reserved Must Set to 0x05 for AM320240N1
00 Hsync_stH_Byte[3:0] For TFT output timing adjust: Description Hsync start position H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x13 00 Hsync_stL_Byte[7:0] For TFT output timing adjust: Description Hsync start position L-Byte The default setting is suitable for AM320240N1. Don't need to modify it.
Register Address (Hex) 0x12
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
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00 Hsync_pwH_Byte[3:0] For TFT output timing adjust: Description Hsync pulse width H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x15 10 Hsync_pwL_Byte[7:0] For TFT output timing adjust: Description Hsync pulse width L-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x16 00 Hact_stH_Byte[3:0] For TFT output timing adjust: Description DE pulse start position H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x17 38 Hact_stL_Byte[7:0] For TFT output timing adjust: Description DE pulse start position L-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x18 01 Hact_pwH_Byte[3:0] For TFT output timing adjust: Description DE pulse width H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x19 40 Hact_pwL_Byte[7:0] For TFT output timing adjust: Description DE pulse width L-Byte The default setting is suitable for AM320240N1. Don't need to modify it.
Register Address (Hex) 0x14
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
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01 HtotalH_Byte[3:0] For TFT output timing adjust: Description Hsync total clocks H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x1B B8 HtotalL_Byte[7:0] For TFT output timing adjust: Description Hsync total clocks H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x1C 00 Vsync_stH_Byte[3:0] For TFT output timing adjust: Description Vsync start position H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x1D 00 Vsync_stL_Byte[7:0] For TFT output timing adjust: Description Vsync start position L-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x1E 00 Vsync_pwH_Byte[3:0] For TFT output timing adjust: Description Vsync pulse width H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x1F 08 Vsync_pwL_Byte[7:0] For TFT output timing adjust: Description Vsync pulse width L-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x20 00 Vact_stH_Byte[3:0] For TFT output timing adjust: Description Vertical DE pulse start position H-Byte The default setting is suitable for AM320240N1. Don't need to modify it.
Register Address (Hex) 0x1A
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
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12 Vact_stL_Byte[7:0] For TFT output timing adjust: Description Vertical DE pulse start position L-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x22 00 Vact_pwH_Byte[3:0] For TFT output timing adjust: Description Vertical Active width H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x23 F0 Vact_pwL_Byte[7:0] For TFT output timing adjust: Description Vertical Active width H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x24 01 VtotalH_Byte[3:0] For TFT output timing adjust: Description Vertical total width H-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x25 09 VtotalL_Byte[7:0] For TFT output timing adjust: Description Vertical total width L-Byte The default setting is suitable for AM320240N1. Don't need to modify it. Register Address (Hex) 26 Default (Hex) 00
Register Address (Hex) 0x21
Default (Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
DB7 DB6 DB5 DB4 X X X X
DB3 X
DB2 DB1
DB0
Remark
[17:16] bits of memory read start address
Description Memory read start address Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) [15:8] bits of memory write start address 27 00 Description Memory read start address
Remark
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Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) [7:0] bits of memory write start address 28 00 Description Memory read start address Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) [7:1] Reversed 29 00 [0] Load output timing related setting (H sync., V sync. and DE) to take Description effect Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x2A 00 X TestPatternRout[6:0] When " REG[0x10]_out_test[6]" : Self test =1 ; Description The Rout data equal to TestPatternRout[6:0] Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x2B 00 X TestPatternGout[6:0] When " REG[0x10]_out_test[6]" : Self test =1 ; Description The Gout data equal to TestPatternGout[6:0] Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Remark (Hex) (Hex) 0x2C 00 X TestPatternBout[6:0] When " REG[0x10]_out_test[6]" : Self test =1 ; Description The Bout data equal to TestPatternBout[6:0] If you set the " REG[0x10]_out_test[6]" : Self test =1 , the TFT controller will skip the connect of the display RAM. The Output port will send the REG[2A] ,REG[2B],REG[2C] data.
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Register Address (Hex) 0x2D
Default DB7 DB6 DB5 DB4 DB3 (Hex) 00 X X X X [3]
DB2
DB1 DB0 Remark
Rising/falling _rotate edge[2] [1:0] [3] Output pin X_DCON level control ; TFT Power ON/OFF control 0: TFT POWER circuit OFF 1: TFT POWER circuit ON Rising/falling edge[2] : 0: The RGB out put data are on the Rising edge of the DCLK. Description 1: The RGB out put data are on the Falling edge of the DCLK. _rotate [1:0]: 00 : rotate 0 degree 01 : rotate90 degree 10 : rotate 270 degree 11 : rotate 180 degree Register Address (Hex) 30 Default (Hex) 00
DB7 DB6 DB5 DB4 X X X X
DB3 X
DB2 DB1 DB0 _H byte H-Offset[3:0]
Remark
Description Set the Horizontal offset Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) 31 00 _L byte H-Offset[7:0] Description Set the Horizontal offset
Remark
Register Address (Hex) 32
Default (Hex) 00
DB7 DB6 DB5 DB4 X X X X
DB3 X
DB2 DB1 DB0 _H byte V-Offset[3:0]
Remark
Description Set the Vertical offset Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) 33 00 _L byte V-Offset[7:0] Description Set the Vertical offset
Remark
Register Address (Hex) 34
Description
Default (Hex) 00
DB7 DB6 DB5 DB4
[7:4] Reserved
DB3
DB2 DB1 DB0
Remark
_H byte H-def[3:0] [3:0] MSB of image horizontal physical resolution in memory
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Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) 35 40 _L byte H-def[7:0] Description [7:0] LSB of image horizontal physical resolution in memory Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) _H byte [7:4] Reserved 36 01 V-def[3:0] Description [3:0] MSB of image vertical physical resolution in memory Register Default Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (Hex) (Hex) 37 E0 _L byte V-def[7:0] Description [7:0] LSB of image vertical physical resolution in memory
Remark
Remark
Remark
The total RAM size is 640x240x18bit. The user can arrange the Horizontal ram size by REG[34],REG[35] and the Vertical ram size by REG[36],REG[37]. EX: 320x480x18bit REG[34]=0x01 , REG[35]=0x40 , REG[36]=0x01 , REG[37]=0xE0 EX: 640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 , REG[37]=0xF0
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Application Note:
/* Exported types ------------------------------------------------------------*/ typedef typedef typedef typedef typedef typedef unsigned char signed signed signed char short int unsigned short unsigned long uint8; int8; uint16; int16; uint32; int32;
/*****************************************************************/ /* STEP1: Define MCU BUS type #define Mode80 //#define Mode68 /* // 8080 MCU /WR /RD // 6800 MCU R/W E */ */ /*****************************************************************/
/*****************************************************************/ STEP2: Define BUS wide //#define C80_18B //#define C80_16B //#define C80_9B #define C80_8B /*****************************************************************/ /* STEP3: Define Landscap/Portrait #define Landscap //#define Portrait /*****************************************************************/ /* #ifdef Landscap #define #define #endif #ifdef Portrait Resolution_X 320 Resolution_Y 240 STEP4: Define Resolution */ /*****************************************************************/ */ /*****************************************************************/ /*****************************************************************/
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#define #define #endif
Resolution_X 240 Resolution_Y 320
/*****************************************************************/ /* STEP5: TFT timing // Don't need to change // Don't need to change */ /*****************************************************************/ # define Rising 0<<2 # define Falling 1<<2
#define LCD_DCLK 10
//Select DCLK Frequency MHz /* LCD_DCLK=(40*(0x42)/(0x41))/R10_B10*/ /*5, 6.67, 7.5, 8.57, 10, 12, 15, */ //Can be 5 , 6 , 7 , 8 ,10,12 ,15
#define LCD_DCLK_Latch
Rising //Rising: for Rising Edge //Falling: for Rising Edge
#define H_Sync_Pluse_Wide 10 #define H_Sync_to_DE #define H_Sync_total #define V_Sync_to_DE #define V_Sync_total 68 440 16 265
// Hsync Pluse Wide // DE horizontal start position // Horizontal total // DE vertical start position // Vertical total
#define V_Sync_Pluse_Wide 8// Vsync Pluse Wide
//*************************************************************// /**************Don't need to change the bellow macro**************/ #if LCD_DCLK== 5 #define R41 #define R42 #endif #if LCD_DCLK== 6 #define R41 3 1 1
#define R10_B10 2
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#define R42 #endif #if LCD_DCLK== 7 #define R41 #define R42 #endif #if LCD_DCLK== 8 #define R41 #define R42 #endif #if LCD_DCLK== 10 #define R41 #define R42 #endif #if LCD_DCLK== 12 #define R41 #define R42 #endif
4
#define R10_B10 2
4 3
#define R10_B10 1
12 10
#define R10_B10 1
1 2
#define R10_B10 2
5 6
#define R10_B10 1
#if LCD_DCLK== 15 #define R41 #define R42 #endif 2 3
#define R10_B10 1
#define _DisplayRAM_WriteEnable_ 0xc1 #define _DisplayRAM_WriteDisable_ 0x80
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typedef struct { uint8 REG_Index; uint8 REG_Value; }FSA506_REG_Setting; #ifdef Landscap static FSA506_REG_Setting FSA506_A[] = { {0x40,0x12}, {0x41,R41}, {0x42,R42}, {0x08,(uint8)(Resolution_X>>8)}, {0x09,(uint8)(Resolution_X)}, {0x0a,0x00}, {0x0b,0x00}, {0x0c,0x00}, {0x10,0x0C|R10_B10}, //{0x10,0x0C|0x02}, {0x11,0x05}, {0x12,0x00}, {0x13,0x00}, {0x14,(uint8)(H_Sync_Pluse_Wide>>8)}, {0x15,(uint8)(H_Sync_Pluse_Wide)}, {0x16,(uint8)(H_Sync_to_DE>>8)}, {0x17,(uint8)(H_Sync_to_DE)}, {0x18,(uint8)(Resolution_X>>8)}, {0x19,(uint8)(Resolution_X)}, {0x1a,(uint8)(H_Sync_total>>8)}, {0x1b,(uint8)(H_Sync_total)}, {0x1c,0x00}, {0x1d,0x00}, {0x1e,(uint8)(V_Sync_Pluse_Wide>>8)},
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{0x1f,(uint8)(V_Sync_Pluse_Wide)}, {0x20,(uint8)(V_Sync_to_DE>>8)}, {0x21,(uint8)(V_Sync_to_DE)}, {0x22,(uint8)(Resolution_Y>>8)}, {0x23,(uint8)(Resolution_Y)}, {0x24,(uint8)(V_Sync_total>>8)}, {0x25,(uint8)(V_Sync_total)}, {0x26,0x00}, {0x27,0x00}, {0x28,0x00}, {0x29,0x01},
{0x2d,LCD_DCLK_Latch|0x08}, // [7:4] Reserved // [3] Output pin X_DCON level control // [2] Output clock inversion // [1:0] Image rotate // 00: 0 01: 90 10: 270 11: 180 0: Normal 1: Inverse
{0x30,0x00}, {0x31,0x00}, {0x32,0x00}, {0x33,0x00}, {0x34,(uint8)(Resolution_X>>8)}, {0x35,(uint8)(Resolution_X)}, {0x36,(uint8)((2*Resolution_Y)>>8)}, {0x37,(uint8)(2*Resolution_Y)}, }; #endif #ifdef Portrait static FSA506_REG_Setting FSA506_A[] = { {0x40,0x12},
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{0x41,R41}, {0x42,R42}, {0x08,(uint8)(Resolution_X>>8)}, {0x09,(uint8)(Resolution_X)}, {0x0a,0x00}, {0x0b,0x00}, {0x0c,0x00}, {0x10,0x0C|R10_B10}, //{0x10,0x0C|0x02}, {0x11,0x05}, {0x12,0x00}, {0x13,0x00}, {0x14,(uint8)(H_Sync_Pluse_Wide>>8)}, {0x15,(uint8)(H_Sync_Pluse_Wide)}, {0x16,(uint8)(H_Sync_to_DE>>8)}, {0x17,(uint8)(H_Sync_to_DE)}, {0x18,(uint8)(Resolution_Y>>8)}, {0x19,(uint8)(Resolution_Y)}, {0x1a,(uint8)(H_Sync_total>>8)}, {0x1b,(uint8)(H_Sync_total)}, {0x1c,0x00}, {0x1d,0x00}, {0x1e,(uint8)(V_Sync_Pluse_Wide>>8)}, {0x1f,(uint8)(V_Sync_Pluse_Wide)}, {0x20,(uint8)(V_Sync_to_DE>>8)}, {0x21,(uint8)(V_Sync_to_DE)}, {0x22,(uint8)(Resolution_X>>8)}, {0x23,(uint8)(Resolution_X)}, {0x24,(uint8)(V_Sync_total>>8)}, {0x25,(uint8)(V_Sync_total)}, {0x26,0x00}, {0x27,0x00}, {0x28,0x00}, {0x29,0x01},
{0x2d,LCD_DCLK_Latch|0x08|0x01}, // [7:4] Reserved
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// [3] Output pin X_DCON level control // [2] Output clock inversion // [1:0] Image rotate // 00: 0 01: 90 10: 270 11: 180 0: Normal 1: Inverse
{0x30,0x00}, {0x31,0x00}, {0x32,0x00}, {0x33,0x00}, {0x34,(uint8)(Resolution_X>>8)}, {0x35,(uint8)(Resolution_X)}, {0x36,(uint8)((2*Resolution_Y)>>8)}, {0x37,(uint8)(2*Resolution_Y)}, }; #define #endif /**************Don't need to change the above macro**************/ NOP() __asm{NOP}
void AMP506_80Mode_Command_SendAddress(uint8 Addr); void AMP506_80Mode_Command_SendData(uint8 Data); void AMP506_80Mode_16Bit_Memory_SendData(uint16 Dat16bit); void AMP506_Command_Write(uint8 CMD_Address,uint8 CMD_Value); void Initial_AMP506(void) ; void AMP506_WindowSet(uint16 S_X,uint16 S_Y,uint16 E_X,uint16 E_Y) ; void FD506_DisplayRAM_WriteEnable(void); void FD506_DisplayRAM_WriteDisable(void); void GUI_RectangleFill(uint32 x0, uint32 y0, uint32 x1, uint32 y1, uint16 color); void Full_LCD(uint16 Dat16bit); void LCD_Pixel(uint16 x , uint16 y , uint16 couleur); /**************FSA506 Write Registr Address function *************************/ void AMP506_80Mode_Command_SendAddress(uint8 Addr) {
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#ifdef Mode68 uint16 i; CLR_nWRL; CLR_RS; CLR_CS1; CLR_nRD; DB16OUT(Addr); NOP();NOP(); SET_nWRL; CLR_nWRL; SET_RS; SET_CS1; #endif //Enable //Enable NOP();NOP();NOP(); NOP();NOP();//NOP(); NOP();NOP();NOP();
#ifdef Mode80 SET_nRD; CLR_RS; DB16OUT(Addr); NOP(); CLR_CS1; CLR_nWRL; NOP();NOP();NOP(); SET_nWRL; SET_RS; SET_CS1; #endif //SER_E // Low to High Latch Data to AMP506 Buffer //CLR_E //SET_RW
} /**************FSA506 Write Command Data function *************************/ void AMP506_80Mode_Command_SendData(uint8 Data) { #ifdef Mode68 uint16 i;
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CLR_nWRL; SET_RS; CLR_CS1; CLR_nRD; NOP();NOP(); SET_nWRL;
//E
//W/R
DB16OUT(Data);
NOP();NOP();NOP();NOP();NOP();//NOP();NOP();NOP(); CLR_nWRL; SET_RS; SET_CS1; #endif #ifdef Mode80 SET_nRD; SET_RS; DB16OUT(Data); NOP(); // NOP() CLR_CS1; CLR_nWRL; NOP();NOP();NOP(); SET_nWRL; SET_RS; SET_CS1; #endif } /**************FSA506 Write Data function *************************/ void AMP506_80Mode_16Bit_Memory_SendData(uint16 Dat16bit) { // Low to High Latch Data to AMP506 Buffer //E nable
#ifdef Mode80 #ifdef C80_16B SET_nRD; SET_RS; DB16OUT(Dat16bit);NOP();
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CLR_CS1; CLR_nWRL; NOP(); NOP(); NOP(); SET_nWRL; SET_CS1; #endif #ifdef C80_8B DB16OUT(Dat16bit>>8);NOP();NOP(); SET_nRD; SET_RS; CLR_CS1; CLR_nWRL; NOP(); NOP(); NOP(); SET_nWRL; SET_CS1; //Delay_uS(1); DB16OUT(Dat16bit);NOP(); NOP(); SET_nRD; SET_RS; CLR_CS1; CLR_nWRL; NOP(); NOP(); NOP(); SET_nWRL; SET_CS1; #endif //Delay_uS(1); // Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer
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#ifdef C80_18B uint32 k=0; uint16 R_temp,G_temp,B_temp; R_temp=((0xf800&Dat16bit)>>11); G_temp=((0x07e0&Dat16bit)>>5); B_temp=((0x001f&Dat16bit)); k|=((R_temp<<1)<<12); //+G_temp+B_temp; k|=(G_temp<<6); k|=(B_temp<<1); FIO1MASK=0xFFE0FFFF; FIO1PIN=k; FIO1MASK=0x00; // FIOMASK P1.20~P1.16 // Address A20~A16 P1.20~P1.16
SET_nRD; SET_RS; DB16OUT(k);NOP(); CLR_CS1; CLR_nWRL; NOP(); NOP(); NOP();
SET_nWRL; SET_CS1; #endif #ifdef C80_9B uint32 k=0; uint16 R_temp,G_temp,B_temp; R_temp=((0xf800&Dat16bit)>>11);
// Low to High Latch Data to AMP506 Buffer
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G_temp=((0x07e0&Dat16bit)>>5); B_temp=((0x001f&Dat16bit)); k|=((R_temp<<1)<<12); //+G_temp+B_temp; k|=(G_temp<<6); k|=(B_temp<<1);
SET_nRD; SET_RS; CLR_CS1; CLR_nWRL; DB16OUT(((k&0x3FE00)>>9)); SET_nWRL; DB16OUT((k&0x1FF)); NOP(); SET_CS1; // Delay_uS(1); SET_nRD; SET_RS; CLR_CS1; CLR_nWRL; NOP(); NOP(); NOP(); SET_nWRL; SET_CS1; #endif #endif // Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer
#ifdef Mode68 #ifdef C80_16B uint16 i; NOP();NOP();
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CLR_nWRL; SET_RS; CLR_CS1; CLR_nRD;
//E=0
// W/R=0
DB16OUT(Dat16bit); SET_nWRL; CLR_nWRL; SET_CS1; #endif // Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
#ifdef C80_8B uint16 i; //for (i=0;i<16;i++); NOP();NOP(); CLR_nWRL; SET_RS; CLR_CS1; CLR_nRD; // W/R=0 //E=0
DB16OUT(Dat16bit>>8); SET_nWRL; CLR_nWRL; SET_CS1; CLR_nWRL; SET_RS; CLR_CS1; CLR_nRD; // W/R=0 //E=0 // Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
DB16OUT(Dat16bit);
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SET_nWRL; CLR_nWRL; SET_CS1; #endif //Delay_uS(1);
// Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
#ifdef C80_18B uint32 k=0; uint16 R_temp,G_temp,B_temp; uint16 i; NOP();NOP(); R_temp=((0xf800&Dat16bit)>>11); G_temp=((0x07e0&Dat16bit)>>5); B_temp=((0x001f&Dat16bit)); k|=((R_temp<<1)<<12); //+G_temp+B_temp; k|=(G_temp<<6); k|=(B_temp<<1); FIO1MASK=0xFFE0FFFF; FIO1PIN=k; FIO1MASK=0x00; // FIOMASK P1.20~P1.16 // Address A20~A16 P1.20~P1.16
CLR_nWRL; SET_RS; CLR_CS1; CLR_nRD; DB16OUT(k); SET_nWRL;
//E=0
// W/R=0
// Low to High Latch Data to AMP506 Buffer
NOP();NOP();NOP();NOP();NOP();//NOP();NOP();NOP();
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CLR_nWRL; SET_CS1; #endif #ifdef C80_9B uint32 k=0; uint16 R_temp,G_temp,B_temp; uint16 i; //for (i=0;i<16;i++); NOP();NOP(); R_temp=((0xf800&Dat16bit)>>11); G_temp=((0x07e0&Dat16bit)>>5); B_temp=((0x001f&Dat16bit));
// Low to High Latch Data to AMP506 Buffer
k|=((R_temp<<1)<<12); //+G_temp+B_temp; k|=(G_temp<<6); k|=(B_temp<<1);
CLR_nWRL; SET_RS; CLR_CS1; CLR_nRD;
//E=0
// W/R=0
DB16OUT(((k&0x3FE00)>>9)); SET_nWRL; CLR_nWRL; SET_CS1; // Delay_uS(1); CLR_nWRL; SET_RS; CLR_CS1; //E=0 // Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
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CLR_nRD;
// W/R=0
DB16OUT((k&0x1FF)); SET_nWRL; CLR_nWRL; SET_CS1; #endif #endif // Low to High Latch Data to AMP506 Buffer // Low to High Latch Data to AMP506 Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
} /**************FSA506 Write Command function *************************/ void AMP506_Command_Write(uint8 CMD_Address,uint8 CMD_Value) { AMP506_80Mode_Command_SendAddress(CMD_Address); AMP506_80Mode_Command_SendData(CMD_Value); }
/**************FSA506 Initial function *************************/ void Initial_AMP506(void) { uint8 i; //
for(i=0;i < (sizeof(FSA506_A) / sizeof (FSA506_A[0]));i++) { AMP506_Command_Write(FSA506_A[i].REG_Index , FSA506_A[i].REG_Value); }
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} /**************FSA506 Set Start & End area function *************************/ void AMP506_WindowSet(uint16 S_X,uint16 S_Y,uint16 E_X,uint16 E_Y) { AMP506_80Mode_Command_SendAddress(0x00); AMP506_80Mode_Command_SendData((S_X)>>8); AMP506_80Mode_Command_SendData(S_X); AMP506_80Mode_Command_SendData((E_X-1)>>8); AMP506_80Mode_Command_SendData(E_X-1); AMP506_80Mode_Command_SendData(S_Y>>8); AMP506_80Mode_Command_SendData(S_Y); AMP506_80Mode_Command_SendData((E_Y-1)>>8); AMP506_80Mode_Command_SendData(E_Y-1); } //**************************************************************************** // Enable Display RAM Write //**************************************************************************** void FD506_DisplayRAM_WriteEnable(void) { AMP506_80Mode_Command_SendAddress(_DisplayRAM_WriteEnable_); } //**************************************************************************** // Disable Display RAM Write //****************************************************************************
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void FD506_DisplayRAM_WriteDisable(void) { AMP506_80Mode_Command_SendAddress(_DisplayRAM_WriteDisable_); } /**************FSA506 Set Start & End area function *************************/ void GUI_RectangleFill(uint32 x0, uint32 y0, uint32 x1, uint32 y1, uint16 color) { uint32 k,l;
AMP506_WindowSet(x0,y0,x1,y1); FD506_DisplayRAM_WriteEnable(); for(k=y0;kDate : 2009/10/21
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AMP506_80Mode_Command_SendAddress(0x00); AMP506_80Mode_Command_SendData((x)>>8); AMP506_80Mode_Command_SendData(x); AMP506_80Mode_Command_SendData((x)>>8); AMP506_80Mode_Command_SendData(x); AMP506_80Mode_Command_SendData(y>>8); AMP506_80Mode_Command_SendData(y); AMP506_80Mode_Command_SendData((y)>>8); AMP506_80Mode_Command_SendData(y); FD506_DisplayRAM_WriteEnable(); AMP506_80Mode_16Bit_Memory_SendData(couleur); FD506_DisplayRAM_WriteDisable(); } void main(void) { Initial_AMP506(); Full_LCD(0xf800); Full_LCD(0x07e0); Full_LCD(0x001f); }
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The TFT LCD controller default value is for AM320240NS already. So we can start to write our data in a few steps: Target: To write a 640x240 data to Display RAM and scroll the display data by change the Horizontal offset register. 9.2 Step 1: Make sure the interface Protocol. 9.3 Step 2: Define the Horizontal ram seize = 640 and Vertical ram size =240 640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 , REG[37]=0xF0 9.4 Step 3: Define the Panel X Size = 320 REG[8]=0x02 , REG[9]=0x80 9.5 Step4: Define the Write window. Start=(0,0) End=(619,239) REG[0]=0x00 , REG[1]=0x00 , REG[2]=0x02 , REG[3]=0x6B , // Start X , End X REG[4]=0x00 , REG[5]=0x00 , REG[6]=0x00 , REG[7]=0xEF , // Star Y ,End Y
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9.6 Step5: Write the 640x240x18 bit data consecutively
9.7 Step6: The display will show the following image.
9.8 Step7: Change the Horizontal offset to switch or scroll the display data. Set the Horizontal offset = 160 , REG[30]=00 REG[31]=A0 . You will see
9.9 Step8: Change the Horizontal offset to switch or scroll the display data. Set the Horizontal offset = 320 , REG[30]=01 REG[31]=40 . You will see
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DISPLAYED COLOR AND INPUT DATA
Color & Gray Scale R5 Black Red(63) Green(63) Basic Color Blue(63) Cyan Magenta Yellow White Black Red(1) Red(2) : Red Red(31) : Red(62) Red(63) Black Green(1) Green(2) : Green Green(31) : Green(62) Green(63) Black Blue(1) Blue(2) : Blue Blue(31) : Blue(62) Blue(63) 0 : 0 0 0 0 0 : 0 : 0 0 0 : 0 0 0 0 0 : 0 : 0 0 0 : 0 0 0 0 0 : 0 : 0 0 0 : 0 0 0 0 0 : 0 : 0 0 0 : 0 0 0 0 0 : 0 : 0 0 0 : 0 0 0 0 0 : 0 : 0 0 0 : 1 1 0 0 0 : 0 : 0 0 1 : 1 1 0 0 0 : 0 : 0 0 1 : 1 1 0 0 0 : 0 : 0 0 1 : 1 1 0 0 0 : 0 : 0 0 1 : 1 1 0 0 0 : 0 : 0 0 0 : 0 1 0 0 0 : 0 : 0 0 0 : 0 0 0 0 0 : 0 : 1 1 0 : 0 0 0 0 0 : 1 : 1 1 0 : 0 0 0 0 0 : 1 : 1 1 0 : 0 0 0 0 0 : 1 : 1 1 0 : 0 0 0 0 1 : 1 : 1 1 0 : 0 0 0 1 0 : 1 : 0 1 0 1 0 0 0 1 1 1 0 0 0 : 0 : 1 1 0 0 0 : R4 0 1 0 0 0 1 1 1 0 0 0 : 1 : 1 1 0 0 0 : R3 0 1 0 0 0 1 1 1 0 0 0 : 1 : 1 1 0 0 0 : R2 0 1 0 0 0 1 1 1 0 0 0 : 1 : 1 1 0 0 0 : R1 0 1 0 0 0 1 1 1 0 0 1 : 1 : 1 1 0 0 0 : R0 0 1 0 0 0 1 1 1 0 1 0 : 1 : 0 1 0 0 0 : G5 0 0 1 0 1 0 1 1 0 0 0 : 0 : 0 0 0 0 0 : G4 0 0 1 0 1 0 1 1 0 0 0 : 0 : 0 0 0 0 0 : DATA SIGNAL G3 0 0 1 0 1 0 1 1 0 0 0 : 0 : 0 0 0 0 0 : G2 0 0 1 0 1 0 1 1 0 0 0 : 0 : 0 0 0 0 0 : G1 0 0 1 0 1 0 1 1 0 0 0 : 0 : 0 0 0 0 1 : G0 0 0 1 0 1 0 1 1 0 0 0 : 0 : 0 0 0 1 0 : B5 0 0 0 1 1 1 0 1 0 0 0 : 0 : 0 0 0 0 0 : B4 0 0 0 1 1 1 0 1 0 0 0 : 0 : 0 0 0 0 0 : B3 0 0 0 1 1 1 0 1 0 0 0 : 0 : 0 0 0 0 0 : B2 0 0 0 1 1 1 0 1 0 0 0 : 0 : 0 0 0 0 0 : B1 0 0 0 1 1 1 0 1 0 0 0 : 0 : 0 0 0 0 0 : B0 0 0 0 1 1 1 0 1 0 0 0 : 0 : 0 0 0 0 0 :
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10 QUALITY AND RELIABILITY
10.2 TEST CONDITIONS Tests should be conducted under the following conditions : Ambient temperature : 25 5C Humidity : 60 25% RH. 10.3 SAMPLING PLAN Sampling method shall be in accordance with MIL-STD-105E , level II, normal single sampling plan .
10.4 ACCEPTABLE QUALITY LEVEL A major defect is defined as one that could cause failure to or materially reduce the usability of the unit for its intended purpose. A minor defect is one that does not materially reduce the usability of the unit for its intended purpose or is an infringement from established standards and has no significant bearing on its effective use or operation. 10.5 APPEARANCE An appearance test should be conducted by human sight at approximately 30 cm distance from the LCD module under flourescent light. The inspection area of LCD panel shall be within the range of following limits.
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10.6 INSPECTION QUALITY CRITERIA No.
1 2 3 4
Item
Non display Irregular operation Short Open
Criterion for defects
No non display is allowed No irregular operation is allowed No short are allowed Any segments or common patterns that don't activate are rejectable. Size D (mm) D 0.15 0.15 < D 0.20 0.20 < D 0.30 0.30 < D
UDefect type
Major Major Major Major
5
Black/White spot (I)
Acceptable number Ignore 3 2 0 Acceptable number 5 3 2 1 Acceptable number Ignore 5 3 0 Acceptable number 5 3 2 1
Minor
6
Black/White line (I)
Length(mm) 10 < L 5.0 < L 1.0 < L 5.0 L 1.0
U0.03 < W 0.04 < W 0.06 < W 0.07 < W
UUUU0.04 0.06 0.07 0.09
Minor
7
Black/White sport (II)
Size D (mm) D 0.30 0.30 < D 0.50 0.50 < D 1.20 1.20 < D
UMinor
8
Black/White line (II)
Length (mm) 20 < L 10 < L 20 5.0 < L 10 L 5.0
UWidth (mm) 0.05 < W 0.07 0.07 < W 0.09 0.09 < W 0.10 0.10 < W 0.15
UMinor
9
Back Light
1. No Lighting is rejectable 2. Flickering and abnormal lighting are rejectable
Major
10
Display pattern
A+B 0.30 0 < C 2
Unit:mm
D+E F+G 0.25 0.25 2 2
Minor
Note: 1. Acceptable up to 3 damages 2. NG if there're to two or more pinholes per dot
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Blemish & Foreign matters
11
Size: A+ B D= 2
Size D (mm) D 0.15 0.15 < D 0.20 0.20 < D 0.30 0.30 < D
UAcceptable number Ignore 3 2 0 Acceptable number Ignore Ignore 1 1 Ignore Note(1)
Minor
Scratch on Polarizer
Width (mm) WU< 3 0.03U0.0
12
U0.05
U0.08
Length (mm) Ignore L 2.0 L > 2.0 L > 1.0 L 1.0 Note (1)
UMinor
Note(1) Regard as a blemish
Bubble in 13 polarizer
Size D (mm) D 0.20 0.20 < D 0.50 0.50 < D 0.80 0.80 < D
UAcceptable number Ignore 3 2 0
Minor
14 LCD panel
surface
Stains on
Stains that cannot be removed even when wiped lightly with a soft cloth or similar cleaning too are rejectable. Rust which is visible in the bezel is rejectable.
Minor Minor
15
Rust in Bezel
Defect of land surface 16 contact (poor soldering) Parts 17 mounting Parts 18 alignment Conductive foreign matter 19 (Solder ball, Solder chips)
Evident crevices which is visible are rejectable.
Minor Major Major Major Minor Minor Major Minor Minor Minor Minor
1. Failure to mount parts 2. Parts not in the specifications are mounted 3. Polarity, for example, is reversed 1. LSI, IC lead width is more than 50% beyond pad outline. 2. Chip component is off center and more than 50% of the leads is off the pad outline. 1. 0.45< ,N1 2. 0.30U0.45
20 correction
Faulty PCB
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The TFT panel may have bright dot or Dark dot. The acceptable number defection:
21
Defect Dot
Bright dot 2
Dark dot Total dot 3 4
Distance between Dark-- dark L5 mm
Minor
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11 Reliability test items :
No. 1 2 3 4 5 6 7 Test items
High temperature storage Low temperature storage High temperature operation Low temperature operation High temperature and high humidity Heat shock Electrostatic discharge
Conditions
Ta=80 Ta=-30 Ta=70 Ta=-20 Ta=40,85% RH 240Hrs 240Hrs 240Hrs 240Hrs 240Hrs
Remark
Non-operation Non-operation Non-operation JIS C7021, A-10 Condition A JIS C7021, A-7 Condition C IEC 68~34 JIS Z0202
8
Vibration
-30~80/200 cycles 1Hrs/cycle 200V,200Pf(0),once for each terminal Frequency range :8~33.3Hz Stoke :1.3mm Sweep :2.9G,33.3~400Hz Cycle :15 minutes 2 hours for each direction of X,Z 4 hours for Y direction 100G, 6ms,X, Y,Z 3 times for each direction Random vibration: 0.015GP2 from 5~200Hz -6dB/octave from 200~500Hz Height:60cm 1 corner,3 edges,6 surfaces
P/Hz
9 10 11
Mechanical shock Vibration (With carton) Drop (with carton)
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12 USE PRECAUTIONS
12.2 Handling precautions 1) The polarizing plate may break easily so be careful when handling it. Do not touch, press or rub it with a hard-material tool like tweezers. 2) Do not touch the polarizing plate surface with bare hands so as not to make it dirty. If the surface or other related part of the polarizing plate is dirty, soak a soft cotton cloth or chamois leather in benzine and wipe off with it. Do not use chemical liquids such as acetone, toluene and isopropyl alcohol. Failure to do so may bring chemical reaction phenomena and deteriorations. 3) Remove any spit or water immediately. If it is left for hours, the suffered part may deform or decolorize. 4) If the LCD element breaks and any LC stuff leaks, do not suck or lick it. Also if LC stuff is stuck on your skin or clothing, wash thoroughly with soap and water immediately. 12.3 Installing precautions 1) The PCB has many ICs that may be damaged easily by static electricity. To prevent breaking by static electricity from the human body and clothing, earth the human body properly using the high resistance and discharge static electricity during the operation. In this case, however, the resistance value should be approx. 1M and the resistance should be placed near the human body rather than the ground surface. When the indoor space is dry, static electricity may occur easily so be careful. We recommend the indoor space should be kept with humidity of 60% or more. When a soldering iron or other similar tool is used for assembly, be sure to earth it. 2) When installing the module and ICs, do not bend or twist them. Failure to do so may crack LC element and cause circuit failure. 3) To protect LC element, especially polarizing plate, use a transparent protective plate (e.g., acrylic plate, glass etc) for the product case. 4) Do not use an adhesive like a both-side adhesive tape to make LCD surface (polarizing plate) and product case stick together. Failure to do so may cause the polarizing plate to peel off. 12.4 Storage precautions 1) Avoid a high temperature and humidity area. Keep the temperature between 0C and 35C and also the humidity under 60%. 2) Choose the dark spaces where the product is not exposed to direct sunlight or
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fluorescent light. 3) Store the products as they are put in the boxes provided from us or in the same conditions as we recommend. 12.5 Operating precautions 1) Do not boost the applied drive voltage abnormally. Failure to do so may break ICs. When applying power voltage, check the electrical features beforehand and be careful. Always turn off the power to the LC module controller before removing or inserting the LC module input connector. If the input connector is removed or inserted while the power is turned on, the LC module internal circuit may break. 2) The display response may be late if the operating temperature is under the normal standard, and the display may be out of order if it is above the normal standard. But this is not a failure; this will be restored if it is within the normal standard. 3) The LCD contrast varies depending on the visual angle, ambient temperature, power voltage etc. Obtain the optimum contrast by adjusting the LC dive voltage. 4) When carrying out the test, do not take the module out of the low-temperature space suddenly. Failure to do so will cause the module condensing, leading to malfunctions. 5) Make certain that each signal noise level is within the standard (L level: 0.2Vdd or less and H level: 0.8Vdd or more) even if the module has functioned properly. If it is beyond the standard, the module may often malfunction. In addition, always connect the module when making noise level measurements. 6) The CMOS ICs are incorporated in the module and the pull-up and pull-down function is not adopted for the input so avoid putting the input signal open while the power is ON. 7) The characteristic of the semiconductor element changes when it is exposed to light emissions, therefore ICs on the LCD may malfunction if they receive light emissions. To prevent these malfunctions, design and assemble ICs so that they are shielded from light emissions. 8) Crosstalk occurs because of characteristics of the LCD. In general, crosstalk occurs when the regularized display is maintained. Also, crosstalk is affected by the LC drive voltage. Design the contents of the display, considering crosstalk.
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12.6 Other 1) Do not disassemble or take the LC module into pieces. The LC modules once disassembled or taken into pieces are not the guarantee articles. 2) The residual image may exist if the same display pattern is shown for hours. This residual image, however, disappears when another display pattern is shown or the drive is interrupted and left for a while. But this is not a problem on reliability. 3) AMIPRE will provide one year warrantee for all products and three months warrantee for all repairing products.
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13 OUTLINE DIMENSION 13.2 OUTLINE DIMENSION
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