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WIY2263
Current Mode PWM Controller
GERNERAL DESCRIPTION
WIY2263 is a highly integrated current mode PWM control IC optimized for high performance, low standby power and cost effective offline flyback converter applications in sub 30W range. PWM switching frequency at normal operation is externally programmable and trimmed to tight range. At no load or light load condition, the IC operates in extended `burst mode' to minimize switching loss. Lower standby power and higher conversion efficiency is thus achieved. VDD low startup current and low operating current contribute to a reliable power on startup design with WIY2263. A large value resistor could thus be used in the startup circuit to minimize the standby power. The internal slope compensation improves system large signal stability and reduces the possible sub-harmonic oscillation at high PWM duty cycle output. Leading-edge blanking on current sense(CS) input removes the signal glitch due to snubber circuit diode reverse recovery and thus greatly reduces the external component count and system cost in the design. WIY2263 offers complete protection coverage with automatic self-recovery feature including Cycle-by-Cycle current limiting (OCP), over load protection (OLP), VDD over voltage clamp and under voltage lockout (UVLO). The Gate-drive output is clamped to maximum 18V to protect the power MOSFET. Excellent EMI performance is achieved with Winsemi proprietary frequency shuffling technique together with soft switching control at the totem pole gate drive output.
FEATURES
Burst Mode function Low startup current (4uA) Low operating current (1.4mA) Built-edge blanking Built-in synchronized slope compensation Current mode External Programmable PWM Switching Frequency By-cycle current limit protection (OCP) VDD over-voltage clamping protection Low voltage shut down function (UVLO) Gate Drive Output Voltage Clamp (18V) Frequency jitter feature Constant output power limit Overload protection (OLP) Work does not produce audio noise
APPLICATIONS
Offline AC/DC flyback converter for Power Adaptor
Open-frame SMPS Battery Charger Set-Top Box Power Supplies
TYPICAL APPLICATION
WIY2263
TL431
Rev. A Mar.2010
Copyright@WinSemi Semiconductor Co.,Ltd.,All rights reserved.
P02-1
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WIY2263
GENERAL INFORMATION
Pin Configuration Marking Information
Y: Year code(0:2010,1:2011......) ww: Week code(1-52)
TERMINAL ASSIGNMENTS
Pin Name
GND FB RI SENSE VDD GATE
Pin No.
1 2 3 4 5 6
I/O
P I I I P O Ground
Description
Feedback input pin. The PWM duty cycle is determined by voltage level into this pin and SENSE pin input Internal Oscillator frequency setting pin. A resistor connected between RI and GND sets the PWM frequency. Current sense input pin. Connected to MOSFET current sensing resistor node. Chip DC power supply pin Totem-pole gate drive output for the power MOSFET.
BLOCK DIAGRAM
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RECOMMENDED OPERATING CONDITION
Symbol
VDD RI T VDD Supply Voltage RI Resistor Value Operating Ambient Temperature
Parameter
Min
10 100 -20
Max
30
Unit
V K
85
ABSOLUTE MAXIMUM RATINGS
Pin Name
VDD VFB VSENSE VRI TJ TS Vcv ICC VDD Pin input voltage VFB Pin input voltage VSENSE Pin input voltage VRI Pin input voltage Operating Junction Temperature Storage Temperature VDD DC Clamping Voltage VDD DC Clamping Current
Parameter
Ratings
30
Units
V V V V V mA
-0.3~7 -0.3~7 -0.3~7 -20~150 -55~160
34 10
Note: more than the limit specified in the table parameters will result in permanent damage to the device. The device is not recommended in these extreme conditions of work, working conditions in the limit above which may affect device reliability.
Electrical Characteristics (Tc = 25C)
Characteristics Supply Voltage (VDD)
Operation voltage Turn on threshold Voltage Turn-off threshold Voltage Start up current Operation Current VDD Zener Clamp Voltage VDD_OP UVLO_ON UVLO_OFF I_VDD_ST I_VDD_OP VDD_Clamp VDD=13V,RI=100K VDD=16V,RI=100K,VFB=3V, GATE with 1nF to GND IVDD=10mA 33 V 7.8 13 8.8 14 4 1.4 30 9.8 15 20 2.4 V V V A mA
Symbol
Test Condition
Min
Typ
Max
Unit
Feedback Input Section(FB Pin)
PWM Input Gain VFB Open Loop Voltage FB pin short circuit current Zero Duty Cycle FB Threshold Voltage Power Limiting FB Threshold Voltage Power limiting Debounce Time Input Impedance Maximum Duty Cycle AVCS VFB_Open IFB_Short VTH_0D VTH_PL TD_PL ZFB_IN DC_MAX FB Shorted to GND VDD = 16V,RI=100Kohm 3.7 35 6 75 VFB /Vcs 2.0 4.8 1.2 0.75 V/V V mA V V ms K %
Current Sense Input(Sense Pin)
Leading edge Blanking Time TLEB 330 8ns
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Input impedance Over Current Detection and Control Delay Over Current Threshold Voltage at zero Duty Cycle VTH_OC FB3V 0.70 0.75 0.80 V Zsense TD_OC GATE with 1nF to GND 40 80 k ns
Oscillator Section
Oscillation Frequency Fosc @RI=100K,CS=0,FB=3V Oscillation Burst mode frequency Frequency variation versus temp. Deviation Frequency variation versus VDD Operating RI Range open Load Voltage Fosc_BM @RI=100K,CS=0,FB=1.1V f_temp f_VDD RI_range V_RI_Open TEMP = -20 to 85 VDD = 12 to 25V 50 5 5 100 2 150 % % K V 22 KHz 60 65 70 KHz
Gate Output Section
Output voltage Low level Output voltage high level Output clamp voltage Rising time VOL VOH VClamp VDD = 16V, tr GATE with 1nF to GND VDD = 16V, Falling time tf GATE with 1nF to GND 70 s 200 s VDD = 16V, Io = -20mA VDD = 16V, Io = 20mA 10 18 0.8 V V V
Frequency Shuffling
Frequency Modulation range f_OSC /Base frequency Shuffling Frequency f_shuffling RI=100K 64 Hz RI=100K -3 3 %
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OPERATION DESCRIPTION
The WIY2263 is a highly integrated PWM controller IC optimized for offline flyback converter applications in sub 30W power range. The extended burst mode control greatly reduces the standby power consumption and helps the design easily meet the international power conservation requirements. Gate drive output switches only when VDD voltage drops below a preset level and FB input is active to output an on state. Otherwise the gate drive remains at off state to standby power consumption to the greatest extend. The frequency control also eliminates the audio noise at any loading conditions.
Startup Current and Start up Control
Startup current of WIY2263 is designed to be very low so that VDD could be charged up above UVLO threshold level and device starts up quickly. A large value startup resistor can therefore be used to minimize the power loss yet provides reliable startup in application. For AC/DC adaptor with A resistor connected between RI and GND sets the constant current source to charge/discharge the internal cap and thus the PWM oscillator frequency is determined. The relationship between RI and switching frequency follows the below equation within the specified RI in Kohm range at nominal loading operational condition.
Oscillator Operation
universal input range design, a 2 M, 1/8 W startup resistor could be used together with a VDD capacitor to provide a fast startup and low power dissipation solution.
Operating Current
The Operating current of WIY2263 is low at 1.4mA. Good efficiency is achieved with WIY2263 low operating current together with extended burst mode control features.
Fosc =
6500 ( KHz ) RI ( K)
Current Sensing and Leading Edge Blanking
Cycle-by-Cycle current limiting is offered in WIY2263 current mode PWM control. The switch current is detected by a sense resistor into the sense pin. An internal leading edge blanking circuit chops off the sense voltage spike at initial MOSFET on state due to Snubber diode reverse recovery so that the external RC filtering on sense input is no longer required. The current limit comparator is disabled and thus cannot turn off the external MOSFET during the blanking period. PWM duty cycle is determined by the current sense input voltage and the FB input voltage.
Frequency shuffling for EMI improvement
The frequency Shuffling/jittering (switching frequency modulation) is implemented in WIY2263. The oscillation frequency is modulated with a random source so that the tone energy is spread out. The spread spectrum minimizes the conduction band EMI and therefore reduces system design challenge.
Extended Burst Mode Operation
At zero load or light load condition, majority of the power dissipation in a switching mode power supply is from switching loss on the MOSFET transistor, the core loss of the transformer and the loss on the snubber circuit. The magnitude of power loss is in proportion to the number of switching events within a fixed period of time. Reducing switching events leads to the reduction on the power loss and thus conserves the energy. WIY2263 self adjusts the switching mode according to the loading condition. At from no load to light/medium load condition, the FB input drops below burst mode threshold level. Device enters Burst Mode control. The
Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM generation. This greatly improves the close loop stability at CCM and prevents the sub-harmonic oscillation and thus reduces the output ripple voltage.
Gate Drive
WIY2263 Gate is connected to an external MOSFET gate
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for power switch control. Too weak the gate drive strength results in higher conduction and switch loss of MOSFET while too strong gate drive output compromises the EMI. A good tradeoff is achieved through the built-in totem pole gate design with right output strength and dead time control. The low idle loss and good EMI system design is easier to achieve with this dedicated control scheme. An internal 18V clamp is added for MOSFET gate protection at higher than expected VDD input. UnderVoltage Lockout on VDD (UVLO) With Winsemi Proprietary technology, the OCP threshold tracks PWM Duty cycles and is line voltage compensated to achieve constant output power limit over the universal input voltage range with recommended reference design. At overload condition when FB input voltage exceeds power limit threshold value for more than TD_PL, control circuit reacts to shut down the output power MOSFET. Device restarts when VDD voltage drops below UVLO limit.
Protection Controls
Good power supply system reliability is achieved with its rich protection features including Cycle-by-Cycle current limiting (OCP), Over Load Protection (OLP) and over voltage clamp,
VDD is supplied by transformer auxiliary winding output. It is clamped when VDD is higher than threshold value. The power MOSFET is shut down when VDD drops below UVLO limit and device enters power on start-up sequence thereafter.
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SOT23-6 Package Dimension
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