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| SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING GENERAL DESCRIPTION The main function of the SX8722 is to acquire signal from Wheatstone bridges or single ended sensors. The input can be a pressure sensor, a GMR or AMR magnetic sensor, a chemical sensor, a thermistor or a mix of several of these sensors. The SX8722 Sensor interface is totally configurable through an I2C compatible interface. Several parameters are configurable through this interface such as alarms or signal post processing. DATASHEET KEY PRODUCT FEATURES 16 + 10 bits differential acquisition Preamplifier programmable gain up to 1000 Sensor offset compensation up to 15 times full scale of input signal 4 differential or 7 single ended signal inputs 2 differential reference inputs I2C compatible connection to application Internal RC and 32 kHz Oscillators Low power modes - Sleep - Shutdown 4 Full configuration pre selections including: - ZoomingADCTM configuration - 2 alarms with on & off thresholds - Digital filtering I2C EEPROM interface Stand alone mode for alarm monitoring Clock out pin APPLICATION Pressure sensing (industrial, altimeter, diving computer) Chemical sensing (monitoring, security) Magnetic sensing (compass) ORDERING INFORMATION Part Number SX8722I070LF Tools Evaluation Kit Temperature Range -40C to 125C Part number XE8000EV120 Package MLPQ44-7x7 Calibration pin Reset pin Ready / Busy pin EE_POW SX8722 BIAS EE_SDA EE_SCL VBATT GND ALRM1 ALRM2 VBATT REF MUX AR1P AR1N AR2P AR2N ZoomingADC TM CONTROL CAL RESET READY MCU AC7 AC6 I2 C SIGNAL MUX SCL SDA GPIO GPIO GPIO Differential Single ended AC5 AC4 AC3 AC2 AC1 AC0 PGA ADC OSC XIN XOUT CKOUT SLEEP SHUT Example of application Typical pressure & temperature sensing application with sleep control POST-PROCESS POWER VREG VMULT ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 1 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Table of contents Section 1. DATASHEET Page Specifications........................................................................................................................................................... 6 1.1. 1.2. 1.3. Absolute Maximum Ratings ............................................................................................................................. 6 Operating conditions ........................................................................................................................................ 6 ZoomingADC Specifications ............................................................................................................................ 7 Pin configuration ............................................................................................................................................ 10 Marking information ....................................................................................................................................... 10 2. Pin configuration and marking information ............................................................................................................ 10 2.1. 2.2. 3. 4. Pin Description....................................................................................................................................................... 11 Timing Characteristics ........................................................................................................................................... 13 4.1. 4.2. 4.3. 4.4. 4.5. I2C timing Waveforms.................................................................................................................................... 13 Time specification without the 32.768 kHz Xtal ............................................................................................. 14 Start-up time with the 32.768 kHz Xtal presence........................................................................................... 14 Changing power mode by pin signal.............................................................................................................. 14 Changing power mode by I2C command....................................................................................................... 15 Detailed bloc diagram .................................................................................................................................... 16 Functional description .................................................................................................................................... 16 ZoomingADC ................................................................................................................................................. 19 Description ..................................................................................................................................................... 20 SX8722 configuration..................................................................................................................................... 20 5. Circuit description .................................................................................................................................................. 16 5.1. 5.2. 5.3. 6. Access the SX8722 ............................................................................................................................................... 20 6.1. 6.2. 7. 8. I2C Commands...................................................................................................................................................... 20 Serial communication ............................................................................................................................................ 21 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. Write data direct............................................................................................................................................. 21 Write data masked ......................................................................................................................................... 22 Read data ...................................................................................................................................................... 22 Other commands ........................................................................................................................................... 23 Unknown commands ..................................................................................................................................... 23 Reading data after a measurement. .............................................................................................................. 23 Introduction .................................................................................................................................................... 24 Features covered by predefined settings....................................................................................................... 24 Input multiplexers........................................................................................................................................... 25 Overview ................................................................................................................................................. 25 Input channel selection ........................................................................................................................... 25 Reference channel selection................................................................................................................... 26 Application example................................................................................................................................ 26 Overview ................................................................................................................................................. 28 October 2008 Page 2 www.semtech.com 9. Predefined settings ................................................................................................................................................ 24 9.1. 9.2. 9.3. 9.3.1. 9.3.2. 9.3.3. 9.3.4. 9.4. 9.4.1. Programmable gain amplifier settings............................................................................................................ 28 ACS - Revision 4.2 (c)2008 Semtech Corp. SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Table of contents Section 9.4.2. 9.4.3. 9.4.4. 9.4.5. 9.4.6. 9.4.7. 9.5. 9.5.1. 9.5.2. 9.6. 9.6.1. 9.6.2. 9.7. 9.7.1. 9.7.2. 10. 11. DATASHEET Page Configuration flow ................................................................................................................................... 29 Enable/disable PGAs .............................................................................................................................. 30 PGA3 gain configuration ......................................................................................................................... 30 PGA2 gain configuration ......................................................................................................................... 30 PGA1 gain configuration ......................................................................................................................... 31 Application example................................................................................................................................ 31 Overview ................................................................................................................................................. 32 Application example................................................................................................................................ 34 Overview ................................................................................................................................................. 35 ADC settings ........................................................................................................................................... 36 Overview ................................................................................................................................................. 36 Measurement engine settings................................................................................................................. 37 Offset cancellation ......................................................................................................................................... 32 ADC parameters ............................................................................................................................................ 35 Measurement engine ..................................................................................................................................... 36 Default configuration.............................................................................................................................................. 38 10.1. ZoomingADC default settings ........................................................................................................................ 38 Advanced configuration ......................................................................................................................................... 39 11.1. Overview ........................................................................................................................................................ 39 11.2. Measurement engine ..................................................................................................................................... 40 11.2.1. Overview ................................................................................................................................................. 40 11.2.2. Functional flowchart ................................................................................................................................ 40 11.3. Control registers............................................................................................................................................. 41 11.3.1. SXCtrl1 - SX8722 Control register 1 ....................................................................................................... 41 11.3.2. SXCtrl2 - SX8722 Control register 2 ....................................................................................................... 41 11.3.3. SXCfgEn - Configuration enabling register ............................................................................................. 42 11.3.4. SXUpdated - Updated configuration register .......................................................................................... 42 11.3.5. Configuration register - measurement mode .......................................................................................... 42 11.4. Filtering .......................................................................................................................................................... 43 11.4.1. Filter types .............................................................................................................................................. 43 11.4.2. Configuration register - filtering............................................................................................................... 43 11.4.3. Filter size register.................................................................................................................................... 44 11.5. Alarms............................................................................................................................................................ 44 11.5.1. Configuration register - alarms................................................................................................................ 44 11.5.2. Alarm threshold registers ....................................................................................................................... 44 11.5.3. SXCtrl2 - SX8722 Control register 2 ....................................................................................................... 45 11.6. I2C EEPROM................................................................................................................................................. 46 11.6.1. Overview ................................................................................................................................................. 46 11.6.2. Schematic ............................................................................................................................................... 46 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 3 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Table of contents Section DATASHEET Page 11.7. Using the SX8722 Stand alone...................................................................................................................... 47 11.7.1. Schematic ............................................................................................................................................... 47 11.8. Frequency calibration process ....................................................................................................................... 48 11.8.1. Overview ................................................................................................................................................. 48 11.8.2. Using an 32.768 kHz XTAL..................................................................................................................... 48 11.8.3. Using a 32.768 kHz External clock source ............................................................................................. 49 11.9. Working below 3 V ......................................................................................................................................... 50 11.9.1. Operating range ...................................................................................................................................... 50 11.9.2. Internal voltage multiplier ........................................................................................................................ 50 11.9.3. Schematic ............................................................................................................................................... 50 12. ZoomingADC ......................................................................................................................................................... 51 12.1. ZoomingADC Features .................................................................................................................................. 51 12.1.1. Overview ................................................................................................................................................. 51 12.2. Acquisition Chain ........................................................................................................................................... 51 12.3. ZoomingADC Detailed block diagram............................................................................................................ 53 12.4. ZoomingADC register map ............................................................................................................................ 54 12.5. ZoomingADCTM registers table ...................................................................................................................... 56 12.6. Input Multiplexers........................................................................................................................................... 57 12.7. Programmable Gain Amplifiers ...................................................................................................................... 58 12.7.1. PGA & ADC Enabling ............................................................................................................................. 58 12.7.2. PGA1 ...................................................................................................................................................... 58 12.7.3. PGA2 ...................................................................................................................................................... 59 12.7.4. PGA3 ...................................................................................................................................................... 60 12.8. ADC Characteristics....................................................................................................................................... 62 12.8.1. Conversion Sequence............................................................................................................................. 62 12.8.2. Sampling Frequency ............................................................................................................................... 63 12.8.3. Over-Sampling Ratio............................................................................................................................... 63 12.8.4. Elementary Conversions......................................................................................................................... 64 12.8.5. Resolution ............................................................................................................................................... 64 12.8.6. Conversion Time & Throughput .............................................................................................................. 65 12.8.7. Output Code Format ............................................................................................................................... 67 12.9. Power Saving Modes ..................................................................................................................................... 69 12.10. Input impedance............................................................................................................................................ 69 12.11. Switched Capacitor Principle......................................................................................................................... 70 12.12. PGA Settling or Input Channel Modifications ................................................................................................ 71 12.13. PGA Gain & Offset, Linearity and Noise ....................................................................................................... 71 12.14. Power Reduction ........................................................................................................................................... 71 12.15. Noise ............................................................................................................................................................. 72 12.16. Gain Error and Offset Error ........................................................................................................................... 73 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 4 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Table of contents Section 13. DATASHEET Page Typical performances ............................................................................................................................................ 75 13.1. Current consumption...................................................................................................................................... 75 13.2. ZoomingADC ................................................................................................................................................. 76 13.2.1. Integral non-linearity ............................................................................................................................... 76 13.2.2. Differential non-linearity ......................................................................................................................... 77 13.2.3. Resolution vs acquisition time................................................................................................................. 78 14. Register Memory Map and Description ................................................................................................................. 79 14.1. Memory Map .................................................................................................................................................. 79 14.2. Register description ....................................................................................................................................... 82 14.2.1. SX8722 general configuration................................................................................................................. 82 14.2.2. Configuration 1 registers......................................................................................................................... 84 14.2.3. Configuration 2 registers......................................................................................................................... 88 14.2.4. Configuration 3 registers......................................................................................................................... 92 14.2.5. Configuration 4 registers......................................................................................................................... 96 15. Power modes....................................................................................................................................................... 100 15.1. Power modes transitions.............................................................................................................................. 100 15.2. Active mode ................................................................................................................................................. 101 15.2.1. Description ............................................................................................................................................ 101 15.2.2. How to set SX8722 in active mode ....................................................................................................... 101 15.3. Sleep mode.................................................................................................................................................. 101 15.3.1. Description ............................................................................................................................................ 101 15.3.2. Operating specifications of the sleep mode .......................................................................................... 101 15.3.3. SX8722 sleep current consumption below 3V Vbat.............................................................................. 102 15.3.4. SX8722 sleep current consumption with the 32.768 kHz Xtal .............................................................. 102 15.3.5. SX8722 sleep current consumption without the 32.768 KHz Xtal......................................................... 102 15.3.6. How to set SX8722 in sleep mode........................................................................................................ 102 15.3.7. Wake up from sleep mode to active mode............................................................................................ 102 15.4. Shutdown mode ........................................................................................................................................... 103 15.4.1. Description ............................................................................................................................................ 103 15.4.2. Operating specifications in shutdown mode ......................................................................................... 103 15.4.3. How to set SX8722 in shutdown mode ................................................................................................. 103 15.4.4. Wake-up from shutdown mode to active mode..................................................................................... 104 15.4.5. Change from shutdown mode to sleep mode ....................................................................................... 104 16. 17. 18. 19. 20. PCB Layout Considerations................................................................................................................................. 105 How to Evaluate................................................................................................................................................... 105 Package Outline Drawing: MLPQ44-7x7mm ....................................................................................................... 105 Land Pattern Drawing: MLPQ44-7x7mm............................................................................................................. 106 Tape and Reel Specification................................................................................................................................ 107 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 5 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 1. Specifications 1.1. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Power supply Storage temperature Max sensor common mode Symbol VBAT TSTORE VVR P VVR N Condition Min VSS - 0.3 -55 VSS - 300 Max 6 150 VBATT + 300 VBATT + 300 260 Units V C mV Input voltage Peak soldering temperature T VSS - 300 mV C Note: This device is ESD sensitive. Use of standard ESD handling precautions is required. 1.2. Operating conditions All values are valid whithin the operating conditions unless otherwise specified. Parameter OPERATING CONDITIONS Power supply Operating temperature CURENT CONSUMPTION Active current Sleep current (1) Sleep current (2) Shutdown current DIGITAL I/O Input logic high Input logic low Output logic high Output logic low VIH VIL VOH VOL IOH < 4 mA IOL < 4 mA 0.4 0.7 x VBAT 0.3 x VBAT VBAT 0.4 V V V V IOP ISLEEP ISLEEP ISHUT Temperature < 85C Temperature < 85C Temperature < 85C 300 1 3 0.5 5.0 10.0 3.5 A A A A VBAT TOP 2.4 -40 5.5 125 V C Symbol Condition Min Typ Max Unit ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 6 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING (1) With external 32.768kHz Xtal connected (2) Without external 32.768kHz Xtal connected DATASHEET 1.3. ZoomingADC Specifications Unless otherwise specified: Temperature TA = +25C, VBATT = +5V, GND = 0V, VREF = +5V, VIN = 0V, RC frequency fRC = 2MHz, sampling frequency fS = 300 kHz, Overall PGA gain GDTOT = 1, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '11'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2. PARAMETER COMMENTS/CONDITIONS MIN ANALOG INPUT CHARACTERISTICS Differential Input Voltage Range VIN = VINP -VINN Gain = 1, OSR = 32 (Note 1) Gain = 100, OSR = 32 Gain = 1000, OSR = 32 Reference Voltage Range VREF,ADC = VREFP -VREFN PROGRAMMABLE GAIN AMPLIFIER Total PGA Gain PGA1 Gain PGA2 Gain PGA3 Gain Gain Settings Precision (each stage) Gain Temperature Dependance Offset PGA2 Offset PGA3 Offset Offset Settings Precision (PGA2 or PGA3) Offset Temperature Dependance Input Impedance PGA1 PGA1 Gain = 1 (Note 3) PGA1 Gain = 10 (Note 3) Input Impedance PGA2 ,PGA3 Output RMS Noise Maximal gain = 1 (Note 3) PGA1 (Note 4) PGA2 (Note 5) PGA3 (Note 6) 1500 150 150 205 340 365 GDoff2 GDoff3 Step = 0.2 V/V, See Table 46 Step = 1.12 V/V, See Table 48 (note 2) -1 -63/12 -3 +/- 0.5 +/-5 GDTOT GD1 GD2 GD3 See Table 15 See Table 16 Step = 1/12 V/V, See Table 47 -3 +/- 0.5 +/- 5 +1 +63/12 +3 0.5 1 1 1000 10 10 127/12 +3 V/V V/V V/V V/V % ppm / C V/V V/V % ppm / C k k k V V V -2.42 -24.2 -2.42 +2.42 +24.2 +2.42 VBATT V mV mV V VALUE TYP MAX UNITS ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 7 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING PARAMETER COMMENTS/CONDITIONS MIN ADC STATIC PERFORMANCES Resolution No Missing Codes Gain Error Offset Error Integral Non-Linearity Differential Non-Linearity Power Supply Rejection Ratio INL DNL PSRR n (Note 7) (Note 8) (Note 9) n = 16 bits (Note 10) resolution n = 16 bits (Note 11) resolution n = 16 bits (Note 12) VBATT = 5V +/- 0.3V (Note 13) VBATT = 3V +/- 0.3V (Note 13) ADC DYNAMIC PERFORMANCES Throughput Rate (Continuous Mode) TCONV n = 12 bits (Note 14) n = 16 bits (Note 14) Throughput Rate (Continuous Mode) 1/TCONV n = 12 bits, fS n = 16 bits, fS Nbr of Initialization Cycles Nbr of End Conversion Cycles PGA Stabilization Delay TIME BASE Max ADC oversampling frequency Min ADC oversampling frequency DIGITAL OUTPUT ADC Output Data Coding TEMPERATURE Specified Range Operating Range -40 -40 See Table 55 and Table 56 NINIT NEND (Note 15) 0 0 OSR 3 0 133 1027 3.76 0.49 +/- 0.15 +/- 1 +/- 1.0 +/- 0.5 78 72 6 VALUE TYP DATASHEET UNITS MAX 16 Bits % of FS LSB LSB LSB dB dB cycles / fS cycles / fS kS/s kS/s 2 5 cycles cycles cycles fSmax fSmin @ 25C, with a 32k XTAL @ 25C, with a 32KXTAL 270 33 300 37.5 330 42 kHz kHz Binary Two's Complement +85 +125 C C Table 1. ZoomingADC specifications ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 8 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Notes (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) Gain defined as overall PGA gain GDTOT = GD1 x GD2 x GD3. Maximum input voltage is given by: VIN,MAX = (VREF/2) (OSR/OSR+1). Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1. DATASHEET Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS = 512 kHz. This figure must be multiplied by 2 for fS = 256 kHz, 4 for fS = 128 kHz. Input impedance is proportional to 1/fS. Figure independent from PGA1 gain and sampling frequency fS. See equation Eq. 21 to calculate equivalent input noise. Figure independent on PGA2 gain and sampling frequency fS. See equation Eq. 21 to calculate equivalent input noise. Figure independent on PGA3 gain and sampling frequency fS. See equation Eq. 21 to calculate equivalent input noise. Resolution is given by n = 2 log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8. If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data. Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function (with the offset error removed). Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For 1 LSB offset, NELCONV must be 2. INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over the full scale. DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes. Values for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage changes. Conversion time is given by: TCONV = (NELCONV (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8. PGAs are reset after each writing operation to registers CxRegAdc1-5. The ADC must be started after a PGA or inputs commonmode stabilisation delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching. Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without the PGAs. Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = '11' and IB_AMP_ADC[1:0] = '11'. Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '10', IB_AMP_ADC[1:0] = '10'. Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = '01', IB_AMP_ADC[1:0] = '01'. Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = '00', IB_AMP_ADC[1:0] = '00'. (16) (17) (18) (19) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 9 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 2. Pin configuration and marking information 2.1. Pin configuration VMULT RESET XOUT VREG 35 44 43 42 41 40 39 38 37 36 NC SLEEP SHUT READY NC NC NC BIAS EE_POW EE_SDA EE_SCL VBAT 34 33 32 31 30 DNC DNC CAL XIN NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VSS AR1N AR1P AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 SX8722 (Top view) 29 28 27 26 25 24 23 NTEST ALRM1 ALRM2 2.2. Marking information nnnnnn = Part Number (Example: SX8722) yyww = Date Code (Example: 0752) xxxxxxxxx = Semtech Lot No. (Example A01E90101) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 CKOUT Page 10 AR2N AR2P SCL SDA NC NC NC www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 3. Pin Description Pin 1 2 3 4 5 6 7 8 9 10 NC SLEEP SHUT READY NC NC NC BIAS EE_POW EE_SDA Digital output Digital output Digital IO Digital input Digital input Digital output Symbol Type Not connected Setting this pin to 0 puts the SX8722 in sleep mode, power consumption ~1.5uA, otherwise the pin can be floating Internal pull-up Function Status at POR Setting this pin to 0 puts the SX8722 in shutdown mode, Internal pull-up power consumption ~0.5uA, otherwise the pin can be floating Is high when a measurement data is available Not connected Not connected Not connected Bias pin, is set to VBAT voltage when a measurement is performed Must be used to power the optional I2C EEPROM Must be connected to SDA pin of the optional EEPROM when used. Otherwise must remain floating (see chapter EEPROM connection) Must be connected to SCL pin of the optional EEPROM when used. Otherwise must remain floating (see chapter EEPROM connection) Alarm1 pin, is high when "on" threshold is reached and low when "off" threshold is reached, when not used can reamin floating Alarm2 pin, is high when "on" threshold is reached and low when "off" threshold is reached, when not used can reamin floating System clock output Not connected Low Low Low Low 11 EE_SCL Digital IO Low 12 ALRM1 Digital output Low 13 ALRM2 Digital output Low 14 15 16 17 18 19 20 21 22 23 CKOUT NC SCL SDA NC NC NTEST AR2P AR2N AC7 Digital output Low Digital IO Digital IO Serial clock line of the I2C compatible interface Serial data line of the I2C compatible interface Not connected Not connected Input Input Digital input Analog input Analog input Analog input Must be connected to VBAT Second analog input reference (positive input) Second analog input reference (negative input) ZoomingADCTM input 7 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 11 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol AC6 AC5 AC4 AC3 AC2 AC1 AC0 AR1P AR1N VSS VBAT VREG RESET VMULT Type Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Power Power Analog input Digital input Analog input ZoomingADCTM input 6 ZoomingADCTM input 5 ZoomingADCTM input 4 ZoomingADCTM input 3 ZoomingADCTM input 2 ZoomingADCTM input 1 ZoomingADCTM input 0 First Analog reference input (positive input) First Analog reference input (negative input) Negative power supply Positive power supply Connected to the internal voltage regulator. Must be connected through 1uF capacitor to the ground. Reset pin, active high, must be tied to ground through a 3k3 resistor. External capacitor for the internal voltage multiplier. Vmult capacitor must be connected through 2nF to the ground when VBAT < 3V XTAL connection, left unconnected when not used XTAL connection, left unconnected when not used Do not connect Do not connect Digital input Calibration pin, set low to use XTAL. Not connected Not connected Function DATASHEET Status at POR 38 39 40 41 42 43 44 XIN XOUT DNC DNC CAL NC NC Digital input Digital output Internal pull-up ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 12 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 4. Timing Characteristics Parameter I2C TIMING SPECIFICATIONS (1) SCL clock frequency SCL low period SCL high period Data setup time Data hold time Repeated start setup time Start condition hold time Stop condition hold time Bus free time between stop and start fSCL tLOW tHIGH tSU;DAT tHHD;DAT tSU;STA tHD;STA tSU;STO tBUF 0 4.7 4.0 250 4.0 4.7 4.0 4.0 4.7 100 kHz s s ns ns s s s s Symbol Condition Min Typ Max Unit (1) All timings specifications are referred to VILMIN and VIHMAX voltage levels defined for the SCL and SDA pins. With 32'768 Hz Xtal presence. 4.1. I2C timing Waveforms SDA SCL tSU ;STA t HD ;STA tSU;STO tBUF Figure 1. I2C Start and Stop timing SDA SCL tLOW tHIGH tSU;DAT tHD;DAT tSP Figure 2. I2C Data timings ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 13 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 4.2. Time specification without the 32.768 kHz Xtal DATASHEET The internal SX8722 RC oscillator accuracy depends on technology tolerance. It can reach 50% difference from one chip to another In this case, and if no calibration is done, the RC clock is centred around 1.2 MHz. SX8722 timing values without Xtal can thus differ of 50% to these with a Xtal. 4.3. Start-up time with the 32.768 kHz Xtal presence The mean time of EEPROM loading at the start-up is typically 140 ms if configuration data are saved in. In this case SX8722 will provide the first sample after typically 180ms. time before EEPROM loading: 7.5 [ms] time after EEPROM loading: 140 [ms] time to have the first sample: 180 [ms] SX8722 power- on t EEPROM loading t Sample available t Figure 3. Start-up timing diagram with EEPROM loading 4.4. Changing power mode by pin signal From To SHUT SLEEP ACTIVE inst. (1) inst. (1) SHUT SLEEP 640ms ACTIVE 650ms 660ms Table 2. Power mode changing timings by pin setting (1) instantaneous ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 14 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 4.5. Changing power mode by I2C command From To SHUT SLEEP ACTIVE inst. (1) SHUT SLEEP 770us ACTIVE 700us 470us DATASHEET Table 3. Power mode changing timings by I2C command (1) instantaneous Note: When time to change a power mode is instantaneous, it doesn't mean that the chip is totally ready to work. There are for example initialization times, EEPROM loading or code execution. The transition time is considered as not low power. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 15 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 5. Circuit description 5.1. Detailed bloc diagram VBAT Supply I2C * EEPROM MCU * EE_POW EE_SDA EE_SCL VBAT SX8722 BIAS AR1P AR1N AC0 AC1 ALRM1 ALRM2 GPIO GPIO GPIO GPIO / CKOUT GPIO Control READY CAL Post Process RESET I2C AC6 AC7 10 + 16 bits ZoomingADCTM I2C I2C CKOUT CKIN/GPIO GPIO GPIO GROUND Parameters RAM RC Oscillator DFLL XTAL Oscillator Power mgmt Regulator Voltage Multiplier VMULT VREG SLEEP SHUT XOUT VSS XIN * Ground * * Optional components Figure 4. SX8722 detailed bloc diagram 5.2. Functional description The SX8722 is a ZoomingADCTM with I2C compatible interface allowing multiple setups. The major modules of the SX8722 are the ZoomingADCTM, the signal post processing, the control unit and the power management The SX8722 offers several configuration possibilities allowing the developer to use it as a peripheral of its system or to use it as a stand alone system generating alarms. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 16 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET The ZoomingADCTM is made of 1 input multiplexer, 3 programmable gain amplifiers and a 16 bits Sigma-Delta ADC. The input multiplexer allows measuring 4 differential sensors or 7 single ended sensors or a combination of differential and single-ended. The total gain of the PGA enables an amplification of 1000 and the offset correction can reach up to 15 times the full scale input signal. The SX8722 is not only giving access to the very efficient ZoomingADCTM technology, it also gives access to a very low power acquisition system entirely configurable to reach as low as 0.5uA in shutdown mode. The low power modes can be reached through pins or specific serial commands. The whole chip is controlled by a set of registers; these registers have factory default settings and can be modified in 2 ways: the serial interface commands or an optional external EEPROM. At Startup the SX8722 checks for EEPROM presence and updates its registers with EEPROM contents. The whole chip is working at 1.2MHz using its internal RC oscillator, this frequency can be calibrated. The clock calibration can be done using several methods: External 32.768 kHz XTAL, External 32.768 kHz reference signal, or EEPROM parameter configuration. Several corrections can be applied on the measured signal such as different digital filters. The SX8722 offers two alarm pins. "on" and "off" thresholds can be set independently. A Clock out pin can be enabled to have the exact frequency of RC oscillator. External EEPROM and sensors can be biased by the dedicated SX8722 pins EE_POW and BIAS allowing the most efficient power management. The pin READY is a single signal that can be used to interrupt the host microcontroller. The RESET pin enables the host system to reset the SX8722 to its startup settings at any time. The internal voltage multipliers is automatically enabled when working below 3 Volts. The SX8722 implements 4 configuration register sets. Each of these sets completely defines the behavior of the ZoomingADCTM. This allows the user to preset 4 different measurement configurations that can be activated by setting a single bit. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 17 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING The diagram below page explains the registers system more in details. DATASHEET Alarms ZoomingADC Registers Measurement Engine 10 + 16 bits TM Alarm pins Control & Configuration Registers sets Service pins Communication Engine External EEPROM I2C Filtering SX8722 Figure 5. Register sets system The measurement engine copies the configuration register sets in the ZoomingADCTM physical registers and writes back the conversion results. The communication engine controls read/write access from the I2C or the external EEPROM. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 18 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 5.3. ZoomingADC DATASHEET The SX8722 core is the ZoomingADCTM, the diagram below shows more in detail the architecture of this acquisition chain. A 0 AC AR 0 1 2 3 4 5 6 7 B fS MUX VIN + PGA1 1 - 10 1 - 2 - 5 - 10 0/12 to 127/12 D fS + PGA2 E + + - + PGA3 + + VIN, ADC + - - - - ADC MEASUREMENT ENGINE C 5/5 ... -5/5 63/12 ... -63/12 1 2 3 MUX VREF + OFF2 + OFF3 - - Figure 6. Acquisition chain architecture The block schematic above is separated in function boxes: A. Input multiplexers Routing of the input signal. Routing of the reference. B. Programmable gain amplifiers Can be enabled/disabled separately. Each PGA has programmable gain from 1 to 10. Total PGA gain available = PGA1 x PGA2 x PGA3 = 1000. C. Offset cancellation Subtract or add a reference multiple to the input signal. Can compensate up to 15 times the full scale signal. D. ADC Sigma-Delta ADC. Offers several sampling frequencies. Over sampling rates and elementary conversion combinations allow setting the ideal resolution for the ideal conversion time. E. Measurement engine Manages up to 4 ZoomingADCTM configurations. Updates the measured values. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 19 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 6. Access the SX8722 6.1. Description The SX8722 is configured trough register sets and general control registers. All the accesses to the SX8722 registers are done through the I2C interface using read and write commands. The next paragraph describes two approaches to configure the SX8722 6.2. SX8722 configuration As it will be shown in the next chapter there are two ways to write data in the SX8722 registers: Direct write: This command writes 8 bits to a defined address. This implies knowledge of the value to be written to this address. Masked write: This command can write a single bit in a byte using a mask. 7. I2C Commands This chapter describes the commands that are coded in the SX8722. The SX8722 commands are summarized below, detailed timing diagrams can be found "Serial Communication" chapter. Type Data access Command write_direct write_masked read Description Writes 8bit data to a given address Writes bits to given address using a given mask Reads 8bit data from a given address Sets the SX8722 to sleep mode Sets the SX8722 to sleep mode Resets the SX8722 Saves the SX8722 registers in the external EEPROM (if present) Loads the SX8722 registers in the external EEPROM (if present) Byte 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 Power modes sleep shutdown reset EEPROM save_eeprom load_eeprom Table 4. SX8722 commands ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 20 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 8. Serial communication The serial interface is a read-write 2 wire slave device. The SCL wire carries the clock information and SDA carries the data. The output drivers on the bus are open drain current sinks. The SCL wire is controlled by the master on the bus. Since the SX8722 is fairly slow, it may stretch the low clock phase when required. The SDA wire is controlled by the master or the slave depending on the operation. SDA only changes while the clock signal is low except for the (repeated) start or stop conditions. The (repeated) start condition for the transmission is a high to low transition on SDA while SCL is high. The stop condition is a low to high transition while SCL is high. To read data from the SX8722, the master has to send successively a start bit, the slave address, a write bit. If the slave address corresponds to the address of the SX8722 and the preceding operation is completed, the SX8722 sends an acknowledge bit. The master then sends the read command which is acknowledged by the salve, the memory address that it would like to read which is also acknowledged by the slave. The master issues a repeated start, repeats the slave address and read bit. The slave acknowledges and returns the data to the master. The master terminates the communication by a "not acknowledge" and a stop bit. To write data to the SX8722, the format is very similar. Only the data direction is different and the acknowledgement of the slave after the data reception. 8.1. Write data direct The diagram below shows the write operation. S T A R T SDA M S B L S B A C K A C K A C K A C K W R I T E S T O P DEVICE ADDRESS COMMAND REGISTER ADDRESS REGISTER VALUE Figure 7. I2C frame: write register, command 0x10 The diagram below shows the write operation at successive addresses (burst mode) S T A R T SDA M S B L S B A C K A C K A C K A C K A C K W R I T E S T O P DEVICE ADDRESS COMMAND REGISTER ADDRESS REGISTER VALUE (n) REGISTER VALUE (n + x) Figure 8. I2C frame: write burst register, command 0x10 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 21 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 8.2. Write data masked The diagram below show the write masked operation. S T A R T SDA M S B L S B A C K A C K A C K A C K W R I T E DATASHEET DEVICE ADDRESS COMMAND REGISTER ADDRESS REGISTER VALUE REGISTER MASK S T O P A C K Figure 9. I2C frame: write mask register, command 0x20 8.3. Read data Read data diagram. S T A R T SDA M S B L S B A C K A C K A C K A C K N O A C K W R I T E R E S T A R T DEVICE ADDRESS COMMAND REGISTER ADDRESS DEVICE ADDRESS R E A D REGISTER VALUE S T O P Figure 10. I2C frame: read register, command : 0x30 Read data diagram successive addresses (burst mode) R E S T A R T A C K S T A R T SDA M S B DEVICE ADDRESS L S B W R I T E A C K COMMAND REGISTER ADDRESS DEVICE ADDRESS R E A D REGISTER VALUE (n) A C K A C K REGISTER VALUE (n+x) N O A C K S T O P A C K Figure 11. I2C frame: read burst register, command 0x30 Note: If a read sequence is initiated without sending previously an address, the data shifted out will be the latest conversion result and its corresponding configuration ID (24 bits). See next page for more information. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 22 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 8.4. Other commands The diagram below shows the other commands syntax. S T A R T SDA M S B L S B A C K A C K W R I T E S T O P DATASHEET DEVICE ADDRESS COMMAND Figure 12. I2C frame: other commands, 0x40 - 0x80 8.5. Unknown commands The SX8722 does not answer to unknown commands. 8.6. Reading data after a measurement. The SX8722 performs measurements successively and stores the latest results in the enabled configurations data out registers. Every time a measurement is performed the pin READY makes a positive pulse allowing the host microcontroller to retrieve data from the SX8722. When the SX8722 is addressed and read the output is as shown below. Config ID indicates which channel is shifted out. S T A R T SDA M S B L S B A C K A C K A C K N O A C K R E S T A R T DEVICE ADDRESS R E A D CONFIG ID DATA MSB DATA LSB S T O P Figure 13. I2C frame: reading after a measurement ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 23 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 9. Predefined settings 9.1. Introduction This chapter intends to ease the handling of the SX8722 using a set of predefined settings. These settings are covering a large range of the SX8722 possibilities. However to avoid too much complexity some features are not handled by these settings. A more detailed use of the SX8722 can be found under the "advanced configuration" of this document. This chapter contains predefined command using the masked write mode. All the settings described in this chapter use the addresses of the 1st configuration register set, use the registers definition table to translate them to other register sets. 9.2. Features covered by predefined settings A 0 AC AR 1 2 3 4 5 6 7 B fS MUX VIN + PGA1 1 - 10 1 - 2 - 5 - 10 0/12 to 127/12 D fS + PGA2 E + + - + PGA3 + + - VIN, ADC + - - - - ADC MEASUREMENT ENGINE C 5/5 ... -5/5 63/12 ... -63/12 MUX The block schematic above shows the functions covered and controlled by the predefined settings set. It includes: A. The input multiplexers B. The programmable gain amplifiers C. The offset cancellation D. The ADC E. The Measurement engine Note: Grayed out blocks in the schematic means that they are used in the current function. ACS - Revision 4.2 (c)2008 Semtech Corp. 0 1 2 3 VREF + OFF2 + OFF3 - - Figure 14. Features covered by predefined settings October 2008 Page 24 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.3. Input multiplexers 9.3.1. Overview A 0 1 2 3 4 5 6 7 B fS MUX VIN + PGA1 1 - 10 1 - 2 - 5 - 10 0/12 to 127/12 DATASHEET D fS + PGA2 E AC + + - + PGA3 + + - VIN, ADC + - - - - ADC MEASUREMENT ENGINE C 5/5 ... -5/5 63/12 ... -63/12 AR MUX The diagram above shows the input multiplexer organization; these are enabling the selection of both the input and the reference sources. 9.3.2. Input channel selection The following settings allow configuring the input multiplexers of the ZoomingADCTM Function AC0 - AC1 AC2 - AC3 AC4 - AC5 AC6 - AC7 Address 0x0F Data 0x00 0x02 0x04 0x06 Mask 0x06 ACS - Revision 4.2 (c)2008 Semtech Corp. 0 1 2 3 VREF + OFF2 + OFF3 - - Figure 15. Input multiplexer overview Table 5. Differential mode October 2008 Page 25 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING . Function AC0 - AC1 AC0 - AC2 AC0 - AC3 AC0 - AC4 AC0 - AC5 AC0 - AC6 AC0 - AC7 Address 0x0F Data 0x22 0x24 0x26 0x28 0x2A 0x2B 0x2C Mask 0x2E DATASHEET Table 6. Single-ended mode Function Sign inversion Address 0x0F Data 0x10 Mask 0x10 Table 7. Invert input polarity 9.3.3. Reference channel selection Function AR1P - AR1N AR2P - AR2N Address 0x0F Data 0x00 0x01 Mask 0x01 Table 8. Reference channel selection 9.3.4. Application example In this example we want to measure a signal between AC0 and AC1 in single ended having a reference voltage between AR1P and AR1N. The following settings must be sent to SX8722: Function Set input to AC1 - AC2 Set reference to AR1P - AR1N Address 0x0F 0x0F Data 0x00 0x00 Mask 0x06 0x01 Table 9. Reference channel selection Note: This command can be optimized, since the reference and input setting are sharing the same address the mask and the settings can be added. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 26 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING The following command shows the optimized way Function Set input to AC1 - AC0, set reference to AR1P - AR1N Address 0x0F Data 0x00 Mask 0x07 DATASHEET Table 10. Optimized command ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 27 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.4. Programmable gain amplifier settings 9.4.1. Overview A 0 1 2 3 4 5 6 7 B fS MUX VIN + PGA1 1 - 10 1 - 2 - 5 - 10 0/12 to 127/12 DATASHEET D fS VIN, ADC + PGA2 E AC + + - + PGA3 + + - + - - - - ADC MEASUREMENT ENGINE C 5/5 ... -5/5 63/12 ... -63/12 AR MUX The diagram above shows the programmable gain amplifier organization, these are 3 PGA that are cascaded, the gain is made by multiplying them (disabled PGAs have the equivalent gain of 1). ACS - Revision 4.2 (c)2008 Semtech Corp. 0 1 2 3 VREF + OFF2 + OFF3 - - Figure 16. Programmable gain amplifiers (PGA) in the acquisition chain October 2008 Page 28 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.4.2. Configuration flow The diagram below shows the flow to set the gain of your configuration: DATASHEET Set gain Gain < 10 ? No Gain < 100 ? No Enable PGA1,2&3 Yes Yes Enable PGA3 Enable PGA2&3 Set PGA 1 gain Set PGA 3 gain Set PGA 2 gain Set PGA 2 gain Set PGA 3 gain Set PGA 3 gain GAIN = PGA3 GAIN = PGA2 x PGA3 GAIN = PGA1 x PGA2 x PGA3 End Figure 17. Gain configuration flowchart ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 29 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.4.3. Enable/disable PGAs Function Enable PGA3 Disable PGA3 Enable PGA2&3 Disable PGA2&3 Enable PGA1,2&3 Disable PGA1,2&3 Address 0x0B Data 0x08 0x00 0x0A 0x00 0x0E 0x00 0x0E 0x0A Mask 0x08 DATASHEET Table 11. PGA enable/disable settings 9.4.4. PGA3 gain configuration Function Gain = 1 Gain = 2 Gain = 3 Gain = 4 Gain = 5 Gain = 6 Gain = 7 Gain = 8 Gain = 9 Gain = 10 Address 0x0D Data 0x0C 0x18 0x24 0x30 0x3C 0x48 0x54 0x60 0x6C 0x78 Mask 0x7F Table 12. PGA3 gain configuration 9.4.5. PGA2 gain configuration Function Gain = 1 Gain = 2 Gain = 5 Gain = 10 Address 0x0C Data 0x00 0x10 0x20 0x30 Mask 0x30 Table 13. PGA2 gain configuration ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 30 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.4.6. PGA1 gain configuration Function Gain = 1 Gain = 10 Address 0x0D Data 0x00 0x80 Mask 0x80 DATASHEET Table 14. PGA1 gain configuration 9.4.7. Application example The total gain to set in this example is 300. The following settings must be sent to SX8722: Function Enable PGA1,2&3 PGA3 gain = 3 PGA2 gain = 10 PGA1 gain = 10 Address 0x0B 0x0D 0x0C 0x0D Data 0x0E 0x24 0x30 0x80 Mask 0x0E 0x7F 0x30 0x80 Table 15. Application example of PGA gain settings Note: This command can be optimized, since PGA1 and PGA3 gains are sharing the same address the mask and the settings can be added. The following list of settings shows the optimized Function Enable PGA1,2&3 PGA3 gain = 3, PGA1 gain = 10 PGA2 gain = 10 Address 0x0B 0x0D 0x0D Data 0x0E 0xA4 0x80 Mask 0x0E 0xFF 0x30 Table 16. Optimized command of PGA gain settings ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 31 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.5. Offset cancellation 9.5.1. Overview A 0 1 2 3 4 5 6 7 B fS MUX VIN + PGA1 1 - 10 1 - 2 - 5 - 10 0/12 to 127/12 DATASHEET D fS + PGA2 E AC + + - + PGA3 + + - VIN, ADC + - - - - ADC MEASUREMENT ENGINE C 5/5 ... -5/5 63/12 ... -63/12 AR MUX The offset cancellation consists in adding or subtracting a fraction or a multiple of the reference to the signal before the ADC input. In the predefined settings only the addition or the subtraction of VREF/2 is implemented. More offsets configuration can be defined using the "advanced configuration" at the end of this document. The drawings below explain the offset concept. (AC1 - AC0) Vref / 2 Vin ADC Vref / 2 0 - Vref / 2 ACS - Revision 4.2 (c)2008 Semtech Corp. 0 1 2 3 VREF + OFF2 + OFF3 - - Figure 18. Offset cancellation in the acquisition chain t GAIN x2 t 0 - Vref / 2 Figure 19. Differential signal October 2008 Page 32 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING (AC1 - AC0) Vref Vin ADC Vref / 2 DATASHEET t OFFSET 0.5 x Vref 0 t 0 - Vref / 2 Figure 20. Single ended signal, AC0 = VSS The following settings add 0.5 x VREF or subtract 0.5 x VREFfrom the signal. Function Offset 3 = 0.5 x VREF Offset 3 = -0.5 x VREF Address 0x0E Data 0x06 0x46 Mask 0x7F Table 17. Example: Adding or remove 0.5 x Vref ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 33 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.5.2. Application example Case 1 Input signal = VREF / 2 Input selection = AC0 - AC1. (see "input multiplexers" chapter) Offset to remove is VREF / 2. The following command must be sent to SX8722: Function Offset 3 = 0.5 x VREF Address 0x0E Data 0x06 Mask 0x7F DATASHEET Case 2 Input signal = VREF Input selection = AC0 - AC1. (see "input multiplexers" chapter) Offset to remove is -VREF / 2. The following command must be sent to SX8722: Function Offset 3 = -0.5 x VREF Address 0x0E Data 0x46 Mask 0x7F ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 34 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.6. ADC parameters 9.6.1. Overview A 0 1 2 3 4 5 6 7 B fS MUX VIN + PGA1 1 - 10 1 - 2 - 5 - 10 0/12 to 127/12 DATASHEET D fS + PGA2 E AC + + - + PGA3 + + VIN, ADC + - - - - ADC MEASUREMENT ENGINE C 5/5 ... -5/5 63/12 ... -63/12 AR MUX The ADC parameters are mainly the resolution and acquisition speed. Detailed ADC parameters and configuration can be found in the "advanced configuration" chapter The table below gives the main configurations available using the predefined settings and their main characteristics: Name S16 N16 F16 N12 N8 ACS - Revision 4.2 (c)2008 Semtech Corp. 0 1 2 3 VREF + OFF2 + OFF3 - - Table 18 ADC in the acquisition chain Resolution [bits] 16 16 16 12 8 Conversion time [ms] (typ) 27.3 6.8 3.4 0.22 0.06 Sampling frequency [kHz] (typ) 300 Oversampling ratio 1024 1024 1024 64 16 Number of elementary conversion 8 2 1 1 1 Comments Maximum resolution, thermal noise reduced to its minimum Standard 16 bits resolution Fastest 16 bits resolution Standard 12 bits resolution Standard 8 bits resolution Table 19. ADC predefined settings October 2008 Page 35 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.6.2. ADC settings Function S16 N16 F16 N12 N8 Address 0x0C Data 0x7C 0x3C 0x1C 0x0C 0x04 Mask 0x7C DATASHEET Table 20. ADC register settings 9.7. Measurement engine 9.7.1. Overview A 0 AC AR 1 2 3 4 5 6 7 B fS MUX VIN + PGA1 1 - 10 1 - 2 - 5 - 10 0/12 to 127/12 D fS + PGA2 E + + - + PGA3 + + - VIN, ADC + - - - - ADC MEASUREMENT ENGINE C 5/5 ... -5/5 63/12 ... -63/12 MUX The measurement engine manages the configuration register sets and controls registers contents. Based on these parameters it configures the ZoomingADCTM, supervises post processing of the measurements, stores the results and flags the READY signal. Once enabled the configuration 1 will be applied to the ZoomingADCTM and measurement will be done until the configuration is disabled using the disable command. Note: All the predefined settings refer to configuration 1, to change other configurations simply adapt the address value. More detailed functionalities are described in "Advanced configuration" chapter. ACS - Revision 4.2 (c)2008 Semtech Corp. 0 1 2 3 VREF + OFF2 + OFF3 - - Figure 21. Measurement engine October 2008 Page 36 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 9.7.2. Measurement engine settings DATASHEET Application Configuration 1 enabled Configuration 1 disabled Address 0x02 Data 0x01 0x00 Mask 0x01 Table 21. Measurement engine settings ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 37 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 10. Default configuration The SX8722 default configuration is described in this chapter. The SX8722 default hardware configuration is as follow: 1uF Vreg capacitor connected to Vreg pin EE_SDA connected to ground 3.0 - 5.0 power supply on Vbat, 0V on GND Wheatstone bridge type sensor connected to AC0-AC1 biased through bias pin VRef = VBias = VBat Host micro controller I2C connected to SDA and SCL of the SX8722 Host micro controller GPIO connected to RESET input of the SX8722 EE_POW EE_SDA EE_SCL SX8722 BIAS VBATT GND ALRM1 ALRM2 VBATT REF MUX AR1P AR1N AR2P AR2N ZoomingADC TM CONTROL CAL RESET READY MCU AC7 AC6 I2C SIGNAL MUX SCL SDA SCL SDA GPIO Differential AC5 AC4 AC3 AC2 AC1 AC0 PGA ADC OSC XIN XOUT CKOUT SLEEP SHUT POST-PROCESS POWER VREG VMULT Figure 22. Schematic of the default configuration Note: Startup conditions Reset = `0' 10.1. ZoomingADC default settings The SX8722 starts upon a power on reset and then goes into measurement mode. By default the measurement mode parameters are as follows: Differential measurement on channel AC0 - AC1, gain 1, 16 bits resolution, reference on AR1P - AR1N, no filtering, continuous measurements. The READY pin will pulse from "0" to "1" at every sample available. The host microcontroller can then read the data. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 38 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 11. Advanced configuration 11.1. Overview The advanced configuration section is entering more in depth in the SX8722 usage. In this section you will find: Measurement engine Configuration control Filtering Alarms I2C EEPROM Using the SX8722 Stand alone Calibration process Working below 3 Volts Control registers ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 39 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.2. Measurement engine 11.2.1. Overview DATASHEET The measurement engine is the interface between the configuration register sets and the ZoomingADCTM. 11.2.2. Functional flowchart RESET / Power on reset Initialization, EEPROM Load Read Enabled Configurations [SXCtrlEn] YES Store intermediate values Measure conf n START Configure ZoomingADC using configuration n parameters START conversion Wait for conversion to finish CONT bit ? (Idle mode) Mcounter + 1 Idle mode Conf 1? YES Measure conf 1 Mcounter = NAverage? Conf 2 ? YES Measure conf 2 Compute average Store result in configuration n OUT registers Clear SINGLE bit Conf 3? YES Measure conf 3 Conf 4? YES Measure conf 4 Update [SXUpdated n] Set READY bit Measure conf n END Figure 23. Measurement engine flowchart The flowchart above shows the measurement engine function. It performs successively the measurements for each enabled configuration. If in one or more configurations the bit CONT is set to 1, the measurements are performed again until the CONT bit is set to 0 through the I2C interface. The engine goes out from the Idle mode every time an event occurs on the I2C interface. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 40 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.3. Control registers DATASHEET The parameters available on these registers affect the whole SX8722 and are common to all configuration register sets. 11.3.1. SXCtrl1 - SX8722 Control register 1 Register SXCtrl1 7 EE_D 6 XTAL_D 5 CKOUT 4 reserved 3 EE 2 SLEEP 1 SHUT 0 CAL Table 22. Control register; address 0x00 Bit 7 6 5 4 3 2 1 0 SXCtrl1 EE_D XTAL_D CKOUT RESERVED EE SLEEP SHUT CAL rw r r rw rw r rw rw r Reset x x 0 0 0 0 0 0 Description Indicates if an EEPROM was detected at startup Indicates if an XTAL was detected at startup Enabled the clock output on CKOUT pin Is set to 1 when SX8722 loaded its configuration from the EEPROM at startup When set to 1 his bit activates the Sleep mode of the SX8722. Setting pin SLEEP to 1 has the same effect. When set to 1 his bit activates the Shutdown mode of the SX8722. Setting pin SHUT to 1 has the same effect. This flag shows if the SX8722 clock has been successfully calibrated. 11.3.2. SXCtrl2 - SX8722 Control register 2 Register SXCtrl2 7 reserved 6 reserved 5 reserved 4 reserved 3 AL1OnC 2 AL1OffC 1 AL2OnC 0 AL2OffC Table 23. Control register 2; address 0x01 Bit 3 2 1 0 SXCtrl1 AL1OnC AL1OffC AL2OnC AL2OffC rw rw rw rw rw Reset 0 0 0 0 Description Sets the logical condition for alarm 1 on (0 = OR, 1 = AND) Sets the logical condition for alarm 1 on (0 = OR, 1 = AND) Sets the logical condition for alarm 1 on (0 = OR, 1 = AND) Sets the logical condition for alarm 1 on (0 = OR, 1 = AND) Note: More information about the alarms condition usage on Alarm section ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 41 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.3.3. SXCfgEn - Configuration enabling register Writing this register allows enabling or disabling the different configuration register sets. Note: DATASHEET When the configuration is set to SINGLE, the bit CONFx is cleared automatically after the measurement is done. 7 reserved 6 reserved 5 reserved 4 reserved 3 CONF4 2 CONF3 1 CONF2 0 CONF1 Register SXCfgEn Table 24. Configuration enabling register; address 0x02 11.3.4. SXUpdated - Updated configuration register The configuration update registers contain which configuration has been updated by a measurement result. Register SXUpdated 7 OVF4 6 OVF3 5 OVF2 4 OVF1 3 UCONF4 2 UCONF3 1 UCONF2 0 UCONF1 Table 25. Updated configuration register; address 0x03 These bits are set to 1 every time a measurement is done on one of the 4 configurations. When the registers are read, these bits are set back to 0 by the communication engine, the bits 4 to 7 indicates an overflow. 11.3.5. Configuration register - measurement mode This register is present in each configuration; the bits 0 & 1 are controlling the measurement mode. Register CxSXCfg 7 reserved 6 5 FILTER TYPE[2:0] 4 3 ALRM1 2 ALRM2 1 SINGLE 0 CONT Table 26. Measurement mode in configuration registers; addresses 0x10, 0x30, 0x50, 0x70 The bit SINGLE is set by the user, once the measurement is done; the measurement engine clears the CONF bit of the configuration. The bit CONT is set by the user, the measurement is done continuously until this bit is cleared by the user. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 42 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.4. Filtering 11.4.1. Filter types There are 2 different filtering types: 1. Average filtering. 2. Moving average filtering. DATASHEET The average filtering is an addition of n values divided by n, this kind of filter is useful when having a very noisy signal; the maximum average value is 256. Advantage: Reduces noise due to the high quantity of samples. Disadvantage: Takes the acquisition time of n samples to have a result. The sliding window averaging is a filter that takes the n last measurements and gives the mean value of them. Advantage: result on each acquisition. Disadvantage: limited at ten samples. Additional delay. Important note: The ADC filtering is faster, these additional filters should be used only if the number of conversion (NELCONV) and the over sampling rate (OSR) are set to their maximum. 11.4.2. Configuration register - filtering This register is present in each configuration; the bits 4 to 6 are controlling the filtering mode. Register CxSXCfg 7 reserved 6 5 FILTER TYPE[2:0] 4 3 ALRM1 2 ALRM2 1 SINGLE 0 CONT Table 27. Filtering mode in configuration registers; addresses 0x10, 0x30, 0x50, 0x70 The table below shows the filter selection. Filter type [6:4] Code 000 001 010 011 none average filtering moving average filtering reserved Mode Table 28. Filter selection ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 43 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.4.3. Filter size register This register is present in each configuration; the bits 0 to 7 are controlling the filter size. Register CxFParam 7 6 5 4 3 2 DATASHEET 1 0 Filter size [7:0] Table 29. Filter size registers; addresses 0x11, 0x31, 0x51, 0x71 This register contains the number of samples used for the filtering. Note that for a moving average filtering, this number is limited to 10. (Putting a higher value will be interpreted as 10.) 11.5. Alarms The SX8722 offers two alarms pins that have configurable on & off thresholds; these thresholds are on 16 bits. Each configuration register set has 2 alarms, which can be enabled, when more than one configuration is using the same alarm pin, logical function is interacting between the two alarms sources. This condition can be a logical OR (default) or a logical AND. 11.5.1. Configuration register - alarms The bits 2 & 3 enable the alarm 1 & 2 when set to 1. Register CxSXCfg 7 reserved 6 5 FILTER TYPE [2:0] 4 3 ALRM1 2 ALRM2 1 SINGLE 0 CONT Table 30. Alarm enabling in configuration registers; addresses 0x10, 0x30, 0x50, 0x70 11.5.2. Alarm threshold registers Registers CxAlrm1OnMsb CxAlrm1OnLsb CxAlrm1OffMsb CxAlrm1OffLsb CxAlrm2OnMsb CxAlrm2OnLsb CxAlrm2OffMsb CxAlrm2OffLsb 7 6 5 4 3 2 1 0 S1ALRM1ON S1ALRM1ON S1ALRM1OFF S1ALRM1OFF S1ALRM2ON S1ALRM2ON S1ALRM2OFF S1ALRM2OFF Table 31. Alarm threshold registers; addresses 0x12 to 0x19, 0x32 to 0x39, 0x52 to 0x59 and 0x72 to 0x79 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 44 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.5.3. SXCtrl2 - SX8722 Control register 2 DATASHEET This register is common to all configurations; it sets the relationship between the different alarm sources. Register SXCtrl2 7 reserved 6 reserved 5 reserved 4 reserved 3 AL1OnC 2 AL1OffC 1 AL2OnC 0 AL2OffC Table 32. Alarm sources in Control register 2; address 0x02 When set to 1 the condition is AND and when set to 0 the condition is OR. The diagram below shows the interaction between alarms sources. Al1OnC Configuration 1 Alarm1 on threshold reached ? Configuration 2 Alarm1 on threshold reached ? Configuration 3 Alarm1 on threshold reached ? Configuration 4 Alarm1 on threshold reached ? Alarm1 on flag set A l1OffC Configuration 1 Alarm1 off threshold reached ? Configuration 2 Alarm1 off threshold reached ? Configuration 3 Alarm1 off threshold reached ? Configuration 4 Alarm1 off threshold reached ? Alarm1 off flag set Figure 24. Alarms sources interaction The flowchart below shows the management of the alarms flag (when at least one alarm is on). Alarm Mgmt Alarm1 on flag set ? Set Alarm 1 pin to 1 Alarm1 off flag set? Set Alarm 1 pin to 0 Alarm Mgmt End Figure 25. Alarms flag managment ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 45 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.6. I2C EEPROM 11.6.1. Overview The SX8722 can interface a Standard I2C EEPROM. This allows: Stand alone usage. Parameters saving by save command. Parameters restore by load command. DATASHEET The EE_POW pin allows the SX8722 to power the EEPROM in order to guarantee the lowest power having the EEPROM unpowered when unused. When no EEPROM is used, the EE_SDA pin must be tied to ground. 11.6.2. Schematic The schematic below shows the connections using standard I2C EEPPROM. EEPROM VBATT GND SDA EE_SDA SCL EE_SCL SX8722 BIAS EE_POW VBATT GND ALRM1 ALRM2 VBATT REF MUX AR1P AR1N AR2P AR2N ZoomingADC TM CONTROL CAL RESET READY MCU AC7 AC6 I 2C SIGNAL MUX SCL SDA SCL SDA GPIO Differential AC5 AC4 AC3 AC2 AC1 AC0 PGA ADC OSC XIN XOUT CKOUT SLEEP SHUT POST-PROCESS POWER VREG VMULT Figure 26. EEPROM connection ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 46 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.7. Using the SX8722 Stand alone DATASHEET The SX8722 can be used stand alone to monitor signals and to generate alarms on configured thresholds. Using a preprogrammed EEPROM allows the setup of these monitoring tasks. 11.7.1. Schematic The schematic below shows an example of a stand alone configuration. EEPROM VBATT GND SDA EE_SDA SCL EE_SCL EE_POW 5V VBATT GND 12V L1 L2 L3 SX8722 BIAS ALRM1 ALRM2 AR1N AR2P AR2N REF MUX AR1P ZoomingADC TM CONTROL CAL RESET READY AC7 AC6 I2C SIGNAL MUX SCL SDA Differential AC5 AC4 AC3 AC2 AC1 AC0 PGA ADC OSC XIN XOUT CKOUT SLEEP SHUT POST-PROCESS POWER VREG VMULT Figure 27. Example of stand alone configuration ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 47 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.8. Frequency calibration process 11.8.1. Overview DATASHEET The SX8722 has an internal RC Oscillator working at 1.2 MHz +/- 600kHz. The calibration is optional. The main reason to calibrate the RC frequency is to fix the input impedance of the acquisition chain, function of the RC frequency. This frequency can be calibrated using 2 methods. 32.768 kHz Xtal Input of a 32.768 kHz signal on the CAL pin. 11.8.2. Using an 32.768 kHz XTAL When the SX8722 is connected to a 32.768 XTAL between XIN & XOUT, the CAL pin must be grounded. This indicates to SX8722 that an XTAL is present and allows frequency auto-calibration at power on. EE_POW EE_SDA EE_SCL 5V VBATT GND SX8722 BIAS VBATT ALRM1 ALRM2 REF MUX AR1P AR1N AR2P AR2N ZoomingADC TM CONTROL CAL RESET READY MCU AC7 AC6 I2C SIGNAL MUX SCL SDA SCL SDA GPIO Differential AC5 AC4 AC3 AC2 AC1 AC0 PGA ADC OSC XIN XOUT 32'768 Hz CKOUT SLEEP SHUT POST-PROCESS POWER VREG VMULT Figure 28. Calibration : using a 32'768 Hz XTAL ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 48 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.8.3. Using a 32.768 kHz External clock source DATASHEET The host microcontroller can at any time send a 32.768kHz signal on CAL pin, the detection of a rising edge on the this pin initiates a calibration process. When the chip is calibrated, the pin READY rises to high level. EE_POW SX8722 BIAS EE_SDA EE_SCL VBATT GND ALRM1 ALRM2 VBATT REF MUX AR1P AR1N AR2P AR2N ZoomingADC TM CONTROL CAL RESET READY 32'768 Hz GPIO GPIO GPIO MCU AC7 AC6 I2C SIGNAL MUX SCL SDA SCL SDA Differential AC5 AC4 AC3 AC2 AC1 AC0 PGA ADC OSC XIN XOUT CKOUT SLEEP SHUT POST-PROCESS POWER VREG VMULT Figure 29. Calibration : using a 32'768 Hz signal NOTE: If an external EEPROM is present, the calibration value is saved in it. The tolerance signal must remain around 32.768 kHz +/- 10% ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 49 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 11.9. Working below 3 V 11.9.1. Operating range DATASHEET The SX8722 operating range is 5.5 Volts downto 2.4 Volts. However, below 3 Volts the SX8722 enables an internal voltage multiplier to power the ZoomingADCTM. 11.9.2. Internal voltage multiplier This internal voltage multiplier is automatically enabled when the power supply goes below 3 Volts but the internal voltage multiplier requires an external capacitor between VMULT pin and ground, the value of this capacitor must be between 1 and 3 nF. 11.9.3. Schematic The schematic below shows the capacitor connection: EE_POW EE_SDA EE_SCL Vbatt < 3V VBATT GND SX8722 BIAS VBATT ALRM1 ALRM2 REF MUX AR1P AR1N AR2P AR2N ZoomingADC TM CONTROL CAL RESET READY MCU GPIO AC7 AC6 I2C SIGNAL MUX SCL SDA SCL SDA GPIO Differential AC5 AC4 AC3 AC2 AC1 AC0 PGA ADC OSC XIN XOUT CKOUT SLEEP SHUT POST-PROCESS POWER VREG VMULT 2 nF Figure 30. SX8722 working below 3V schematic ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 50 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 12. ZoomingADC 12.1. ZoomingADC Features The ZoomingADC is a complete and versatile low-power analog front-end interface typically intended for sensing applications. The key features of the ZoomingADC are: Programmable 6 to 16-bit dynamic range oversampled ADC Flexible gain programming between 0.5 and 1000 Flexible and large range offset compensation 4-channel differential or 8-channel single-ended input multiplexer 2-channel differential reference inputs Power saving modes 12.1.1. Overview fS fS MUX VIN + PGA1 AC + + AR 1 2 3 MUX VREF + OFF2 - + OFF3 - - Figure 31. ZoomingADC general functional block diagram The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an oversampled A/D converter. The reference voltage can be selected on two different channels. Two offset compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset allow to zoom in on a small portion of the reference voltage defined input range. 12.2. Acquisition Chain The figure above shows the general block diagram of the acquisition chain (AC). Analog inputs can be selected among eight input channels, while reference input is selected between two differential channels. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 51 - 0 0 1 2 3 4 5 6 7 + PGA2 + - + PGA3 + - VIN, ADC + - - - - ADC 16 bits www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of a combination of input and reference signals VIN and VREF, the input voltage is modulated and amplified through stages 1 to 3. Fine gain programming up to 1'000V/V is possible. In addition, the last two stages provide programmable offset. Each amplifier can be bypassed if needed. The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal VIN,ADC into digital. Like most ADCs intended for instrumentation or sensing applications, the ZoomingADC is an over-sampled converter (See Note1). The ADC is a so-called incremental converter with bipolar operation (the ADC accepts both positive and negative input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers the quantity: OUTADC VIN , ADC FS / 2 VREF / 2 (Eq. 1) in two's complement (see Section 12.8.7 for details). The output code OUTADC is -FS/2 to +FS/2 for VIN,ADC, -VREF/2 to +VREF/2 respectively. As will be shown in section 0, VIN,ADC is related to input voltage VIN by the relationship: VIN , ADC = GDTOT VIN - GDoff TOT VREF (Eq. 2) where GDTOT is the total PGA gain, and GDoffTOT is the total PGA offset. Note: [V] Over-sampled converters are operated with a sampling frequency fS much higher than the input signal's Nyquist rate (typically fS is 20-1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 52 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 12.3. ZoomingADC Detailed block diagram INPUTS fS fS MUX VIN + PGA1 DATASHEET AC + + AR 1 2 3 MUX VREF + OFF2 - + OFF3 - - - CxAdcReg6 CxAdcReg5 CxAdcReg4 CxAdcReg3 CxAdcReg2 Sampling frequency fs CxAdcReg1 ACS - Revision 4.2 (c)2008 Semtech Corp. 0 0 1 2 3 4 5 6 7 VIN, ADC + PGA2 + - + PGA3 + - + - - - - ADC Acquisition chain Register bank CxDataOutMsb CxDataOutLsb Power Saving Modes PGA Enabling Nb of elementary cycles Oversampling ratio Figure 32. ZoomingADC detailed functional block diagram October 2008 Page 53 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 12.4. ZoomingADC register map DATASHEET There are six registers in the acquisition chain (AC), namely CxZadcReg1, CxZadcReg2, CxZadcReg3, CxZadcReg4, CxZadcReg5 and CxZadcReg6. Tables below shows the mapping of control bits and functionality of these registers while Table 33 gives an overview of these six. The register map only gives a short description of the different configuration bits. More detailed information is found in subsequent sections. Registers CxZadcReg1 CxZadcReg2 CxZadcReg3 CxZadcReg4 CxZadcReg5 CxZadcReg6 Addresses 0x0A - 0x2A - 0x4A - 0x6A 0x0B - 0x2B - 0x4B - 0x6B 0x0C - 0x2C - 0x4C - 0x6C 0x0D - 0x2D - 0x4D - 0x6D 0x0E - 0x2E - 0x4E - 0x6E 0x0F - 0x2F - 0x4F - 0x6F Table 33. ADC settings registers Bit 7 6:5 4:2 1 0 CxZadcReg1 reserved SET_NELCONV [1:0] SET_OSR [2:0] reserved reserved rw rw rw rw rw rw Reset 0 01 010 0 0 Description Sets the number of elementary conversions sets the oversampling rate of an elementary conversion Table 34. CxZadcReg1; addresses 0x0A - 0x2A - 0x4A - 0x6A Bit 7:6 5:4 3:0 CxZadcReg2 IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] rw rw rw rw Reset 11 11 0000 Description Bias current selection of the A/D converter Bias current selection of the PGA stages Enabled the different PGA stages and the ADC Table 35. CxZadcReg2; addresses 0x0B - 0x2B - 0x4B - 0x6B ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 54 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:6 5:4 3:0 CxZadcReg3 FIN[1:0] PGA2_PGA[1:0] PGA2_OFFSET[3:0] rw rw rw rw Reset 00 00 0000 Description Sampling frequency selection PGA2 stage gain selection PGA2 stage offset selection Table 36. CxZadcReg3; addresses 0x0C - 0x2C - 0x4C - 0x6C Bit 7 6:0 CxZadcReg4 PGA1_GAIN PGA3_PGA[6:0] rw rw rw Reset 0 Description PGA1 stage gain selection 0000000 PGA3 stage gain selection Table 37. CxZadcReg4; addresses 0x0D - 0x2D - 0x4D - 0x6D Bit 7 6:0 CxZadcReg5 reserved PGA3_OFFSET[6:0] rw r rw Reset 0 Description 0000000 PGA3 stage offset selection Table 38. CxZadcReg5; addresses 0x0E - 0x2E - 0x4E - 0x6E Bit 7 6 5:1 0 CxZadcReg6 PGA1_GAIN PGA3_PGA[6:0] AMUX[4:0] VMUX rw r r rw rw Reset 0 0 00000 0 Activity flag Description Select default configuration Input channel configuration selector Reference channel selector Table 39. CxZadcReg6; addresses 0x0F - 0x2F - 0x4F - 0x6F ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 55 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 12.5. ZoomingADCTM registers table DATASHEET In table below the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain (CxZAdcReg1 to 6), and two registers are used to store the output code of the analog-to-digital conversion (CxDataOutMSB & LSB). Register Name 7 CxDataOutLSB CxDataOutMSB CxZadcReg1 Default values CxZadcReg2 Default value CxZadcReg3 Default value CxZadcReg4 Default value CxZadcReg5 Default value CxZadcReg6 Default value R 0 SET_NC[1:0] 01 IB_AMP_PGA[1:0] 11 PGA2_GAIN[1:0] 00 PGA3_GAIN[6:0] 0000000 PGA3_OFFSET[6:0] 0000000 R 0 AMUX[4:0] 00000 VMUX 0 6 5 4 OUT[7:0] OUT[15:8] SET_OSR[2:0] 010 R 0 ENABLE[3:0] 0001 PGA2_OFFSET 0000 R 0 Bit position 3 2 1 0 IB_AMP_ADC[1:0] 11 FIN[1:0] 00 PGA1_GAIN 0 0 R 0 Table 40. ZoomingADC registers Note Bits labelled R are reserved With: OUT: SET_NELC: SET_OSR: CONT: IB_AMP_ADC: IB_AMP_PGA: ENABLE: FIN: PGA1_GAIN: PGA2_GAIN: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15]) (rw) sets the number of elementary conversions to 2SET_NELC[1:0] . To compensate for offsets, the input signal is chopped between elementary conversions (1,2,4,8). (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]) . OSR = 8, 16, 32, ..., 512, 1024. (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1. (rw) sets the bias current in the ADC to 0.25 x (1+ IB_AMP_ADC[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. (rw) sets the bias current in the PGAs to 0.25 x (1+ IB_AMP_PGA[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i = 1,2,3). PGA stages that are disabled are bypassed. (rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the sampling frequency is given as: 00 ' 1/4 fRC, 01 ' 1/8 fRC, 10 ' 1/32 fRC, 11' ~8kHz. (rw) sets the gain of the first stage: 0 ' 1, 1 ' 10. (rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 56 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING PGA3_GAIN: PGA2_OFFSET: PGA3_OFFSET: AMUX(4:0): VMUX: (rw) sets the gain of the third stage to PGA3_GAIN[6:0] 1/12. DATASHEET (rw) sets the offset of the second stage between -1 and +1, with increments of 0.2. The MSB gives the sign (0 positive, 1 negative); amplitude is coded with the bits PGA2_OFFSET[5:0]. (rw) sets the offset of the third stage between -5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 positive, 1 negative); amplitude is coded with the bits PGA3_OFFSET[5:0]. (rw) AMUX[4] sets the mode (0 ' 4 differential inputs, 1 ' 7 inputs with A(0) = common reference) AMUX(3) sets the sign (0 ' straight, 1' cross) AMUX[2:0] sets the channel. (rw) sets the differential reference channel (0 ' R(1) and R(0), 1 ' R(3) and R(2)). (r = read; w = write; rw = read & write) 12.6. Input Multiplexers The ZoomingADC has eight analog inputs AC_A(0) to AC_A(7) and four reference inputs AC_R(0) to AC_R(3). Let us first define the differential input voltage VIN and reference voltage VREF respectively as: VIN = VINP - VINN (Eq. 3) and: [V] VREF = VREFP - VREFN (Eq. 4) [V] As shown in Table 41 the inputs can be configured in two ways: either as 4 differential channels (VIN1 = AC_A(1) AC_A(0),..., VIN4 = AC_A(7) - AC_A(6)), or AC_A(0) can be used as a common reference, providing 7 signal paths all referred to AC_A(0). The control word for the analog input selection is AMUX[4:0]. Notice that the bit AMUX[3] controls the sign of the input voltage. AMUX [4:0] (RegACCfg5[5:1]) 00x00 00x01 00x10 00x11 10000 10001 10010 10011 10100 10101 10110 10111 VINP AC_A(1) AC_A(3) AC_A(5) AC_A(7) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) AC_A(6) AC_A(7) VINN AC_A(0) AC_A(2) AC_A(4) AC_A(6) AC_A(0) AMUX [4:0] (RegACCfg5[5:1]) 01x00 01x01 01x10 01x11 11000 11001 11010 11011 11100 11101 11110 11111 VINP AC_A(0) AC_A(2) AC_A(4) AC_A(6) AC_A(0) VINN AC_A(1) AC_A(3) AC_A(5) AC_A(7) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) AC_A(6) AC_A(7) Table 41. Analog input selection ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 57 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Similarly, the reference voltage is chosen among two differential channels (VREF1 = AC_R(1)-AC_R(0) or VREF2 = AC_R(3)-AC_R(2)) as shown in Table 42 The selection bit is VMUX. The reference inputs VREFP and VREFN (commonmode) can be up to the power supply range. VMUX (RegACCfg5[0]) 0 1 VREFP AC_R(1) AC_R(3) VREFN AC_R(0) AC_R(2) Table 42. Analog input reference selection 12.7. Programmable Gain Amplifiers The zooming function is implemented with three programmable gain amplifiers (PGA). These are: PGA1: coarse gain tuning PGA2: medium gain and offset tuning PGA3: fine gain and offset tuning All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and gain, as well as the offset of stages 2 and 3. These functions are examined hereafter. 12.7.1. PGA & ADC Enabling Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the word ENABLE and the coding given in Table 43. To reduce power dissipation, the ADC can also be inactivated while idle. Enable [3:0] XXX0 XXX1 XX0X XX1X X0XX X1XX 0XXX 1XXX Block ADC disabled ADC enabled PGA1 disabled PGA1 enabled PGA2 disabled PGA2 enabled PGA3 disabled PGA3 enabled Table 43. PGA and ADC enabling 12.7.2. PGA1 The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 44). The voltage VD1 at the output of PGA1 is: VD1 = GD1 VIN (Eq. 5) [V] ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 58 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN. PGA1_GAIN 0 1 PGA1 gain [V/V] 1 10 DATASHEET Table 44. PGA1 gain settings 12.7.3. PGA2 The second PGA has a finer gain and offset tuning capability, as shown in Table 45 and Table 46. The voltage VD2 at the output of PGA2 is given by: VD 2 = GD2 VD1 - GDoff 2 VREF (Eq. 6) [V] where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words PGA2_GAIN[1:0] and PGA2_OFFSET[3:0]. PGA2_GAIN 00 01 10 11 PGA2 gain [V/V] 1 2 5 10 Table 45. PGA2 gain settings PGA2_OFFSET 0000 0001 0010 0011 0100 0101 1000 1001 1010 1011 PGA2 offset [V/V] 0 +0.2 +0.4 +0.6 +0.8 +1 -0.2 -0.4 -0.6 -0.8 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 59 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING PGA2_OFFSET 1100 PGA2 offset [V/V] -1 DATASHEET Table 46. PGA2 offset settings 12.7.4. PGA3 The finest gain and offset tuning is performed with the third and last PGA stage, according to the following coding Tables. PGA3_GAIN[6:0] 0000000 0000001 ... 0000110 ... 0001100 0010000 ... 0100000 ... 1000000 ... 1111111 PGA3 gain [V/V] 0 1/12 (=0.083) ... 6/12 ... 12/12 16/12 ... 32/12 ... 64/12 ... 127/12 (=10.58) Table 47. PGA3 gain settings PGA3_GAIN[6:0] 0000000 0000001 0000010 ... 0010000 ... 0100000 PGA3 gain [V/V] 0 +1/12(=0.083) +2/12 ... +16/12 ... +32/12 0111111 +63/12 (=+5.25) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 60 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING PGA3_GAIN[6:0] 1000000 1000001 1000010 ... 1010000 ... 1100000 ... 1111111 PGA3 gain [V/V] 0 -1/12(=-0.083) -2/12 ... -16/12 ... -32/12 ... -63/12(=5.25) DATASHEET Table 48. PGA3 offset settings The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the voltage entering the ADC is given by: VIN , ADC = GD3 VD 2 - GDoff 3 VREF (Eq. 7) [V] where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are PGA3_GAIN[6:0] and PGA3_OFFSET[6:0] . To remain within the signal compliance of the PGA stages, the condition: VD1 , VD 2 < VDD (Eq. 8) must be verified. [V] Finally, combining equations Eq. 5 to Eq. 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related to VIN by: VIN , ADC = GDTOT VIN - GDoffTOT VREF (Eq. 9) [V] ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 61 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING where the total PGA gain is defined as: DATASHEET GDTOT = GD3 GD2 GD1 (Eq. 10) and the total PGA offset is: [V] GDoffTOT = GDoff 3 + GD3 GDoff 2 (Eq. 11) [V V] 12.8. ADC Characteristics The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three programmable parameters: Oversampling frequency fS, over-sampling ratio OSR, and number of elementary conversions NELCONV. The setting of these parameters and the resulting performances are described hereafter. 12.8.1. Conversion Sequence A conversion is started each time the bit START or the bit DEF is set. As depicted in Figure 3, a complete analog-to-digital conversion sequence is made of a set of NELCONV elementary incremental conversions and a final quantization step. Each elementary conversion is made of (OSR+1) sampling periods TS=1/fS, i.e.: TELCONV = (OSR + 1) / f S (Eq. 12) [s] The result is the mean of the elementary conversion results. An important feature is that the elementary conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the output code. Thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.e. if NELCONV = 2). A few additional clock cycles are also required to initiate and end the conversion properly. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 62 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET TELCONV= (OSR+1)/f S Init Elementary Conversion 1 + Elementary Conversion 2 - Elementary Conversion NELCONV- 1 + Elementary Conversion N ELCONV - End Conversion Result Conversion index Offset T CONV Figure 33. Analog-to-digital conversion sequence 12.8.2. Sampling Frequency The word FIN[1:0] is used to select the sampling frequency fS (Table 49). Three sub-multiples of the internal RC-based frequency fRCEXT can be chosen. For FIN = "11", sampling frequency is about 8 kHz. Additional information on oscillators and their control can be found in the clock block documentation. FIN[1:0] 00 01 10 11 Sampling frequency Fs [Hz] 1/4 fRC 1/8 fRC 1/32 fRC 1/64 fRC Table 49. Sampling frequency settings (fRC = RC-based frequency) 12.8.3. Over-Sampling Ratio The over-sampling ratio (OSR) defines the number of integration cycles per elementary conversion. Its value is set with the word SET_OSR[2:0] in power of 2 steps (see Table 49) given by: OSR = 2 3 + SET_OSR[2 : 0] (Eq. 13) SET_OSR[2:0] (RegACCfg[4:2]) 000 001 Over-Sampling Ratio OSR [-] 8 16 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 63 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING SET_OSR[2:0] (RegACCfg[4:2]) 010 011 100 101 110 111 Over-Sampling Ratio OSR [-] 32 64 128 256 512 1024 DATASHEET Table 50. Over-sampling ratio settings 12.8.4. Elementary Conversions As mentioned previously, the whole conversion sequence is made of a set of NELCONV elementary incremental conversions. This number is set with the word SET_NELC[1:0] in power of 2 steps (see Table 50) given by: SET_NELC[1 : 0] N ELCONV = 2 (Eq. 14) SET_OSR[2:0] (RegACCfg[4:2]) 00 01 10 11 # of Elementary Conversion NELCONV [-] 1 2 4 8 Table 51. Number of elementary conversion As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier offsets. 12.8.5. Resolution The theoretical resolution of the ADC, without considering thermal noise, is given by: n = 2 log 2 (OSR) + log 2 ( N ELCONV ) (Eq. 15) [ bits ] ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 64 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 17 15 Resolution - n [Bits] 13 11 9 7 5 000 001 010 011 100 101 110 111 SET_NELC= 11 10 01 00 SET_OSR Figure 34. Resolution vs. SET_OSR[2:0] and SET_NELC[2:0] SET_OSR [2:0] 00 000 001 010 011 100 101 110 111 6 8 10 12 14 16 16 16 01 7 9 11 13 15 16 16 16 SET_NELC 10 8 10 12 14 16 16 16 16 11 9 11 13 15 16 16 16 16 (shaded area: resolution truncated to 16 bits due to output register size CxDataOutMSB + CxDataOutLSB [15:0]) Table 52. Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] settings Using look-up Table 52, resolution can be set between 6 and 16 bits. Notice that, because of 16-bit register use for the ADC output, practical resolution is limited to 16 bits, i.e. n = 16. Even if the resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and NELCONV to higher values in order to reduce the influence of the thermal noise in the PGA . 12.8.6. Conversion Time & Throughput As explained using Figure 3, conversion time is given by: TCONV = ( N ELCONV (OSR + 1) + 1) / f S (Eq. 16) [s] ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 65 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET and throughput is then simply 1/TCONV. For example, consider an over-sampling ratio of 256, 2 elementary conversions, and a sampling frequency of 300 kHz (SET_OSR = "101", SET_NELC = "01", fRC = 1.2MHz, and FIN = "00"). In this case, using Table 53, the conversion time is 515 sampling periods, or 1.71ms. This corresponds to a throughput of 582Hz in continuoustime mode. The plot of figure below illustrates the classic trade-off between resolution and conversion time. SET_OSR [2:0] 00 000 001 010 011 100 101 110 111 10 18 34 66 130 258 514 1026 01 19 35 67 SET_NELC 10 37 69 133 261 517 1029 2053 4101 11 73 137 265 521 1033 2057 4105 8201 131 259 515 1027 2051 Table 53. Normalized conversion time (TCONV x fS) vs. SET_OSR[2:0] and SET_NELC[1:0] (normalized to sampling period 1/fS) 16.0 Resolution - n [Bits] 14.0 12.0 10.0 8.0 6.0 4.0 10.0 100.0 1000.0 10000.0 10 00 01 11 SET_NELC Normalized Conversion Time - TCONV*fS [-] Table 54. Resolution vs. normalized conversion time for different SET_NELC[1:0] ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 66 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 12.8.7. Output Code Format DATASHEET The ADC output code is a 16-bit word in two's complement format (see Table 55). For input voltages outside the range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller than 16 bits, the nonsignificant bits are forced to the values shown in Table 56. The output code, expressed in LSBs, corresponds to: OUTADC = 216 VIN , ADC OSR + 1 VREF OSR [ LSB ] (Eq. 17) Recalling equation Eq. 9, this can be rewritten as: OUTADC = 216 VIN VREF V GDTOT - GDoffTOT REF VIN (Eq. 18) OSR + 1 OSR [ LSB ] where, from Eq. 10 and Eq. 11, the total PGA gain and offset are respectively: GDTOT = GD3 GD2 GD1 and: [V V] GDoffTOT = GDoff 3 + GD3 GDoff 2 [V V] ADC Input Voltage VIN,ADC +2.49505 V +2.49497 V ... +76.145 V 0 -76.145 V ... % of Full Scale (FS) +0.5 x FS ... ... ... 0 ... ... Output in LSBs +215-1 = 32'767 +215-2 = 32'767 ... +1 0 -1 ... Output Code in Hex 7FFF 7FFE ... 0001 0000 8FFF ... ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 67 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING ADC Input Voltage VIN,ADC +2.49505 V +2.49513 V % of Full Scale (FS) ... -0.5 x FS Output in LSBs -215-1 = -32'767 -215 = -32'768 DATASHEET Output Code in Hex 8001 8000 Table 55. Basic ADC Relationships (example for: VREF = 5V, OSR = 512, n = 16 bits) SET_OSR[2:0] 000 001 010 011 100 101 110 111 SET_NELC = 00 1000000000 10000000 100000 1000 10 - SET_NELC = 01 100000000 1000000 10000 100 1 - SET_NELC = 10 10000000 100000 1000 10 - SET_NELC = 11 1000000 10000 100 1 - Table 56. Last forced LSBs in conversion output registers for resolution settings smaller than 16 bits (n < 16) (CxDataOutMsb[7:0] & CxDataOutLsb[7:0]) The equivalent LSB size at the input of the PGA chain is: LSB = 1 VREF OSR n 2 GDTOT OSR + 1 (Eq. 19) [V] Notice that the input voltage VIN,ADC of the ADC must satisfy the condition: VIN , ADC 1 OSR (VREFP - VREFN ) 2 OSR + 1 (Eq. 20) [V V] ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 68 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING to remain within the ADC input range. IB_AMP_ADC [1:0] 00 01 10 11 00 01 10 11 IB_AMP_PGA [1:0] ADC Bias Current 1/4 x IADC 1/2 x IADC 3/4 x IADC IADC 1/4 x IADC 1/2 x IADC 3/4 x IADC IADC PGA Bias Current Max. fS [KHz] 37.5 75 150 300 37.5 75 150 300 DATASHEET Table 57. ADC & PGA power saving modes and maximum sampling frequency 12.9. Power Saving Modes During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0] (see Table 57). If the system is idle, the PGAs and ADC can even be disabled, thus, reducing power consumption to its minimum. This can considerably improve battery lifetime. 12.10. Input impedance The PGAs of the ZoomingADC are a switched capacitor based blocks (see Switched Capacitor Principle chapter). This means that it does not use resistors to fix gains, but capacitors and switches. This has important implications on the nature of the input impedance of the block. Using switched capacitors is the reason why, while a conversion is done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency fs and to stage gain as given in Equation 21. Z in 768 109 Hz f s gain (Eq. 21) [ Ohm ] The input impedance observed is the input impedance of the first PGA stage that is enabled or the input impedance of the ADC if all three stages are disabled. PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input impedance of 256 kOhm at fs = 300 kHz. Larger input impedance can be obtained by reducing the gain and/or by reducing the sampling frequency. Therefore, with a gain of 1 and a sampling frequency of 75 kHz, Zin > 10.2 MOhm. The input impedance on channels that are not selected is very high (>100MOhm). ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 69 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 12.11. Switched Capacitor Principle DATASHEET Basically, a switched capacitor is a way to emulate a resistor by using a capacitor. The capacitors are much easier to realize on CMOS technologies and they show a very good matching precision. V1 R V2 V1 f f V2 Figure 35. The Switched Capacitor Principle A resistor is characterized by the current that flows through it (positive current leaves node V1): I= V1 - V2 R [A] (Eq. 22) One can verify that the mean current leaving node V1 with a capacitor switched at frequency f is: I = (V 1 - V 2 ) f C (Eq. 23) [A] Therefore as a mean value, the switched capacitor 1/ (f x C) is equivalent to a resistor. It is important to consider that this is only a mean value. If the current is not integrated (low impedance source), the impedance is infinite during the whole time but the transition. What does it mean for the ZoomingADC? If the fs clock is reduced, the mean impedance is increased. By dividing the fs clock by a factor 10, the impedance is increased by a factor 10. One can reduce the capacitor that is switched by using an amplifier set to its minimal gain. In particular if PGA1 is used with gain 1, its mean impedance is 10x bigger than when it is used with gain 10. Sensor impedence Sensor Current integration V1 ZoomingADC (model) f f V2 C Node Capacitance Figure 36. The Switched Capacitor Principle One can increase the effective impedance by increasing the electrical bandwidth of the sensor node so that the switching current is absorbed through the sensor before the switching period is over. Measuring the sensor node will show short voltage spikes at the frequency fs, but these will not influence the measurement. Whereas if the bandwidth of the node is ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 70 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET lower, no spikes will arise, but a small offset can be generated by the integration of the charges generated by the switched capacitors, this corresponds to the mean impedance effect. Note: One can increase the mean input impedance of the ZoomingADC by lowering the acquisition clock fs. One can increase the mean input impedance of the ZoomingADC by decreasing the gain of the first enabled amplifier. One can increase the effective input impedance of the ZoomingADC by having a source with a high electrical bandwidth (sensor electrical bandwidth much higher than fs). 12.12. PGA Settling or Input Channel Modifications PGAs are reset after each writing operation to registers CxZadcReg1-5. Similarly, input channels are switched after modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA or inputs common-mode stabilization delay. This is done by writing bit START several cycles after PGA settings modification or channel switching. Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without the PGAs. If the ADC is not settled within the specified period, there is most probably an input impedance problem (see previous section). 12.13. PGA Gain & Offset, Linearity and Noise Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC : 1. Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but degrades noise performance. 2. Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset. Bypass unnecessary PGAs. 3. Put most gain on PGA3 and use PGA2 and PGA1 only if necessary. 4. PGA3 should be always ON for best linearity. 5. For low-noise applications where power consumption is not a primary concern, maintain the largest bias currents in the PGAs and in the ADC; i.e. set IB_AMP_PGA[1:0] = IB_AMP_ADC[1:0] = '11'. 6. For lowest output offset error at the output of the ADC, bypass PGA2 and PGA3. Indeed, PGA2 and PGA3 typically introduce an offset of about 5 to 10 LSB (16 bit) at their output. Note, however, that the ADC output offset is easily calibrated out by software. 12.14. Power Reduction The ZoomingADC is particularly well suited for low-power applications. When very low power consumption is of primary concern, such as in battery operated systems, several parameters can be used to reduce power consumption as follows: 1. Operate the acquisition chain with a reduced supply voltage VBATT. 2. Disable the PGAs which are not used during analog-to-digital conversion with ENABLE[3:0]. 3. Disable all PGAs and the ADC when the system is idle and no conversion is performed. 4. Use lower bias currents in the PGAs and the ADC using the control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0]. 5. Reduce sampling frequency. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 71 www.semtech.com [V ] 2 SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed. 12.15. Noise Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions for a constant input voltage was performed to derive the equivalent noise levels of PGA1, PGA2, and PGA3. The extracted rms output noise of PGA1, 2, and 3 are given in Table 58: standard output deviation and output rms noise voltage. Figure 37 shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed). Quantization noise is dominant in this case, and, thus, the ADC thermal noise is below 16 bits. The simple noise model of Figure 38 is used to estimate the equivalent input referred rms noise VN,IN of the acquisition chain in the model of Figure 39. This is given by the relationship: VN , IN 2 VN 1 VN 2 VN 3 GD + GD GD + GD GD GD 1 1 2 1 2 3 = (OSR N ELCONV ) (Eq. 24) 2 2 2 [V 2 rms ] where VN1, VN2, and VN3 are the output rms noise figures of Table 58, GD1, GD2, and GD3 are the PGA gains of stages 1 to 3 respectively. As shown in this equation, noise can be reduced by increasing OSR and NELCONV (increases the ADC averaging effect, but reduces noise). Parameter Standard deviation at ADC output (LSB) Output RMS noise(uV) PGA1 0.85 205 x (VN1) PGA2 1.4 340 x (VN2) PGA3 1.5 365 x (VN3) Table 58. PGA Noise Measurements (n = 16 bits, OSR = 512, NELCONV = 2, VREF = 5 V) 80 Occurences [% of total samples] 60 40 20 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 Output Code Deviation From Mean Value [LSB] Figure 37. ADC Noise (PGA1, 2 & 3 Bypassed, OSR = 512, NELCONV = 2) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 72 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET PGA1 VN1 GD1 PGA2 VN2 GD2 PGA3 VN3 GD3 fs ADC Figure 38. Simple Noise Model for PGAs and ADC PGA1 VN,IN GD1 VN1 GD2 PGA2 VN2 GD3 PGA3 VN3 ADC fs Figure 39. Total Input Referred Noise As an example, consider the system where: GD2 = 10 (GD1 = 1; PGA3 bypassed), OSR = 512, NELCONV = 2, VREF = 5 V. In this case, the noise contribution VN1 of PGA1 is dominant over that of PGA2. Using Equation 24, we get: VN,IN = 6.4 V (rms) at the input of the acquisition chain, or, equivalently, 0.85 LSB at the output of the ADC. Considering 0.2 V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB. Noise can also be reduced by the additional average filters implemented in the Measurement Engine. These filters are described in section 11.4 Filtering. By making an average on a number of subsequent measurements, the apparent noise is reduced the square root of the number of measurement used to make the average. 12.16. Gain Error and Offset Error Gain error is defined as the amount of deviation between the ideal transfer function (theoretical Equation 18) and the measured transfer function (with the offset error removed). The actual gain of the different stages can vary depending on the fabrication tolerances of the different elements. Although these tolerances are specified to a maximum of +/-3%, they will be most of the time around 0.5%. Moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error in the same direction in all stages is very low. Finally, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance. Figure 40 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of Full-Scale Range (FSR) normalized to 25C. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 73 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC and the PGA1 stage are completely suppressed if NELCONV > 1. The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 41. The output offset error, expressed in LSB for 16-bit setting, is normalized to 25C. Notice that if the ADC is used alone, the output offset error is below +/-1 LSB and has no drift. Output Offset Error [LSB] 0.2 100 80 60 40 20 0 -20 -40 Gain Error [% of FSR] 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100 1 5 20 100 1 5 20 100 -50 -25 0 25 50 75 100 Temperature [C] Temperature [C] Figure 40. Gain Error vs. Temperature for Different PGA Gains Figure 41. Offset Error vs. Temperature for Different PGA Gains ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 74 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 13. Typical performances 13.1. Current consumption SX8722 mean current consumption in active mode is around 200 [A], without enabled PGA. The value of the gain of de PGA can have a negligible influence on consumption in active mode. Additional consumption depends on the active PGA and on the bias current parameter. Current for each amplifier in [uA] IPGA1 bias 25 % bias 50 % bias 75 % bias 100 % 50 95 140 185 IPGA2 40 75 110 145 IPGA3 50 98 145 190 Table 59. PGA current consumption Example 1 : Bias current 25% PGA1: enabled PGA2: enabled PGA3: enabled SX8722 measured current consumption: ~330 A Example 2 : Bias current 100% PGA1: enabled PGA2: enabled PGA3: enabled SX8722 measured current consumption: ~710 A ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 75 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 13.2. ZoomingADC 13.2.1. Integral non-linearity ADC without PGA -40C 25C DATASHEET 85C PGA1 off; PGA2 off; PGA3 off; set_osr = 7, set_nelconv = 3, Vbat=5V, Vref=5V, Vcommon=0V PGA1 off; PGA2 off; PGA3 off; set_osr = 7; set_nelconv = 3; Vbat = 5V; Vref = 5V; Vcommon = 0V PGA1 off; PGA2 off; PGA3 off; set_osr = 7, set_nelconv = 3, Vbat=5V, Vref=5V, Vcommon=0V 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 500 1000 1500 Vin [mV] 2000 2500 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 500 1000 1500 Vin [mV] 2000 2500 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 500 1000 1500 Vin [mV] 2000 2500 INL[LSB] INL[LSB] Gain 1 -40C 25C 85C PGA1 off; PGA2 off; PGA3 = 1; set_osr = 7; set_nelconv = 3, Vbat = 5V; Vref = 5V; Vcommon = 0V PGA1 off; PGA2 off; PGA3 = 1; set_osr = 7; set_nelconv = 3, VBAT = 5V; Vref = 5V; Vcommon = 0V 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 500 1000 1500 Vin [mV] 2000 2500 10 8 6 INL[LSB] INL[LSB] 0 500 1000 1500 Vin [mV] 2000 2500 4 2 0 -2 -4 -6 -8 -10 INL[LSB] PGA1 off; PGA2 off; PGA3 = 1; set_osr = 7; set_nelconv = 3, Vbat = 5V; Vref = 5V; Vcommon = 0V 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 500 1000 1500 Vin [mV] 2000 2500 INL[LSB] Gain 10 -40C 25C 85C PGA1 off; PGA2 off; PGA3 = 10; set_osr = 7; set_nelconv = 3; VBAT = 5V; Vref = 5V; Vcommon = 0V PGA1 off; PGA2 off; PGA3 = 10; set_osr = 7; set_nelconv = 3; Vbat = 5V; Vref = 5V; Vcommon = 0V PGA1 off; PGA2 off; PGA3 = 10; set_osr = 7; set_nelconv = 3; VBAT = 5V; Vref = 5V; Vcommon = 0V 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 50 100 Vin [mV] 150 200 250 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 50 100 Vin [mV] 150 200 250 10 8 6 4 INL[LSB] 2 0 -2 -4 -6 -8 -10 0 50 100 Vin [mV] 150 200 250 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 INL[LSB] INL[LSB] Page 76 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Gain 100 -40C 25C 85C PGA1 off; PGA2 = 10; PGA3 = 10; set_osr = 7; set_nelconv = 3; Vbat = 5V; Vref = 5V; Vcommon = 0V PGA1 off; PGA2 = 10; PGA3 = 10; set_osr = 7; set_nelconv = 3; VBAT = 5V; Vref = 5V; Vcommon = 0V PGA1 = 10; PGA2 off; PGA3 = 10; set_osr = 7; set_nelconv = 3; Vbat=5V; Vref = 5V; Vcommon = 0V 10 8 6 4 INL[LSB] INL[LSB] 2 0 -2 -4 -6 -8 -10 0 5 10 Vin [mV] 15 20 25 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 5 10 Vin [mV] 15 20 25 INL[LSB] 10 8 6 4 2 0 -2 -4 -6 -8 -10 0 5 10 Vin [mV] 15 20 25 Figure 42. INL over temperature for different gains 13.2.2. Differential non-linearity DNL: significantly lower than one LSB Figure 43. ADC differential non-linearity ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 77 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 13.2.3. Resolution vs acquisition time resolution vs acquisition time 18 16 14 12 10 8 6 4 2 0 10 100 1000 time [us] 10000 100000 DATASHEET resolution [bits] Figure 44. ADC resolution vs Acquisition time ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 78 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 14. Register Memory Map and Description 14.1. Memory Map The table below describes the register/memory map that can be accessed through the I2C interface. It indicates the register name, register address and the register contents. Adress Register Bit SX8722 General Configuration Description 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 SXCtrl1 SXCtrl2 SXCfgEn SXUpdated SXRcFrequ1 SXRcFrequ2 SXTest SXAI1 SXAI2 SXReserved1 8 8 8 8 8 8 8 8 8 8 Configuration register of the SX8722 Configuration register of the SX8722 Configuration enable register,enables configurations from 1 to 4 Updated value on configuration registers Fine RC adjustment register Coarse RC adjustment register Test purpose register puts SX8722 in remote mode Reserved Reserved Reserved Configuration 1 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 C1ZAdcReg1 C1ZAdcReg2 C1ZAdcReg3 C1ZAdcReg4 C1ZAdcReg5 C1ZAdcReg6 C1SXCfg C1FParam C1Alrm1OnMsb C1Alrm1OnLsb C1Alrm1OffMsb C1Alrm1OffLsb C1Alrm2OnMsb C1Alrm2OnLsb 8 8 8 8 8 8 8 8 16 ZoomingADC Register 01 ZoomingADC Register 02 ZoomingADC Register 03 ZoomingADC Register 04 ZoomingADC Register 05 ZoomingADC Register 06 SX configurations related to this set Filter size Alarm 1 "ON" threshold 16 Alarm 1 "OFF" threshold 16 Alarm 2 "ON" threshold ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 79 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Adress 0x18 0x19 0x1A 0x1B Register C1Alrm2OffMsb C1Alrm2OffLsb C1DataOutLsb C1DataOutMsb Configuration 2 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B C2ZAdcReg1 C2ZAdcReg2 C2ZAdcReg3 C2ZAdcReg4 C2ZAdcReg5 C2ZAdcReg6 C2SXCfg C2FParam C2Alrm1OnMsb C2Alrm1OnLsb C2Alrm1OffMsb C2Alrm1OffLsb C2Alrm2OnMsb C2Alrm2OnLsb C2Alrm2OffMsb C2Alrm2OffLsb C2DataOutMsb C2DataOutLsb Configuration 3 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 C3ZAdcReg1 C3ZAdcReg2 C3ZAdcReg3 C3ZAdcReg4 C3ZAdcReg5 C3ZAdcReg6 C3SXCfg C3FParam 8 8 8 8 8 8 8 8 ZoomingADC Register 01 ZoomingADC Register 02 ZoomingADC Register 03 ZoomingADC Register 04 ZoomingADC Register 05 ZoomingADC Register 06 SX configurations related to this set Filter size 16 Configuration 2 data out 16 Alarm 2 "OFF" threshold 16 Alarm 2 "ON" threshold 16 Alarm 1 "OFF" threshold 8 8 8 8 8 8 8 8 16 ZoomingADC Register 01 ZoomingADC Register 02 ZoomingADC Register 03 ZoomingADC Register 04 ZoomingADC Register 05 ZoomingADC Register 06 SX configurations related to this set Filter size Alarm 1 "ON" threshold 16 Configuration 1 data out Bit 16 Alarm 2 "OFF" threshold Description DATASHEET ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 80 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Adress 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B Register C3Alrm1OnMsb C3Alrm1OnLsb C3Alrm1OffMsb C3Alrm1OffLsb C3Alrm2OnMsb C3Alrm2OnLsb C3Alrm2OffMsb C3Alrm2OffLsb C3DataOutMsb C3DataOutLsb Configuration 4 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B C4ZAdcReg1 C4ZAdcReg2 C4ZAdcReg3 C4ZAdcReg4 C4ZAdcReg5 C4ZAdcReg6 C4SXCfg C4FParam C4Alrm1OnMsb C4Alrm1OnLsb C4Alrm1OffMsb C4Alrm1OffLsb C4Alrm2OnMsb C4Alrm2OnLsb C4Alrm2OffMsb C4Alrm2OffLsb C4DataOutMsb C4DataOutLsb 16 Configuration 4 data out 16 Alarm 2 "OFF" threshold 16 Alarm 2 "ON" threshold 16 Alarm 1 "OFF" threshold 8 8 8 8 8 8 8 8 16 ZoomingADC Register 01 ZoomingADC Register 02 ZoomingADC Register 03 ZoomingADC Register 04 ZoomingADC Register 05 ZoomingADC Register 06 SX configurations related to this set Filter size Alarm 1 "ON" threshold 16 Configuration 3 data out 16 Alarm 2 "OFF" threshold 16 Alarm 2 "ON" threshold 16 Alarm 1 "OFF" threshold Bit 16 Alarm 1 "ON" threshold Description DATASHEET ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 81 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 14.2. Register description DATASHEET The register descriptions are presented here in ascending order of Register Address. Some registers carry several individual data fields of various sizes; from single-bit values (e.g. flags), upwards. Some data fields are spread across multiple registers. Unused bits are 'don't care' and writing either 0 or 1 will not affect any function of the device. After power on reset the registers will have the values indicated in the tables "Reset" column. 14.2.1. SX8722 general configuration Bit 7 6 5 4 3 2 1 0 EE_D XTAL_D CKOUT RESERVED EE SLEEP SHUT CAL Bit Name r r rw rw r rw rw r Mode Reset x x 0 0 0 0 0 0 Is set to 1 when SX8722 loaded its configuration from the EEPROM at startup. When set to 1 his bit activates the Sleep mode of the SX8722. Setting pin SLEEP to 1 has the same effect. When set to 1 his bit activates the Shutdown mode of the SX8722. Setting pin SHUT to 1 has the same effect. This flag shows if the SX8722 clock has been successfully calibrated. Description Indicates if an EEPROM was detected at startup Indicates if an XTAL was detected at startup Enabled the clock output on CKOUT pin Table 60. SXCtrl1 (0x00) Bit 7:4 3 2 1 0 reserved AL1OnC AL1OffC AL2OnC AL2OffC Bit name r rw rw rw rw Mode Reset x 0 0 0 0 Description Sets the logical condition for alarm 1 on (0 = OR, 1 = AND) Sets the logical condition for alarm 1 off (0 = OR, 1 = AND) Sets the logical condition for alarm 2 on (0 = OR, 1 = AND) Sets the logical condition for alarm 2 off (0 = OR, 1 = AND) Table 61. SXCtrl2 (0x01) Bit 7:4 3 2 1 reserved CONF4 CONF3 CONF2 Name r rw rw rw Mode Reset x 0 0 0 Configuration 4 enabling Configuration 3 enabling Configuration 2 enabling Description ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 82 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Bit 0 CONF1 Name Mode rw Reset 0 Configuration 1 enabling Description DATASHEET Table 62. SXCfgEn (0x02) Bit 7 6 5 4 3 2 1 0 OVF4 OVF3 OVF2 OVF1 UCONF4 UCONF3 UCONF2 UCONF1 Name Mode r r r r r r r r Reset 0 0 0 0 0 0 0 0 Overflow on configuration 4 Overflow on configuration 3 Overflow on configuration 2 Overflow on configuration 1 Description Indicates that configuration 4 has been updated by a measurement result. Indicates that configuration 3 has been updated by a measurement result. Indicates that configuration 2 has been updated by a measurement result. Indicates that configuration 1 has been updated by a measurement result. Table 63. SXUpdated (0x03) Bit 7:0 Fine RC Name Mode rw Reset x Description Fine RC adjustment. Set by the calibration procedure. Table 64. SXRcFrequ1 (0x04) Bit 7:0 Name Coarse RC Mode rw Reset x Description Coarse RC adjustment. Set by the calibration procedure. Table 65. SXRcFrequ2 (0x05) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 83 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 14.2.2. Configuration 1 registers Bit 7 6:5 reserved SET_NELC Name Mode r rw Reset x 01 Description DATASHEET Sets the number of elementary conversion to 2SET_NELC[1:0]. To compensate for offset the signal is chopped between elementary conversion. Sets the ADC over-sampling rate of an elementary conversion to 23+SET_OSR[2:0]. 4:2 SET_OSR rw 010 1 0 reserved reserved r r x x Table 66. C1ZAdcReg1 (0x0A) Bit 7:6 5:4 3:0 Name IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] rw rw rw Mode Reset 11 11 0000 Description Bias current selection of the A/D converter. Bias current selection of the PGA stages. Enables the different PGA stages and ADC. XXX1 - ADC enable XX1X - PGA3 enable X1XX - PGA2 enable 1XXX - PGA1 enable Table 67. C1ZAdcReg2 (0x0B) Bit 7:6 5:4 3:0 FIN[1:0] Name rw rw rw Mode Reset 00 00 0000 Description Sampling frequency selection PGA2 stage gain selection PGA2 stage offset selection PGA2_GAIN[1:0] PGA2_OFFSET[3:0] Table 68. C1ZAdcReg3 (0x0C) Bit 7 6:0 Name PGA1_GAIN PGA3_GAIN[6:0] rw rw Mode Reset 0 0000000 PGA1 stage gain selection PGA3 stage gain selection Description Table 69. C1ZAdcReg4 (0x0D) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 84 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7 6:0 reserved Name r rw Mode Reset 0 0000000 Unused PGA3 stage offset selection Description PGA3_OFFSET[6:0] Table 70. C1ZAdcReg5 (0x0E) Bit 7 6 5:1 0 reserved reserved AMUX[4:0] VMUX Name r r rw rw Mode Reset Description 00000 0 Input channel configuration selector Reference channel selector Table 71. C1ZAdcReg6 (0x0F) Bit 7 6:4 reserved Name r r Mode Reset Description FILTER TYPE [2:0] Filter selection selection 000 - none 001 - average filtering 010 - moving average filtering 011 - reserved 3 2 1 0 ALRM1 ALRM2 SINGLE CONT rw rw rw rw Alarm 1 enable Alarm 2 enable Configuration 1 in single acquisition mode Configuration 1 in continuous acquisition mode Table 72. C1SXCfg (0x10) Bit 7:0 SIZE Name Mode rw Reset Description 00000000 Filter size. Limited to 10 for a moving average filter. Table 73. C1FParam (0x11) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 85 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 1 Table 74. C1Alrm1OnMsb (0x12) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 1 Table 75. C1Alrm1OnLsb (0x13) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 1 Table 76. C1Alrm1OffMsb (0x14) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 1 Table 77. C1Alrm1OffLsb (0x15) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 1 Table 78. C1Alrm1OnMsb (0x16) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 1 Table 79. C1Alrm1OnLsb (0x17) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 1 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 86 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING Table 80 C1Alrm1OffMsb (0x18) DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 1 Table 81. C1Alrm1OffLsb (0x19) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 1 data out MSB Table 82. C1DataOutMsb (0x1A) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 1 data out LSB Table 83. C1DataOutLsb (0x1B) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 87 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 14.2.3. Configuration 2 registers Bit 7 6:5 reserved SET_NELC Name Mode r rw Reset x 01 Description DATASHEET Sets the number of elementary conversion to 2SET_NELC[1:0]. To compensate for offset the signal is chopped between elementary conversion. Sets the ADC over-sampling rate of an elementary conversion to 23+SET_OSR[2:0]. 4:2 SET_OSR rw 010 1 0 reserved reserved r r x x Table 84. C2ZAdcReg1 (0x2A) Bit 7:6 5:4 3:0 Name IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] rw rw rw Mode Reset 11 11 0000 Description Bias current selection of the A/D converter. Bias current selection of the PGA stages. Enables the different PGA stages and ADC. XXX1 - ADC enable XX1X - PGA3 enable X1XX - PGA2 enable 1XXX - PGA1 enable Table 85. C2ZAdcReg2 (0x2B) Bit 7:6 5:4 3:0 FIN[1:0] Name rw rw rw Mode Reset 00 00 0000 Description Sampling frequency selection PGA2 stage gain selection PGA2 stage offset selection PGA2_GAIN[1:0] PGA2_OFFSET[3:0] Table 86. C2ZAdcReg3 (0x2C) Bit 7 6:0 Name PGA1_GAIN PGA3_GAIN[6:0] rw rw Mode Reset 0 0000000 PGA1 stage gain selection PGA3 stage gain selection Description Table 87. C2ZAdcReg4 (0x2D) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 88 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7 6:0 reserved Name r rw Mode Reset 0 0000000 Unused PGA3 stage offset selection Description PGA3_OFFSET[6:0] Table 88. C2ZAdcReg5 (0x2E) Bit 7 6 5:1 0 reserved reserved AMUX[4:0] VMUX Name r r rw rw Mode Reset Description 00000 0 Input channel configuration selector Reference channel selector Table 89. C2ZAdcReg6 (0x2F) Bit 7 6:4 reserved Name r r Mode Reset Description FILTER TYPE [2:0] Filter selection selection 000 - none 001 - average filtering 010 - moving average filtering 011 - reserved 3 2 1 0 ALRM1 ALRM2 SINGLE CONT rw rw rw rw Alarm 1 enable Alarm 2 enable Configuration 1 in single acquisition mode Configuration 1 in continuous acquisition mode Table 90. C2SXCfg (0x30) Bit 7:0 SIZE Name Mode rw Reset Description 00000000 Filter size. Limited to 10 for a moving average filter. Table 91. C2FParam (0x31) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 89 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 2 Table 92. C2Alrm1OnMsb (0x32) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 2 Table 93. C2Alrm1OnLsb (0x33) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 2 Table 94 C2Alrm1OffMsb (0x34) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 2 Table 95. C2Alrm1OffLsb (0x35) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 2 Table 96. C2Alrm1OnMsb (0x36) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 2 Table 97. C2Alrm1OnLsb (0x37) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 90 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 2 Table 98 C2Alrm1OffMsb (0x38) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 2 Table 99. C2Alrm1OffLsb (0x39) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 2 data out MSB Table 100. C2DataOutMsb (0x3A) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 2 data out LSB Table 101. C2DataOutLsb (0x3B) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 91 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 14.2.4. Configuration 3 registers Bit 7 6:5 reserved SET_NELC Name Mode r rw Reset x 01 Description DATASHEET Sets the number of elementary conversion to 2SET_NELC[1:0]. To compensate for offset the signal is chopped between elementary conversion. Sets the ADC over-sampling rate of an elementary conversion to 23+SET_OSR[2:0]. 4:2 SET_OSR rw 010 1 0 reserved reserved r r x x Table 102. C3ZAdcReg1 (0x4A) Bit 7:6 5:4 3:0 Name IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] rw rw rw Mode Reset 11 11 0000 Description Bias current selection of the A/D converter. Bias current selection of the PGA stages. Enables the different PGA stages and ADC. XXX1 - ADC enable XX1X - PGA3 enable X1XX - PGA2 enable 1XXX - PGA1 enable Table 103. C3ZAdcReg2 (0x4B) Bit 7:6 5:4 3:0 FIN[1:0] Name rw rw rw Mode Reset 00 00 0000 Description Sampling frequency selection PGA2 stage gain selection PGA2 stage offset selection PGA2_GAIN[1:0] PGA2_OFFSET[3:0] Table 104. C3ZAdcReg3 (0x4C) Bit 7 6:0 Name PGA1_GAIN PGA3_GAIN[6:0] rw rw Mode Reset 0 0000000 PGA1 stage gain selection PGA3 stage gain selection Description Table 105. C3ZAdcReg4 (0x4D) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 92 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7 6:0 reserved Name r rw Mode Reset 0 0000000 Unused PGA3 stage offset selection Description PGA3_OFFSET[6:0] Table 106. C3ZAdcReg5 (0x4E) Bit 7 6 5:1 0 reserved reserved AMUX[4:0] VMUX Name r r rw rw Mode Reset Description 00000 0 Input channel configuration selector Reference channel selector Table 107. C3ZAdcReg6 (0x4F) Bit 7 6:4 reserved Name r r Mode Reset Description FILTER TYPE [2:0] Filter selection selection 000 - none 001 - average filtering 010 - moving average filtering 011 - reserved 3 2 1 0 ALRM1 ALRM2 SINGLE CONT rw rw rw rw Alarm 1 enable Alarm 2 enable Configuration 3 in single acquisition mode Configuration 3 in continuous acquisition mode Table 108. C3SXCfg (0x50) Bit 7:0 SIZE Name Mode rw Reset Description 00000000 Filter size. Limited to 10 for a moving average filter. Table 109. C3FParam (0x51) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 93 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 3 Table 110. C3Alrm1OnMsb (0x52) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 3 Table 111. C3Alrm1OnLsb (0x53) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 3 Table 112 C3Alrm1OffMsb (0x54) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 3 Table 113. C3Alrm1OffLsb (0x55) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 3 Table 114. C3Alrm1OnMsb (0x56) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 3 Table 115. C3Alrm1OnLsb (0x57) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 94 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 3 Table 116 C3Alrm1OffMsb (0x58) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 3 Table 117. C3Alrm1OffLsb (0x59) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 3 data out MSB Table 118. C3DataOutMsb (0x5A) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 3 data out LSB Table 119. C3DataOutLsb (0x5B) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 95 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 14.2.5. Configuration 4 registers Bit 7 6:5 reserved SET_NELC Name Mode r rw Reset x 01 Description DATASHEET Sets the number of elementary conversion to 2SET_NELC[1:0]. To compensate for offset the signal is chopped between elementary conversion. Sets the ADC over-sampling rate of an elementary conversion to 23+SET_OSR[2:0]. 4:2 SET_OSR rw 010 1 0 reserved reserved r r x x Table 120. C4ZAdcReg1 (0x6A) Bit 7:6 5:4 3:0 Name IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] rw rw rw Mode Reset 11 11 0000 Description Bias current selection of the A/D converter. Bias current selection of the PGA stages. Enables the different PGA stages and ADC. XXX1 - ADC enable XX1X - PGA3 enable X1XX - PGA2 enable 1XXX - PGA1 enable Table 121. C4ZAdcReg2 (0x6B) Bit 7:6 5:4 3:0 FIN[1:0] Name rw rw rw Mode Reset 00 00 0000 Description Sampling frequency selection PGA2 stage gain selection PGA2 stage offset selection PGA2_GAIN[1:0] PGA2_OFFSET[3:0] Table 122. C4ZAdcReg3 (0x6C) Bit 7 6:0 Name PGA1_GAIN PGA3_GAIN[6:0] rw rw Mode Reset 0 0000000 PGA1 stage gain selection PGA3 stage gain selection Description Table 123. C4ZAdcReg4 (0x6D) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 96 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7 6:0 reserved Name r rw Mode Reset 0 0000000 Unused PGA3 stage offset selection Description PGA3_OFFSET[6:0] Table 124. C4ZAdcReg5 (0x6E) Bit 7 6 5:1 0 reserved reserved AMUX[4:0] VMUX Name r r rw rw Mode Reset Description 00000 0 Input channel configuration selector Reference channel selector Table 125. C4ZAdcReg6 (0x6F) Bit 7 6:4 reserved Name r r Mode Reset Description FILTER TYPE [2:0] Filter selection selection 000 - none 001 - average filtering 010 - moving average filtering 011 - reserved 3 2 1 0 ALRM1 ALRM2 SINGLE CONT rw rw rw rw Alarm 1 enable Alarm 2 enable Configuration 4 in single acquisition mode Configuration 4 in continuous acquisition mode Table 126. C4SXCfg (0x70) Bit 7:0 SIZE Name Mode rw Reset Description 00000000 Filter size. Limited to 10 for a moving average filter. Table 127. C4FParam (0x71) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 97 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 4 Table 128. C4Alrm1OnMsb (0x72) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 4 Table 129. C4Alrm1OnLsb (0x73) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold MSB for configuration 4 Table 130 C4Alrm1OffMsb (0x74) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 1 threshold LSB for configuration 4 Table 131. C4Alrm1OffLsb (0x75) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 4 Table 132. C4Alrm1OnMsb (0x76) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 4 Table 133. C4Alrm1OnLsb (0x77) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 98 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold MSB for configuration 4 Table 134 C4Alrm1OffMsb (0x78) Bit 7:0 Name Mode rw Reset Description 00000000 Alarm 2 threshold LSB for configuration 4 Table 135. C4Alrm1OffLsb (0x79) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 4 data out MSB Table 136. C4DataOutMsb (0x7A) Bit 7:0 Name Mode r Reset Description 00000000 Configuration 4 data out LSB Table 137. C4DataOutLsb (0x7B) ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 99 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 15. Power modes SX8722 has 3 operating modes: active mode sleep mode shutdown mode 15.1. Power modes transitions Start-up from shutdown: Initializes the SX8722 Load EEPROM if present Restores EEPROM configuration and set the SX8722 Start-up from sleep: Restores the RC active value Enables VLD Restores SX8722 configuration saved in RAM Sleep sequence: Waits for I2C STOP sequence Stops the ADC Disable VLD Bias current off Set the clock to RC minimum value or to Xtal if present Shutdown sequence: Waits for I2C STOP sequence Stops the ADC Disable VLD Bias current off Stops the SX8722 The timing of the transition states depends mainly on the Xtal presence, the EEPROM presence and if the transition is caused by an I2C command or by a pin signal (SLEEP, SHUT, RESET). ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 100 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING 15.2. Active mode In this chapter you will find: The description of the active mode How to set SX8722 in active mode DATASHEET 15.2.1. Description In active mode, SX8722 and all its peripherals can work and execute the measurement engine. The acquisition chain, the alarms and the signal post processing can be activated and parameterized. 15.2.2. How to set SX8722 in active mode Start-up At start-up SX8722 is automatically set in active mode. If there is no EEPROM configuration loaded at start-up, PGA are not active. From Sleep mode Positive pulse on RESET pin Negative pulse on the SLEEP pin SLEEP bit toggle in the SXCtrl1 register (I2C write mask command) Other interruption From Shutdown mode Positive pulse on RESET pin Power-on-reset (negative pulse on VBAT pin) 15.3. Sleep mode 15.3.1. Description The sleep mode is a low power mode. It can be called by an I2C sequence or by sending a negative pulse to SX8722 SLEEP pin. 15.3.2. Operating specifications of the sleep mode Summary SX8722 configuration saved in RAM ADC stopped VLD stopped (voltage level detector) If Xtal present, clock set to Xtal 32k If Xtal not present, clock set to RC minimum value (~80kHz) Bias current off ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 101 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET Program HALT, SX8722 needs an interrupt to wake up (I2C communication, SLEEP pin signal, reset, etc). 15.3.3. SX8722 sleep current consumption below 3V Vbat Below 3 Volts SX8722 enables the internal voltage multiplier to power the ZoomingADCTM. This internal voltage multiplier is automatically enabled when the power supply goes below 3V Vbat. This voltage multiplier increases SX8722 consumption. This is why the chip consumption in sleep mode with 2.5V supply is higher than with 5.5V supply. There is a possibility to consume less current when the Vbat voltage is lower than 3V: the SLEEP signal has to be sent to the SLEEP pin when Vbat is higher than 3V, and then decrease the Vbat value. In this case, the voltage multiplier is not activated. 15.3.4. SX8722 sleep current consumption with the 32.768 kHz Xtal The sleep mode current consumption with the presence of the 32.768 kHz Xtal is around 1A if the supply voltage is above 3V. Below 3V, the current consumption is around 4 A because the VMULT is enabled. In addition to set the precise RC frequency, the presence of an external 32.768 kHz Xtal allows SX8722 sleep current consumption 3x lower than without the Xtal. In this case SX8722 main clock is generated by the Xtal. 15.3.5. SX8722 sleep current consumption without the 32.768 KHz Xtal The current consumption in sleep mode without the 32.768 kHz Xtal is around 3 A if the supply voltage is above 3V. Below 3V, the current consumption is around 9 A because the voltage multiplier is enabled. The RC min frequency is set and its value is around 80 kHz. 15.3.6. How to set SX8722 in sleep mode I2C sleep Through the I2C interface, send a write mask command at address 00 and toggle the SLEEP bit of the SXCtrl1 register. When SX8722 is in sleep mode, send a write mask command at address 00 and toggle the SLEEP bit to restore SX8722 active mode. WARNING: The I2C SLEEP command does not allow reaching as low current consumption as the SLEEP pin command or writing the SXCtrl1 register SLEEP bit. The sleep mode called by I2C SLEEP command (0x40) has a current consumption around 80A. SLEEP pin Put the SLEEP input signal to VSS, the SLEEP input is active on negative edge. Is the SX8722 in SLEEP mode? There are pulses on the READY pin in active mode every 36ms. In sleep mode there is no pulse on the READY pin. 15.3.7. Wake up from sleep mode to active mode ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 102 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET In sleep mode the internal program is in "HALT" assembler equivalent mode. The SLEEP bit toggling in SXCtrl1 or a signal on the SLEEP pin can wake up the SX8722. See active mode section for more information. 15.4. Shutdown mode 15.4.1. Description This is a very low-power mode because all circuit clocks and all peripherals are stopped. Only some service blocks remain active. 15.4.2. Operating specifications in shutdown mode Summary ADC stopped VLD stopped If Xtal present, clock set to Xtal 32k If Xtal not present, clock set to RC minimum value (~80kHz) Bias current off Program HALT, interrupt off No possible I2C communication Internal voltage multiplier Like in sleep mode, internal voltage multiplier is automatically enabled when the power supply goes below 3 Volts but the internal voltage multiplier requires an external capacitor between VMULT pin and Vss, the value of this capacitor must be between 1 and 3nF. Shutdown mode current consumption The current consumption in shutdown mode is around 0.5 A if the supply voltage is above 3V. Below 3V, the current consumption is around 3.5 A because the voltage multiplier is enabled. How to set shutdown mode consumption around 0.5A By default, with a supply voltage below 3V the shutdown mode current is around 3.5A. To obtain 0.5A consumption, the shut command (I2C, pin) has to be received by the SX8722 when the internal voltage multiplier is not enabled. It means when the supply voltage is above 3V. Then, if the supply voltage is lowered under 3V, the SX8722 will conserve the 0.5A consumption. 15.4.3. How to set SX8722 in shutdown mode I2C Shutdown command Send the 0x50 command through the I2C interface. I2C SHUT bit toggle Through the I2C interface, send a write mask command at address 00 and toggle the SHUT bit of the SXCtrl1 register. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 103 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING SHUT pin DATASHEET Put the SHUT input signal to VSS, the SHUT input is active on negative edge. 15.4.4. Wake-up from shutdown mode to active mode There are two possible ways to wake-up from the shutdown mode: The POR (power-on-reset caused by a power-down followed by power-on). The RESET pin. In both case the RAM information is lost. SX8722 configuration must be restored from the EEPROM saved configuration. 15.4.5. Change from shutdown mode to sleep mode This is not possible. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 104 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 16. PCB Layout Considerations PCB layout considerations to be taken when using the SX8722 are relatively simple to get the highest performances out. The most important to achieve good performances is to have a good voltage reference. Separating the digital from the analog lines will be also a good choice to reduce the noise induced by the digital lines. It is also advised to have separated ground planes for digital and analog signals with the shortest return path, as well as making the power supply lines as wider as possible and to have good decoupling capacitors. 17. How to Evaluate For evaluation purposes the XE8000EV120 evaluation kit can be ordered. This kit connects to any PC using a USB port. The "SX8722 Evaluation Tools" software gives the user the ability to control the SX8722 and displaying configurations on the "Graphical User interface". For more information please look at SEMTECH web site (http://www.semtech.com). 18. Package Outline Drawing: MLPQ44-7x7mm A D B DIM A A1 A2 b D D1 E E1 e L N aaa bbb DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX - .040 .031 .000 - .002 - (.008) .007 .010 .012 .271 .275 .279 .197 .203 .207 .271 .275 .279 .197 .203 .207 .020 BSC .017 .021 .025 44 .003 .004 1.00 0.80 0.05 0.00 - (0.20) 0.18 0.25 0.30 6.90 7.00 7.10 5.00 5.15 5.25 6.90 7.00 7.10 5.00 5.15 5.25 0.50 BSC 0.45 0.55 0.65 44 0.08 0.10 PIN 1 INDICATOR (LASER MARK) E A2 A aaa C A1 SEATING PLANE C D1 LxN E/2 E1 2 1 N bxN e bbb CAB D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 105 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 19. Land Pattern Drawing: MLPQ44-7x7mm H DIMENSIONS DIM C G H K P X Y Z INCHES (.268) .228 .207 .207 .021 .011 .039 .307 MILLIMETERS (6.80) 5.80 5.25 5.25 0.50 0.30 1.00 7.80 (C) K G Z Y X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 106 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET 20. Tape and Reel Specification MLP/QFN (0.70mm - 1.00mm package thickness) Single Sprocket holes Tolerances for Ao & Bo are +/- 0.20mm Tolerances for Ko is +/- 0.10mm Tolerance for Pocket Pitch is +/- 0.10mm Tolerance for Tape width is +/-0.30mm Trailer and Leader Length are minimum required length Package Orientation and Feed Direction MLP (square) MLP (rectangular) Direction of Feed Direction of Feed Pkg size Tape Width (W) 8 12 12 12 12 16 12 16 16 24 24 carrier tape (mm) Pocket Pitch (P) 4 8 8 8 8 12 8 12 12 16 16 Ao Bo Ko Reel Size (in) 7 13 13 13 7/13 13 13 13 13 13 13 Reel Reel Width (mm) 8.4 12.4 12.4 12.4 12.4 16.4 12.4 16.4 16.4 24.4 24.4 Trailer Length (mm) 160 400 400 400 200/400 400 400 400 400 400 400 Leader Length (mm) 400 400 400 400 400 400 400 400 400 400 400 QTY per Reel 3000 3000 3000 3000 500/3000 3000 3000 3000 3000 3000 3000 2x2 3x3 4x4 4x3 5x5 6x6 6x5 7x7 9X9 10x10 11x11 2.25 3.30 4.35 3.30 5.25 6.30 5.30 7.30 9.30 10.30 11.40 2.25 3.30 4.35 4.30 5.25 6.30 6.30 7.30 9.30 10.30 11.40 1.00 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.20 ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 107 www.semtech.com SX8722 High gain acquisition for sensor interface ADVANCED COMMUNICATIONS & SENSING DATASHEET (c) Semtech 2008 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact information Semtech Corporation Advanced Communications & Sensing Products E-mail: sales@semtech.comacsupport@semtech.comInternet: http://www.semtech.com USA 200 Flynn Road, Camarillo, CA 93012-8790. Tel: +1 805 498 2111 Fax: +1 805 498 3804 12F, No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 Semtech Ltd., Units 2 & 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN. Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601 FAR EAST EUROPE ISO9001 CERTIFIED ACS - Revision 4.2 (c)2008 Semtech Corp. October 2008 Page 108 www.semtech.com |
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