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| M Features * Implements CAN V2.0B - Programmable bit rate up to 1 Mb/s - One programmable mask - Two programmable filters - Three auto-transmit buffers - Two message reception buffers - Does not require synchronization or configuration messages * Hardware Features - Non-volatile memory for user configuration - User configuration automatically loaded on power-up - Eight general-purpose I/O lines individually selectable as inputs or outputs - Individually selectable transmit-on-pinchange for each input - Four 10-bit, analog input channels with programmable conversion clock and VREF sources (MCP2505X devices only) - Message scheduling capability - Two 10-bit PWM outputs with independently programmable frequencies - Device configuration can be modified via CAN bus messages - In-Circuit Serial ProgrammingTM (ICSPTM) of default configuration memory - Optional 1-wire CAN bus operation * Low-power CMOS technology - Operates from 2.7V to 5.5V - 10 mA active current, typical - 30 A standby current (CAN Sleep mode) * 14-pin PDIP (300 mil) and SOIC (150 mil) packages * Available temperature ranges: - Industrial (I): -40C to +85C - Extended (E): -40C to +125C MCP2502X/5X CAN I/O Expander Family Description The MCP2502X/5X devices operate as I/O expanders for a Controller Area Network (CAN) system, supporting CAN V2.0B active, with bus rates up to 1 Mb/s. The MCP2502X/5X allows a simple CAN node to be implemented without the need for a microcontroller. The devices exceptions: are identical, with the following Device MCP25020 MCP25025 MCP25050 MCP25055 A/D No No Yes Yes One Wire Digital CANbus No Yes No Yes The MCP2502X/5X devices feature a number of peripherals, including digital I/Os, four-channel 10-bit A/D (MCP2505X) and PWM outputs with automatic message transmission on change-of-input state. This includes an analog input exceeding a preset threshold. One mask and two acceptance filters are provided to give maximum flexibility during system design with respect to identifiers that the device will respond to. The device can also be configured to automatically transmit a unique message whenever any of several error conditions occur. The device is pre-programmed in non-volatile memory so that the part defaults to a specific configuration at power-up. 2003 Microchip Technology Inc. DS21664C-page 1 MCP2502X/5X Package Types PDIP/SOIC GP0/AN0 GP1/AN1 GP2/AN2/PWM1 GP3/AN3/PWM2 GP4/VREFGP5/VREF+ VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD TXCAN/TXRXCAN* RXCAN/NC* GP7/RST/VPP GP6/CLKOUT OSC2 OSC1/CLKIN Threshold Detection - refers to the MCP2502X/5X's ability to automatically transmit a message when a predefined analog threshold is reached. * One-wire option available on MCP250X5 devices. Definition of Terms The following document: terms are used throughout this I/O Expander - refers to the integrated circuit (IC) device being described (MCP2502X/5X). Input Message - term given to messages that are received by the MCP2502X/5X and cause the internal registers to be modified. Once the register modification has been performed, the MCP2502X/5X transmits a Command Acknowledge message to indicate that the command was received and processed. Command Acknowledge Message - term given to the message that is automatically transmitted by the MCP2502X/5X after receiving and processing an input message. Information Request Message - term given to Remote Request messages that are received by the MCP2502X/5X that subsequently generate an output message (data frame) in response. Output Message - term given to the message that the MCP2502X/5X sends in response to an Information Request message. On Bus Message - term given to the message that the MCP2502X/5X transmits after completing the power-on/ self-configuration sequence at timed intervals, if enabled. Self-Configuration - term used to describe the process of transferring the contents of the EPROM memory array to the SRAM memory array. On Bus - term used to describe the condition when the MCP2502X/5X is fully-configured and ready to transmit, or receive, on the bus. This is the only state in which the MCP2502X/5X can transmit on the bus. Edge Detection - refers to the MCP2502X/5X's ability to automatically transmit a message based upon the occurance of a predefined edge on any digital input. DS21664C-page 2 2003 Microchip Technology Inc. MCP2502X/5X 1.0 DEVICE OVERVIEW This document contains device-specific information on the MCP2502X/5X family of CAN I/O expanders. The CAN protocol is not discussed in depth in this document. Additional information on the CAN protocol can be found in the CAN specification, as defined by Robert Bosch GmbH. Figure 1-1 is the block diagram of the MCP2502X/5X and Table 1-1 is the pinout description. The following sections detail the modules as listed in Figure 1-1. FIGURE 1-1: MCP2502X/5X BLOCK DIAGRAM GPIO GP0/AN0 GP1/AN1 GP2/AN2/PWM1 GP3/AN3/PWM2 GP4/VREFGP5/VREF+ User Memory GP6/CLKOUT GP7RST/VPP State Machine and Control Logic CAN Protocol Engine OSC1/CLKIN OSC2/CLKOUT Timing Generation TXCAN/ TXRXCAN RXCAN PWM2 PWM1 A/D * * Only the MCP2505X devices have the A/D module. TABLE 1-1: Pin Name GP0/AN0 * GP1/AN1 * GP2/AN2/PWM2 * GP3/AN3/PWM3 * GP4/VREFGP5/VREF+ VSS OSC1/CLKIN OSC2 GP6/CLKOUT GP7/RST/VPP RXCAN TXCAN/TXRXCAN VDD PINOUT DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Standard Function Bidirectional I/O pin, TTL input buffer Bidirectional I/O pin, TTL input buffer Bidirectional I/O pin, TTL input buffer Bidirectional I/O pin, TTL input buffer Bidirectional I/O pin, TTL input buffer Bidirectional I/O pin, TTL input buffer Ground External oscillator input External oscillator output Bidirectional I/O pin, TTL input buffer Input pin, TTL input buffer CAN data receive input CAN data transmit output Power Alternate Function Analog input channel Analog input channel Analog input/PWM output Analog input/PWM output External VREFExternal VREF input None External clock input None CLKOUT output External Reset input Not connected for 1-wire CAN TX and RX for 1-wire operation (MCP250X5) None Programming Mode Function None None None None Data Clock Ground None None None Vpp None None Power * Only the MCP2505X devices have the A/D module. 2003 Microchip Technology Inc. DS21664C-page 3 MCP2502X/5X NOTES: DS21664C-page 4 2003 Microchip Technology Inc. MCP2502X/5X 2.0 CAN MODULE The CAN module is a protocol controller that converts between raw digital data and CAN message packets. The main functional block of the CAN module is shown in Figure 2-1 and consists of: * CAN protocol engine * Buffers, masks and filters The module features include: * Implementation of the CAN protocol * Double-buffered receiver with two separate receive buffers * One full-acceptance mask (standard and extended) * Two full-acceptance filters (standard and extended) * One filter for each receive buffer * Three prioritized transmit buffers for transmitting predefined message types * Automatic wake-up on bus traffic function * Error management logic for transmit and receive error states * Low-power SLEEP mode FIGURE 2-1: BUFFERS CAN MODULE TXB0 MESSAGE TXREQ ABTF MLOA TXERR TXB1 MESSAGE TXREQ ABTF MLOA TXERR TXB2 MESSAGE A c c e p t R X B 0 TXREQ ABTF MLOA TXERR Acceptance Mask RXM Acceptance Filter RXF0 M A B Acceptance Filter RXF1 R X B 1 A c c e p t Message Queue Control Identifier Data Field Identifier Data Field Transmit Byte Sequencer PROTOCOL ENGINE Transmit<7:0> Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator CRC<14:0> Receive<7:0> Receive Error Counter Transmit Error Counter REC TEC ErrPas BusOff Protocol Finite State Machine Transmit Logic Bit Timing Logic RXCAN Clock Generator TXCAN/TXRXCAN Configuration Registers 2003 Microchip Technology Inc. DS21664C-page 5 MCP2502X/5X 2.1 CAN Protocol Finite State Machine 2.3 Error Management Logic The heart of the engine is the Finite State Machine (FSM). This state machine sequences through messages on a bit-by-bit basis, changing states as the fields of the various frame types are transmitted or received. The FSM is a sequencer controlling the sequential data stream between the TX/RX Shift register, the CRC register and the bus line. The FSM also controls the Error Management Logic (EML) and the parallel data stream between the TX/RX Shift registers and the buffers. The FSM insures that the processes of reception, arbitration, transmission and error signaling are performed according to the CAN protocol. The automatic retransmission of messages on the bus line is also handled. The error management logic is responsible for the fault confinement of the CAN device. Its two counters (the Receive Error Counter (REC) and the Transmit Error Counter (TEC)) are incremented and decremented by commands from the Bit Stream processor. According to the values of the error counters, the MCP2502X/5X is set into the states error-active, error-passive or bus-off. Error-active: Both error counters are below the errorpassive limit of 128. Error-passive: At least one of the error counters (TEC or REC) equals or exceeds 128. Bus-off: The transmit error counter (TEC) equals or exceeds the bus-off limit of 256. The device remains in this state until the bus-off recovery sequence is received. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits. Note: The MCP2502X/5X, after going bus-off, will recover back to error-active automatically if the bus remains idle for 128 x 11 bits. OPTREG2.ERRE must be set to force the MCP2502X/5X to enter Listen-only mode instead of Normal mode during bus recovery. The current error mode (except for bus-off) of the MCP2502X/5X can be determined by reading the EFLG register via the Read CAN error message. 2.2 Cyclic Redundancy Check (CRC) The Cyclic Redundancy Check register generates the Cyclic Redundancy Check (CRC) code that is transmitted after either the Control field (for messages with 0 data bytes) or the Data field and is used to check the CRC field of incoming messages. FIGURE 2-2: ERROR MODES STATE DIAGRAM RESET REC < 127 or TEC < 127 Error-Active 128 occurrences of 11 consecutive "recessive" bits REC > 127 or TEC > 127 Error-Passive TEC > 255 Bus-Off DS21664C-page 6 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 2-1: TEC - TRANSMITTER ERROR COUNTER R-0 TEC7 bit 7 bit 7-0 TEC7:TEC0: Transmit Error Counter bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 TEC6 R-0 TEC5 R-0 TEC4 R-0 TEC3 R-0 TEC2 R-0 TEC1 R-0 TEC0 bit 0 REGISTER 2-2: REC - RECEIVER ERROR COUNTER R-0 REC7 bit 7 R-0 REC6 R-0 REC5 R-0 REC4 R-0 REC3 R-0 REC2 R-0 REC1 R-0 REC0 bit 0 bit 7-0 REC7:REC0: Receive Error Counter bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown FIGURE 2-3: BIT TIME PARTITIONING Input Signal Sync Prop Segment Phase Segment 1 Sample Point Phase Segment 2 TQ 2.4 Bit Timing Logic The Bit Timing Logic (BTL) monitors the bus line input and handles the bus-related bit timing based on the CAN protocol. The BTL synchronizes on a recessiveto-dominant bus transition at Start-of-Frame (hard synchronization) and on any further recessive-todominant bus line transition if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL also provides programmable time segments to compensate for the propagation delay time, phase shifts and to define the position of the sample point within the bit time. These programmable segments are made up of integer units called Time Quanta (TQ). The nominal bit time is calculated by programming the TQ length and the number of TQ in each time segment, as discussed below. 2.4.1 TIME QUANTUM (TQ) Time Quantum is a fixed unit of time derived from the oscillator period. There is a programmable baud rate prescaler (BRP) (with integral values ranging from 1 to 64) as well as a fixed division by two for clock generation. 2003 Microchip Technology Inc. DS21664C-page 7 MCP2502X/5X The base TQ is defined as twice the oscillator period. Adding the BRP into the equation yields: T Q = 2*T O SC * ( BRP + 1 ) where BRP = binary value represented by CNF1.BRP<5:0> By definition, the nominal bit time is programmable from a minimum of 8 TQ to 25 TQ. Also, the minimum nominal bit time is 1 s, which corresponds to 1 Mb/s. 2.4.2.3 Phase Buffer Segments The Phase Buffer Segments are used to optimally locate the sampling point of the received bit within the nominal bit time. The sampling point occurs between PS1 and PS2. These segments can be automatically lengthened or shortened by the resynchronization process. Thus, the variation of the values of the phase buffer segments represent the DPLL functionality. Phase Segment 1 (PS1): The end of PS1 determines the sampling point within a bit time. PS1 is programmable from 1 TQ - 8 TQ in duration. Phase Segment 2 (PS2): PS2 provides delay before the next transmitted data transition and is also programmable from 1 TQ - 8 TQ in duration. However, due to IPT requirements, the actual minimum length of phase segment 2 is 2 TQ. It may also be defined to be equal to the greater of PS1 or the information processing time (IPT). 2.4.2 TIME SEGMENTS Time segments make up the nominal bit time. The nominal bit time can be thought of as being divided into separate non-overlapping time segments. These segments are shown in Figure 2-3. * * * * Synchronization Segment (SyncSeg) Propagation Segment (PropSeg) Phase Buffer Segment 1 (PS1) Phase Buffer Segment 2 (PS2) Nominal Bit Time = T Q * ( Sync_Seg + PropSeg + Phase_Seg1 + Phase_Seg2 ) 2.4.3 SAMPLE POINT Rules for Programming the Segments There are a few rules to follow when programming the time segments: * PropSeg + PS1 PS2 * PS2 > Sync Jump Width * PS2 Information Processing Time The sample point is the point of time at which the bus level is read and the value of the received bit is determined. The sampling point occurs at the end of PS1. If desired, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is determined to be the value of the majority decision of three values. The three samples are taken at the sample point, and twice before, with a time of TQ/2 between each sample. 2.4.4 INFORMATION PROCESSING TIME 2.4.2.1 Synchronization Segment This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the SyncSeg. The duration is fixed at 1 TQ. The Information Processing Time (IPT) is the time segment (starting at the sample point) that is reserved for calculation of the subsequent bit level. The CAN specification defines this time to be less than or equal to 2 TQ. The MCP2502X/5X defines this time to be 2 TQ. Thus, PS2 must be at least 2 TQ long. 2.4.2.2 Propagation Segment 2.4.5 SYNCHRONIZATION JUMP WIDTH This part of the bit time is used to compensate for physical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The delay is calculated as being the round-trip time from transmitter to receiver (twice the signal's propagation time on the bus line), the input comparator delay and the output driver delay. The length of the Propagation Segment can be programmed from 1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits of the CNF2 register. To compensate for phase shifts and oscillator tolerances between the nodes in the system, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When a recessive-to-dominant edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (SyncSeg). The circuit will then adjust the values of PS1 and PS2, as necessary, using the programmed Synchronization Jump Width (SJW). This adjustment is made for resynchronization during a message and not hard synchronization, which occurs only at the message Start-of-Frame (SOF). DS21664C-page 8 2003 Microchip Technology Inc. MCP2502X/5X As a result of resynchronization, PS1 may be lengthened or PS2 may be shortened. The amount of lengthening or shortening of the phase buffer segments has an upper-bound given by the SJW. The SJW is programmable between 1 TQ and 4 TQ. The value of the SJW will be added to PS1 (or subtracted from PS2) depending on the phase error (e) of the edge in relation to the receiver's SyncSeg. The phase error is defined as follows: * e = 0 if the edge lies within SYNCESEG - No resynchronization is required. * e > 0 if the edge lies before the sample point - PS1 will be lengthened by the amount of the SJW. * e < 0 if the edge lies after the sample point of the previous bit and before the SyncSeg of the current bit - PS2 will be shortened by the amount of the SJW. 2.4.6.2 CNF2 The PRSEG<2:0> bits set the length (in TQ's) of the propagation segment. The PS1<2:0> bits set the length (in TQ's) of phase segment 1. The SAM bit controls how many times the RXCAN pin is sampled. Setting this bit to a `1' causes the bus to be sampled three times. Twice at TQ/2 before the sample point and once at the normal sample point (which is at the end of PS1). The value of the bus is determined to be the value read during at least two of the samples. If the SAM bit is set to a `0', the RXCAN pin is sampled only once at the sample point. The BTLMODE bit controls how the length of PS2 is determined. If this bit is set to a `1', the length of PS2 is determined by the PS2<2:0> bits of CNF3. If the BTLMODE bit is set to a `0' then the length of PS2 is the greater of PS1 and the information processing time (which is fixed at 2 TQ for the MCP2502X/5X). 2.4.6.3 CNF3 2.4.6 CONFIGURATION REGISTERS There are three registers (in the configuration register module) associated with the CAN bit timing logic that controls the bit timing for the CAN bus interface. The PS2<2:0> bits set the length, in TQ's, of PS2, if the CNF2.BTLMODE bit is set to a `1'. If the BTLMODE bit is set to a `0', the PS2<2:0> bits have no effect. Additionally, the wake-up filter (CNF3.WAKFIL) is implemented in the CNF3 register. This filter is a lowpass filter that can be used to prevent the MCP2502X/ 5X from waking up due to short glitches on the CAN bus. 2.4.6.1 CNF1 The BRP<5:0> bits control the baud rate prescaler. These bits set the length of TQ relative to the OSC1 input frequency, with the minimum length of TQ being 2 TOSC in length (when BRP<5:0> are set to 000000). The SJW<1:0> bits select the synchronization jump width in terms of number of TQ's. REGISTER 2-3: CNF1 - CAN CONFIGURATION REGISTER 1 R/W-0 SJW1 bit 7 R/W-0 SJW0 R/W-0 BRP5 R/W-0 BRP4 R/W-0 BRP3 R/W-0 BRP2 R/W-0 BRP1 R/W-0 BRP0 bit 0 bit 7-6 SJW1:SJW0: Synchronized Jump Width bits 11 = Length = 4 x TQ 10 = Length = 3 x TQ 01 = Length = 2 x TQ 00 = Length = 1 x TQ BRP5:BRP0: Baud Rate Prescaler bits 111111 =TQ = 2 x 64 x 1/FOSC 000000 =TQ = 2 x 1 x 1/FOSC Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 5-0 2003 Microchip Technology Inc. DS21664C-page 9 MCP2502X/5X REGISTER 2-4: CNF2 - CAN CONFIGURATION REGISTER 2 R/W-0 BTLMODE bit 7 bit 7 BTL MODE: Length determination of PHSEG2 bit 1 = Length of Phase_Seg2 determined by bits 2:0 of CNF3 0 = Length of Phase_Seg2 is the greater of Phase_Seg1 or IPT(2Tq) SAM: Sample of the CAN bus line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point PHSEG12:PHSEG10: Phase Buffer Segment1 bits 111 = length = 8 x TQ 000 = length = 1 x TQ PRSEG2:PRSEG0: Propagation Time Segment bits R/W-0 SAM R/W-0 R/W-0 R/W-0 PHSEG10 R/W-0 PRSEG2 R/W-0 PRSEG1 R/W-0 PRSEG0 bit 0 PHSEG12 PHSEG11 bit 6 bit 5-3 bit 2-0 111 = length = 8 x TQ 000 = length = 1 x T Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 2-5: CNF3 - CAN CONFIGURATION REGISTER 3 U-0 -- R/W-0 WAKFIL U-0 -- U-0 -- U-0 -- R/W-0 PHSEG22 R/W-0 PHSEG21 R/W-0 PHSEG20 bit 0 bit 7 bit 7 bit 6 Unimplemented: (Reads as 0) WAKFIL: Wake-up filter bit 1 = Wake-up filter enabled 0 = Wake-up filter disabled Unimplemented: (Reads as 0) PHSEG22:PHSEG20: Phase Buffer Segment2 bits 111 = length = 8 x TQ 001 = length = 2 x TQ 000 = Invalid Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 5-3 bit 2-0 DS21664C-page 10 2003 Microchip Technology Inc. MCP2502X/5X 2.5 Buffers, Masks, and Filters This part of the CAN module supports the transmitting, receiving and acceptance of CAN messages. Three transmit buffers are used for the three transmit message IDs, as discussed later in this section. Two receive buffers store the CAN message's arbitration field, control field and the data field. One mask defines which bits are to be applied to either filter. The mask can be regarded as defining "don't care" bits for the filter. Each of the two filters define a bit pattern that will be compared to all incoming messages. All filter bits that have not been defined as "don't care" by the mask are applied to the message. Command Acknowledge: TXID1 sends a Command Acknowledge message when the MCP2502X/5X receives an Input Message and processes the instruction (and OPTREG2.CAEN = 1). This message is used as a hand shake for the node requesting the modification of the MCP2502X/5X. There is no data associated with this message. Receive Overflow: TXID1 sends a Receive Overflow message if there is a Receive Overflow condition (and OPTREG2.CAEN = 0). This only occurs if the device has received a valid message before processing the previous valid message from the same receive buffer. There is no data associated with this message. Error Condition: An Error Condition message is transmitted if the TEC or REC counters reach error warning (> 95) or error passive (> 127). This message contains the TXID1 identifier and the TEC, REC and EFLG counters. A hysteresis is implemented in hardware that prevents messages from repeatedly being transmitted due to error counts changing by one or two bits. Once a message is sent for an error warning (TEC or REC > 95), the message will not trigger again until the error counter 79 and back to > 95 (hysteresis = 17 counts). Similarly, an error passive message is sent at TEC or REC > 127 and is not sent again until the error counter 111 and back to >127 (hysteresis = 17 counts). 2.5.1 TRANSMIT MESSAGE ID'S The MCP2502X/5X device contains three separate transmit message ID's: TXID0, TXID1 and TXID2. The data length code is predefined for each of the various output messages, with the data that is transmitted coming directly from the contents of the device's peripheral registers. 2.5.1.1 Transmit Message ID0 (TXID0) TXID0 contains the identifier that is used when transmitting the On Bus message. If enabled (STCON.STEN = 1), the On Bus message will be transmitted at predefined intervals. Depending on the message-select bit (STCON.STMS = 1), the CAN message will send GPIO and A/D data. Transmit Message ID0 will not automatically be sent when the device is brought out of sleep. 2.5.1.3 Transmit Message ID2 (TXID2) 2.5.1.2 Transmit Message ID1 (TXID1) TXID1 contains the identifier that is used when the MCP2502X/5X sends the Command Acknowledge message, the Receive Overflow message and/or the Error Condition message. All message types use the same identifier. The CAEN bit, in the OPTREG2 register, selects between the Command Acknowledge and Receive Overflow operation. These message types have a DLC of 0 and do not contain any data. The Error Condition message can occur anytime, has a DLC of 3 and contains the EFLG, TEC and REC data values. Note: A zero data length On Bus message will be transmitted once after power-up, regardless of scheduled transmissionenable status. Transmit ID2 contains the identifier that is used when transmitting auto-conversion-initiated messages, including digital input edge detection and/or analog input exceeding a threshold. This message will also be sent when the device wakes up from sleep due to a digital input change-of-state condition (i.e., change-ofstate occurs on input configured to transmit on change-of-state). 2.6 Receive Buffers The MCP2505X contains two receive buffers, each with their own filter. There is also a Message Assembly Buffer (MAB) that acts as a third receive buffer (see Figure 2-1). The two receive buffers, combined with the MAB help, insure that received messages will be processed while minimizing the chances of receive buffer overrun due to maximum bus loading of messages destined for the MCP2502X/5X. Note: The receive buffers are used by the MCP2502X/5X to implement the command messages and are not externally accessible. 2003 Microchip Technology Inc. DS21664C-page 11 MCP2502X/5X 2.7 Acceptance Mask The acceptance mask is used to define which bits in the CAN ID are to be compared against the programmable filters. Individual bits within the mask correspond to bits in the CAN ID that, in turn, correspond to bits in the acceptance filters. Any bit in the mask that is set to a `1' will cause the corresponding CAN ID bit to be compared against the associated filter bit. Any bit in the mask that is set to a `0' is not compared and effectively sets the associated CAN ID bit to `don't care'. Message with an extended ID - the three least significant bits of the standard identifier (RXMSIDL.SID2:SID0) are configurable and the three least significant bits of the extended identifier (RXMEID0.EID2:EID0) are always `don't cares' and effectively becomes `0'. Note: The EXIDE bit in the Mask register (RXMSIDL) can be used to mask the IDE bit in the corresponding Receive buffer register (RXBnSIDL). 2.7.1 MASKS AND STANDARD/ EXTENDED IDS 2.8 Acceptance Filters To insure proper operation of the information request and input messages, some mask bits (as configured in the mask registers) may be ignored as explained: Message with a standard ID - the three least significant bits of a standard identifier (RXMSIDL.SID2:SID0) are `don't care' for the mask registers and effectively become `0'. There are two separate acceptance filters defined for the MCP2502X/5X: RXF0 and RXF1. RXF0 is used for Information Request messages and RXF1 is used for input messages (see Table 4-2 and Table 4-3). Each bit in the filters corresponds to a bit in the CAN ID. Every bit in the CAN ID, for which the corresponding Mask bit is set, must match the associated filter bit in order for the message to be accepted. Messages that fail to meet the mask/fIlter criteria are ignored. REGISTER 2-6: TXIDNSIDH - TRANSMIT IDENTIFIER N STANDARD IDENTIFIER HIGH R/W-x SID10 bit 7 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS21664C-page 12 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 2-7: TXIDNSIDL - TRANSMIT IDENTIFIER N STANDARD IDENTIFIER LOW R/W-x SID2 bit 7 bit 7-5 bit 4 bit 3 SID2:SID0: Standard Identifier bits Unimplemented: Read as '0' EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier Unimplemented: Read as '0' EID17:EID16: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDE U-0 -- R/W-x EID17 R/W-x EID16 bit 0 bit 2 bit 1-0 REGISTER 2-8: TXIDNEID8 - TRANSMIT IDENTIFIER N EXTENDED IDENTIFIER HIGH R/W-x EID15 bit 7 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 2-9: TXIDNEID0 - TRANSMIT IDENTIFIER N EXTENDED IDENTIFIER LOW R/W-x EID7 bit 7 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown 2003 Microchip Technology Inc. DS21664C-page 13 MCP2502X/5X REGISTER 2-10: RXMSIDH - ACCEPTANCE FILTER MASK STANDARD IDENTIFIER HIGH R/W-x SID10 bit 7 bit 7-0 SID10:SID3: Standard Identifier bits * If OPTREG2.MTYPE = 1, then SID3 is forced to zero. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3* bit 0 REGISTER 2-11: RXMSIDL - ACCEPTANCE FILTER MASK STANDARD IDENTIFIER LOW R/W-x SID2 bit 7 R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDE U-0 -- R/W-x EID17 R/W-x EID16 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits Standard messages, bits = b'000' Extended messages, bits = SID2:SID0 Unimplemented: Read as '0' EXIDE: Extended Identifier Enable bit 1 = Apply filter to RXFnSIDL.EXIDE (filter applies to standard or extended message frames depending on filter bit) 0 = Do not apply filter to RXFnSIDL.EXIDE (filter will be applied to both standard and extended message frames) Unimplemented: Read as '0' EID17:EID16: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2 bit 1-0 REGISTER 2-12: RXMEID8 - ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER MID R/W-x EID15 bit 7 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS21664C-page 14 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 2-13: RXMEID0 - ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER LOW R/W-x EID7 bit 7 bit 7-3 bit 2-0 EID7:EID3: Extended Identifier bits EID2:EID0: Extended Identifier bits (always reads as `0') Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 REGISTER 2-14: RXFNSIDH - ACCEPTANCE FILTER N STANDARD IDENTIFIER HIGH R/W-x SID10 bit 7 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3* bit 0 bit 7-0 SID10:SID3: Standard Identifier bits * If OPTREG2.MTYPE = 1, then SID3 = X Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 2-15: RXFNSIDL - ACCEPTANCE FILTER N STANDARD IDENTIFIER LOW R/W-x SID2 bit 7 R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDE U-0 -- R/W-x EID17 R/W-x EID16 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits 1 = When EXIDE = 1, SID2:SID0 = b'xxx' 0 = When EXIDE = 0, SID2:SID0 = as configured Unimplemented: Read as `0' EXIDE: Extended Identifier Enable bit 1 = Filter will apply to extended identifier 0 = Filter will apply to standard identifier Unimplemented: Read as `0' EID17:EID16: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2 bit 1-0 2003 Microchip Technology Inc. DS21664C-page 15 MCP2502X/5X REGISTER 2-16: RXFNEID8 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER MID R/W-x EID15 bit 7 bit 7-0 EID15:EID8: Extended Identifier Bit Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 REGISTER 2-17: RXFNEID0 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER LOW R/W-x EID7 bit 7 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 bit 7-0 EID7:EID0: Extended Identifier Bit (always = b'xxx') Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS21664C-page 16 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 2-18: EFLG - ERROR FLAG REGISTER R-0 ESCF bit 7 bit 7 ESCF: Error State Change (for sending Error state message) 1 = An error state change occurred 0 = No error state change RBO: Receive Buffer Overflow 1 = Overflow occurred 0 = No overflow occurred TXBO: Transmitter in Bus Off Error State bit 1 = TEC reaches 256 0 = Indicates a successful bus recovery sequence TXEP: Transmitter in Error Passive State bit 1 = TEC is equal to or greater than 128 0 = TEC is less than 128 RXEP: Receiver in Error Passive State bit 1 = REC is equal to or greater than 128 0 = REC is less than 128 TXWAR: Transmitter in Error Warning State bit 1 = TEC is equal to or greater than 96 0 = TEC is less than 96 RXWAR: Receiver in Error Warning State bit 1 = REC is equal to or greater than 96 0 = REC is less than 96 EWARN; Either the Receive Error counter or Transmit error counter has reached or exceeded 96 errors 1 = TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1) 0 = Both REC and TEC are less than 96 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 RBO R-0 TXBO R-0 TXEP R-0 RXEP R-0 TXWAR R-0 RXWAR R-0 EWARN bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2003 Microchip Technology Inc. DS21664C-page 17 MCP2502X/5X NOTES: DS21664C-page 18 2003 Microchip Technology Inc. MCP2502X/5X 3.0 3.1 USER REGISTERS Description The MCP2502X/5X allows the user to pre-program registers pertaining to CAN module and device configuration into non-volatile EPROM memory. In this way, the device is initialized to a default state after power-up. The user registers are transferred to SRAM during the power-up sequence and many of the registers are able to be accessed via the CAN bus once the device establishes a connection with the bus. Additionally, there are 16 user-defined registers that can be used to store information about the part (e.g., serial number, node identifier, etc.). The registers are summarized in Table 3-1. Note 1: When transferred to RAM, the register addresses are offset by 1Ch. Accessing individual registers using the "Write Register" or "Read Register command requires use of the offset address. Also, see Table 3-2 for information on accessible registers not contained in user EPROM. 2: Do not address locations outside of the user memory map or unexpected results may occur. TABLE 3-1: Address 00h 01h USER MEMORY MAP Name Description Enable inputs for Transmit-On-Change feature Defines polarity for I/O or greater than/ less than operator for A/D Transmit-OnChange inputs General Purpose I/O (GPIO) Register Address 1Bh 1Ch Name RXF0EID0 RXF1SIDH Description Acceptance Filter 0, Extended ID LSB Acceptance Filter 1, Standard ID MSB Acceptance Filter 1, Standard ID LSB, Extended ID USB, and Extended ID enable Acceptance Filter 1, Extended ID MSB Acceptance Filter 1, Extended ID LSB Transmit Buffer 0, Standard ID MSB Transmit Buffer 0, Standard ID LSB, Extended ID USB, and Extended ID enable Transmit Buffer 0, Extended ID MSB Transmit Buffer 0, Extended ID LSB Transmit Buffer 1, Standard ID MSB Transmit Buffer 1, Standard ID LSB, Extended ID USB, and Extended ID enable Transmit Buffer 1, Extended ID MSB IOINTEN IOINTPO 02h GPLAT 1Dh RXF1SIDL 03h 04h 0xFF OPTREG1 Reserved Configuration options, including GPIO pull-up enable, clockout enable and prescaler PWM1 Timer Control Register; contains enable bit, clock prescale and DC LSBs PWM2 Timer Control Register; contains enable bits, clock prescale and DC LSBs PWM1 Period Register PWM2 Period Register 1Eh 1Fh RXF1EID8 RXF1EID0 05h 06h T1CON T2CON 20h 21h TXID0SIDH TXID0SIDL 07h 08h 09h 0Ah PR1 PR2 22h 23h 24h 25h TXID0EID8 TXID0EID0 TXID1SIDH TXID1SIDL PWM1DCH PWM1 Duty Cycle (DC) MSBs PWM2DCH PWM2 Duty Cycle (DC) MSBs 0Bh CNF1 3 CAN module register configures synchronization jump width and baud rate prescaler CAN module register configures propagation segment, phase segment 1, and determines number of sample points CAN module register configures phase buffer segment 2, Sleep mode 26h TXID1EID8 0Ch CNF2 3 27h TXID1EID0 Transmit Buffer 1, Extended ID LSB 0Dh Note 1: 2: 3: 4: CNF3 3 28h TXID2SIDH Transmit Buffer 2, Standard ID MSB GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch. User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via "Read User Mem" commands. Cannot be modified from initial programmed values. Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F). 2003 Microchip Technology Inc. DS21664C-page 19 MCP2502X/5X TABLE 3-1: Address 0Eh USER MEMORY MAP (CONTINUED) Name Description 4 Address 29h Name TXID2SIDL Description Transmit Buffer 2, Standard ID LSB, Extended ID USB, and Extended ID enable Transmit Buffer 2, Extended ID MSB ADCON0 A/D Control Register; contains enable, conversion rate, channel select bits A/D Control Register; contains voltage reference source, conversion rate and A/D input enable bits Scheduled Transmission Control Register Configuration options, including Sleep mode, RTR message and error recovery enables Reserved Reserved Acceptance Filter Mask, Standard ID MSB Acceptance Filter Mask, Standard ID LSB and Extended ID USB Acceptance Filter Mask, Extended ID MSB Acceptance Filter Mask, Extended ID LSB Acceptance Filter 0, Standard ID MSB Acceptance Filter 0, Standard ID LSB, Extended ID USB, and Extended ID enable Acceptance Filter 0, Extended ID MSB 0Fh ADCON14 2Ah TXID2EID8 10h 11h STCON OPTREG2 2Bh 2Ch TXID2EID0 ADCMP3H 4 Transmit Buffer 2, Extended ID LSB Analog Channel 3 Compare Value MSB Analog Channel 3 Compare Value LSb's 12h 13h 14h 15h 16h 17h 18h 19h -- -- RXMSIDH RXMSIDL RXMEID8 RXMEID0 RXF0SIDH RXF0SIDL 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h ADCMP3L4 ADCMP2H4 Analog Channel 2 Compare Value MSB ADCMP2L4 Analog Channel 2 Compare Value LSb's ADCMP1H4 Analog Channel 1 Compare Value MSB ADCMP1L4 Analog Channel 1 Compare Value LSb's ADCMP0H4 Analog Channel 0 Compare Value MSB ADCMP0L4 GPDDR1 Analog Channel 0 Compare Value LSb's General Purpose I/O Data Direction Register 1Ah Note 1: 2: 3: 4: RXF0EID8 35-44h USER[0:F]2 User Defined Bytes (0-15) GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch. User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via "Read User Mem" commands. Cannot be modified from initial programmed values. Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F). TABLE 3-2: Addr* 1Fh** 18h 19h 1Ah 50h 51h 52h 53h 54h 55h 56h 57h * ** Name GPDDR EFLG TEC REC ACCESSIBLE RAM REGISTERS NOT IN THE EPROM MAP bit7 -- ESCF bit6 DDR6 RBO bit5 DDR4 TXEP bit4 DDR4 TXEP bit3 DDR3 RXEP bit2 DDR2 TXWAR bit1 DDR1 RXWAR bit0 DDR0 EWARN Value on POR -111 1111 Value on RST -111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Transmit Error Counters Receive Error Counters AN3.9 AN3.1 AN2.9 AN2.1 AN1.9 AN1.1 AN0.9 AN0.1 AN3.8 AN3.0 AN2.8 AN2.0 AN1.8 AN1.0 AN0.8 AN0.0 AN3.6 -- AN2.6 -- AN1.6 -- AN0.6 -- AN3.6 -- AN2.6 -- AN1.6 -- AN0.6 -- AN3.5 -- AN2.5 -- AN1.5 -- AN0.5 -- AN3.4 -- AN2.4 -- AN1.4 -- AN0.4 -- AN3.3 -- AN2.3 -- AN1.3 -- AN0.3 -- AN3.2 -- AN2.2 -- AN1.2 -- AN0.2 -- ADRES3H ADRES3L ADRES2H ADRES2L ADRES1H ADRES1L ADRES0H ADRES0L xxxx xxxx xx-- ---xxxx xxxx xx-- ---xxxx xxxx xx-- ---xxxx xxxx xx-- ---- uuuu uuuu uu-- ---uuuu uuuu uu-- ---uuuu uuuu uu-- ---uuuu uuuu uu-- ---- These addresses are used when using the "Write Register" or "Read Register" command The GPDDR register is not offset to RAM the same as the other registers in the EPROM DS21664C-page 20 2003 Microchip Technology Inc. MCP2502X/5X 4.0 4.1 DEVICE OPERATION Power-Up Sequence Scheduled Transmissions Once the MCP2502X/5X has gone on bus it will transmit the On Bus message once, regardless of whether enabled or not. This message notifies the network of the MCP2502X/5X's presence. The On Bus message will (if enabled STCON.STEN) repeat at a frequency determined by the STCON register (Register 4-1). This message can also be configured to send the "Read A/D Register" data bytes along with the predefined identifier in TXID2 by setting STCON.STMS = 1. Note: The first On Bus message sent after power-up will NOT send the "Read A/D Register" data bytes, regardless of the STCON.STMS value. If the MCP2502X/5X enters SLEEP mode, the scheduled transmissions will cease until the device wakes up again. This implies that SLEEP mode has priority over scheduled transmissions. The following sections describe the events/actions of the MCP2502X/5X during normal power-up and operation. 4.1.1 POWER-ON RESET The MCP2502X/5X goes through a sequence of events at power-on reset (POR) in order to load the programmed configuration and insure that errors are not introduced on the bus. During this time, the device is prevented from generating a low condition on the TXCAN pin. The TXCAN pin must remain high from power-on until the device goes on bus. Operational Mode at Power-On The MCP2502X/5X initially powers up in Configuration mode. While in this mode, the MCP2502X/5X will be prevented from sending or receiving messages via the CAN interface. The ADC and PWM peripherals are disabled while in this mode. Self-Configuration Once the MCP2502X/5X is out of reset, it will perform a self-configuration. This is accomplished by transferring the contents of the EPROM array to the corresponding locations within the SRAM array. In addition, the checksum of the data written to SRAM will be compared to a pre-programmed value as a test of valid data. Going On Bus Once the self-configuration cycle has successfully completed, the MCP2502X/5X switches to Listen-only mode. It will remain in this mode until an error-free CAN message is detected. This is done to ensure that the device is at the correct bus rate for the system. Once the device detects an error-free message, it waits for CAN bus idle before switching to Normal mode. This prevents it from going on bus in the middle of another node's transmission and generating an error frame. Alternately, the MCP2505X may directly enter Normal mode (without first entering Listen-only Mode) after completing its self-configuration. This is configured by the user via a control bit (OPTREG2.PUNRM). Once the MCP2502X/5X enters Normal mode, it is ready to send/receive messages via the CAN interface. At this point the ADC and PWM peripherals are operational, if enabled. Note: 4.2 Message Functions The MCP2502X/5X uses the global mask (RXMASK), two filters (RXF0 and RXF1) and two receive buffers (RB0 and RB1) to determine if a received message should be acted upon. There are 16 functions that can be performed by the MCP2502X/5X based on received messages (see Table 4-1).These functions allow the device to not only be accessed for Information Request/Input/Output operations, but also to be reconfigured via the CAN bus, if necessary. 4.3 Message Types There are three types of messages that are used to implement the functions of Table 4-1. 1. 2. 3. Information Request Messages (IRM) - Received by the MCP2502X/5X. Output Messages - Transmitted from the MCP2502X/5X as a response to IRMs. Input Messages - Received by the MCP2502X/ 5X and used to modify registers. Note: Information Request Messages (IRMs) and Input messages are both input messages to the MCP2502X/5X. IRMs are received into receive buffer 0 and input messages are received into receive buffer 1. This must be taken into account while configuring the acceptance filters. 2003 Microchip Technology Inc. DS21664C-page 21 MCP2502X/5X 4.3.1 INFORMATION REQUEST MESSAGES 4.3.1.1 RTR Message Type Information Request Messages (IRM) are messages that the MCP2502X/5X receives into Receive Buffer 0 (matches Filter 0) and then responds to by transmitting a message (output message) containing the requested data. IRMs can be implemented as either a Remote Transfer Request (RTR) or a Data Frame message by configuring the MTYPE bit in the OPTREG2 register. When RTR message types are selected (OPTREG2.MTYPE) and a node in the system wants information from the MCP2502X/5X, it has to send a remote frame on the bus. The identifier for the remote frame must be such that it will be accepted through the MCP2502X/5X's mask/filter process (using RXF0). The RTR message type (remote frames) is the default configuration (MTYPE bit = 0). Information Request "RTR" messages must not only meet the RXMASK/RXF0 criteria but must also have the RTR bit of the CAN ID set (since the filter registers do not contain an explicit RTR bit). If a message passes the mask/filter process and the RTR bit is a `0', that message will be ignored. Once the MCP2502X/5X has received a remote frame, it will determine the function to be performed based upon the three LSb's (RXB0SIDL.SID2:SID0 for standard messages and RXB0EID0.EID2:EID0 for extended messages) of the received remote frame. Additionally, a predefined Data Length Code (DLC) must be sent to signify the number of data bytes that the MCP2502X/5X must return in it's output message (see Table 4-2 and Table 4-3). TABLE 4-1: Name Read A/D Registers Read Control Registers Read Configuration Registers Read CAN error states Read PWM Configuration Read User Registers 1 Read User Registers 2 Read Register* MESSAGE FUNCTION Description Transmits a single message containing the current state of the analog and I/O registers, including the configuration Transmits several control registers not included in other messages Transmits the contents of many of the configuration registers Transmits the error flag register and the error counts Transmits the registers associated with the PWM modules Transmits the values in bytes 0 - 7 of the user memory Transmits the values in bytes 8 -15 of the user memory Transmits a single byte containing the value in an addressed user memory register Uses a mask to write a value to an addressed register 4.3.1.2 Data Frame Message Type Write Register When a non-RTR (or data frame) message type is selected and a node in the system wants information from the MCP2502X/5X, it sends an Information Request in the form of a data frame. The identifier for this request must be such that it will be accepted through the MCP2502X/5X's mask/filter process (using RXF0). Information request messages in the data frame format must not only meet the RXMASK/RXF0 criteria, but must also have the RTR bit of the CAN ID cleared (since the filter registers do not contain an explicit RTR bit). If a message passes the mask/filter process and the RTR bit is a `1', that message will be ignored. Once the MCP2502X/5X has received a data frame information request, it will determine the function to be performed based upon the three LSb's (RXB0SIDL.SID2:SID0 for standard messages and RXB0EID0.EID2:EID0 for extended messages) of the received data frame. Also, Bit 3 of the received message ID must be set to a `1'. In addition, the data length code (DLC) must be set to a zero. Refer to Table 4-2 and Table 4-3 for more information. Regardless of the message format, all messages except the Read Register message can use either standard or extended identifiers. The Read Register message has one additional requirement; it must be an extended identifier. This is discussed in more detail in Table 4-1 and Table 4-3 for more information. Write TX Message Writes the identifiers to a specified ID0 (TXID0) value Write TX Message Writes the identifiers to a specified ID1 (TXID1) value Write TX Message Writes the identifiers to a specified ID2 (TXID2) value Write I/O Configuration Registers Write RX Mask Write RX Filter0 Write RX Filter1 Writes specified values to the three IOCON registers Changes the receive mask to the specified value Changes the specified filter to the specified value Changes the specified filter to the specified value * The Read Register command is available when using extended message format only. Not available with standard message format. DS21664C-page 22 2003 Microchip Technology Inc. MCP2502X/5X 4.3.2 OUTPUT MESSAGES The data frame sent in response to the information request message is defined as an output message. If the data fame is in response to a remote frame, it will have the same identifier (standard or extended) and contain the same number of data bytes specified by the DLC of the remote frame (per the CAN 2.0B specification). Note: If the DLC of the incoming remote frame differs from the message definitions summarized in Table 4-2 and Table 4-3, the resulting output message will limit itself to the erroneous DLC that was received (to maintain compliance with the Bosch CAN specification). The output message will concatenate the number of data bytes for an erroneous DLC that is less than the defined number. For an erroneous DLC that is greater than the defined number, the MCP2502X/5X will extend the number of data bytes, with the data value of the last defined data byte being repeated in the extra bytes in the data field. If the output message is in response to a data frame, the lower-three LSb's of the identifier (standard or extended) must be the same as the received message, as well as the upper-seven MSb's in the case of a standard identifier, or the upper 25 MSb's in the case of an extended identifier. Bit 3 of a standard or extended identifier of the output message will differ from the received information request message in that the value equals `1' for an IRM and equals `0' for the resulting output message. Output messages contain the requested data (in the data field). Example: The information request message Read CAN error is a remote transmit request received by the MCP2502X/5X with a DLC of 3. The responding output message will return a data frame that contains the same identifier (standard or extended) as the receive message. The accompanying data bytes will contain the values of the predefined GPIO registers and related control/status registers, as shown in Table 4-2 and 4-3. three bits of the standard identifier (RXF1SIDL.SID2:SID0) will indicate which register(s) are to be written. The values for the register(s) are contained in the data byte registers as defined in Table 4-2. Note: If using more than one controlling node, the MCP2502X/5X must be set up to accept input messages with different identifiers in order to avoid possible message collisions in the DLC or data bytes if transmitted at the same time. Note 1: IRMs can theoretically be sent by more than one controlling node because the message is a predefined constant and destructive collisions will not occur. 2: The number of data bytes in an input message must match the DLC number as defined in Table 4-2 and Table 4-3. If the user specifies and transmits an input message with a DLC that is less than the required number of data bytes, the MCP25020 will operate on corrupted data for the bytes that it did not receive and unknown results will occur. 4.4 Dynamic Message Handling The design insures that transmit and receive messages are handled properly for variable bus-loading conditions and different transmit/receive combinations. 4.4.1 MESSAGE ACCEPTANCE/ REJECTION Messages received that meet the Mask/RXFn criteria are then compared to the requirements for input messages or IRMs, as determined by the filter used to accept the message. If the message meets the requirements of one of the associated input or information request messages, the appropriate actions for that message function are taken. 4.4.2 RECEIVING MULTIPLE MESSAGES 4.3.3 INPUT MESSAGES Input messages are received into receive buffer 1 and are used to change the values of the pre-defined groups of registers. There is also an input message that can change a single register's contents. The primary purpose of input messages are to reconfigure MCP2502X/5X parameters (if needed) while in an operating CAN system and are, therefore, optional in system implementation. These messages are in the form of standard (or extended) data frames (per the CAN 2.0B specification) that have identifiers which pass the MCP2502X/5X's mask/filter process (using RXF1). After passing the mask and filter, the lower- The MCP2502X/5X can only receive and process one message at a time. While the MCP2502X/5X should have ample time to process any received message before another is completely received, a second message received before the first message is finished processing will be lost. However, the MCP2502X/5X has the ability to notify the network if a message is lost. TXID1 can be configured to transmit a message if a receive overflow occurs (OPTREG2.CAEN = 0). 2003 Microchip Technology Inc. DS21664C-page 23 MCP2502X/5X 4.4.3 TRANSMIT MESSAGE PRIORITY There is a priority for all transmit messages, including TXIDn and all "Output" messages. The transmit message priority is as follows: 1. Output messages have the highest priority. Prioritization of the individual output message types is determined by the three bits that determine message type, with the lowest value having the highest priority (e.g., Read A/D Regs is a higher priority than Read Control Regs). TXID2 (Transmit auto-converted messages) has the second-highest priority. TXID1 (Command acknowledge) has the thirdhighest priority. TXID0 (On Bus message) has the lowest priority. 2. 3. 4. In the event two or more messages are pending transmission, transmit-message-prioritization will occur and the highest message type will be sent first. Messages that are currently transmitting will not be prioritized. DS21664C-page 24 2003 Microchip Technology Inc. TABLE 4-2: COMMAND MESSAGES (STANDARD IDENTIFIER) Information Request Messages (to MCP2502X/5X) Standard ID 19876543210 0 R T R 1* 1* 1* 1* 1* 1* 1* I D E 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 DLC 0 1 0 1 1 0 0 0 1 1 1 0 0 0 8* 7* 5* 3* 6* 8* 8* n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Data Bytes 2003 Microchip Technology Inc. DS21664C-page 25 Read A/D Regs Read Control Regs Read Config Regs Read CAN Error Read PWM Config Read User Mem (bank1) Read User Mem (bank 2) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x * * * * * * * 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Output Messages (from MCP2502X/5X) Standard ID 19876543210RI 0 TD RE Read A/D Regs Read Control Regs Read Config Regs Read CAN Error Read PWM Config Read User Mem (bank1) Read User Mem (bank 2) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x * * * * * * * 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 DLC 0 1 0 1 1 0 0 0 1 1 1 0 0 0 8 7 5 3 6 8 8 IOINTFL ADCON0 DDR EFLG PR1 USERID0 USERID8 GPIO ADCON1 GPIO TEC PR2 USERID1 USERID9 AN0H OPTREG CNF1 REC T1CON USERID2 USERID1 AN1H OPTREG CNF2 n/a T2CON USERID3 USERID1 AN10L STCON CNF3 n/a PWM1DC USERID4 USERID1 AN2H IOINTEN n/a n/a PWM2DC USERID5 USERID1 AN3H IOINTPO n/a n/a n/a USERID6 USERID1 AN32L n/a n/a n/a n/a USERID7 USERID1 Data Bytes Input Messages** (to MCP2502X/5X) Standard ID 19876543210RI 0 TD RE DLC Data Bytes MCP2502X/5X Write Register xxxxxxxx0000000113 addr mask value n/a n/a n/a n/a n/a Write TX Message ID 0 x x x x x x x x 0 0 1 0 0 0 1 0 0 4 TX0SIDH TX0SIDL TX0EID8 TX0EID0 n/a n/a n/a n/a Write TX Message ID 1 x x x x x x x x 0 1 0 0 0 0 1 0 0 4 TX1SIDH TX1SIDL TX1EID8 TX1EID0 n/a n/a n/a n/a Write TX Message ID 2 x x x x x x x x 0 1 1 0 0 0 1 0 0 4 TX2SIDH TX2SIDL TX2EID8 TX2EID0 n/a n/a n/a n/a Write I/O Configuration x x x x x x x x 1 0 0 0 0 0 1 0 1 5 IOINTEN IOINTPO DDR OPTREG ADCON1 n/a n/a n/a Write RX Mask x x x x x x x x 1 0 1 0 0 0 1 0 0 4 RXMSIDH RXMSIDL RXMEID8 RXMEID0 n/a n/a n/a n/a Write RX Filter0 x x x x x x x x 1 1 0 0 0 0 1 0 0 4 RXF0SID RXF0SID RXF0EID RXF0EID n/a n/a n/a n/a Write RX Filter1 x x x x x x x x 1 1 1 0 0 0 1 0 0 4 RXF1SID RXF1SID RXF1EID RXF1EID n/a n/a n/a n/a * If using non-RTR messages for information request messages (IRM), the RTR bit = 0, DLC bit field = 0, and bit 3 of the IRM ID = 1. Also, bit 3 of the output message ID = 0. If using RTR messages for IRMs, the RTR bit = 1, DLC bit field = number of bytes in corresponding output message, and bit three of the IRM ID = x (don't care), also, bit 3 of the output message = x (don't care). ** User-defined IRM IDs must be different from input message IDs to avoid message contention between the corresponding output message and the input message. TABLE 4-3: COMMAND MESSAGES (EXTENDED IDENTIFIER) Information Request Messages (to MCP2502X/5X) Standard ID 1987654321 0RI 0 TD RE DLC 11 76 8* 7* 5* 3* 6* 8* 8* 1* x x x x x x x x x x x x x x x x Extended ID RXBEID8 (8 bits) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx addr RXBEID0 (8 bits) xxxx *000 xxxx *001 xxxx *010 xxxx *011 xxxx *100 xxxx *101 xxxx *110 xxxx *111 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Data Bytes DS21664C-page 26 2003 Microchip Technology Inc. MCP2502X/5X Read A/D Regs Read Control Regs Read Config Regs Read CAN Error Read PWM Config Read User Mem Read User Mem Read Register x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 Output Messages (from MCP2502X/5X) Standard ID 1987654321 0RI 0 TD RE Read A/D Regs Read Control Regs Read Config Regs Read CAN Error Read PWM Config Read User Mem Read User Mem Read Register x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 DLC Extended ID 1 1 RXBEID8 7 6 (8 bits) 8 7 5 3 6 8 8 1 x x x x x x x x x x x x x x x x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx addr RXBEID0 (8 bits) xxxx *000 xxxx *001 xxxx *010 xxxx *011 xxxx *100 xxxx *101 xxxx *110 xxxx *111 IOINTFL GPIO AN0H AN1H AN10L AN2H AN3H AN32L ADCON0 ADCON1 OPTREG OPTREG STCON IOINTEN IOINTPO n/a DDR GPIO CNF1 CNF2 CNF3 n/a n/a n/a EFLG TEC REC n/a n/a n/a n/a n/a PR1 PR2 T1CON T2CON PWM1D PWM2D n/a n/a USERID0 USERID1 USERID2 USERID3 USERID4 USERID5 USERID6 USERID7 USERID8 USERID9 USERID1 USERID1 USERID1 USERID1 USERID1 USERID1 value n/a n/a n/a n/a n/a n/a n/a Data Bytes 0 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 Input Messages (to MCP2502X/5X) Standard ID 1987654321 0RI 0 TD RE DLC Extended ID 1 1 RXBEID8 7 6 (8 bits) RXBEID0 (8 bits) Data Bytes Write Register x x x x x x x x x x x 0 1 0 0 1 1 3 x x xxxx xxxx xxxx x000 addr mask value n/a n/a n/a n/a n/a Write TX Message x x x x x x x x x x x 0 1 0 1 0 0 4 x x xxxx xxxx xxxx x001 TX0SIDH TX0SIDL TX0EID8 TX0EID0 n/a n/a n/a n/a Write TX Message x x x x x x x x x x x 0 1 0 1 0 0 4 x x xxxx xxxx xxxx x010 TX1SIDH TX1SIDL TX1EID8 TX1EID0 n/a n/a n/a n/a Write TX Message x x x x x x x x x x x 0 1 0 1 0 0 4 x x xxxx xxxx xxxx x011 TX2SIDH TX2SIDL TX2EID8 TX2EID0 n/a n/a n/a n/a Write I/O Configura- x x x x x x x x x x x 0 1 0 1 0 1 5 x x xxxx xxxx xxxx x100 IOINTEN IOINTPO DDR OPTREG ADCON1 n/a n/a n/a Write RX Mask x x x x x x x x x x x 0 1 0 1 0 0 4 x x xxxx xxxx xxxx x101 RXMRXMSIDL RXMEID8 RXMEID0 n/a n/a n/a n/a Write RX Filter0 x x x x x x x x x x x 0 1 0 1 0 0 4 x x xxxx xxxx xxxx x110 RXF0SID RXF0SID RXF0EID RXF0EID n/a n/a n/a n/a Write RX Filter1 x x x x x x x x x x x 0 1 0 1 0 0 4 x x xxxx xxxx xxxx x111 RXF1SID RXF1SID RXF1EID RXF1EID n/a n/a n/a n/a * If using non-RTR messages for information request messages (IRM), the RTR bit = 0, DLC bit field = 0, and bit 3 of the IRM ID = 1. Also, bit 3 of the output message ID = 0. If using RTR messages for IRMs, the RTR bit = 1, DLC bit field = number of bytes in corresponding output message, and bit three of the IRM ID = x (don't care), also, bit 3 of the output message = x (don't care). ** User-defined IRM IDs must be different from input message IDs to avoid message contention between the corresponding output message and the input message. MCP2502X/5X 4.5 Automatic Transmission A hysteresis example: * The user sets the upper-eight bits of the 10-bit compare register (ADCMP0H). The lower-two bits of the compare register are not configurable by the user and are forced to either b'11' or b'00' depending on the polarity of the compare threshold (i.e., transmit is triggered above or below the compare value via the IOINTPO register). * The user sets the polarity of the compare threshold (IOINTPO). In this example, the threshold is set for triggering a message on an A/D > compare register. The two LSb's are forced to b'11'. * When the A/D conversion exceeds the compare register (b'nnnn nnnn 11'), an automatic transmission will occur once. * In order for the automatic transmission to occur again, the A/D value must first drop below the compare register b'nnnn nnnn 00' and then back above the compare register b'nnnn nnnn 11'. The MCP2502X/5X can automatically initiate four different message types to indicate the following situations: * * * * Edge detected on a digital input (TXID2). Threshold exceeded on an analog input (TXID2). Error condition (Read Error output message). Scheduled transmissions (TXID0). The buffers have an implied transmit priority, where buffer 2 is the highest and buffer 0 is the lowest. Therefore, multiple message buffers can be requested for transmission and each one will be sent in order of priority. 4.5.1 DIGITAL INPUT EDGE DETECTION Each GPIO pin configured as a digital input can be individually configured to automatically transmit a message when a defined edge occurs, as explained in the GPIO module section. When transmitting this message, the MCP2502X/5X uses TXID2. The DLC is set to two and the first two bytes of the Read A/D registers (IOINTFL and GPIO) are sent. FIGURE 4-1: 4.5.2 ANALOG INPUT THRESHOLD DETECTION HYSTERESIS FUNCTION Each GPIO pin that has been configured as an analog input can be individually configured to automatically transmit a message when a threshold is exceeded as described in the Analog-to-Digital Converter Module section. The MCP2502X/5X sends TXID2 when transmitting this message. The DLC is set to eight and the eight bytes of the `Read A/D Registers' are sent. Note: The GPIO register that is sent with the message (data byte 2) can be ignored if there are no digital inputs enabled for change-of-state, as it contains no useful information for the Analog Input Threshold Detect function. Set to Trigger when A/D>Compare Register LSbs = b'11' LSbs = b'00' A/D above compare, A/D above compare, Message sent Message sent A/D below compare, Reset Set to Trigger when A/D 4.5.2.1 Hysteresis Function This function is automatic and will insure that an analog value that is on the compare edge (i.e., toggling LSb) does not fill the CAN bus with continuous A/D message transmissions. The hysteresis uses the two LSb's of the compare register. These two bits are forced and are not configurable by the user. They will be forced to either b'00' or b'11', depending on the compare polarity. If configured for A/D result > compare register, the automatic transmission will occur when the A/D value is greater than or equal to b'nnnn nnnn 11' and reset when less than or equal to b'nnnn nnnn 00'. The opposite conditions must occur if the compare polarity is set for A/D result < compare register. 4.5.3 ERROR CONDITION The MCP2502X/5X can be configured to automatically transmit a message whenever one or more of the following error conditions occur: * * * * * Receiver has entered error-warning state Receiver has entered error-passive state Transmitter has entered error-warning state Transmitter has entered error-passive state A Receive buffer has overflowed 2003 Microchip Technology Inc. DS21664C-page 27 MCP2502X/5X If the Error Condition message is enabled (OPTREG2.TXONE = 1) and one of the above conditions occur, the MCP2502X/5X sends TXID1 identifier with output message Read CAN Error States data field (three data bytes). Scheduled Transmission = STBF1:STBF0(STM3:STM0) Message Type - The message sent for scheduled transmissions consists of either TXID0 with zero data bytes or TXID0 with eight data bytes containing the Read A/D Regs message, depending on STMS bit in the STCON register. Note: The actual scheduled transmission intervals may vary slightly due to the internal event que of the control module. 4.5.4 SCHEDULED TRANSMISSIONS The MCP2502X/5X has the capability of sending scheduled transmissions (On Bus message), if enabled. The scheduled transmission control register (STCON) enables and configures the occurrence of the scheduled message. Setting the STEN bit in the STCON register enables the scheduled message. The STBF1:STBF0 and STM3:STM0 bits allow a scheduled transmission to be initiated from a minimum of 256 s to a maximum of 16.8 seconds (using a 16 MHz FOSC) and the following equation: REGISTER 4-1: STCON - SCHEDULED TRANSMISSION CONTROL REGISTER R/W-0 STEN bit 7 R/W-0 STMS R/W-1 STBF1 R/W-1 STBF0 R/W-1 STM3 R/W-1 STM2 R/W-1 STM1 R/W-1 STM0 bit 0 bit 7 STEN: Scheduled Transmission Enable bits 1 = Enabled 0 = Disabled STMS: Scheduled Transmission Message Select 1 = Sends Transmit ID 0 (TXID0) with the "Read A/D Regs" data (DLC = 8) 0 = Sends Transmit ID 0 (TXID0) with no data (DLC = 0) STBF1:STBF0: Base Transmission Frequency bits 00 = 4096TOSC 01 = 16*(4096TOSC) 10 = 256*(4096TOSC) 10 = 4096*(4096TOSC) (e.g., STBF1:STBF0 => 00 => 256 s for a 16 MHz FOSC) STM3:STM0: Scheduled Transmission Multiplier bits 0000 = 1 0001 = 2 1110 = 15 1111 = 16 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 6 bit 5-4 bit 3-0 DS21664C-page 28 2003 Microchip Technology Inc. MCP2502X/5X TABLE 4-4: Addr 0Bh 0Ch 0Dh 10h 11h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh Name CNF1 CNF2 CNF3 STCON OPTREG2 RXMSIDH RXMSIDL RXMEID8 RXMEID0 RXF0SIDH RXF0SIDL RXF0EID8 RXF0EID0 RXF1SIDH RXF1SIDL RXF1EID8 RXF1EID0 TXB0SIDH TXB0SIDL TXB0EID8 TXB0EID0 TXB1SIDH TXB1SIDL TXB1EID8 TXB1EID0 TXB2SIDH TXB2SIDL TXB2EID8 TXB2EID0 REGISTERS ASSOCIATED WITH THE CAN MODULE bit7 SJW1 BTLMODE -- STEM CAEN SID10 SID2 EID15 EID7 SID10 SID2 EID15 EID7 SID10 SID2 EID15 EID7 SID10 SID2 EID15 EID7 SID10 SID2 EID15 EID7 SID10 SID2 EID15 EID7 bit6 SJW0 SAM WAKF STMS ERRE SID9 SID1 EID14 EID6 SID9 SID1 EID14 EID6 SID9 SID1 EID14 EID6 SID9 SID1 EID14 EID6 SID9 SID1 EID14 EID6 SID9 SID1 EID14 EID6 bit5 BRP5 PHSEG12 -- STBF1 TXONE SID8 SID0 EID13 EID5 SID8 SID0 EID13 EID5 SID8 SID0 EID13 EID5 SID8 SID0 EID13 EID5 SID8 SID0 EID13 EID5 SID8 SID0 EID13 EID5 bit4 BRP4 PHSEG11 -- STBF0 SLPEN SID7 -- EID12 EID4 SID7 -- EID12 EID4 SID7 -- EID12 EID4 SID7 -- EID12 EID4 SID7 -- EID12 EID4 SID7 -- EID12 EID4 bit3 BRP3 PHSEG10 -- STM3 MTYPE SID6 -- EID11 EID3 SID6 -- EID11 EID3 SID6 -- EID11 EID3 SID6 EXIDE EID11 EID3 SID6 EXIDE EID11 EID3 SID6 EXIDE EID11 EID3 bit2 BRP2 PRSEG2 PHSEG22 STM2 PDEFEN SID5 -- EID10 EID2 SID5 -- EID10 EID2 SID5 -- EID10 EID2 SID5 -- EID10 EID2 SID5 -- EID10 EID2 SID5 -- EID10 EID2 bit1 BRP1 PRSEG1 PHSEG21 STM1 PUSLP SID4 EID17 EID9 EID1 SID4 EID17 EID9 EID1 SID4 EID17 EID9 EID1 SID4 EID17 EID9 EID1 SID4 EID17 EID9 EID1 SID4 EID17 EID9 EID1 bit0 BRP0 PRSEG0 PHSEG20 STM0 PUNRM SID3 EID16 EID8 EID0 SID3 EID16 EID8 EID0 SID3 EID16 EID8 EID0 SID3 EID16 EID8 EID0 SID3 EID16 EID8 EID0 SID3 EID16 EID8 EID0 Value on POR xxxx xxxx xxxx xxxx -x-- xxxx 0xxx xxxx 0000 0000 xxxx xxxx xxx- --xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- --xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- --xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx Value on RST uuuu uuuu uuuu uuuu -u-- uuuu 0uuu uuuu uuuu uuuu uuuu uuuu uuu- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu 2003 Microchip Technology Inc. DS21664C-page 29 MCP2502X/5X NOTES: DS21664C-page 30 2003 Microchip Technology Inc. MCP2502X/5X 5.0 5.1 GPIO MODULE Description 5.2 Digital Input Edge Detection The MCP2502X/5X has eight general-purpose input/ output pins (GP0 to GP7), collectively labeled GPIO. All GPIO port pins have TTL input levels and full CMOS output drivers, with the exception of GP7, which is input only. Pins GP6:GP0 can be individually configured as input or output via the GPDDR register. Note: The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure that the bits in the GPDDR register are maintained set (input) when using them as analog inputs. All GPIO pins have a digital input edge detection feature that will automatically transmit a message when an edge with the proper polarity occurs on any of the digital inputs. Only pins configured as inputs and enabled for this function via control register IOINTPO will perform this operation. Note: Refer to Section 7.4 "A/D Threshold Detection" for information regarding A/D channels. Each of the GPIO pins has a weak internal pull-up resistor. A single control bit (OPTREG.GPPU) can turn on/off all the pull-ups. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled during a Power-on Reset. All pins are multiplexed with an alternate function, including analog-to-digital conversion on up to four of the GPIO pins, analog VREF inputs up to two pins, PWM outputs up to two pins, clock-out function and external reset. The operation of each pin is selected by clearing, or setting, control bits in various control registers. GPIO pin functions are summarized in Table 5-1. Three control registers are associated with this function. An enable pin for each GPIO pin resides in the IOINTEN register. When a bit is set to a '1', the corresponding GPIO pin is enabled to generate a transmit-on-change message (TXID2) when an edge of specified polarity occurs. The digital edge detection function on a GPIO pin configured as a digital input is edge triggered. A risingedge will generate a transmission if the corresponding bit in the IOINTPO register is set. A falling-edge will generate a transmission if the bit is cleared. When a valid edge appears on the enabled GPIO pin, CAN message TXID2 is initiated. The edge-detection function on any given GPIO pin (configured as a digital input) can wake up the processor from SLEEP if the corresponding interrupt enable bit in the IOINTEN register was set prior to going into SLEEP mode. If a wake-up from SLEEP is caused in this manner, the device will immediately initiate a transmit message (TXID2). TABLE 5-1: Name GP0/AN0 GP1/AN1 GP2/AN2/PWM2 GP3/AN3/PWM3 GP4/VREFGP5/VREF+ GP6/CLKOUT GP7/nRST/VPP GPIO FUNCTIONS Bit # Function bit0 I/O or analog input bit1 I/O or analog input bit2 I/O, analog input or PWM out bit3 I/O, analog input or PWM out bit4 I/O or analog voltage reference bit5 I/O or analog voltage reference bit6 I/O or Clock output bit7 Input, external reset input or programming voltage input 2003 Microchip Technology Inc. DS21664C-page 31 MCP2502X/5X REGISTER 5-1: GPDDR - DATA DIRECTION REGISTER U-0 -- bit 7 bit 7 bit 6-0 Unimplemented: Read as `0' DDR6:DDR0: Data Direction Register* bits 1 = corresponding GPIO pin is configured as an input 0 = corresponding GPIO pin is configured as an output * must bet set if corresponding analog channel is enabled (see ADCON1) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 DDR6 R/W-1 DDR5 R/W-1 DDR4 R/W-1 DDR3 R/W-1 DDR2 R/W-1 DDR1 R/W-1 DDR0 bit 0 REGISTER 5-2: GPLAT - GPIO OUTPUT REGISTER U-0 -- bit 7 R/W-0 GP6 R/W-0 GP5 R/W-0 GP4 R/W-0 GP3 R/W-0 GP2 R/W-0 GP1 R/W-0 GP0 bit 0 bit 7 bit 6-0 Unimplemented: Read as '0' GP6:GP0: GPIO Bits 1 = corresponding GPIO pin output latch is a `1' 0 = corresponding GPIO pin output latch is a `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 5-3: IOINTEN REGISTER R/W-0 GP7TXC bit 7 R/W-0 GP6TXC R/W-0 GP5TXC R/W-0 GP4TXC R/W-0 GP3TXC R/W-0 GP2TXC R/W-0 GP1TXC R/W-0 GP0TXC bit 0 bit 7-0 GP7TXC:GP0TXC: Transmit-on-change Enable bits 1 = Enable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel 0 = Disable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS21664C-page 32 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 5-4: IOINTPO REGISTER R/W-0 GP7POL bit 7 bit 7-0 R/W-0 GP6POL R/W-0 GP5POL R/W-0 GP4POL R/W-0 GP3POL R/W-0 GP2POL R/W-0 GP1POL R/W-0 GP0POL bit 0 GP7POL:GP0POL: Transmit-on-change Polarity bits 1 = Digital Inputs: Low-to-High Transition On Corresponding GPIO Input Pin Generates a transmit message Analog Inputs: A/D result above compare value generates a transmit message 0 = Digital Inputs: High-to-Low Transition On Corresponding GPIO Input Generates transmit message Analog Inputs: A/D result below compare value generates a transmit message Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 5-5: IOINTFL REGISTER R-0 GP7TXF bit 7 R-0 GP6TXF R-0 GP5TXF R-0 GP4TXF R-0 GP3TXF R-0 GP2TXF R-0 GP1TXF R-0 GP0TXF bit 0 bit 7-0 GP7TXF:GP0TXF: Transmit-on-change Polarity bits 1 = Digital Inputs: A valid edge has occurred on the digital input Analog Inputs: A/D result does exceed the compare threshold 0 = Digital Inputs: A valid edge has not occurred on the digital input Analog Inputs: A/D result does not exceed the compare threshold Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown 2003 Microchip Technology Inc. DS21664C-page 33 MCP2502X/5X REGISTER 5-6: OPTREG1 REGISTER R/W-1 GPPU bit 7 bit 7 GPPU: Weak pull-up enabled 1 = Weak pull-ups disabled 0 = Weak pull-ups enabled (GP7:GP0) CLKEN: 1 = Clock Out Function disabled 0 = Clock Out Function enabled CLKPS1:CLKPS0: CLKOUT Prescaler bits 00 = FOSC/1 01 = FOSC/2 10 = FOSC/4 11 = FOSC/8 Reserved: CMREQ: Requests mode of operation (allows mode changes via the CAN bus) 1 = Requests Listen-only mode 0 = Requests Normal mode * * CMREQ must be cleared as default to avoid device entering Listen-only mode on first "Input" message. AQT1:AQT0: Analog Acquisition Time bits 00 = 64TOSC 01 = 2*(64TOSC) 10 = 4*(64TOSC) 11 = 8*(64TOSC) (e.g., AQT1:AQT0 => 00 => 2.56 s for a 25 MHz FOSC) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 CLKEN R/W-1 CLKPS1 R/W-1 CLKPS0 U-0 -- R/W-0 CMREQ R/W-0 AQT1 R/W-0 AQT0 bit 0 bit 6 bit 5-4 bit 3 bit 2 bit 1-0 DS21664C-page 34 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 5-7: OPTREG2 REGISTER R/W-0 CAEN bit 7 bit 7 CAEN: Command Acknowledge Enable bit 1 = Enables the command acknowledge message (TXID1) 0 = Enables the receive overflow message (TXID1) ERREN: Error Recovery Enable bit 1 = MCP2502X/5X will recover into Listen-only mode from bus off 0 = MCP2502X/5X will recover into Normal mode from bus-off TXONEN: Transmit on Error Condition bit(REC or TEC) 1 = Enable, will send message if error counter(s) go high enough 0 = Disable, will NOT send message regardless of error counter values SLPEN: Low power SLEEP mode enable/disable 1 = Device will enter Sleep if bus is idle for at least 1408 bit times 0 = SLEEP mode is disabled MTYPE: Determines if information request messages use RTR or not 1 = RTR is NOT used for IRM (Data Frame) 0 = RTR is used for IRM (Remote Frame) PDEFEN: Enables PWM outputs to return to POR default values when CAN bus communication is lost 1 = Enables PWM output default values 0 = Disables PWM output default values PUSLP: Allows device to enter SLEEP while in Listen-only mode during power-up sequence 1 = Enables SLEEP when in Listen-only mode during power-up sequence 0 = Disables SLEEP when in Listen-only mode during power-up sequence PUNRM: Enters Normal mode after completing self-configuration during power-up sequence 1 = Enters "Normal" mode after completing self-configuration during power-up sequence 0 = Enables "Listen-only" mode after completing self-configuration during power-up sequence and waits for an error-free message before switching to Normal mode Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ERREN R/W-0 TXONEN R/W-0 SLPEN R/W-0 MTYPE R/W-0 PDEFEN R/W-0 PUSLP R/W-0 PUNRM bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TABLE 5-2: Addr Bank 0 34h 00h 01h 04h GPDDR IOINTEN IOINTPO OPTREG1 Name SUMMARY OF REGISTERS ASSOCIATED WITH GPIO MODULE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Value on POR Value on RST -- GP7TXC GP7POL GPPU DDR6 GP6TXC GP6POL CLKEN DDR5 GP5TXC GP5POL CLKPS1 DDR4 GP4TXC GP4POL CLKPS0 DDR3 GP3TXC GP3POL -- DDR2 GP2TXC GP2POL CMREQ DDR1 GP1TXC GP1POL AQT1 DDR0 GP0TXC GP0POL AQT0 -111 1111 -111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 ---- Legend: x = unknown, U = unchanged, - = unimplemented read as `0'. Shaded cells are not used by module. 2003 Microchip Technology Inc. DS21664C-page 35 MCP2502X/5X NOTES: DS21664C-page 36 2003 Microchip Technology Inc. MCP2502X/5X 6.0 6.1 PWM MODULE Description reconfigure to their default conditions. This includes the PWM module itself being disabled and the GPIO being forced low, high or tri-state. There are two Pulse Width Modulation (PWM) modules (PWM1 and PWM2) that generate up to a 10-bit resolution output signal on GP2 and GP3, respectively. Each of these outputs can be separately enabled, with each having its own associated timer, duty cycle and period registers for controlling the PWM output shape. Each PWM module contains a set of master/slave duty cycle registers, providing up to a 10-bit resolution PWM output. Figure 6-1 shows a simplified block diagram of the PWM module. A PWM output has a time base (period) and a time that the output stays high (duty cycle), as shown in Figure 6-2. The frequency of the PWM is the inverse of the period (1/period). At power-on, the PWM outputs are not enabled until after the self-configuration sequence has been completed (i.e., all SRAM registers have been loaded with their default values) to prevent invalid signals from occurring on the PWM outputs. FIGURE 6-2: Period PWM OUTPUT Duty Cycle TMRn = PRn TMRn = PRn TMRn=Duty Cycle 6.2 PWM Timer Modules There are two 8-bit timers supporting the two PWM outputs. Both timers have a prescaler only. The timers are readable and writable and are cleared on any device reset or when the timer is turned off. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits TnCKPS[1:0] in register TnCON<5:4> (where n corresponds to the appropriate timer). Each timer module has an 8-bit period register, PRn. PRn is a readable and writable register. The timer module increments from 00h until it matches PRn and then resets to 00h on the next increment cycle. The PRn register is set when the device is reset. Each timer can be shut off by clearing control bit TMRnON (TnCON<7>). FIGURE 6-1: Duty cycle registers PWMnDCH SIMPLIFIED BLOCK DIAGRAM TnCON (2 LSB) PWMnDBH 6.2.1 Comparator R S Q GP TIMER MODULE PRESCALER The prescaler counters are cleared when a write to the TnCON or TMRn register or any device reset (RST reset or Power-on reset) occurs. TMRn Note 1 6.3 PWM Modules Comparator Each PWM module contains a set of master/slave duty cycle registers, providing up to a 10-bit resolution PWM output. Figure 6-2 shows a simplified block diagram of the PWM module. Prn 6.3.1 Q clock or 2 bits of the prescaler to create 10-bit time base PWM PERIOD Note 1: 8-bit timer is concatenated with 2-bit internal The PWM period is specified by writing to the PRn register. The PWM period can be calculated using the following formula: PWM period = [ ( PR n ) + 1 ]*4T OSC * ( TMRn prescale value ) The PWM outputs can be forced to their default POR conditions if CAN bus communication is lost and is enabled via OPTREG2.PDEFEN. The system designer must implement a hand-shaking protocol, such that the MCP2505X will receive a valid message into one of the receive buffers before four successive scheduled transmissions occur. If a valid message is not received, the PWM outputs GP2 and GP3 will automatically PWM frequency = 1 ( PWM period ) When TMRn is equal to PRn, the following two events occur on the next cycle: * TMRn is cleared * The PWM duty cycle is latched from PWMnDCH into PWMnDBH 2003 Microchip Technology Inc. DS21664C-page 37 MCP2502X/5X 6.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the PWMnDCH and TnCON registers. Up to 10-bit resolution is available. The PWMnDCH contains the eight MSb's, while the TnCON register contains the two LSb's. This 10-bit value is represented by PWM1DCH:T1CON<1:0> for PWM Module 1 and PWM2DCH:T2CON<1:0> for PWM Module 2. The following equation is used to calculate the PMW duty cycle: PWMDC = ( PWMnDC ) *T OSC *TMRn (prescale) PWMnDCH can be written to at any time, but the duty cycle value is not latched into PWMnDBH until after a match between PRn and TMRn occurs (i.e., the period is complete). The PWMnDBH register and 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the PWMnDBH and 2-bit latch match TMRn concatenated with an internal 2-bit Q clock or 2 bits of the TMRn prescaler, the PWM output pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency is equal to: log ( ( F OSC ) ( Fpwm ) ) ( log ( 2 )bits ) Note: If the PWM duty cycle value is longer than the PWM period (PWM duty cycle = 100%), the PWM output pin will not be cleared. In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. Table 6-1 lists example PWM frequencies and resolutions for FOSC = 20 MHz. TMRn prescaler and PRn values are also shown. TABLE 6-1: PWM FREQUENCIES AND RESOLUTIONS AT 20 MHZ 1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 156.30 kHz 208.30 kHz 1 0x3F 8 1 0x1F 7 1 0x17 5.5 PWM Frequency Timer Prescaler (1, 4, 16) PRn Value Maximum Resolution (bits) REGISTER 6-1: PWM1 DUTY CYCLE REGISTER MSB (PWM1DCH) R/W-x DC1B9 bit 7 R/W-x DC1B8 R/W-x DC1B7 R/W-x DC1B6 R/W-x DC1B5 R/W-x DC1B4 R/W-x DC1B3 R/W-x DC1B2 bit 0 bit 7-0 DC1B9:DC1B2: Most Significant PWM0 Duty Cycle bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 6-2: PWM2 DUTY CYCLE REGISTER MSB (PWM2DCH) R/W-x DC2B9 bit 7 R/W-x DC2B8 R/W-x DC2B7 R/W-x DC2B6 R/W-x DC2B5 R/W-x DC2B4 R/W-x DC2B3 R/W-x DC2B2 bit 0 bit 7-0 DC2B9:DC2B2: Most Significant PWM2 Duty Cycle bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS21664C-page 38 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 6-3: T1CON: TIMER1 CONTROL REGISTER R/W-0 TMR1ON bit 7 bit 7 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Disables Timer1 Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Unimplemented: Read as '0' DC1B1:DC1B0: Least Significant PWM1 Duty Cycle bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 U-0 -- U-0 -- R/W-x DC1B1 R/W-x DC1B0 bit 0 T1CKPS1 T1CKPS0 bit 6 bit 5-4 bit 3-2 bit 1-0 REGISTER 6-4: T2CON: TIMER2 CONTROL REGISTER R/W-0 TMR2ON bit 7 U-0 -- R/W-0 R/W-0 U-0 -- U-0 -- R/W-x DC2B1 R/W-x DC2B0 bit 0 T2CKPS1 T2CKPS0 bit 7 TMR2ON: Timer2 On bit 1 = Enables Timer2 0 = Disables Timer2 Unimplemented: Read as '0' T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Unimplemented: Read as '0' DC2B1:DC2B0: Least Significant PWM2 Duty Cycle bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 6 bit 5-4 bit 3-2 bit 1-0 2003 Microchip Technology Inc. DS21664C-page 39 MCP2502X/5X REGISTER 6-5: PR1: PERIOD REGISTER R/W-x PR1B7 bit 7 bit 7-0 PR1B7:PR1B0: PWM1 Period Register bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x PR1B6 R/W-x PR1B5 R/W-x PR1B4 R/W-x PR1B3 R/W-x PR1B2 R/W-x PR1B1 R/W-x PR1B0 bit 0 REGISTER 6-6: PR2: PERIOD REGISTER R/W-x PR2B7 bit 7 R/W-x PR2B6 R/W-x PR2B5 R/W-x PR2B4 R/W-x PR2B3 R/W-x PR2B2 R/W-x PR2B1 R/W-x PR2B0 bit 0 bit 7-0 PR2B7:PR2B0: PWM2 Period Register bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TABLE 6-2: Addr 34h 05h 06h 07h 08h 09h 0Ah Name GPDDR T1CON T2CON PR1 PR2 PWM1DCH PWM2DCH REGISTERS ASSOCIATED WITH THE PWM MODULE bit7 -- TMR1ON TMR2ON bit6 DDR6 -- -- bit5 DDR5 T1CKPS1 T2CKPS1 bit4 DDR4 T1CKPS0 T2CKPS0 bit3 DDR3 -- -- bit2 DDR2 -- -- bit1 DDR1 DC1B1 DC2B1 bit0 DDR0 DC1B0 DC2B0 Value on POR Value on RST -111 1111 -111 1111 0-00 --xx 0-00 --uu 0-00 --xx 0-00 --uu 1111 1111 1111 1111 1111 1111 1111 1111 Timer 1 Module's Period Register Timer 2 Module's Period Register DC1B9 DC2B9 DC1B8 DC2B8 DC1B7 DC2B7 DC1B6 DC2B6 DC1B5 DC2B5 DC1B4 DC2B4 DC1B3 DC2B3 DC1B2 DC2B2 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Legend: x = unknown, U = unchanged, - = unimplemented read as `0'. Shaded cells are not used by module. DS21664C-page 40 2003 Microchip Technology Inc. MCP2502X/5X 7.0 7.1 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE Description 7.3 A/D Conversion Modes The Analog-to-Digital (A/D) module is a four-channel, 10-bit successive approximation type of A/D. The A/D allows conversion of an analog input signal to a corresponding 10-bit number. The four channels are multiplexed on the GP[3:0] pins. The converter is turned off/on via the ADCON0 register and each channel is individually enabled via the ADCON1 control register. The VREF+ and VREF- sources are userselectable as internal or external. Each channel can be set to one of two conversion modes: 1. 2. Auto-conversion Convert-on-request. There are two modes of conversion that can be individually selected for each analog channel that has been enabled. These are auto-conversion and conversion-on-request. 7.3.1 AUTO-CONVERSION MODE If the Auto-conversion mode is selected (STCON), an A/D conversion is performed sequentially for each channel that has been set to Analog Input mode and has been configured for Auto-conversion mode. Conversion starts with AN0 and is immediately followed by AN1, etc. Once the conversion has completed, the value is stored in the analog channel registers for the respective channel. The rate of the auto-conversion is determined by a timer and prescaler. The formula for determining conversion rates is: ( T OSC ) ( 1024 ) ( Prescaler rate ) Typical conversion rates with a 20 MHz oscillator input are shown in Table 7-1. 7.2 A/D Module Registers The A/D module itself has several registers. The registers are: * * * * * A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) Transmit-on-Change Register (IOINTEN) Compare and Polarity Register (ADCMPnL) A/D Result Registers (ADRESnL, ADRESnH) TABLE 7-1: AUTO-CONVERSION RATES FOR GIVEN PRESCALE RATES AT 20 MHZ Prescale Rate 1:1 1:8 1:32 1:128 1:512 1:1024 1:2048 1:4096 Auto-Conversion Rate 51 s 410 s 2 ms 7 ms 26 ms 52 ms 105 ms 210 ms The ADCON0 register controls the operation of the A/D module, including auto-conversion rate and enable bit. The ADCON1 register enables the A/D function on port pins GP3:GP0, A/D conversion rate and selects the voltage reference source. The IOINTEN register's four least significant bits enable/disable the transmiton-change function. The ADCMPnL.ADPOL bit sets the polarity (above or below threshold) for the transmiton-change function. The result of an A/D conversion is made available to the user within the data field of the Read A/D Registers output message via the CAN bus. This message can be directly requested by another CAN node or be automatically transmitted (TXIDO), as has been described previously. Additionally, the individual channel results may be read using the "Read Register" command as described in Section 4.3.1 "Information Request Messages" and as shown in Table 3-2 by addressing the appropriate A/D result register (ADRESnL and ADRESnH). Note: The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure that the bits in the GPDDR register are maintained set (input) when using them as analog inputs. TOPS[2:0] 000 001 010 011 100 101 110 111 The timer is turned on if one of the GPnTXC bits are set in the IOINTEN register and configured as analog input. The prescaler counter is cleared when the device is reset (RST reset or Power-on reset). 2003 Microchip Technology Inc. DS21664C-page 41 MCP2502X/5X 7.3.2 CONVERSION-ON-REQUEST MODE 7.4 A/D Threshold Detection If the Conversion-on-request mode is selected, the device performs an A/D conversion only after receiving a Read A/D Registers or Read Register Receive message (IRM). In the case of the Read A/D Registers command, all of the GPIO pins that have been configured as analog input channels will have an A/D conversion done before the data frame is sent. When a Read Register Receive message is initiated (extended message format only), the A/D conversion is performed when the MSB of the analog channel is requested, with the MSB result being transferred. A subsequent read of the LSB will transmit the value latched when the MSB was requested (it is recommended that the Read A/D Registers receive message is used to obtain complete analog channel values in one message). Once an A/D auto-conversion has been completed, the A/D channel result(s) can be compared to a value stored in the associated A/D channel comparator registers. If the value in the analog channel result registers (i.e., AN0L and AN10H registers for analog channel 0) is lower or higher than the value in the A/D comparator registers (as specified by a corresponding polarity bit), a transmit-on-change message will be sent (TXID2). The threshold-detection function for all analog channels is bit-selectable. If the A/D channel has been configured for transmit-onchange mode, the MCP2505 will send a transmit message with the appropriate data. It is possible that more than one A/D channel has a change-of-state condition. This does not pose a problem since all analog channel data is provided in the transmit message. REGISTER 7-1: A/D MODULE RESULT REGISTER MSB (ADRESNH) R-x AD9 bit 7 R-x AD8 R-x AD7 R-x AD6 R-x AD5 R-x AD4 R-x AD3 R-x AD2 bit 0 bit 7-0 AD9:AD2: Most Significant A/D Result bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 7-2: A/D MODULE RESULT REGISTER LSB (ADRESNL) R-x AD1 bit 7 R-x AD0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 bit 7-6 bit 5-0 AD1:AD0: Least significant A/D Result bits Unimplemented: Reads as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS21664C-page 42 2003 Microchip Technology Inc. MCP2502X/5X REGISTER 7-3: A/D MODULE COMPARE REGISTER MSB (ADCMPNH) R/W-x R/W-x R/W-x R/W-x ANnCMP5 R/W-x R/W-x R/W-x bit 0 ANnCMP4 ANnCMP3 ANnCMP2 R/W-x bit 7 bit 7-0 ANnCMP9:ANnCMP2: Most Significant A/D Compare bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ANnCMP9 ANnCMP8 ANnCMP7 ANnCMP6 REGISTER 7-4: A/D MODULE COMPARE REGISTER LSB (ADCMPNL) R/W-x U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-x bit 7 bit 7-6 bit 5-0 ANnCMP1 ANnCMP0 ANnCMP1:ANnCMP0: Least Significant A/D Compare bits Unimplemented: Reads as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 7-5: ADCON0 REGISTER R/W-0 ADON bit 7 R/W-0 T0PS2 R/W-0 T0PS1 R/W-0 T0PS0 U-x -- U-0 -- U-x -- U-x -- bit 0 bit 7 ADON: A/D On Bit 1 = A/D converter module is operating 0 = A/D converter module is shut off and consumes no operating current T0PS2:T0PS0: Timer0 Prescaler Rate Select bits (used for auto-conversions) 000 = 1:1 Prescaller Rate 001 = 1:8 Prescaller Rate 010 = 1:32 Prescaller Rate 011 = 1:128 Prescaller Rate 100 = 1:512 Prescaller Rate 101 = 1:1024 Prescaller Rate 110 = 1:2048 Prescaller Rate 111 = 1:4096 Prescaller Rate Formula: (TOSC)(1024) (Prescaler Rate) Reserved Unimplemented: Reads as `0' Reserved Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 6-4 bit 3 bit 2 bit 1-0 2003 Microchip Technology Inc. DS21664C-page 43 MCP2502X/5X REGISTER 7-6: ADCON1 REGISTER R/W-0 ADCS1 bit 7 bit 7-6 ADCS1:ADCS0: A/D Conversion Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = Reserved VCFG1:VCFG0: Voltage Reference Configuration bits VCFG1:VCFG0 00 01 10 11 R/W-0 ADCS0 R/W-0 VCFG1 R/W-0 VCFG0 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 bit 5-4 A/D VREF+ VDD External VREF+ VDD External VREF+ A/D VREFVSS VSS External VREFExternal VREF- bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits* 1 = Corresponding GPIO pin configured as Digital I/O 0 = Corresponding GPIO pin configured as A/D Input * corresponding data direction bit (GPDDR register) must be set for each enabled analog channel. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS21664C-page 44 2003 Microchip Technology Inc. MCP2502X/5X 7.5 Read A/D Registers Output Message When the MCP2502X/5X responds to a Read A/D Regs IRM with an OM, the analog values are contained in Register 7-7, Register 7-8 and Register 7-9. REGISTER 7-7: A/D OM RESULT REGISTER (ANnH) R-x ANnR9 bit 7 R-x ANnR8 R-x ANnR7 R-x ANnR6 R-x ANnR5 R-x ANnR4 R-x ANnR3 R-x ANnR2 bit 0 bit 7-0 ANnR9:ANnR2: Bits 9-2 of channel `n' results Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 7-8: A/D OM RESULT REGISTER (AN32L) R-x AN3R.1 bit 7 R-x AN3R.0 U-x -- U-x -- R-x AN2R.1 R-x AN2R.0 U-x -- U-x -- bit 0 bit 7-6 bit 5-4 bit 3-2 bit 1-0 AN3R.1:AN3R.0: A/D Channel 3, bits 1:0 results Unimplemented: Reads as `0' AN2R.1:AN2R.0: A/D Channel 2, bits 1:0 results Unimplemented: Reads as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown 2003 Microchip Technology Inc. DS21664C-page 45 MCP2502X/5X REGISTER 7-9: A/D OM RESULT REGISTER (AN10L) R-x AN1R.1 bit 7 bit 7-6 bit 5-4 bit 3-2 bit 1-0 AN1R.1:AN1R.0: A/D Channel 1, bits 1:0 results Unimplemented: Reads as `0' AN0R.1:AN0R.0: A/D Channel 0, bits 1:0 results Unimplemented: Reads as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-x AN1R.0 U-x -- U-x -- R-x AN0R.1 R-x AN0R.0 U-x -- U-x -- bit 0 TABLE 7-2: Addr 1Eh 34h 00h 01h 0Eh 0Fh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 10h Name GPPIN GPDDR * IOINTEN IOINTPO ADCON0 ADCON1 ADCMP3 ADCMP3 ADCMP2 ADCMP2 ADCMP1 ADCMP1 ADCMP0 ADCMP0 STCON REGISTERS ASSOCIATED WITH THE A/D MODULE bit7 GP7 -- GP7TXC GP7POL ADON ADCS1 AN3CM AN3CM AN2CM AN2CM AN1CM AN1CM AN0CM AN0CM STEM bit6 GP6 DDR6 GP6TXC GP6POL T0PS2 ADCS0 AN3CMP. AN3CMP. AN2CMP. AN2CMP. AN1CMP. AN1CMP. AN0CMP. AN0CMP. STMS bit5 GP5 DDR5 GP5TXC GP5POL T0PS1 VCFG1 AN3CMP. -- AN2CMP. -- AN1CMP. -- AN0CMP. -- STBF1 bit4 GP4 DDR4 GP4TXC GP4POL T0PS0 VCFG0 AN3CMP. -- AN2CMP. -- AN1CMP. -- AN0CMP. -- STBF0 STM3 bit3 GP3 DDR3 GP3TXC GP3POL GO/DONE PCFG3 bit2 GP2 DDR2 GP2TXC GP2POL -- PCFG2 bit1 GP1 DDR1 GP1TXC GP1POL CHS1 PCFG1 AN3CMP. bit0 GP0 DDR0 GP0TXC GP0POL CHS0 PCFG0 Value on POR Value on RST 0000 0000 0000 0000 -111 1111 -111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0-00 0000 0-00 0000 0000 0000 0000 AN3CMP.5 AN3CMP.4 Reserved AN2CMP.5 AN2CMP.4 Reserved AN1CMP.5 AN1CMP.4 Reserved AN0CMP.5 AN0CMP.4 Reserved STM2 AN3CMP2 xxxx xxxx uuuu uuuu ADPOL xx-- ---- uu-- ---- AN2CMP. AN2CMP2 xxxx xxxx uuuu uuuu ADPOL xx-- ---- uu-- ---- AN1CMP. AN1CMP2 xxxx xxxx uuuu uuuu ADPOL xx-- ---- uu-- ---- AN0CMP. AN0CMP2 xxxx xxxx uuuu uuuu -- xx-- ---- uu-- ---0xxx xxxx 0uuu uuuu STM1 STM0 * The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure that the bits in the GPDDR register are maintained set (input) when using them as analog inputs. DS21664C-page 46 2003 Microchip Technology Inc. MCP2502X/5X 8.0 8.1 SPECIAL FEATURES OF THE MCP2502X/5X Description FIGURE 8-2: EXTERNAL CLOCK INPUT OPERATION There are a number of special circuits in the MCP2502X/5X that deal with the needs of real-time applications. These features are intended to maximize system reliability, minimize cost through elimination of external components and provide power-saving operating modes. These are: * Oscillator selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) * SLEEP * In-Circuit Serial Programming Several oscillator options are offered to allow the device to fit the application. XT and HS modes allow the device to support a wide range of crystal frequencies while the LP crystal option saves power. Two timers are implemented to offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the device in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, transmit-on-change or CAN bus activity. A set of configuration bits are used to select various options. Clock from ext. System Open OSC1 MCP2505X OSC2 8.2 Configuration Bits The configuration bits can be either programmed (read as `0') or unprogrammed (read as `1') to select various device configurations. These bits are mapped in program memory location 2007h. The configuration register is actually beyond program memory space and belongs to the special test/configuration memory space (2000h-3FFFh) that can be accessed only during programming. 8.3 Oscillator Configurations Four different oscillator modes may be selected. The user can program two configuration bits (FOSC1:FOSC0) in the CONFIG register to select one of these modes: * LP = Low-Power Crystal * XT = Crystal/Resonator * HS = High-speed Crystal Resonator In all modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 8-1). The oscillator design requires the use of a parallel-cut crystal. The device can also have an external clock source to drive the OSC1/CLKIN pin (Figure 8-2). The device will default to HS mode if the CONFIG register is not programmed. FIGURE 8-1: CRYSTAL/CERAMIC RESONATOR OPERATION OSC1 TO INTERNAL LOGIC RF SLEEP C1 XTAL OSC2 C2 MCP2505X 2003 Microchip Technology Inc. DS21664C-page 49 MCP2502X/5X REGISTER 8-1: U-0 -- bit 13 R/W-x R bit 7 bit 13-11 bit 10-3 bit 2 Unimplemented: Read as '0' Reserved: do not attempt to modify RSTEN: Enable RST input on GP7 1 = RST input Enabled 0 = RST input Disabled FOSC1:FOSC0: Oscillator Selection bits 11 = HS oscillator 10 = Reserved for Test (EC oscillator) 01 = XT oscillator 00 = LP oscillator Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x R R/W-x R R U-0 -- CONFIGURATION REGISTER R/W-x R R/W-x R R/W-x R R/W-x R bit 8 R/W-x R/W-x R R/W RSTEN R/W FOSC1 R/W FOSC0 bit 0 bit 1-0 8.4 Reset 8.4.1 POWER-ON RESET The MCP2502X/5X differentiates between two kinds of reset: * Power-on Reset (POR) * External RST reset Some registers are not affected in any reset condition. Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a reset state on Power-on Reset (POR), on RST and on RST during SLEEP. They are not affected by a wake-up from SLEEP, which is viewed as the resumption of normal operation. A simplified block diagram of the on-chip reset circuit is shown in Figure 8-3. The MCP2502X/5X has a RST noise filter in the RST reset path. The filter will detect and ignore small pulses. A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V to 2.1V). If the RST input on the GP7 pin is selected, the RST pin may be tied through a series resistor to V DD, eliminating the need for external RC components usually required for a Power-on Reset. A maximum rise time for VDD is specified in Section 9.0 "Electrical Characteristics" of this document. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure proper operation. For additional information, refer to AN607, "Power-up Troubleshooting", DS00607). DS21664C-page 50 2003 Microchip Technology Inc. MCP2502X/5X FIGURE 8-3: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RST VDD Rise Detect VDD OST 10-bit Ripple Counter OSC1 PWRT 10-bit Ripple Counter Enable PWRT Enable OST Q Chip Reset Power-on Reset S On-chip RC OSC 8.4.2 POWER-UP TIMER The Power-up Timer (PWRT) provides a fixed, 72 ms nominal time-out, on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator, with the device being kept in reset as long as the PWRT is active. The PWRT's time delay allows V DD to rise to an acceptable level. The power-up time delay will vary from device to device due to VDD, temperature and process variation. For more information, please see Section 9.2 "DC Characteristics". as a valid message before entering Normal mode. This feature is enabled via the PUSLP bit in the OPTREG2 register. While in SLEEP, the I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or hi-impedance). The following operations will not function while the device is in SLEEP: * * * * * A/D Module data conversion Auto-conversion mode Auto-messaging PWM module and outputs Clock output 8.5 Oscillator Start-up Timer The Oscillator Start-up Timer (OST) provides a 512 oscillator cycle (TOSC) delay after the PWRT delay is complete. This ensures that the crystal oscillator has started and stabilized and must be less than the total time it takes (704 oscillator cycles or 44 TQ) for the minimum standard data frame or remote transmit message to be completed on the CAN bus once a wake-up from SLEEP occurs. The OST time-out is invoked only on Power-on Reset or wake-up from SLEEP. 8.6.1 WAKE-UP FROM SLEEP The MCP2502X/5X can wake-up from SLEEP through one of the following events: * External reset input on RST pin * Transmit-on-change due to edge detected on GPIO pin * Activity detected on CAN bus For the device to wake-up due to a GPIO transmit-onchange, the corresponding interrupt enable bit must be set (enabled). Wake-up occurs regardless of the state of the GIE bit. If a wake-up from SLEEP is caused by activity on the CAN bus, the message that caused the wake-up will not be received or acknowledged by the MCP2502X/5X. 8.6 Power-down Mode (SLEEP) Power-down mode (or SLEEP) is enabled via the SLPEN bit in the OPTREG2 register. When enabled, the MCP2502X/5X will enter SLEEP once the CAN bus has been idle for a minimum 1408 bit times while in Normal mode. Additionally, the device may be configured to enter SLEEP while in Listen-only mode immediately after power-up if there is no activity on the CAN bus. Subsequent CAN bus activity will wake the device up from SLEEP and the NEXT message will be confirmed 2003 Microchip Technology Inc. DS21664C-page 51 MCP2502X/5X 8.7 In-Circuit Serial Programming The MCP2502X/5X can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product, also allowing the most recent firmware (or a custom firmware) to be programmed. The device is placed into a program/verify mode by holding the GP4 and GP5 pins low while raising GP7 (VPP) pin from VIL to VIH (see the MCP2502X/5X programming specification, "MCP250XX In-Circuit Serial ProgrammingTM (ICSP)", DS20072, for more information). GP4 becomes the programming data and GP5 becomes the programming clock. Both GP4 and GP5 are Schmitt Trigger inputs in this mode. The signal definitions are summarized in Table 8-1 TABLE 8-1: IN-CIRCUIT SERIAL PROGRAMMING PIN FUNCTIONS Pin Number 7 5 6 11 14 Programming Mode Function Ground Data Clock VPP Power Pin Name VSS GP4 GP5 GP7 VDD DS21664C-page 52 2003 Microchip Technology Inc. MCP2502X/5X 9.0 9.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias............................................................................................................. -55C to +125C Storage temperature ............................................................................................................................... -65C to +150C Voltage on any pin with respect to Vss (except VDD and RST)....................................................... -0.3V to (VDD + 0.6V) VDD................................................................................................................................................................... 0V to 7.0V Voltage on RST with respect to Vss.................................................................................................................. 0V to 14V Total power dissipation (Note 1) ..............................................................................................................................1.0 W Maximum source current out of VSS pin ............................................................................................................... 300 mA Maximum sink current into VDD pin ....................................................................................................................... 250 mA Input clamp current, Iik (Vi < 0 or Vi > VDD) .......................................................................................................... 20 mA Output clamp current, Iok (VO < 0 or VO > VDD).................................................................................................... 20 mA Maximum current sunk by any I/O pin..................................................................................................................... 25 mA Maximum current sourced by any input pin ............................................................................................................ 25 mA Maximum current sunk by GPIO port.................................................................................................................... 200 mA Maximum current sourced by GPIO port .............................................................................................................. 200 mA Soldering temperature of leads (10 seconds) ....................................................................................................... +300C ESD protection on all pins .................................................................................................................................................. 3.5 kV Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. FIGURE 9-1: 6.0V 5.5V 5.0V 4.5V Voltage 4.0V 3.5V 3.0V 2.7V 2.0V MCP2505X VOLTAGE-FREQUENCY GRAPH MCP2505X 4.5V 8 MHz 25 MHz Frequency Fmax = (9.44 MHz/V) (VDDAPPMIN - 2.7V) + 8 MHz Note: VDDAPPMIN is the minimum voltage of the MCP2505X device in the application. Characterized and not 100% tested. 2003 Microchip Technology Inc. DS21664C-page 53 MCP2502X/5X 9.2 DC Characteristics Industrial (I): TAMB = -40C to +85C VCC = 2.7V to 5.5V Automotive (E): TAMB = -40C to +125C VCC = 4.5V to 5.5V Characteristics Supply Voltage Min 2.7 4.5 0.05 Max 5.5 5.5 -- Units V V V/ms Test Conditions XT and LP OSC configuration HS OSC configuration (Note 2) (Note 3) DC Characteristics Param. No. Sym VDD SVDD VDD Rise Rate to ensure internal power-on reset signal High-level input voltage VIH VIH GPIO pins RXCAN (Schmitt Trigger) OSC1 Low-level input voltage VIL VIL RXCAN (Schmitt Trigger) GPIO pins OSC1 Low-level output voltage VOL VOH TXCAN GPIO pins High-level output voltage TXCAN, GPIO pins Input leakage current ILI CINT All I/O except OSC1, GP7 OSC1, GP7 pin Internal Capacitance (all inputs and outputs, except GP7) GP7 IDD IDDS Note 1: 2: 3: Operating Current Standby Current (CAN Sleep Mode) 2 .7 VDD .85 VDD VSS -0.3 VSS -- VDD -0.7 VDD+0.3 VDD VDD -- 0.2 VDD 0.5V 0.2 VDD 0.6 -- V V V V V V V V V IOH =-3.0 mA, VDD = 4.5V, I-temp IOL = 8.5 mA, VDD = 4.5V -1 -5 -- +1 +5 7 A A pF TAMB = 25C, fC = 1.0 MHz, VDD = 5.0V (Note 3) -- -- -- 15 20 30 pF mA A XT OSC VDD = 5.5V; FOSC = 25 MHz Inputs tied to VDD or VSS This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. Refer to Figure 9-1. This parameter is periodically sampled and not 100% tested. DS21664C-page 54 2003 Microchip Technology Inc. MCP2502X/5X 9.3 AC Characteristics Industrial (I): TAMB = -40C to +85C VCC = 2.7V to 5.5V Automotive (E): TAMB = -40C to +125C VCC = 4.5V to 5.5V Characteristics CLKIN Frequency Min DC DC DC FOS Oscillator Frequency 0.1 4 5 1 TOSC CLKIN Period 250 40 5 Oscillator Period 0.25 40 5 3 TOSL TOSH 4 Tosr CLKIN Rise or Fall Time CLKIN High or Low Time 100 15 2.5 -- -- -- 10 12 13 20 21 30 32 33 34 TDCLKOUT CLKOUT Propagation Delay TCKR TCKR TIOR TIOF TMCL TOST TPWRT TIOZ TPWMR TPWMF TAD TCNV Note 1: 2: 3: CLKOUT Rise Time CLKOUT Fall Time Port output rise time Port output fall time RST Pulse Low Oscillation Start-up Timer Power-up Timer I/O Hi-impedance from RST low PWM output rise time PWM output fall time A/D clock period Conversion Time (not including acquisition time) -- -- -- -- -- 2 512 28 -- -- -- 1.6 3.0 -- Max 4 25 200 4 25 200 -- -- -- 10 250 -- -- -- -- 25 50 15 60 100 200 40 40 -- -- 132 2.1 25 25 -- -- 13 Units MHz MHz kHz MHz MHz kHz ns ns s s ns s ns ns s ns ns ns ns ns ns ns ns s Tosc ms s ns ns s s TAD Test Conditions XT osc mode HS osc mode (Note 3) LP osc mode XT osc mode HS osc mode (Note 3) LP osc mode XT osc mode HS osc mode LP osc mode XT osc mode HS osc mode LP osc mode XT osc mode HS osc mode LP osc mode XT osc mode (Note 1) HS osc mode (Note 1) LP osc mode (Note 1) VDD = 4.5 V (Note 2) Note 2 Note 2 Note 1 Note 1 VDD = 5V TOSC = OSC1 period VDD = 5V Note 1 Note 1 Note 1 VREF 2.5V VREF full range AC Characteristics Param. No. Sym FOS This parameter is periodically sampled and not 100% tested. Measurements are taken with CLKOUT output configured as 4 x TOSC. Refer to Figure 9-1. 2003 Microchip Technology Inc. DS21664C-page 55 MCP2502X/5X FIGURE 9-2: I/O TIMING OSC1 I/O Pin (input) I/O Pin (output) Old Value 20, 21 New Value 10 13 12 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins. FIGURE 9-3: VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal RESET RESET, OST AND POWER-UP-TIMER 30 33 32 34 I/O Pins 34 DS21664C-page 56 2003 Microchip Technology Inc. MCP2502X/5X 9.4 A/D Converter Characteristics Industrial (I): TAMB = -40C to +85C VCC = 2.7V to 5.5V Automotive (E): TAMB = -40C to +125C VCC = 4.5V to 5.5V Min -- -- -- -- -- -- 4.096 VREFVSS-0.3 VREF-- -- -- Max 10-bits less than 1 LSb less than 1 LSb less than 1 LSb less than 2 LSb -- VDD+0.3 VDD+0.3 VREF+ VREF+ 2.5 10 2 LSb V V V V k A Specified by design (see Section 4.5.2.1 "Hysteresis Function") Note Units Test Conditions VREF = VDD = 5.12V, VSS in VREF VREF+ = VDD = 5.12V, VSS- = VSS = 0 V (I TEMP) VREF+ = VDD = 5.12V, VSS- = VSS = 0 V (I TEMP) VREF+ = VDD = 5.12V, VSS- = VSS = 0 V VREF+ = VDD = 5.12V, VSS- = VSS = 0 V VSS in VREF Absolute minimum to ensure 10-bit accuracy. Minimum resolution for A/D is 1 mV. Minimum resolution for A/D is 1 mV. AC Converter Characteristics Param. No. Sym NR NINT NDIF NG NOFF Characteristics A/D resolution A/D Integral error A/D Differential error A/D Gain error A/D Offset error Monotonicity VREF VREF+ VREFVAIN ZAIN IREF NHYS Reference Voltage Reference V high Reference V low Analog input V Recommended impedance of analog voltage source VREF input current Analog Transmit-on-change Hysteresis Note: Design guidance only 2003 Microchip Technology Inc. DS21664C-page 57 MCP2502X/5X NOTES: DS21664C-page 58 2003 Microchip Technology Inc. MCP2502X/5X 10.0 10.1 PACKAGING INFORMATION Package Marking Information 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP25050 XXXXXXXXXXXXXX 0325NNN 14-Lead SOIC (208 mil) Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN MCP25055 XXXXXXXXXXX 0337NNN Legend: XX...X Y YY WW NNN Note: Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard device marking consists of Microchip part number, year code, week code and traceability code.. 2003 Microchip Technology Inc. DS21664C-page 59 MCP2502X/5X 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c eB A1 B1 B p L Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21664C-page 60 2003 Microchip Technology Inc. MCP2502X/5X 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L Units Dimension Limits n p A A2 A1 E E1 D h L c B INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 A1 MIN MAX MIN MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2003 Microchip Technology Inc. DS21664C-page 61 MCP2502X/5X NOTES: DS21664C-page 62 2003 Microchip Technology Inc. MCP2502X/5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) c) Device: MCP25020: MCP25020T: MCP25025: MCP25025T: MCP25050: MCP25050T: CAN I/O Expander CAN I/O Expander (Tape and Reel) CAN I/O Expander CAN I/O Expander (Tape and Reel) Mixed Signal CAN I/O Expander Mixed Signal CAN I/O Expander (Tape and Reel) MCP25055: Mixed Signal CAN I/O Expander MCP25055T: Mixed Signal CAN I/O Expander (Tape and Reel) I E = = -40C to +85C -40C to +125C (not available on MCP25025 or MCP25055 devices) Plastic DIP (300 mil Body), 14-lead Plastic SOIC (150 mil Body), 14-lead d) Industrial temperature, PDIP package. MCP25025-I/SL: Industrial temperature, SOIC package. MCP25050T-E/SL: Tape and Reel, Extended temperature, SOIC package. MCP25055-I/SL: Industrial temperature SOIC package. MCP25020-I/P: Temperature Range: Package: P SL = = Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. DS21664C-page 63 MCP2502X/5X NOTES: DS21664C-page 64 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. 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No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Atlanta 3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307 Taiwan Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 China - Chengdu Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 Taiwan Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 China - Fuzhou Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 EUROPE Austria Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 China - Hong Kong SAR Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Denmark Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910 China - Shanghai Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Kokomo 2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387 France Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 China - Shenzhen Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393 Germany Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Phoenix 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 China - Shunde Room 401, Hongjian Building No. 2 Fengxiangnan Road, Ronggui Town Shunde City, Guangdong 528303, China Tel: 86-765-8395507 Fax: 86-765-8395571 Italy Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 San Jose 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 China - Qingdao Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205 Netherlands P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 Japan Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 DS21664C-page 66 2003 Microchip Technology Inc. |
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