|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
CTLDM7120-M621H SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CTLDM7120M621H is an Enhancement-mode N-Channel Field Effect Transistor, manufactured by the N-Channel DMOS Process, designed for high speed pulsed amplifier and driver applications. This MOSFET offers Low rDS(ON) and Low Threshold Voltage. MARKING CODE: CNH TLM621H CASE * Device is Halogen Free by design FEATURES: * ESD protection up to 2kV * Low rDS(ON) (0.25 MAX @ VGS=1.5V) * High current (ID=1.0A) * Logic level compatibility SYMBOL VDS VGS ID IDM PD TJ, Tstg JA UNITS V V A A W C C/W UNITS A A V V V S pF pF pF ns ns APPLICATIONS: * Load/Power switches * Power supply converter circuits * Battery powered portable equipment MAXIMUM RATINGS: (TA=25C) Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (Steady State) Maximum Pulsed Drain Current, tp=10s Power Dissipation (Note 1) Operating and Storage Junction Temperature Thermal Resistance (Note 1) 20 8.0 1.0 4.0 1.6 -65 to +150 75 MAX 10 10 1.2 1.1 0.10 0.14 0.25 ELECTRICAL CHARACTERISTICS: (TA=25C unless SYMBOL TEST CONDITIONS IGSSF, IGSSR VGS=8.0V, VDS=0 IDSS VDS=20V, VGS=0 BVDSS VGS=0, ID=250A VGS(th) VDS=10V, ID=1.0mA VSD VGS=0, IS=1.0A rDS(ON) VGS=4.5V, ID=0.5A rDS(ON) VGS=2.5V, ID=0.5A rDS(ON) VGS=1.5V, ID=0.1.0A gFS VDS=10V, ID=0.5A Crss VDS=10V, VGS=0, f=1.0MHz Ciss VDS=10V, VGS=0, f=1.0MHz Coss VDS=10V, VGS=0, f=1.0MHz ton VDD=10V, VGS=5.0V, ID=0.5A toff VDD=10V, VGS=5.0V, ID=0.5A otherwise noted) MIN TYP 20 0.5 0.075 0.10 0.17 4.2 45 220 120 25 140 Notes: (1) Mounted on a 4-layer JEDEC test board with one thermal vias connecting the exposed thermal pad to the first buried plane. PCB was constructed as per JEDEC standards JESD51-5 and JESD51-7. R2 (17-February 2010) CTLDM7120-M621H SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET TLM621H CASE - MECHANICAL OUTLINE OPTIONAL MOUNTING PADS (Dimensions in mm) *Exposed pad P internally connected to pins 2, 3, 4, and 5. For standard mounting refer to TLM621H Package Details PIN CONFIGURATION LEAD CODE: 1) Source 2) Drain 3) Drain 4) Drain 5) Drain 6) Gate MARKING CODE: CNH R2 (17-February 2010) w w w. c e n t r a l s e m i . c o m |
Price & Availability of CTLDM7120-M621H |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |