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DRAM
FEATURES
X4 organization EDO (Extended Data-Out) access mode Single power supply : 5V 10% Vcc for 5V product 3.3V 10% Vcc for 3.3V product y Interface for inputs and outputs www..com TTL-compatible for 5V products LVTTL-compatible for 3.3V products y 2048-cycle refresh in 32ms y Refresh modes : RAS only, CAS BEFORE RAS (CBR) and HIDDEN capabilities, y Optional self-Refresh capabilities(S-ver. Only) y JEDEC standard pinout y Key AC Parameter -45 -50 -60 tRAC 45 50 60 tCAC 11 13 15 tRC 77 84 104 tPC 16 20 25
y y y
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
4M x 4 DRAM
EDO PAGE MODE
ORDERING INFORMATION - PACKAGE
24 / 26-pin 300mil SOJ 24 / 26-pin 300mil TSOP (TypeII) PRODUCT NO. M11B1644A-45J/50J/60J M11B1644SA-45J/50J/60J M11L1644A-45J/50J/60J M11L1644SA-45J/50J/60J M11B1644A-45T/50T/60T M11B1644SA-45T/50T/60T M11L1644A-45T/50T/60T M11L1644SA-45T/50T/60T * Ordered by special request Refresh Vcc Normal *SelfRefresh Normal SelfRefresh Normal *SelfRefresh Normal SelfRefresh 3.3V 5V TSOPII 3.3V 5V SOJ PACKING TYPE
GENERAL DESCRIPTION
The M11B1644/M11L1644 series is a randomly accessed solid state memory, organized as 4,194,304 x 4 bits device. It offers Extended Data-Output access mode. Single power supply (5V 10%, 3.3V 10%), access time (-45,-50,-60), selfrefresh function and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before RAS , RAS -only refresh and Hidden refresh.
The primary advantage of EDO is the availability of data-out even after CAS returns high. EDO allows CAS precharge time (tPC) to occur without the output data going invalid. This elimination of CAS output control allows pipeline Read.
PIN ASSIGNMENT
SOJ Top View
VCC I/ O0 I/ O1 WE R AS NC A10 A0 A1 A2 A3 VCC
TSOP (TypeII) Top View
VS S I /O 3 I /O 2 C AS OE A9 A8 A7 A6 A5 A4 VS S VC C I/O 0 I/O 1 WE RA S NC A10 A0 A1 A2 A3 VC C
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VS S I/ O3 I/ O2 CA S OE A9 A8 A7 A6 A5 A4 VS S
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 1/16
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FUNCTIONAL BLOCK DIAGRAM
WE RAS CAS CONTROL LOGIC
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
DATA-IN BUFFER 4 IO0 : IO3
CLOCK GENERATOR
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A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11 ROW. ADDRESS BUFFERS(11) 11 11 ROW DECODER 2048 x 2048 x 4 MEMORY ARRAY REFRESH COUNTER 2048 x 4 REFRESH CONTROLER 11 COLUMN ADDRESS BUFFER 11 COLUMN DECODER 2048 4
DATA-OUT BUFFER OE 4
SENSE AMPLIFIERS I/O GATING 8
2048
VBB GENERATOR
VCC VSS
PIN DESCRIPTIONS
PIN NO. 8~11,14~19,7 5 21 4 20 2,3,22,23 1,12 13,24 6
PIN NAME A0~A10
RAS CAS WE OE
TYPE Input Input Input Input Input Input / Output Supply Ground -
DESCRIPTION Address Input Row Address : A0~A10 Column Address : A0~A10 Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input / Output Power, (5V or 3.3V) Ground No Connect
I/O0 ~ I/O3 VCC VSS NC
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 2/16
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss 5V Product ... ......-1V to +7V 3.3V Product ... ......-0.5V to +4.6V Operating Temperature, TA (ambient) ....0 C to +70 C Storage Temperature (plastic) ..........-55 C to +150 C Power Dissipation .......................................1.0W Short Circuit Output Current ........................50mA
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M11B1644A / M11B1644SA M11L1644A / M11L1644SA
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0 C TA 70 C )
PARAMETER Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage 0V VIN VIH(max) 0V VOUT VCC Output(s) disable 5V IOH = -5 mA 3.3V IOH = -2 mA 5V IOL = 4.2 mA 3.3V IOL = 2 mA CONDITIONS SYMBOL MIN VCC VSS VIH VIL ILI ILO VOH VOL 3.0 0 2.0 -0.3 -10 -10 2.4 3.3V MAX 3.6 0 VCC +0.3 0.8 10 10 0.4 MIN 4.5 0 2.4 -0.3 -10 -10 2.4 5V MAX 5.5 0 VCC +0.3 0.8 10 10 0.4 V V V V A A V V 1 1 1 UNITS NOTES
Note : 1.All Voltages referenced to VSS MAX -45 150 4 2 ICC3 ICC4 ICC6 ICC7 ICC8 150 150 150 2 2 -50 140 4 2 140 140 140 2 2 -60 130 4 2 130 130 130 2 2
PARAMETER Operating Current Standby Current
CONDITIONS
RAS , CAS cycling , tRC =min
SYMBOL ICC1 ICC2
UNITS NOTES mA mA mA mA mA mA mA mA 2 1,3 1,2
TTL interface , RAS , CAS = VIH , DOUT =High-Z CMOS interface, RAS , CAS VCC-0.2V
RAS only refresh Current
tRC = min tPC = min tRC = min Standby with CBR refresh, tRC =31.2us tRAS 300ns, DOUT =Hi-Z, CMOS interface
RAS , CAS 0.2V, DOUT =Hi-Z, CMOS interface
EDO Page Mode Current
CAS Before RAS Refresh Current Battery Backup Current (S-ver. Only)
Self Refresh Current
Note : 1. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS =VIL . 3. Address can be changed once or less while CAS =VIH . Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 3/16
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CAPACITANCE (Ta = 25 C , VCC = 5V 10% or 3.3V 10%)
PARAMETER Input Capacitance (address) Input Capacitance ( RAS , CAS , WE , OE ) Output capacitance (I/O0~I/O3) SYMBOL CI1 CI2 CI / O TYP -
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
MAX 5 7 10
UNIT pF pF pF
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 C , VCC =5V 10% or 3.3V 10%, VSS = 0V) (note 14)
Test Conditions www..com Input timing reference levels : 0.8V, 2.4V (for 5V power supply), 0.8V, 2.0V (for 3.3V power supply) Output reference level : VOL= 0.8V, VOH=2.0V Output Load : 2TTL gate + CL (50pF) Assumed tT = 2ns PARAMETER Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time EDO-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge
RAS Pulse Width RAS Pulse Width (EDO Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time
SYMBOL tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS tRASC tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL tACH
-45 MIN 77 97 16 53 45 11 11 22 25 45 45 6 28 6 35 6 10 5 0 6 8 0 6 40 23 10 23 34 10,000 10,000 100,000 50 50 7 30 7 37 7 11 5 0 7 9 0 7 44 25 11 MAX MIN 84 110 20 58
-50 MAX MIN 104 135 25 68 50 13 13 25 28 10,000 100,000 60 60 10 40 10,000 10 40 10 37 14 5 0 10 25 12 0 10 55 30 13
-60 MAX
UNIT Notes ns ns ns ns
60 15 15 30 33 10,000 100,000
ns ns ns ns ns ns ns ns ns
4 5 13
10,000
ns ns ns
18
6 7
45
ns ns ns ns
Row Address Setup Time Row Address Hold Time
RAS to Column Address Delay Time
30
ns ns ns ns ns ns
8
Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Column Address setup to CAS precharge
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 4/16
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(Continued)
-45 PARAMETER Read Command Setup Time Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
-50
MIN MAX
-60
MIN MAX
UNIT
Notes
SYMBOL tRCS tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tOES tOEHC tOEP tORD tCOH tWHZ tRASS tRPS tCHS tRSR tRHR
MIN
MAX
0 0 0 0 0 0 0 6 40 6 11 6 0 6 40 57 34 23 1 5 5 10 6 5 2 2 0 3 0 100 77 -50 0 6 11 50 32 11 11
0 0 0 0 0 0 0 7 44 7 13 7 0 7 44 67 42 30 1 5 5 10 7 5 2 2 0 3 0 100 84 -50 0 7 13 50 32 13 13
0 0 0 0 0 0 0 10 55 10 15 10 0 10 55 79 49 34 1 5 5 10 10 5 2 2 0 3 0 100 104 -50 0 10 15 50 32 15 15
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns us ns ns ns ns
15 9,15 9
Output Buffer Turn-off Delay From CAS or RAS Output Buffer Turn-off to OE Write Command Setup Time www..com Write Command Hold Time Write Command Hold Time(Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
10,17 17,19 11,15 15 15 15 15 15 12 12 11 11 11 2,3
Column Address to WE Delay Time
CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (2048 cycles) RAS to CAS Precharge Time CAS Setup Time(CBR REFRESH) CAS Hold Time(CBR REFRESH) OE Hold Time From WE During Read-Mode-Write Cycle OE Low to CAS High Setup Time OE High Hold Time From CAS High OE precharge time OE Setup Prior to RAS During Hidden Refresh Cycle
1 1 16
Data Output Hold After CAS Returning Low Output Disable Delay From WE Self Refresh RAS Low Pulse width Self Refresh RAS High Precharge Time Self Refresh CAS Hold Time
WE Setup Time Reference to RAS in CBR/SR WE Hold Time Reference to RAS in CBR/SR
20,21 20,21 20,21 20,21 20,21
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 5/16
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Notes : 1. 2. Enables on-chip refresh and address counters. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Assume that tRCD tRCD (max) If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and RAS must be pulsed high. Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF1(max) defines the time at which the output achieves the open circuit condition ; it is not a reference to VOH or VOL. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFYWRITE cycle only. If tWCS tWCS(min) , the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min) , tAWD tAWD(min) and tCWD tCWD(min) , the
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
3.
cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH ) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE controlled) cycle. 12. Those parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY- WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFYWRITE operation is not possible. 14. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 15. WRITE command is defined as WE going low. 16. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 17. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. 18. Each CAS must meet minimum pulse width. 19. All IOs controlled by OE , regardless CAS . 20. Self refresh mode is initiated by performing a CBR refresh cycle and holding RAS low for the specified tRASS. Self refresh mode is terminated by rising RAS high for a minimum time of tRPS. 21. For all of the refresh mode except the distributed CBR refresh mode, all rows must be refreshed within the refresh rate before and after self refresh.
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4.
5. 6.
7.
8.
9. 10.
11.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 6/16
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TRUTH TABLE
FUNCTION Standby Read Write (Early Write) Read-Write
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M11B1644A / M11B1644SA M11L1644A / M11L1644SA
ADDRESSES
RAS CAS
WE X H L HAEL H H H L L HAEL HAEL H X H H
OE
DQS High-Z Data-Out Data-In Data-Out, Data-In Data-Out Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out High-Z High-Z High-Z
ROW X ROW ROW ROW ROW X X ROW X ROW X ROW ROW X X
COL X COL COL COL COL COL X COL COL COL COL COL X X X
H L L L 1st Cycle L L L L L L L LAEHAEL L HAEL HAEL
HAEX L L L HAEL HAEL LAEH HAEL HAEL HAEL HAEL L H L L
X L X LAEH L L L X X LAEH LAEH L X X X
EDO-Page-Mode Read 2nd Cycle Any Cycle EDO-Page-Mode 1st Cycle Write (Early) 2nd Cycle
EDO-Page-Mode 1st Cycle Read-Write Hidden Refresh
RAS -Only Refresh
2nd Cycle
CBR Refresh Self Refresh
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Publication Date : May. 2001 Revision : 1.1 7/16
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READ CYCLE
tRC t R AS
RA S VIH VIL
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
t RP
tCRP
CA S VIH VIL
t RC D
tC SH tRSH t CAS
tRRH
tAR tASR t R AD t R AH
ROW
t RAL tASC t CAH
COLUMN
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AD DR
tACH
ROW
VIH VIL
tRCS
WE VIH VIL
tRCH
tAA t RAC tCAC t CLZ
I/O VO H VO L OPE N
NOTE1
tOFF1
V ALI D DAT A
OPE N
t O AC
OE VIH VIL
tOF F2
EARLY WRITE CYCLE
tRC tRAS
RAS VIH VIL
tRP
tCRP
CAS VIH VIL
tRCD
tC SH tR SH tCAS
t AR tASR
ADDR VIH VIL ROW
t R AD t R AH
tASC
COLUMN
tRAL tCAH
tACH
R OW
tWCS
tCWL tRWL tWCR tWCH tWP
WE
V IH V IL
tDS
I/O VIH VIL VIH VIL
tDHR tDH
VAL I D DAT A
OE
DON'T CARE UNDEFINED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
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Publication Date : May. 2001 Revision : 1.1 8/16
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READ WRITE CYCLE
tRW C tR AS
RA S VIH VIL
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRP tC S H tRS H tCAS
tC RP
CA S VIH VIL
tRCD
tASR
tAR tR A D tR AH
tASC
COLUMN
tRAL tCAH
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ADDR VIH VIL ROW
tACH
R OW
tR C S
tR W D tCW D tAWD
tCWL tRWL tWP
WE
VIH VIL
tAA tRAC tC AC tCLZ
I/ O VI/O H VI/O L OPEN VAL ID DO UT
tDS
tD H
VA L I D D I N
tO AC
V IH OE V IL
tO FF2
tOEH
EDO-PAGE-MODE READ CYCLE
tR AS C
RAS VIH VIL
tRP
tC R P
CAS VIH VIL
tC S H tRC D
tC AS
t P C ( N OT E2) tC AS tCP
tCP
tRS H tC AS
tCP
tAR tR AD tAS R
AD DR V IH V IL
tACH tASC tC A H tAS C
tACH tC AH tAS C
tR A H
tACH tR AL tCAH
R OW
ROW
COLUMN
COLUMN
COL UM N
tRC S
WE VIH VIL
tRC H
tRR H
tA A tR AC tCAC tCLZ
I/ O VO H VO L OPEN
tA A tAC P tCAC tCO H
V AL I D D AT A
V AL ID D ATA
tAA tAC P tC AC tC L Z tOEHC tO AC tO FF2 tO ES tOE P
VALID DATA N O TE 1
tO FF1
OPEN
tO AC tOE S
OE VIH VIL
tOF F2
DON'T CARE
UNDEFINED
*NOTE : 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of
CAS . Both measurements must meet the tPC specification.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 9/16
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t R AS C
RA S VIH VIL
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRP
tCS H tCRP
CA S VIH VIL
tRC D
t C AS
tPC (NOTE1) t C AS tCP
t CP
tRSH t CA S
tCP
tAR t R AD tASR
AD DR VIH VIL
tRAH
tASC
t AC H t CA H
tACH t AS C t C AH tASC
tACH t R AL tCAH
ROW
ROW
COLUMN
COLUM N
COL U MN
tCWL
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WE VIH VIL
tWCS
tWCH tWP
tWCS
tCWL tWCH tWP
tWCS
tCWL tWCH tWP
tDS
I/ O VIH VIL
tWCR tDH R tDH
tRWL tDS tDH tDS tDH
VA L I D D AT A
VALID DATA
VA L I D D A T A
OE
VIH VIL
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRASC
RA S VIH VIL
tRP
tCSH tCRP
CAS VIH VIL
tRCD
t C AS
tCP
tPCM t C AS
tCP
tRSH tCAS
tCP
tAR t R AD tASR
ADDR V IH V IL
t R AH
tASC
tACH t C AH
tACH t AS C t C AH tASC
t AC H tRAL tCAH
ROW
ROW
COLUM N
C OL UM N
C OL UM N
tRWD tRCS tCWL tWP t A WD tCWD t CW L tWP tAWD tCWD
tRWL tCWL tWP
t A WD t CWD
WE
VIH VIL
tAA tRAC t C AC tCLZ
I/ O VI/ O H VI/ O L
V A L I D VA L I D DOUT DIN
tAA tDH tDS tACP t C AC tCLZ
VALI D VAL ID DO U T DIN
tAA tDH tDS t AC P t C AC tCLZ
VALI D DOUT VA L I D DIN
tDH tDS
tOFF2 t O AC
OE V IH V IL
tOFF2 t O AC tO AC
tOFF 2 tOEH
DON'T CARE
UNDEFINED
Note : 1. tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 10/16
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t RASC
RAS V IH V IL
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
tRP
tC SH tC RP
CA S V IH V IL
tRCD
tPC tCAS
tCP t CP tCAS tCP
tR SH tCAS
tCP
tAR t RAD
tRAL tACH t C AH t ASC tACH tCAH tASC tACH tCAH
ROW
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AD DR VIH VIL
t A S R t R AH
ROW
tAS C
C OLU MN(A)
COLUMN( B)
COLUMN(N)
tRCS
WE VIH VIL
t RC H
tWCS
t WCH
tAA tRAC t CAC tACP
tAA tW HZ tCAC tCO H
VA LI D DA T A( A )
VA LI D D ATA (B )
t DS
tDH
I/ O
VI/O H VI/O L
OPE N
VALID DATA IN
t O AC
OE VIH VIL
RAS ONLY REFRESH CYCLE (ADDR = A0~A10 ; OE , WE = DON'T CARE)
tR C tRAS
RAS VIH VIL
tRP
tCRP
CA S VIH VIL
tRPC
t AS R
ADDR VIH VIL ROW
tRAH
ROW
I/ O
VOH VOL
OP EN
DON'T CARE
UNDEFINED
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CBR REFRESH CYCLE (A0~A10 ; OE = DON'T CARE)
tRP
RAS VIH VIL
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
tRAS
t RP
tRAS
tR PC t CP
CAS VIH VIL
tCSR
tCHR
tRPC
tC SR
t CH R
I/O
OPE N
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WE VIH VIL
tRCH
tRSR
tRHR
tRSR
tRHR
HIDDEN REFRESH CYCLE ( WE = HIGH ; OE = LOW)
(READ)
( RE F R ES H )
tRAS
RAS VIH VIL
tRP
tRAS
tC RP
CAS VIH VIL
tRCD
tRSH
t CHR
tAR tRAD t AS R t RAH
ROW
tAS C
tRAL tCAH
VIH AD DR VIL
COLUMN
tAA t R AC tCAC tCLZ
I/O VO H VO L OPE N VA LI D DAT A OP EN NOTE1
tOF F 1
tO AC tO RD
VIH OE V I L
tOF F2
DON'T CARE
UNDEFINE D
Note : 1. tOFF1 is reference from the rising edge of RAS or CAS , whichever occurs last.
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Publication Date : May. 2001 Revision : 1.1 12/16
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SELF REFRESH CYCLE ( OE = DON'T CARE)
tRP
RAS VIH VI L
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
tRASS
tRPS
tRP C tCS R
CA S VIH VI L
tRP C tC HS
tC RP
tCP tAS R
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ADD R
VI H VI L
I/O
VOH VOL
O P EN
tRC H tRSR
WE VIH VIL
tRHR
D ON'T CARE
U N DEFIN ED
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PACKING DIMENSIONS SOJ(300mil) 24 / 26-LEAD
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
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Symbol A A1 A2 B B1 B2 C C1 D E E1 e
Min 3.25 2.08 0.635 0.41 0.41 0.66 0.18 0.18 17.02 7.49 0
Dimension mm Nom 3.51 0.46 0.71 0.20 17.15 8.51 7.62 1.27 BASIC
Max 3.76 0.51 0.48 0.81 0.28 0.28 17.27 7.75 10
Min 0.128 0.082 0.025 0.016 0.016 0.026 0.007 0.007 0.670 0.295 0
Dimension inch Nom 0.138 0.018 0.028 0.008 0.675 0.335 0.300 0.050 BASIC
Max 0.148 0.020 0.019 0.032 0.012 0.011 0.680 0.305 10
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PACKING 24 / 26-LEAD DIMENSIONS TSOP(II) DRAM(300mil)
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
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Symbol A A1 A2 B B1 C C1 D ZD E E1 L L1 e R R1 y
Min 0.05 0.95 0.30 0.30 0.12 0.12 17.01 9.02 7.49 0.40
0.12 0.12 0 -
Dimension in mm Nom 1.00 0.40 0.15 17.14 0.95 REF 9.22 7.62 0.50 0.031 REF 1.27 BSC -
Max 1.20 0.15 1.05 0.52 0.45 0.21 0.16 17.27 9.42 7.75 0.60
Min 0.002 0.037 0.012 0.012 0.005 0.005 0.67 0.355 0.295 0.016
0.25 5 0.10
0.005 0.005 0 -
Dimension in inch Nom 0.039 0.016 0.006 0.675 0.374 REF 0.363 0.3 0.020 0.080 REF 0.05 BSC -
Max 0.047 0.006 0.041 0.02 0.018 0.008 0.0063 0.68 0.371 0.305 0.024
0.01 5 0.004
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 15/16
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Important Notice All rights reserved.
M11B1644A / M11B1644SA M11L1644A / M11L1644SA
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT.
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The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001 Revision : 1.1 16/16

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