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FSDL0365RN, FSDM0365RN
Features
* Internal Avalanche Rugged Sense FET * Consumes only 0.65W at 240VAC & 0.3W load with Advanced Burst-Mode Operation * Frequency Modulation for EMI Reduction * Precision Fixed Operating Frequency * Internal Start-up Circuit * Pulse-by-Pulse Current Limiting * Abnormal Over Current Protection (AOCP) * Over Voltage Protection (OVP) * Over Load Protection (OLP) * Internal Thermal Shutdown Function (TSD) * Auto-Restart Mode * Under Voltage Lockout (UVLO) * Low Operating Current (3mA) * Adjustable Peak Current Limit * Built-in Soft Start
Green Mode Fairchild Power Switch (FPSTM)
effective flyback converters. OUTPUT POWER TABLE
230VAC 15%(3) PRODUCT FSDL321 FSDH321 FSDL0165RN FSDM0265RN FSDH0265RN FSDL0365RN FSDM0365RN FSDL321L FSDH321L FSDL0165RL FSDM0265RL FSDH0265RL FSDL0365RL FSDM0365RL Adapter(1) 11W 11W 13W 16W 16W 19W 19W 11W 11W 13W 16W 16W 19W 19W Open Frame(2) 17W 17W 23W 27W 27W 30W 30W 17W 17W 23W 27W 27W 30W 30W 85-265VAC Adapter(1) 8W 8W 11W 13W 13W 16W 16W 8W 8W 11W 13W 13W 16W 16W Open Frame(2) 12W 12W 17W 20W 20W 24W 24W 12W 12W 17W 20W 20W 24W 24W
Applications
* SMPS for VCR, SVR, STB, DVD & DVCD Player * SMPS for Printer, Facsimile & Scanner * Adapter for Camcorder
Related Application Notes
* AN-4137, 4141, 4147(Flyback) / AN-4134(Forward)
Description
Each product in the FSDx0365RN (x for L, M) family consists of an integrated Pulse Width Modulator (PWM) and Sense FET, and is specifically designed for high performance off-line Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are integrated high voltage power switching regulators which combine an avalanche rugged Sense FET with a current mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shut Down (TSD) protection, Abnormal Over Current Protection (AOCP) and temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSDx0365RN devices reduce total component count, design size, weight while increasing efficiency, productivity and system reliability. Both devices provide a basic platform that is well suited for the design of costFPSTM is a trademark of Fairchild Semiconductor Corporation. (c)2005 Fairchild Semiconductor Corporation
Notes: 1. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sinker, at 50C ambient. 2. Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sinker, at 50C ambient. 3. 230 VAC or 100/115 VAC with doubler.
Typical Circuit
AC IN
DC OUT
Vstr Ipk PWM Vfb
Drain
Vcc
Source
Rev.1.0.8
FSDL0365RN, FSDM0365RN
Figure 1. Typical Flyback Application
Internal Block Diagram
Vcc 2
+
Vstr 5
Drain 6,7,8
ICH
8V/12V
Vcc
VBURH
-
Vcc good
Freq. Modulation OSC
Vref
VBURL/VBURH
IBUR(pk) Vcc IDELAY Vcc I FB
Internal Bias
Vfb 3
Normal
PWM
Burst
S R
Q Q
2.5R Ipk 4 Soft Start R
Gate driver LEB
V SD Vcc Vovp Vcc good TSD
R Q
1 GND
S Q
AOCP Vocp
Figure 2. Functional Block Diagram of FSDx0365RN
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FSDL0365RN, FSDM0365RN
Pin Definitions
Pin Number 1 Pin Name GND Pin Function Description Sense FET source terminal on primary side and internal control ground. Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (12V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA current source connected internally while a capacitor and optocoupler are typically connected externally. A feedback voltage of 6V triggers over load protection (OLP). There is a time delay while charging external capacitor Cfb from 3V to 6V using an internal 5uA current source. This time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. This pin adjusts the peak current limit of the Sense FET. The feedback 0.9mA current source is diverted to the parallel combination of an internal 2.8k resistor and any external resistor to GND on this pin to determine the peak current limit. If this pin is tied to Vcc or left floating, the typical peak current limit will be 2.15A. This pin connects directly to the rectified AC line voltage source. At start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the Vcc reaches 12V, the internal switch is opened. The drain pins are designed to connect directly to the primary lead of the transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer will decrease leakage inductance.
2
Vcc
3
Vfb
4
Ipk
5
Vstr
6, 7, 8
Drain
Pin Configuration
8DIP 8LSOP GND 1 Vcc 2 Vfb 3 Ipk 4 8 Drain 7 Drain 6 Drain 5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDL0365RN, FSDM0365RN
Absolute Maximum Ratings
(Ta=25C, unless otherwise specified) Characteristic Drain Pin Voltage Vstr Pin Voltage Drain Current Pulsed Supply Voltage Feedback Voltage Range Total Power Dissipation Operating Junction Temperature Operating Ambient Temperature Storage Temperature
(1) (2)
Symbol VDRAIN VSTR IDM EAS VCC VFB PD TJ TA TSTG
Value 650 650 12.0 127 20 -0.3 to VCC 1.56 Internally limited -25 to +85 -55 to +150
Unit V V A mJ V V W C C C
Single Pulsed Avalanche Energy
Note: 1. Repetitive rating: Pulse width is limited by maximum junction temperature 2. L = 51mH, starting Tj = 25C
Thermal Impedance
(Ta=25C, unless otherwise specified) Parameter 8DIP Junction-to-Ambient Thermal(1) Junction-to-Case Thermal Junction-to-Top Thermal
(2) (3)
Symbol
Value 80.01 18.85 33.70
Unit C/W C/W C/W
JA JC JT
Note: 1. Free standing with no heatsink; Without copper clad. / Measurement Condition : Just before junction temperature TJ enters into OTP. 2. Measured on the DRAIN pin close to plastic interface. 3. Measured on the PKG top surface. - all items are tested with the standards JESD 51-2 and 51-10 (DIP).
4
FSDL0365RN, FSDM0365RN
Electrical Characteristics
(Ta = 25C unless otherwise specified) Parameter SENSE FET SECTION VDS=650V, VGS=0V Zero-Gate-Voltage Drain Current Drain-Source On-State Resistance(1) Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time CONTROL SECTION Switching Frequency Switching Frequency Modulation Switching Frequency Switching Frequency Modulation Switching Frequency Variation(2) Maximum Duty Cycle Minimum Duty Cycle UVLO Threshold Voltage Feedback Source Current Internal Soft Start Time BURST MODE SECTION Burst Mode Voltage PROTECTION SECTION Peak Current Limit Current Limit Delay Time
(3)
Symbol
Condition
Min. 61 1.5 45 1.0 71 0
Typ. 3.6 315 47 9 11.2 34 28.2 32 67 2.0 50 1.5 5 77 0 12 8 0.9 15 0.5 0.35 2.15 500 140 6.0 19 5.0 3 0.85 -
Max. 50 200 4.5 73 2.5 55 2.0 10 83 0 13 9 1.1 20 0.6 0.45 2.41 6.5 6.5 5 1.0 -
Unit A A
IDSS RDS(ON) CISS COSS CRSS td(on) tr td(off) tf fOSC fMOD fOSC fMOD fOSC DMAX DMIN VSTART VSTOP IFB tS/S VBURH VBURL ILIM tCLD TSD VSD VOVP IDELAY tLEB IOP ICH VSTR
VDS=520V, VGS=0V, TC=125C VGS=10V, ID=0.5A VGS=0V, VDS=25V, f=1MHz
pF pF pF ns ns ns ns KHz KHz KHz KHz % % % V V mA ms V V A ns C V V A ns mA mA V
VDS=325V, ID=1.0A
FSDM0365R FSDL0365R -25C Ta 85C
VFB=GND VFB=GND VFB=GND VFB=4V Max. inductor current -
11 7 0.7 10 0.4 0.25 1.89 125 5.5 18 3.5 200
Thermal Shutdown Temperature Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage
VFB=4V
VCC=14V VCC=0V VCC=0V
1 0.7 35
Note: 1. Pulse test: Pulse width 300us, duty 2% 2. These parameters, although guaranteed, are tested in EDS (wafer test) process 3. These parameters, although guaranteed, are not 100% tested in production
5
FSDL0365RN, FSDM0365RN
Comparison Between KA5x0365RN and FSDx0365RN
Function Soft-Start KA5x0365RN not applicable FSDx0365RN 15ms FSDx0365RN Advantages * Gradually increasing current limit during soft-start further reduces peak current and voltage stresses * Eliminates external components used for soft-start in most applications * Reduces or eliminates output overshoot * Smaller transformer * Allows power limiting (constant overload power) * Allows use of larger device for lower losses and higher efficiency. * Reduces conducted EMI * Improves light load efficiency * Reduces power consumption at noload * Transformer audible noise reduction * Greater immunity to arcing provoked by dust, debris and other contaminants
External Current Limit
not applicable
Programmable of default current limit
Frequency Modulation Burst Mode Operation
not applicable not applicable
2.0KHz @67KHz 1.5KHz @50KHz Built into controller
Drain Creepage at Package
1.02mm
7.62mm
6
FSDL0365RN, FSDM0365RN
Typical Performance Characteristics (Control Part)
(These characteristic graphs are normalized at Ta = 25C)
1.20 1.00 Normalized
Normalized
1.20 1.00 0.80 0.60 0.40 0.20 0.00
0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ] 100 150
-50
0
50 T emp[]
100
150
Operating Frequency (Fosc) vs. Ta
Frequency Modulation (FMOD) vs. Ta
1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[] 100 150
Normalized
1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ] 100 150
Maximum Duty Cycle (DMAX) vs. Ta
Operating Supply Current (IOP) vs. Ta
1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[] 100 150
1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[] 100 150
Normalized
Start Threshold Voltage (VSTART) vs. Ta
Stop Threshold Voltage (VSTOP) vs. Ta
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FSDL0365RN, FSDM0365RN
Typical Performance Characteristics (Continued)
1.20 1.00 Normalized
Normalized
1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[] 100 150 -50 0 50 T emp[] 100 150
0.80 0.60 0.40 0.20 0.00
Feedback Source Current (IFB) vs. Ta
Start Up Charging Current (ICH) vs. Ta
1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[] 100 150
1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ] 100 150
Normalized
Peak Current Limit (ILIM) vs. Ta
Burst Peak Current (IBUR(pk)) vs. Ta
1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[] 100 150
Over Voltage Protection (VOVP) vs. Ta
8
FSDL0365RN, FSDM0365RN
Functional Description
1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vstr pin had an external resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source and a switch that shuts off when 15ms goes by after the supply voltage, Vcc, gets above 12V. The source turns back on if Vcc drops below 8V. 3. Leading Edge Blanking (LEB) : At the instant the internal Sense FET is turned on, the primary side capacitance and secondary side rectifier diode reverse recovery typically cause a high current spike through the Sense FET. Excessive voltage across the Rsense resistor leads to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the Sense FET is turned on.
Vin,dc ISTR
Vstr Vcc
Vcc<8V UVLO on 15ms after Vcc12V UVLO off
J-FET ICH
Figure 4. High Voltage Current Source
2. Feedback Control : The FSDx0365RN employs current mode control, as shown in Figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increases, the feedback voltage Vfb is pulled down and it reduces the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased.
4. Protection Circuits : The FPS has several protective functions such as over load protection (OLP), over voltage protection (OVP), abnormal over current protection (AOCP), under voltage lock out (UVLO) and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, the reliability is improved without increasing cost. Once a fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage VSTOP (8V), the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage VSTART (12V), the FPS resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated.
Vcc 5uA
Vcc 0.9mA
OSC
Vo
Vfb 3
CFB
+
D1
D2 VFB,in
VFB
-
2.5R Gate driver
R
431
VSD
OLP
4.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is operating normally, the over load protection (OLP) circuit can be activated during the load transition. In order to avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. In conjunction with the Ipk current limit pin (if used) the current mode feedback path would limit the current in the Sense FET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (Vo) decreases below its rating voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 3V, the feedback input diode is blocked and the 5uA current source (IDELAY) starts to charge Cfb slowly up to Vcc. In this condition, VFB increases until it reaches 6V, when the switching operation is terminated as shown in Figure 6. The shutdown delay time is the time required to charge Cfb from 3V to 6V with 5uA current source.
Figure 5. Pulse Width Modulation (PWM) Circuit
9
FSDL0365RN, FSDM0365RN
VFB Over Load Protection 6V
VFB,in
PWM COMPARATOR
LEB
CLK Gate Driver
Drain
Vsense
AOCP COMPARATOR
S R
Q
3V
VAOCP
Rsense
t12= CFBx(V(t2)-V(t1)) / IDELAY t1 t2 t
t12 = C FB
V (t 2 ) - V (t1 ) ; I DELAY = 5 A, V (t1 ) = 3V , V (t 2 ) = 6V I DELAY
Figure 7. Abnormal Over Current Protection (AOCP)
Figure 6. Over Load Protection (OLP)
4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC to detect the temperature of the Sense FET. When the temperature exceeds approximately 140C, thermal shutdown is activated.
4.3 Abnormal Over Current Protection (AOCP) : Even though the FPS has OLP (Over Load Protection) and current mode PWM feedback, these are not enough to protect the FPS when a secondary side diode short or a transformer pin short occurs. In addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after latch mode is activated. The FPS has an internal AOCP (Abnormal Over Current Protection) circuit, as shown in Figure 7. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, pulse-by-pulse AOCP is triggered regardless of uncontrollable LEB time. Here, pulse-by-pulse AOCP stops the Sense FET within 350ns after it is activated.
4.4 Over Voltage Protection (OVP) : In the event of a malfunction in the secondary side feedback circuit, or an open feedback loop caused by a soldering defect, the current through the opto-coupler transistor becomes almost zero (refer to Figure 5). Then, VFB climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because excess energy is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FPS uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, OVP circuit is activated resulting in termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be properly designed to be below 19V.
10
FSDL0365RN, FSDM0365RN
5. Soft Start : The FPS has an internal soft start circuit that slowly increases the feedback voltage together with the Sense FET current after it starts up. The typical soft start time is 15msec, as shown in Figure 8, where progressive increments of the Sense FET current are allowed during the start-up phase. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode.
Burst Operation VFB
Burst Operation Normal Operation
VBURH VBURL Current Waveform Switching OFF Switching OFF
+
VBURH
Drain current
2.15A
Vcc IBUR(pk)
VBURL/VBURH
1ms 15steps
Vcc
Vcc IFB
Vfb
Current limit
0.98A
3
IDELAY
Normal
PWM
Burst
2.5R R
t
MOSFET Current
Figure 8. Soft Start Function Figure 9. Burst Operation Function
6. Burst Operation : In order to minimize power dissipation in standby mode, the FPS enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 9, the device automatically enters burst mode when the feedback voltage drops below VBURH(500mV). Switching still continues but the current limit is set to a fixed limit internally to minimize flux density in the transformer. The fixed current limit is larger than that defined by VFB = VBURH and therefore, VFB is driven down further. Switching continues until the feedback voltage drops below VBURL(350mV). At this point switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes the feedback voltage to rise. Once it passes VBURH(500mV), switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode.
7. Frequency Modulation : Modulating the switching frequency of a switched power supply can reduce EMI. Frequency modulation can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The amount of EMI reduction is directly related to the depth of the reference frequency. As can be seen in Figure 10, the frequency changes from 65KHz to 69KHz in 4ms for the FSDM0365RN (48.5KHz to 51.5KHz for FSDL0365RN). Frequency modulation allows the use of a cost effective inductor instead of an AC input mode choke to satisfy the requirements of world wide EMI limits.
Drain Current
ts fs=1/ts
69kHz 67kHz 65kHz
4ms
t
Figure 10. Frequency Modulation Waveform
11
FSDL0365RN, FSDM0365RN
Amplitude (dBV)
8. Adjusting Peak Current Limit : As shown in Figure 13, a combined 2.8k internal resistance is connected to the non-inverting lead on the PWM comparator. A external resistance of Rx on the current limit pin forms a parallel resistance with the 2.8k when the internal diodes are biased by the main current source of 900uA.
Vcc IDELAY
Vcc
5uA
Vfb 3
IFB
900uA 2k
PWM Comparator
0.8k
Frequency (MHz)
Figure 11. KA5-series FPS Full Range EMI scan(67KHz, no Frequency Modulation) with DVD Player SET
Rx
Ipk 4
SenseFET Current Sense
Figure 13. Peak Current Limit Adjustment
Amplitude (dBV)
For example, FSDx0365RN has a typical Sense FET peak current limit (ILIM) of 2.15A. ILIM can be adjusted to 1.5A by inserting Rx between the Ipk pin and the ground. The value of the Rx can be estimated by the following equations: 2.15A : 1.5A = 2.8k : Xk , X = Rx || 2.8k . (X represents the resistance of the parallel network)
Frequency (MHz)
Figure 12. FSDX-series FPS Full Range EMI Scan (67KHz, with Frequency Modulation) with DVD Player SET
12
FSDL0365RN, FSDM0365RN
Application Tips
1. Methods of Reducing Audible Noise Switching mode power converters have electronic and magnetic components, which generate audible noises when the operating frequency is in the range of 20~20,000 Hz. Even though they operate above 20 kHz, they can make noise depending on the load condition. Designers can employ several methods to reduce these noises. Here are three of these methods: Glue or Varnish The most common method involves using glue or varnish to tighten magnetic components. The motion of core, bobbin and coil and the chattering or magnetostriction of core can cause the transformer to produce audible noise. The use of rigid glue and varnish helps reduce the transformer noise. But, it also can crack the core. This is because sudden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio according to the temperature. Ceramic Capacitor Using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise reduction solution. Some dielectric materials show a piezoelectric effect depending on the electric field intensity. Hence, a snubber capacitor becomes one of the most significant sources of audible noise. It is considerable to use a zener clamp circuit instead of an RCD snubber for higher efficiency as well as lower audible noise. Adjusting Sound Frequency Moving the fundamental frequency of noise out of 2~4 kHz range is the third method. Generally, humans are more sensitive to noise in the range of 2~4 kHz. When the fundamental frequency of noise is located in this range, one perceives the noise as louder although the noise intensity level is identical. Refer to Figure 14. Equal Loudness Curves. When FPS acts in Burst mode and the Burst operation is suspected to be a source of noise, this method may be helpful. If the frequency of Burst mode operation lies in the range of 2~4 kHz, adjusting feedback loop can shift the Burst operation frequency. In order to reduce the Burst operation frequency, increase a feedback gain capacitor (CF), opto-coupler supply resistor (RD) and feedback capacitor (CB) and decrease a feedback gain resistor (RF) as shown in Figure 15. Typical Feedback Network of FPS.
Figure 14. Equal Loudness Curves
Figure 15. Typical Feedback Network of FPS
2. Other Reference Materials AN-4134: Design Guidelines for Off-line Forward Converters Using Fairchild Power Switch (FPSTM) AN-4137: Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS) AN-4140: Transformer Design Consideration for Off-line Flyback Converters using Fairchild Power Switch (FPSTM) AN-4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4147: Design Guidelines for RCD Snubber of Flyback AN-4148: Audible Noise Reduction Techniques for FPS Applications 13
FSDL0365RN, FSDM0365RN
Typical Application Circuit
Application Output power Input voltage Universal input (85-265Vac) Output voltage (Max current) 3.3V (1.0A) DVD Player 21W 5.1V (0.8A) 12V (0.5A) 16V (0.5A)
Features
* * * * * * High efficiency (>76% at universal input) Low standby mode power consumption (<1W at 230Vac input and 0.6W load) Low component count Enhanced system reliability through various protection functions Low EMI through frequency modulation Internal soft-start (15ms)
Key Design Notes
* The delay time for over load protection is designed to be about 30ms with C106 of 47nF. If faster/slower triggering of OLP is required, C106 can be changed to a smaller/larger value(eg. 100nF for about 60ms). * Using a resistor R104(39) on Ipk pin (#4), the pule-by-pulse peak current limit level(ILIM) is adjusted to about 2A. * The branch formed by D103, C108 and R106 provides another ILIM adjustment having a negative slope to the input voltage. The ILIM value decreases as the input voltage level increases. 1. Schematic
T101 EER2828 RT101 5D-9 R105 200k C103 47uF 400V 2 5 4 R106 300k R104 39k C107 47nF 50V 3 R102 56k C104 3.3nF 630V 1 11 D203 EGP20D L203 10uH 16V C205 470uF 35V L205 10uH 10 3 D204 EGP20D 12 L207 4.7uH D103 UF 4004 C106 D102 R103 47uF UF 4004 5 50V 4 5 C108 1uF 100V LF101 55mH 8 C302 2.2nF C101 100nF AC275V R201 510 R203 6.2k R202 1k TNR F101 FUSE IC302 FOD817A IC301 KA431 R205 6k R204 20k C215 100nF 6 D207 SB360 C213 1000uF 10V L206 4.7uH 9 D205 SB360 C209 1000uF 10V C210 1000uF 10V 3.3V C214 1000uF 10V 5.1V C207 470uF 35V C208 470uF 35V 12V C206 470uF 35V
2 D101 UF 4007
IC101 FSDM0365RN 3 Vstr Ipk Vfb 8 Drain 7 Drain 6 Drain Vcc 2
1
BD101
4 C102 100nF AC275V
GND 1
14
FSDL0365RN, FSDM0365RN
2. Transformer Schematic Diagram
EER2828 12 Np/2 1 Np/2 11 10 N16V N12V N16V N12V Na N5.1V 6mm 7 6 N3.3V Np/2 N5.1V 3mm
Np/2 2 3 Na 4 5
9N 3.3V 8
3. Winding Specification
P in (S F ) N p /2 3 2 W ire 0 .2 5 x 1 T u rn s 50 W in d in g M e th o d C e n te r S o le n o id w in d in g
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs N 3 .3 V N 5 .1 V 9 8 6 9 0 .3 3 x 2 0 .3 3 x 1 4 2 C e n te r S o le n o id w in d in g C e n te r S o le n o id w in d in g
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs Na 4 5 0 .2 5 x 1 16 C e n te r S o le n o id w in d in g
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs N 12V N 16V 10 12 11 12 0 .3 3 x 1 0 .3 3 x 1 14 18 C e n te r S o le n o id w in d in g C e n te r S o le n o id w in d in g In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 3 L a ye rs
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs N p /2 2 1 0 .2 5 x 1 50 C e n te r S o le n o id w in d in g
In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs
4. Electrical Characteristics
P in In d u c ta n c e Leakage 1 3 1 3 Spec. 1 .4 m H 1 0 % 25 uH M ax. R e m a rk 100kH z, 1V S h o r t a ll o t h e r p in s
5. Core & Bobbin Core : EER2828 ( Ae = 86.66 mm2 ) Bobbin : EER2828
15
FSDL0365RN, FSDM0365RN
6. Demo Circuit Part List
Part R102 R103 R104 R105 R106 R201 R202 R203 R204 R205 C101 C102 C103 C104 C106 C107 C108 C205 C206 C207 C208 C209 C210 C213 C214 C215 C302
Value Resistor 56K 5 39K 200K 300K 510 1K 6.2 K 20K 6K Capacitor 100nF/275AC 100nF/275AC 47uF/400V 3.3nF/630V 47uF/50V 47nF/50V 1uF/100V 470uF/35V 470uF/35V 470uF/35V 470uF/35V 1000uF/10V 1000uF/10V 1000uF/10V 1000uF/10V 100nF/50V 2.2nF
Note 1W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W Box Box Electrolytic Film Electrolytic Ceramic Electrolytic Electrolytic Electrolytic Electrolytic Electrolytic Electrolytic Electrolytic Electrolytic Electrolytic Ceramic AC Ceramic
Part L203 L205 L206 L207 D101 D102 D103 D203 D204 D205 D207 IC101 IC301 IC302
Value Inductor 10uH 10uH 4.7uH 4.7uH Diode UF4007 UF4004 UF4004 EGP20D EGP20D SB360 SB360 IC FSDM0365RN KA431(TL431) FOD817A Fuse
Note PN Ultra Fast PN Ultra Fast PN Ultra Fast PN Ultra Fast PN Ultra Fast Schottky Schottky FPSTM Voltage reference Opto-Coupler
FUSE
2A/250V NTC
RT101
5D-9 Bridge Diode
BD101
2KBP06M 2N257 Line Filter
Bridge Diode
LF101
55mH
-
16
FSDL0365RN, FSDM0365RN
7. Layout
7.1 Top image of PCB
7.2 Bottom image of PCB
17
FSDL0365RN, FSDM0365RN
Package Dimensions
8DIP
18
FSDL0365RN, FSDM0365RN
Package Dimensions (Continued)
8LSOP
19
FSDL0365RN, FSDM0365RN
Ordering Information
Product Number FSDM0365RN FSDL0365RN FSDM0365RL FSDL0365RL Package 8DIP 8DIP 8LSOP 8LSOP Marking Code DM0365R DL0365R DM0365R DL0365R BVDSS 650V 650V 650V 650V fOSC 67KHz 50KHz 67KHz 50KHz RDS(ON) 3.6 3.6 3.6 3.6
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 9/29/05 0.0m 001 (c) 2005 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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