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| www..com RTL8111C-GR RTL8111C-VB-GR RTL8111C-VC-GR INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESSTM APPLICATIONS DATASHEET Rev. 1.5 11 January 2008 Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw RTL8111C Datasheet COPYRIGHT (c)2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include www..com inaccuracies or typographical errors. technical TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engineer's reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision 1.0 1.1 Release Date 2006/12/12 2007/02/09 Summary First release. Changed Figure 1 Pin Assignments, page 3. Changed Table 8 Power and Ground, page 6. Removed SMBus table. Added Table 9 GPIO Pins, page 7. Changed Table 10 NC (Not Connected) Pins, page 4. Renamed VDD12 to DVDD12. Changed Figure 1 Pin Assignments, page 3 Changed Table 9 GPIO Pins, page 7. Added section 7 Switching Regulator, page 25. Changed Table 26 Absolute Maximum Ratings, page 31. Changed Table 27 Recommended Operating Conditions, page 31. Changed Table 30 Thermal Characteristics, page 32. Changed Table 37 Ordering Information, page 41. Changed Figure 19 Power Sequence, page 30 Changed Table 25 Power Sequence Parameter, page 30. Added Table 29 Oscillator Requirements, page 32. Changed Table 24 Inductor and Capacitor Parts List, page 25. Changed Table 37 Ordering Information, page 41. 1.2 2007/08/10 1.3 1.4 1.5 2007/09/05 2007/11/08 2008/01/11 Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet Table of Contents 1. 2. 3. 4. 5. GENERAL DESCRIPTION ..............................................................................................................................................1 FEATURES .........................................................................................................................................................................2 SYSTEM APPLICATIONS...............................................................................................................................................2 PIN ASSIGNMENTS .........................................................................................................................................................3 4.1. 5.1. www..com 5.2. PACKAGE IDENTIFICATION...........................................................................................................................................3 POWER MANAGEMENT/ISOLATION ..............................................................................................................................4 PCI EXPRESS INTERFACE .............................................................................................................................................4 EEPROM ....................................................................................................................................................................5 TRANSCEIVER INTERFACE............................................................................................................................................5 CLOCK .........................................................................................................................................................................5 REGULATOR AND REFERENCE......................................................................................................................................6 LEDS ...........................................................................................................................................................................6 POWER AND GROUND ..................................................................................................................................................6 GPIO PINS ...................................................................................................................................................................7 NC (NOT CONNECTED) PINS ........................................................................................................................................7 PIN DESCRIPTIONS.........................................................................................................................................................4 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 5.10. 6. FUNCTIONAL DESCRIPTION.......................................................................................................................................8 6.1. PCI EXPRESS BUS INTERFACE......................................................................................................................................8 6.1.1. PCI Express Transmitter ........................................................................................................................................8 6.1.2. PCI Express Receiver .............................................................................................................................................8 6.2. LED FUNCTIONS..........................................................................................................................................................8 6.2.1. Link Monitor...........................................................................................................................................................8 6.2.2. Rx LED ...................................................................................................................................................................9 6.2.3. Tx LED ...................................................................................................................................................................9 6.2.4. Tx/Rx LED ............................................................................................................................................................10 6.2.5. LINK/ACT LED ....................................................................................................................................................11 6.3. PHY TRANSCEIVER ...................................................................................................................................................12 6.3.1. PHY Transmitter...................................................................................................................................................12 6.3.2. PHY Receiver .......................................................................................................................................................12 6.4. NEXT PAGE ................................................................................................................................................................13 6.5. EEPROM INTERFACE ................................................................................................................................................13 6.6. POWER MANAGEMENT...............................................................................................................................................14 6.7. VITAL PRODUCT DATA (VPD)...................................................................................................................................16 6.8. MESSAGE SIGNALED INTERRUPT (MSI) .....................................................................................................................17 6.8.1. MSI Capability Structure in PCI Configuration Space ........................................................................................17 6.8.2. Message Control...................................................................................................................................................18 6.8.3. Message Address ..................................................................................................................................................19 6.8.4. Message Upper Address .......................................................................................................................................19 6.8.5. Message Data .......................................................................................................................................................19 6.9. MSI-X .......................................................................................................................................................................20 6.9.1. MSI-X Capability Structure in PCI Configuration Space.....................................................................................20 6.9.2. Message Control...................................................................................................................................................21 6.9.3. Table Offset/BIR ...................................................................................................................................................21 6.9.4. PBA Offset/PBA BIR.............................................................................................................................................22 6.9.5. Message Address for MSI-X Table Entries...........................................................................................................22 6.9.6. Message Upper Address for MSI-X Table Entries................................................................................................22 6.9.7. Message Data for MSI-X Table Entries................................................................................................................22 6.9.8. Vector Control for MSI-X Table Entries ..............................................................................................................23 Integrated Gigabit Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.9.9. Pending Bits for MSI-X PBA Entries....................................................................................................................23 6.10. RECEIVE-SIDE SCALING (RSS) ..................................................................................................................................23 6.10.1. Receive-Side Scaling (RSS) Initialization ........................................................................................................23 6.10.2. RSS Operation .................................................................................................................................................24 7. SWITCHING REGULATOR..........................................................................................................................................25 7.1. 7.2. 7.3. 7.4. 7.5. 8. www..com PCB LAYOUT.............................................................................................................................................................25 INDUCTOR AND CAPACITOR PARTS LIST....................................................................................................................25 MEASUREMENT CRITERIA..........................................................................................................................................26 TYPICAL SWITCHING REGULATOR PCB LAYOUT ......................................................................................................30 POWER SEQUENCE .....................................................................................................................................................30 CHARACTERISTICS......................................................................................................................................................31 8.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................31 8.2. RECOMMENDED OPERATING CONDITIONS .................................................................................................................31 8.3. CRYSTAL REQUIREMENTS..........................................................................................................................................31 8.4. OSCILLATOR REQUIREMENTS ....................................................................................................................................32 8.5. THERMAL CHARACTERISTICS.....................................................................................................................................32 8.6. DC CHARACTERISTICS...............................................................................................................................................32 8.7. AC CHARACTERISTICS...............................................................................................................................................33 8.7.1. Serial EEPROM Interface Timing ........................................................................................................................33 8.8. PCI EXPRESS BUS PARAMETERS................................................................................................................................34 8.8.1. Differential Transmitter Parameters ....................................................................................................................34 8.8.2. Differential Receiver Parameters .........................................................................................................................35 8.8.3. REFCLK Parameters............................................................................................................................................35 8.8.4. Auxiliary Signal Timing Parameters ....................................................................................................................39 MECHANICAL DIMENSIONS......................................................................................................................................40 ORDERING INFORMATION ...................................................................................................................................41 9. 10. Integrated Gigabit Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet List of Tables TABLE 1. POWER MANAGEMENT/ISOLATION ...............................................................................................................................4 TABLE 2. PCI EXPRESS INTERFACE..............................................................................................................................................4 TABLE 3. EEPROM .....................................................................................................................................................................5 TABLE 4. TRANSCEIVER INTERFACE ............................................................................................................................................5 TABLE 5. CLOCK ..........................................................................................................................................................................5 TABLE 6. REGULATOR AND REFERENCE ......................................................................................................................................6 TABLE 7. LEDS............................................................................................................................................................................6 TABLE 8. POWER AND GROUND ...................................................................................................................................................6 TABLE 9. GPIO PINS ....................................................................................................................................................................7 TABLE 10. NC (NOT CONNECTED) PINS ........................................................................................................................................7 www..com TABLE 11. EEPROM INTERFACE ................................................................................................................................................13 TABLE 12. MESSAGE CONTROL...................................................................................................................................................18 TABLE 13. MESSAGE ADDRESS ...................................................................................................................................................19 TABLE 14. MESSAGE UPPER ADDRESS ........................................................................................................................................19 TABLE 15. MESSAGE DATA .........................................................................................................................................................19 TABLE 16. MESSAGE CONTROL...................................................................................................................................................21 TABLE 17. TABLE OFFSET/BIR ...................................................................................................................................................21 TABLE 18. PBA OFFSET/PBA BIR..............................................................................................................................................22 TABLE 19. MESSAGE ADDRESS FOR MSI-X TABLE ENTRIES ......................................................................................................22 TABLE 20. MESSAGE UPPER ADDRESS FOR MSI-X TABLE ENTRIES ...........................................................................................22 TABLE 21. MESSAGE DATA FOR MSI-X TABLE ENTRIES ............................................................................................................22 TABLE 22. VECTOR CONTROL FOR MSI-X TABLE ENTRIES ........................................................................................................23 TABLE 23. PENDING BITS FOR MSI-X PBA ENTRIES ..................................................................................................................23 TABLE 24. INDUCTOR AND CAPACITOR PARTS LIST....................................................................................................................25 TABLE 25. POWER SEQUENCE PARAMETER.................................................................................................................................30 TABLE 26. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................31 TABLE 27. RECOMMENDED OPERATING CONDITIONS .................................................................................................................31 TABLE 28. CRYSTAL REQUIREMENTS..........................................................................................................................................31 TABLE 29. OSCILLATOR REQUIREMENTS ....................................................................................................................................32 TABLE 30. THERMAL CHARACTERISTICS.....................................................................................................................................32 TABLE 31. DC CHARACTERISTICS...............................................................................................................................................32 TABLE 32. EEPROM ACCESS TIMING PARAMETERS ..................................................................................................................33 TABLE 33. DIFFERENTIAL TRANSMITTER PARAMETERS ..............................................................................................................34 TABLE 34. DIFFERENTIAL RECEIVER PARAMETERS.....................................................................................................................35 TABLE 35. REFCLK PARAMETERS .............................................................................................................................................35 TABLE 36. AUXILIARY SIGNAL TIMING PARAMETERS.................................................................................................................39 TABLE 37. ORDERING INFORMATION ..........................................................................................................................................41 Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet List of Figures FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. FIGURE 10. www..com FIGURE 11. FIGURE 12. FIGURE 13. FIGURE 14. FIGURE 15. FIGURE 16. FIGURE 17. FIGURE 18. FIGURE 19. FIGURE 20. FIGURE 21. FIGURE 22. FIGURE 23. FIGURE 24. FIGURE 25. FIGURE 26. FIGURE 27. FIGURE 28. PIN ASSIGNMENTS .......................................................................................................................................................3 RX LED.......................................................................................................................................................................9 TX LED.......................................................................................................................................................................9 TX/RX LED...............................................................................................................................................................10 LINK/ACT LED .......................................................................................................................................................11 MSI CAPABILITY STRUCTURE ...................................................................................................................................17 MSI-X CAPABILITY STRUCTURE ...............................................................................................................................20 MSI-X TABLE STRUCTURE........................................................................................................................................20 MSI-X PBA STRUCTURE...........................................................................................................................................20 SWITCHING REGULATOR ILLUSTRATION...................................................................................................................25 INPUT VOLTAGE OVERSHOOT <4V (GOOD)..............................................................................................................26 INPUT VOLTAGE OVERSHOOT >4V (BAD) ................................................................................................................26 CERAMIC 22F 1210 (X5R) (GOOD).........................................................................................................................27 CERAMIC 22F 0805 (Y5V) (BAD) ...........................................................................................................................27 ELECTROLYTIC 100F (RIPPLE TOO HIGH) ...............................................................................................................28 4R7GTSD32 (GOOD) ...............................................................................................................................................29 1H BEAD (BAD) ......................................................................................................................................................29 TYPICAL SWITCHING REGULATOR PCB LAYOUT .....................................................................................................30 POWER SEQUENCE ....................................................................................................................................................30 SERIAL EEPROM INTERFACE TIMING......................................................................................................................33 SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING .................................................37 SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT ..........................................................................37 SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING .......................................................37 DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD ...................................................................38 DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME ...........................................................................38 DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK............................................................................................38 REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING .........................................................................39 AUXILIARY SIGNAL TIMING......................................................................................................................................39 Integrated Gigabit Ethernet Controller for PCI Express vi Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 1. General Description The Realtek RTL8111C-GR/RTL8111C-VB-GR/RTL8111C-VC-GR Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8111C offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. www..com The RTL8111C is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. Advanced Configuration Power management Interface (ACPI)--power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)--is supported to achieve the most efficient power management possible. PCI MSI (Message Signaled Interrupt) and MSI-X are also supported. In addition to the ACPI feature, remote wake-up (including AMD Magic PacketTM and Microsoft(R) Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To support WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8111C. The RTL8111C is fully compliant with Microsoft(R) NDIS5, NDIS6(IPv4, IPv6, TCP, UDP) Checksum and Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The RTL8111C supports Receive Side Scaling (RSS) to hash incoming TCP connections and load-balance received data processing across multiple CPUs. RSS improves the number of transactions per second and number of connections per second, for increased network throughput. The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin count, serial, interconnect technology that offers significant improvements in performance over conventional PCI and also maintains software compatibility with existing PCI infrastructure. The device embeds an adaptive equalizer in the PCIe PHY for ease of system integration and excellent link quality. The equalizer enables the length of the PCB traces to reach 40 inches. The RTL8111C is suitable for multiple market segments and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications. Note: RTL8111C-GR, RTL8111C-VB-GR, and RTL8111C-VB-GR differences are listed in section 10 Ordering Information, page 41. Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 2. Features Integrated 10/100/1000 transceiver Auto-Negotiation with Next Page capability Supports PCI ExpressTM 1.1 Supports IEEE 802.1P Layer 2 Priority Encoding Supports IEEE 802.1Q VLAN tagging Serial EEPROM Transmit/Receive on-chip buffer support Supports power down/link down power saving Built-in switching regulator Supports PCI MSI (Message Signaled Interrupt) and MSI-X Supports Receive-Side Scaling (RSS) 64-pin QFN package (Green package) Embeds an adaptive equalizer in PCI Express PHY (PCB traces can reach up to 40 inches) www..com Supports pair swap/polarity/skew correction Crossover Detection & Auto-Correction Wake-on-LAN and remote wake-up support Microsoft(R) NDIS5, NDIS6 Checksum Offload (IPv4, IPv6, TCP, UDP) and Segmentation Task-offload (Large send and Giant send) support Supports Full Duplex flow control (IEEE 802.3x) Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab 3. System Applications PCI ExpressTM Gigabit Ethernet on Motherboard, Notebook, or Embedded system Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 4. Pin Assignments ISOLATEB CLKREQB EEDI/AUX DVDD12 VDD33 DVDD12 EEDO EESK EECS VDD33 NC NC NC NC DVDD12 GPI www..com GPO DVDD12 VDD33 LED3 LED2 LED1 LED0 AVDD12 AVDD33 CKTAL1 CKTAL2 ENSR VDDSR RSET 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 65 GND (Exposed Pad) 31 30 29 28 NC NC DVDD12 EGND HSON HSOP EVDD12 REFCLK_N REFCLK_P EGND HSIN HSIP EVDD12 DVDD12 PERSTB LANWAKEB NC NC RTL8111C 27 26 25 24 23 LLLLLLL TXXXV 22 21 20 19 18 17 10 11 12 13 14 15 16 AVDD33 AVDD12 AVDD12 SROUT12 Figure 1. Pin Assignments 4.1. Package Identification `Green' package is indicated by a `G' in the location marked `T' in Figure 1. The version number is shown in the location marked `V'. Integrated Gigabit Ethernet Controller for PCI Express 3 AVDD12 MDIN3 Track ID: JATR-1076-21 VDD33 MDIP0 MDIN0 MDIN1 MDIP2 MDIN2 MDIP1 MDIP3 FB12 NC Rev. 1.5 RTL8111C Datasheet 5. Pin Descriptions I: Input O: Output T/S: Tri-State Bi-Directional Input/Output S/T/S: Sustained Tri-State O/D: Open Drain The signal type codes below are used in the following tables: www..com 5.1. Power Management/Isolation Type O/D Pin No 19 Table 1. Power Management/Isolation Description Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot's main power rails and reference clocks. Isolate Pin: Active low. Used to isolate the RTL8111C from the PCI Express bus. The RTL8111C will not drive its PCI Express outputs (excluding LANWAKEB) and will not sample its PCI Express input as long as the Isolate pin is asserted. Symbol LANWAKEB ISOLATEB I 36 5.2. PCI Express Interface Type I I O O I I I Table 2. PCI Express Interface Pin No Description 26 PCI Express Differential Reference Clock Source: 100MHz 300ppm. 27 29 PCI Express Transmit Differential Pair. 30 23 PCI Express Receive Differential Pair. 24 PCI Express Reset Signal: Active low. When the PERSTB is asserted at power-on state, the RTL8111C returns to a 20 pre-defined reset state and is ready for initialization and configuration after the de-assertion of the PERSTB. Reference Clock Request Signal. 33 This signal is used by the RTL8111C to request starting of the PCI Express reference clock. Symbol REFCLK_P REFCLK_N HSOP HSON HSIP HSIN PERSTB CLKREQB O/D Integrated Gigabit Ethernet Controller for PCI Express 4 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 5.3. Symbol EESK EEPROM Type O Pin No 48 Table 3. EEPROM Description Serial Data Clock. EEDI: Output to serial data input pin of EEPROM. AUX: Input pin to detect if Aux. Power exists or not on initial power-on. This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8111C assumes that no Aux. Power exists. Input from Serial Data Output Pin of EEPROM. EECS: EEPROM chip select. EEDI/AUX OI 47 EEDO www..com EECS I O 45 44 5.4. Symbol MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 Transceiver Interface Type IO IO IO IO IO IO IO IO Pin No 3 4 6 7 9 10 12 13 Table 4. Transceiver Interface Description In MDI mode, this is the first pair in 1000Base-T, i.e., the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in 10Base-T and 100Base-TX. In MDI mode, this is the second pair in 1000Base-T, i.e., the BI_DB+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair. 5.5. Symbol CKTAL1 CKTAL2 Clock Type I O Pin No 60 61 Table 5. Clock Description Input of 25MHz Clock Reference. Output of 25MHz Clock Reference. Integrated Gigabit Ethernet Controller for PCI Express 5 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 5.6. Symbol SROUT12 FB12 ENSR VDDSR RSET www..com Regulator and Reference Type O I I Power I Pin No 1 5 62 63 64 Table 6. Regulator and Reference Description Switching Regulator 1.2V Output. Connect to 5H inductor. Feedback Pin for Switching Regulator. 3.3V: Enable switching regulator. 0V: Disable switching regulator. Digital 3.3V Power Supply for Switching Regulator. Reference. External resistor reference. 5.7. Symbol LED0 LED1 LED2 LEDs Table 7. Type O O O Pin No 57 56 55 Description LEDS1-0 LED0 LED1 00 Tx/Rx LINK100 LINK10 LINK1000 01 Tx/Rx LINK10/100/ 1000 LINK10/100 LINK1000 10 Tx LINK Rx FULL 11 LINK10/ACT LINK100/ ACT FULL LINK1000/ ACT LEDs LED3 O 54 LED2 LED3 Note 1: During power down mode, the LED signals are logic high. Note 2: LEDS1-0's initial value comes from the 93C46. If there is no 93C46, the default value of the (LEDS1, LEDS0)=(1, 1). 5.8. Power and Ground Table 8. Power and Ground Symbol Type Pin No Description VDD33 Power 16, 37, 46, 53 Digital 3.3V Power Supply. DVDD12 Power 21, 32, 38, 43, 49, 52 Digital 1.2V Power Supply. AVDD12 Power 8, 11, 14, 58 Analog 1.2V Power Supply. EVDD12 Power 22, 28 Analog 1.2V Power Supply. AVDD33 Power 2, 59 Analog 3.3V Power Supply. EGND Power 25, 31 Analog Ground. GND Power 65 Ground (Exposed Pad). Note: Refer to the most updated schematic circuit for correct configuration. Integrated Gigabit Ethernet Controller for PCI Express 6 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 5.9. Symbol GPI GPO GPIO Pins Type I O Pin No 50 51 Table 9. GPIO Pins Description General Purpose Input Pin. General Purpose Output Pin. This pin reflects the link up or link down state. High: Link up Low: Link down www..com 5.10. NC (Not Connected) Pins Symbol NC Type Table 10. NC (Not Connected) Pins Pin No Description 15, 17, 18, 34, 35, 39, 40, 41, 42 Not Connected. Integrated Gigabit Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6. 6.1. Functional Description PCI Express Bus Interface The RTL8111C is compliant with PCI Express Base Specification Revision 1.1, and runs at a 2.5GHz signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8111C supports four types of PCI Express messages: interrupt messages, error messages, power management messages, and hot-plug messages. To ease PCB layout constraints, PCI Express lane polarity reversal and link reversal are also supported. www..com 6.1.1. PCI Express Transmitter The RTL8111C's PCI Express block receives digital data from the Ethernet interface and performs data scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology into 10-bit code groups. Data scrambling is used to reduce the possibility of electrical resonance on the link, and 8B/10B coding technology is used to benefit embedded clocking, error detection, and DC balance by adding an overhead to the system through the addition of 2 extra bits. The data code groups are passed through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB trace to its upstream device via a differential driver. 6.1.2. PCI Express Receiver The RTL8111C's PCI Express block receives 2.5Gbps serial data from its upstream device to generate parallel data. The receiver's PLL circuits are re-synchronized to maintain bit and symbol lock. Through 8B/10B decoding technology and data de-scrambling, the original digital data is recovered and passed to the RTL8111C's internal Ethernet MAC to be transmitted onto the Ethernet media. 6.2. LED Functions The RTL8111C supports four LED signals in four different configurable operation modes. The following sections describe the various LED actions. 6.2.1. Link Monitor The Link Monitor senses link integrity, such as LINK10, LINK100, LINK1000, LINK10/100/1000, LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no network connection exists. Integrated Gigabit Ethernet Controller for PCI Express 8 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.2.2. Rx LED Power On In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. LED = High www..com Receiving Packet? Yes No LED = High for 40 ms LED = Low for 40 ms Figure 2. Rx LED 6.2.3. Tx LED Power On In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. LED = High Transmitting Packet? Yes No LED = High for 40 ms LED = Low for 40 ms Figure 3. Integrated Gigabit Ethernet Controller for PCI Express Tx LED 9 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.2.4. Tx/Rx LED In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring. Power On LED = High www..com Tx/Rx Packet? Yes No LED = High for 40 ms LED = Low for 40 ms Figure 4. Tx/Rx LED Integrated Gigabit Ethernet Controller for PCI Express 10 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.2.5. LINK/ACT LED In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8111C is linked and operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Power On LED = High www..com Link? Yes LED = Low No No Tx/Rx Packet? Yes LED = High for 40 ms LED = Low for 40 ms Figure 5. LINK/ACT LED Integrated Gigabit Ethernet Controller for PCI Express 11 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.3. 6.3.1. PHY Transceiver PHY Transmitter Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8111C operates at 10/100/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), and CAT.3 UTP cable (10Mbps). GMII (1000Mbps) Mode The RTL8111C's PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding technology. These code groups are www..com passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter. MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. MII (10Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter. 6.3.2. PHY Receiver GMII (1000Mbps) Mode Input signals from the media pass through the sophisticated on-chip hybrid circuit to separate the transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received signal is processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5 decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the Rx Buffer Manager. MII (100Mbps) Mode The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz. MII (10Mbps) Mode The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz. Integrated Gigabit Ethernet Controller for PCI Express 12 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.4. Next Page If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and Reg8 as defined in IEEE 802.3ab. 6.5. EEPROM Interface The RTL8111C requires the attachment of an external EEPROM. The 93C46/93C56 is a 1K-bit/2K-bit EEPROM. The EEPROM interface permits the RTL8111C to read from, and write data to, an external www..com serial EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be overridden following a power-on or software EEPROM auto-load command. The RTL8111C will auto-load values from the EEPROM. If the EEPROM is not present, the RTL8111C initialization uses default values for the appropriate Configuration and Operational Registers. Software can read and write to the EEPROM using bit-bang accesses via the 9346CR Register, or using PCI VPD (Vital Product Data). The interface consists of EESK, EECS, EEDO, and EEDI. The correct EEPROM (i.e., 93C46/93C56) must be used in order to ensure proper LAN function. EEPROM EECS EESK EEDI/Aux EEDO Table 11. EEPROM Interface Description 93C46/93C56 Chip Select. EEPROM Serial Data Clock. Input Data Bus/Input Pin to Detect Whether Aux. Power Exists on Initial Power-On. This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8111C assumes that no Aux. Power exists. Output Data Bus. Integrated Gigabit Ethernet Controller for PCI Express 13 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.6. Power Management The RTL8111C is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI Express Active State Power Management (ASPM), and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8111C can monitor the network for a Wakeup Frame, a Magic Packet, and notify the system via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin when such a packet or event occurs. Then the system can be restored to a normal state to process incoming jobs. www..com When the RTL8111C is in power down mode (D1 ~ D3): * The Rx state machine is stopped. The RTL8111C monitors the network for wakeup events such as a Magic Packet and Wakeup Frame in order to wake up the system. When in power down mode, the RTL8111C will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx on-chip buffer. * The on-chip buffer status and packets that have already been received into the Rx on-chip buffer before entering power down mode are held by the RTL8111C. * Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held. * After being restored to D0 state, the RTL8111C transmits data that was not moved into the Tx on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI configuration space depend on the existence of Aux power. If aux. power is absent, the above 4 bits are all 0 in binary. Example: If EEPROM D3c_support_PME = 1: * If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C3 FF, then PCI PMC = C3 FF) * If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0's (if EEPROM PMC = C3 FF, then PCI PMC = 03 7E) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C3 FF (Realtek EEPROM default value). If EEPROM D3c_support_PME = 0: * If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C3 7F, then PCI PMC = C3 7F) * If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0's (if EEPROM PMC = C3 7F, then PCI PMC = 03 7E) In the above case, if wakeup support is not desired when main power is off, it is suggested that the EEPROM PMC be set to 03 7E. Integrated Gigabit Ethernet Controller for PCI Express 14 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet Magic Packet Wakeup occurs only when the following conditions are met: * * * The destination address of the received Magic Packet is acceptable to the RTL8111C, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8111C adapter. The received Magic Packet does not contain a CRC error. The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state. The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet. * www..com A Wakeup Frame event occurs only when the following conditions are met: The destination address of the received Wakeup Frame is acceptable to the RTL8111C, e.g., a broadcast, multicast, or unicast address to the current RTL8111C adapter. * The received Wakeup Frame does not contain a CRC error. * The PMEn bit (CONFIG1#0) is set to 1. * The 16-bit CRCA of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup Frame pattern given by the local machine's OS. Or, the RTL8111C is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. Note: 16-bit CRC: The RTL8111C supports eight long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). The corresponding wake-up method (message or LANWAKEB) is asserted only when the following conditions are met: * * * The PMEn bit (bit0, CONFIG1) is set to 1. The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1. The RTL8111C may assert the corresponding wake-up method (message or LANWAKEB) in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space. A Magic Packet, LinkUp, or Wakeup Frame has been received. Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8111C to stop asserting the corresponding wake-up method (message or LANWAKEB) (if enabled). * * * When the RTL8111C is in power down mode, e.g., D1-D3, the IO and MEM accesses to the RTL8111C are disabled. After a PERSTB assertion, the device's power state is restored to D0 automatically if the original power state was D3cold. There is almost no hardware delay at the device's power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed from the EEPROM, if required. Integrated Gigabit Ethernet Controller for PCI Express 15 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.7. Vital Product Data (VPD) Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8111C's PCI Configuration Space is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data between the VPD data register and the 93C46/93C56/93C66 has completed or not. Write VPD register: (write data to the 93C46/93C56/93C66) Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When the flag bit is reset to 0 by the RTL8111C, the VPD data (4 bytes per VPD access) has been transferred from the VPD data register to EEPROM. www..com Read VPD register: (read data from the 93C46/93C56/93C66) Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8111C, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register. Note1: Refer to the PCI 2.3 Specifications for further information. Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.3 Specifications. VPD data is always consecutive 4-byte data starting from the VPD address specified. Note3: Realtek reserves offset 60h to 7Fh in EEPROM mainly for VPD data to be stored. Note4: The VPD function of the RTL8111C is designed to be able to access the full range of the 93C46/93C56/93C66 EEPROM. Integrated Gigabit Ethernet Controller for PCI Express 16 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.8. 6.8.1. Message Signaled Interrupt (MSI) MSI Capability Structure in PCI Configuration Space www..com Figure 6. MSI Capability Structure Integrated Gigabit Ethernet Controller for PCI Express 17 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.8.2. Bits 15:8 7 Message Control RW RO RO Table 12. Message Control Description Reserved. Always return 0 1: The RTL8111C is capable of generating a 64-bit message address. 0: The RTL8111C is NOT capable of generating a 64-bit message address. This bit is read only and the RTL8111C is set to 1. Multiple Message Enable System software (e.g., BIOS, OS) indicates to the RTL8111C the number of allocated messages/vectors (equal to or less than the number of requested messages/vectors). This field after PCI reset is `000'. Encoding Number of Messages/Vectors 000 1 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved Field Reserved 64-bit Address Capable Multiple Message Capable Indication to system software (e.g., BIOS, OS) of the number of RTL8111C requested vectors. The RTL8111C supports only one vector messages/vectors. Encoding Number of Messages/Vectors 000 1 Others Reserved MSI Enable 1: Enable MSI (Also the INTx pin is disabled automatically, MSI and INTx are mutually exclusive), this bit is set by system software. 0: Disable MSI (Default value after power-on or PCI reset) 6:4 RW www..com 3:1 RO 0 RW Integrated Gigabit Ethernet Controller for PCI Express 18 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.8.3. Bits 31:02 01:00 Message Address RW RW RO Field Message Address Reserved Table 13. Message Address Description System-Specified Message/Vector Address. Low DWORD aligned address for MSI memory write transaction. Always Return `00'. This bit is read only. www..com 6.8.4. Message Upper Address RW RW Table 14. Message Upper Address Field Description Message Upper Address System-Specified Message/Vector Upper Address. Upper 32 bits of a 64-bit message/vector address. This register is effective only when the DAC function is enabled, i.e., 64-bit addressing is enabled; bit7 in Message Control register is set. If the contents of this register are 0, the RTL8111C only performs 32-bit addressing for the memory write of the messages/vectors. This bit is read/write. Bits 31:00 6.8.5. Bits 15:00 Message Data RW RW Field Message Data Table 15. Message Data Description If the Message Enable bit is set, the message/vector data is driven onto the lower word of the memory write transaction's data phase. This bit is read/write. Integrated Gigabit Ethernet Controller for PCI Express 19 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.9. 6.9.1. MSI-X MSI-X Capability Structure in PCI Configuration Space www..com Figure 7. MSI-X Capability Structure Figure 8. MSI-X Table Structure Figure 9. MSI-X PBA Structure Integrated Gigabit Ethernet Controller for PCI Express 20 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.9.2. Bits 15 Message Control RW RW Field MSI-X Enable Table 16. Message Control Description If 1 and the MSI Enable bit in the MSI Message Control register is 0, the function is permitted to use MSI-X to request service and is prohibited from using its INTx# pin. System configuration software sets this bit to enable MSI-X. A device driver is prohibited from writing this bit to mask a function's service request. If 0, the function is prohibited from using MSI-X to request service. This bit's state after reset is 0 (MSI-X is disabled). This bit is read/write. If 1, all of the vectors associated with the function are masked, regardless of their per-vector Mask bit states. If 0, each vector's Mask bit determines whether the vector is masked or not. Setting or clearing the MSI-X Function Mask bit has no effect on the state of the per-vector Mask bits. This bit's state after reset is 0 (unmasked). This bit is read/write. Always Returns 0 on a Read. A write operation has no effect. System software reads this field to determine the MSI-X Table Size N, which is encoded as N-1. The RTL8111C value is `00000000001', indicating a table size of 2. www..com 14 RW Function Mask 13:11 10:00 RO RO Reserved Table Size 6.9.3. Bits 31:03 Table Offset/BIR RW RW Field Table Offset Table 17. Table Offset/BIR Description Used as an offset from the address contained by one of the function's Base Address registers to point to the base of the MSI-X Table. The lower 3 BIR bits are masked off (set to zero) by software to form a 32bit QWORD-aligned offset. This field is read only. Indicates which one of a function's Base Address registers, located beginning at 10h in Configuration Space, is used to map the function's MSI-X Table into Memory Space. BIR Value Base Address Register 0 10h 1 14h 2 18h 3 1Ch 4 20h 5 24h 6 Reserved 7 Reserved For a 64-bit Base Address register, the BIR indicates the lower DWORD. With PCI-to-PCI bridges, BIR values 2 through 5 are also reserved. The function's Base Address registers of RTL8111C located beginning at 20h. This field is read only. 02:00 RO BIR Integrated Gigabit Ethernet Controller for PCI Express 21 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.9.4. Bits 31:03 PBA Offset/PBA BIR RW RO Field PBA Offset Table 18. PBA Offset/PBA BIR Description Used as an offset from the address contained by one of the function's Base Address registers to point to the base of the MSI-X PBA. The lower 3 PBA BIR bits are masked off (set to zero) by software to form a 32-bit QWORD-aligned offset. This field is read only. Indicates which one of a function's Base Address registers, located beginning at 10h in Configuration Space, is used to map the function's MSI-X PBA into Memory Space. The PBA BIR value definitions are identical to those for the MSI-X Table BIR. This field is read only. 02:00 www..com RO PBA BIR 6.9.5. Bits 31:02 Message Address for MSI-X Table Entries RW RW Table 19. Message Address for MSI-X Table Entries Field Description Message Address System-Specified Message Lower Address. For MSI-X messages, the contents of this field from an MSI-X Table entry specifies the lower portion of the DWORD aligned address for the memory write transaction. This field is read/write. Message Address For proper DWORD alignment, software must always write zeroes to these two bits; otherwise the result is undefined. The state of these bits after reset must be 0. These bits are permitted to be read only or read/write. 01:00 RW 6.9.6. Bits 31:00 Message Upper Address for MSI-X Table Entries RW RW Table 20. Message Upper Address for MSI-X Table Entries Field Description Message Upper Address System-Specified Message Upper Address Bits. This field is read/write. 6.9.7. Bits 31:00 Message Data for MSI-X Table Entries RW RW Table 21. Message Data for MSI-X Table Entries Field Description Message Data System-Specified Message Data. For MSI-X messages, the contents of this field are taken from an MSI-X Table entry. In contrast to message data used for MSI messages, the low-order message data bits in MSI-X messages are not modified by the function. This field is read/write. Integrated Gigabit Ethernet Controller for PCI Express 22 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 6.9.8. Bits 31:01 Vector Control for MSI-X Table Entries RW RW Table 22. Vector Control for MSI-X Table Entries Field Description Reserved After reset, the state of these bits must be 0. However, for potential future use, software must preserve the value of these reserved bits when modifying the value of other Vector Control bits. If software modifies the value of these reserved bits, the result is undefined. Mask Bit When this bit is set, the function is prohibited from sending a message using this MSI-X Table entry. However, any other MSI-X Table entries programmed with the same vector will still be capable of sending an equivalent message unless they are also masked. This bit's state after reset is 1 (entry is masked). This bit is read/write. 00 RW www..com 6.9.9. Bits 63:00 Pending Bits for MSI-X PBA Entries RW RW Table 23. Pending Bits for MSI-X PBA Entries Field Description Pending Bits For each Pending Bit that is set, the function has a pending message for the associated MSI-X Table entry. Pending bits that have no associated MSI-X Table entry are reserved. After reset, the state of reserved Pending bits must be 0. Software should never write, and should only read Pending Bits. If software writes to Pending Bits, the result is undefined. Each Pending Bit's state after reset is 0 (no message pending). These bits are permitted to be read only or read/write. 6.10. Receive-Side Scaling (RSS) The RTL8111C is compliant with the new Network Driver Interface Specification (NDIS) 6.0 Receive-Side Scaling (RSS) technology for the Microsoft Windows family of operating systems. RSS allows packet receive-processing from a network adapter to be balanced across the number of available computer processors, increasing performance on multi CPU platforms. 6.10.1. Receive-Side Scaling (RSS) Initialization During RSS initialization, the Windows operating system will inform the RTL8111C to store the following parameters: hash function, hash type, hash bits, indirection table, BaseCPUNumber, and the secret hash key. Hash Function The default hash function is the Toeplitz hash function. Integrated Gigabit Ethernet Controller for PCI Express 23 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet Hash Type The hash types indicate which field of the packet needs to be hashed to get the hash result. There are several combinations of these fields, mainly, TCP/IPv4, IPv4, TCP/IPv6, IPv6, and IPv6 extension headers. TCP/IPv4 requires hash calculations over the IPv4 source address, the IPv4 destination address, the source TCP port and the destination TCP port. * IPv4 requires hash calculations over the IPv4 source address and the IPv4 destination address. * TCP/IPv6 requires hash calculations over the IPv6 source address, the IPv6 destination address, the source TCP port and the destination TCP port. www..com * IPv6 requires hash calculations over the IPv6 source address and the IPv6 destination address (Note: The RTL8111C does not support the IPv6 extension header hash type in RSS). Hash Bits Hash bits are used to index the hash result into the indirection table Indirection Table The Indirection Table stores values that are added to the BaseCPUNumber to enable RSS interrupts to be restricted from some CPUs. The OS will update the Indirection Table to rebalance the load. BaseCPUNumber The lowest number CPU to use for RSS. BaseCPUNumber is added to the result of the indirection table lookup. Secret hash key The key used in the Toeplitz function. For different hash types, the key size is different. * 6.10.2. RSS Operation After the parameters are set, the RTL8111C will start hash calculation on each incoming packet and forward each packet to its correct queue according to the hash result. If the incoming packet is not in the hash type, it will be forwarded to the primary queue. The hash result plus the BaseCPUNumber will be indexed into the indirection table to get the correct CPU number. The RTL8111C uses three methods to inform the system of incoming packets: inline interrupt, MSI, and MSIX. Periodically the OS will update the indirection table to rebalance the load across the CPUs. Integrated Gigabit Ethernet Controller for PCI Express 24 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 7. 7.1. * * Switching Regulator PCB Layout The RTL8111C incorporates a state-of-the-art switching regulator which requires a well-designed PCB layout in order to achieve good power efficiency and lower the output voltage ripple and input overshoot. The input 3.3V power trace connected to pin 63 (VDDSR) should be wider than 40mils. The bulk de-coupling capacitors (C82 and C83) should be placed within 200mils (0.5cm) of pin 63 to prevent input voltage overshoot. * The output power trace out of pin 1 (SROUT12) should be wider than 60mils. www..com * Keep L20 within 200mils (0.5cm) of pin1. * Keep C18 and C19 within 200mils (0.5cm) of L20 to ensure stable output power and better power efficiency. * Both C18 and C82 are strongly recommended to be ceramic capacitors. Note: Violation of the above rules will damage the IC. Figure 10. Switching Regulator Illustration 7.2. Inductor and Capacitor Parts List Table 24. Inductor and Capacitor Parts List Q at 500KHz ESR at 500KHz (M) Max I (mA) 57.15 281 1100 67.35 59.7 313 375 900 1510 Output Ripple (mV) 12.6 12 10.4 Load Transient (mV) 81.0 73.0 Inductor Type 4R7GTSD32 (best efficiency) 6R8GTSD32 6R8GTSD53 Capacitor Type Capacitance ESR at 500KHz (M) Output Ripple (mV) 22F 1210 TDK 21.5F 24.25 9.6 22F 1210 X5R 22.15F 24.90 10.4 Note: Capacitors (C18 & C82) are suggested to be ceramic due to their low ESR value. Integrated Gigabit Ethernet Controller for PCI Express 25 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 7.3. Measurement Criteria In order for the switching regulator to operate properly, the input and output voltage measurement criteria must be met. From the input side, the voltage overshoot cannot exceed 4V; otherwise the chip may be damaged. Note that the voltage signal must be measured directly at Pin 63, not at the capacitor. In order to reduce the input voltage overshoot, the C82 and C83 must be placed close to Pin 63. The following figures show what a good input voltage and a bad one look like. www..com Figure 11. Input Voltage Overshoot <4V (Good) Figure 12. Input Voltage Overshoot >4V (Bad) Integrated Gigabit Ethernet Controller for PCI Express 26 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet From the output side measured at Pin 1, the voltage ripple must be within 100mV. Choosing different types and values of output capacitor (C18, C19) and power inductor (L20) will seriously affect the efficiency and output voltage ripple of switching regulators. The following figures show the effects of different types of capacitors on the switching regulator's output voltage. The blue square wave signal (top row) is measured at the output of SROUT12 (Pin1) before the power inductor (L20). The yellow signal (second row) is measured after the power inductor (L20), and shows there is a voltage ripple. The green signal (lower row) is the current. Data in the following figures was measured at gigabit speed. www..com Figure 13. Ceramic 22F 1210 (X5R) (Good) Figure 14. Ceramic 22F 0805 (Y5V) (Bad) Integrated Gigabit Ethernet Controller for PCI Express 27 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet A ceramic 22F (X5R) will have a lower voltage ripple compared to the electrolytic 100F. The key to choosing a proper output capacitor is to choose the lowest ESR to reduce the output voltage ripple. Choosing a ceramic 22F 0805 (Y5V) in this case will cause malfunction of the switching regulator. Placing several Electrolytic capacitors in parallel will help lower the output voltage ripple. www..com Figure 15. Electrolytic 100F (Ripple Too High) Integrated Gigabit Ethernet Controller for PCI Express 28 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet The following figures show how different inductors affect the PIN 1 output waveform. The typical waveform should look like Figure 16, which has a square waveform with a dip at the falling edge and the rising edge. If the inductor is not carefully chosen, the waveform may look like Figure 17, where the waveform looks like a distorted square. This will cause insufficient current supply and will undermine the stability of the system at gigabit speed. Data in the following figures was measured at gigabit speed. www..com Figure 16. 4R7GTSD32 (Good) Figure 17. 1H Bead (Bad) Integrated Gigabit Ethernet Controller for PCI Express 29 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 7.4. Typical Switching Regulator PCB Layout www..com Figure 18. Typical Switching Regulator PCB Layout 7.5. Power Sequence Figure 19. Power Sequence Table 25. Power Sequence Parameter Symbol Description Min Typical Max Units Rt1 3.3V Rise Time 1 100 ms Rt2 3.3V Fall Time 200 ms Note1: The RTL8111C does not support fast 3.3V rising. The 3.3V rise time must be controlled over 1ms. If the rise time is too short it will induce a peak voltage in PIN63, which may cause permanent damage to the switching regulator. Note 2: If there is any action which involves consecutive ON/OFF toggling of the switching-regulator source (3.3V), the design must makes sure the OFF state of both the switching-regulator source (3.3V) and output (1.2V) reach 0V and the time period between the consecutive ON/OFF toggling action must be longer than 200ms. Integrated Gigabit Ethernet Controller for PCI Express 30 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 8. 8.1. Characteristics Absolute Maximum Ratings WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise specified. Table 26. Absolute Maximum Ratings Symbol Description Minimum Maximum VDD33, AVDD33 Supply Voltage 3.3V -0.3 +0.30 www..com DVDD12 AVDD12, Supply Voltage 1.2V -0.3 +0.12 EVDD12 Supply Voltage 1.2V -0.3 +0.12 DCinput Input Voltage -0.3 Corresponding Supply Voltage + 0.5 DCoutput Output Voltage -0.3 Corresponding Supply Voltage + 0.5 N/A Storage Temperature -55 +125 Note: Refer to the most updated schematic circuit for correct configuration. Unit V V V V V C 8.2. Recommended Operating Conditions Maximum 3.63 1.32 1.26 70 125 Unit V V V C C Table 27. Recommended Operating Conditions Pins Minimum Typical VDD33, AVDD33 2.97 3.3 Supply Voltage VDD AVDD12, DVDD12 1.1 1.2 EVDD12 1.14 1.2 Ambient Operating Temperature TA 0 Maximum Junction Temperature Note: Refer to the most updated schematic circuit for correct configuration. Description 8.3. Symbol Fref Crystal Requirements Table 28. Crystal Requirements Description/Condition Minimum Parallel resonant crystal reference frequency, fundamental mode, AT-cut type. Parallel resonant crystal frequency stability, fundamental mode, AT-cut type. -50 Ta = 25C. Parallel resonant crystal frequency tolerance, fundamental mode, AT-cut type. -30 Ta = -20C ~ +70C. Reference Clock Input Duty Cycle. 40 Equivalent Series Resistance. Drive Level. Typical 25 Maximum +50 Unit MHz ppm Fref Stability Fref Tolerance Fref Duty Cycle ESR DL - +30 60 30 0.5 ppm % mW Integrated Gigabit Ethernet Controller for PCI Express 31 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 8.4. Oscillator Requirements Table 29. Oscillator Requirements Condition Minimum Typical 25 -30 Ta = 25C -50 Ta = 0C ~ +70C 40 3.15 3.3 0 Maximum +30 +50 60 50 3.45 10 10 70 Unit MHz ppm ppm % ps V ns ns C Parameter Frequency Frequency Stability Frequency Tolerance Duty Cycle Jitter Vp-p Rise Time www..com Fall Time Operation Temp Range 8.5. Thermal Characteristics Table 30. Thermal Characteristics Minimum Maximum -55 +125 0 70 Units C C Parameter Storage Temperature Ambient Operating Temperature 8.6. Symbol VDD33, AVDD33 DVDD12, AVDD12 EVDD12 Voh Vol Vih Vil Iin DC Characteristics Parameter 3.3V Supply Voltage 1.2V Supply Voltage 1.2V Supply Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Table 31. DC Characteristics Conditions Minimum Ioh = -4mA Iol= 4mA 2.97 1.1 1.14 0.9*VDD33 0 1.8 Typical 3.3 1.2 1.2 68 340 Maximum 3.63 1.32 1.26 VDD33 0.1*VDD33 0.8 0.5 Units V V V V V V V A mA mA Vin = VDD33 or 0 GND Average Operating Supply At 1Gbps with heavy Icc33 Current from 3.3V network traffic Average Operating Supply At 1Gbps with heavy Icc12 Current from 1.2V network traffic Note: Refer to the most updated schematic circuit for correct configuration. Integrated Gigabit Ethernet Controller for PCI Express 32 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 8.7. 8.7.1. AC Characteristics Serial EEPROM Interface Timing EESK EECS EEDI (Read) (Read) 93C46(64*16)/93C56(128*16) tcs 1 1 0 An A2 A1 A0 0 Dn D1 D0 www..com EEDO High Impedance EESK EECS EEDI (Write) (Write) tcs 1 0 1 An ... A0 Dn ... D0 BUSY twp READY EEDO High Impedance tsk EESK tskh tskl tcsh EECS EEDI tcss tdis tdih tdos tdoh EEDO (Read) EEDO tsv (Program) STATUS VALID Figure 20. Serial EEPROM Interface Timing Symbol tcs twp tsk tskh tskl tcss tcsh tdis tdih tdos tdoh tsv Table 32. EEPROM Access Timing Parameters Parameter EEPROM Type Min. Minimum CS Low Time 9346 1000 Write Cycle Time 9346 SK Clock Cycle Time 9346 4 SK High Time 9346 1000 SK Low Time 9346 1000 CS Setup Time 9346 200 CS Hold Time 9346 0 DI Setup Time 9346 400 DI Hold Time 9346 400 DO Setup Time 9346 2000 DO Hold Time 9346 CS to Status Valid 9346 33 Max. 10 2000 1000 Unit ns ms s ns ns ns ns ns ns ns ns ns Rev. 1.5 Integrated Gigabit Ethernet Controller for PCI Express Track ID: JATR-1076-21 RTL8111C Datasheet 8.8. 8.8.1. PCI Express Bus Parameters Differential Transmitter Parameters Table 33. Differential Transmitter Parameters Parameter Min Typical Max Units Unit Interval 399.88 400 400.12 ps Differential Peak to Peak Output Voltage 0.800 1.2 V De-Emphasized Differential Output Voltage (Ratio) -3.0 -3.5 -4.0 dB Minimum Tx Eye Width 0.75 UI 0.125 UI Maximum Time between The Jitter Median and www..com Maximum Deviation from The Median to-MAX-JITTER TTX-RISE, TTX-FALL D+/D- Tx Output Rise/Fall Time 0.125 UI VTX-CM-ACp RMS AC Peak Common Mode Output Voltage 20 mV 0 100 mV VTX-CM-DCACTIVEAbsolute Delta of DC Common Mode Voltage During L0 and Electrical Idle IDLEDELTA 0 25 mV VTX-CM-DCLINEAbsolute Delta of DC Common Mode Voltage between D+ and DDELTA VTX-IDLE-DIFFp Electrical Idle Differential Peak Output Voltage 0 20 mV VTX-RCV-DETECT 600 mV The Amount of Voltage Change Allowed During Receiver Detection VTX-DC-CM The Tx DC Common Mode Voltage 0 3.6 V ITX-SHORT Tx Short Circuit Current Limit 90 mA TTX-IDLE-MIN Minimum Time Spent in Electrical Idle 50 UI TTX-IDLE- SETTO-IDLE Maximum Time to Transition to A Valid Electrical Idle 20 UI After Sending An Electrical Idle Ordered Set 20 UI TTX-IDLE-TOTOMaximum Time to Transition to Valid Tx Specifications After Leaving An Electrical Idle DIFF-DATA Condition RLTX-DIFF Differential Return Loss 10 dB RLTX-CM Common Mode Return Loss 6 dB ZTX-DIFF-DC DC Differential Tx Impedance 80 100 120 LTX-SKEW Lane-to-Lane Output Skew 500+2*UI ps CTX AC Coupling Capacitor 75 200 nF Tcrosslink Crosslink Random Timeout 0 1 ms Note1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter. Note2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding 30kHz - 33kHz. The 300ppm requirement still holds, which requires the two communicating ports be modulated such that they never exceed a total of 600ppm difference. Symbol UI VTX-DIFFp-p VTX-DE-RATIO TTX-EYE TTX-EYE-MEDIAN- Integrated Gigabit Ethernet Controller for PCI Express 34 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 8.8.2. Differential Receiver Parameters Table 34. Differential Receiver Parameters Parameter Min. Typical Max. Units Unit Interval 399.88 400 400.12 ps Differential Input Peak to Peak Voltage 0.175 1.200 V Minimum Receiver Eye Width 0.4 UI 0.3 UI Maximum Time Between The Jitter Median and Maximum Deviation from The Median MAX-JITTER VRX-CM-ACp AC Peak Common Mode Input Voltage 150 mV RLRX-DIFF Differential Return Loss 10 dB www..com RLRX-CM Common Mode Return Loss 6 dB ZRX-DIFF-DC DC Differential Input Impedance 80 100 120 ZRX--DC DC Input Impedance 40 50 60 ZRX-HIGH-IMP-DC Powered Down DC Input Impedance 200k VRX-IDLE-DET-DIFFp-p Electrical Idle Detect Threshold 65 175 mV 10 ms TRX-IDLE-DETUnexpected Electrical Idle Enter Detect Threshold Integration Time DIFFENTERTIME LRX-SKEW Total Skew 20 ns Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter. Symbol UI VRX-DIFFp-p TRX-EYE TRX-EYE-MEDIAN-to- 8.8.3. Symbol REFCLK Parameters Table 35. REFCLK Parameters Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Absolute Crossing Point Voltage Variation of VCROSS Over All Rising Clock Edges Ring-Back Voltage Margin Time before VRB is Allowed Average Clock Period Accuracy Absolute Period (Including Jitter and Spread Spectrum) Cycle to Cycle Jitter Absolute Maximum Input Voltage Absolute Minimum Input Voltage 100MHz Input Min Max 0.6 4.0 0.6 4.0 +150 -150 +250 +550 +140 -100 +100 500 -300 +2800 9.847 10.203 150 +1.15 -0.3 Units V/ns V/ns mV mV mV mV mV ps ppm ns ps V V Note 2, 3 2, 3 2 2 1, 4, 5 1, 4, 9 2, 12 2, 12 2, 10, 13 2, 6 2 1, 7 1, 8 Rise Edge Rate Fall Edge Rate VIH VIL VCROSS VCROSS DELTA VRB TSTABLE TPERIOD AVG TPERIOD ABS TCCJITTER VMAX VMIN Integrated Gigabit Ethernet Controller for PCI Express 35 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet Symbol Duty Cycle Rise-Fall Matching Parameter 100MHz Input Min Max 40 60 20 Units Note Duty Cycle % 2 % 1, 14 Rising Edge Rate (REFCLK+) to Falling Edge Rate (REFCLK-) Matching ZC-DC Clock Source DC Impedance 40 60 1, 11 Note1: Measurement taken from single-ended waveform. Note2: Measurement taken from differential waveform. Note3: Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Figure 24, page 38. Note4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the www..com falling edge of REFCLK-. See Figure 20, page 33. Note5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Figure 20, page 33. Note6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. See Figure 23, page 37. Note7: Defined as the maximum instantaneous voltage including overshoot. See Figure 20, page 33. Note8: Defined as the minimum instantaneous voltage including undershoot. See Figure 20, page 33. Note9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS for any particular system. See Figure 21, page 37. Note10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding ppm considerations. Note11: System board compliance measurements must use the test load card described in Figure 27, page 39. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL=2pF. Note12: TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is allowed to droop back into the VRB 100mV differential range. See Figure 26, page 38. Note13: ppm refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly, or 100Hz. For 300ppm then we have an error budget of 100Hz/ppm*300ppm=30kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The 300ppm applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800ppm Note14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a 75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 22, page 37. Note15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment setting of each parameter. Integrated Gigabit Ethernet Controller for PCI Express 36 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet www..com Figure 21. Single-Ended Measurement Points for Absolute Cross Point and Swing Figure 22. Single-Ended Measurement Points for Delta Cross Point Figure 23. Single-Ended Measurement Points for Rise and Fall Time Matching Integrated Gigabit Ethernet Controller for PCI Express 37 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet www..com Figure 24. Differential Measurement Points for Duty Cycle and Period Figure 25. Differential Measurement Points for Rise and Fall Time Figure 26. Differential Measurement Points for Ringback Integrated Gigabit Ethernet Controller for PCI Express 38 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet www..com Figure 27. Reference Clock System Measurement Point and Loading 8.8.4. Symbol TPVPERL TPERST-CLK TPERST TFAIL TWKRF Auxiliary Signal Timing Parameters Table 36. Auxiliary Signal Timing Parameters Parameter Min Power Stable to PERSTB Inactive 100 REFCLK Stable before PERSTB Inactive 100 PERSTB Active Time 100 Power Level Invalid to PWRGD Inactive LANWAKEB Rise - Fall Time Max 500 100 Units ms s s ns ns 3.3 Vaux 3.3/12V PERSTB REFCLK PCI-E Link Inactive Power Stable Wakeup Event Power Stable Clock Stable Clock not Stable Clock Stable Active T PVPERL T PERST-CLK Inactive T PERST T FAIL Active Figure 28. Auxiliary Signal Timing Integrated Gigabit Ethernet Controller for PCI Express 39 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 9. Mechanical Dimensions www..com NOTE: RTL8111C's exposed pad size is L/F 3 Integrated Gigabit Ethernet Controller for PCI Express 40 Track ID: JATR-1076-21 Rev. 1.5 RTL8111C Datasheet 10. Ordering Information Status Production Production Production Table 37. Ordering Information Part Number Package RTL8111C-GR 64-Pin QFN `Green' Package RTL8111C-VB-GR RTL8111C-GR Version B Silicon RTL8111C-VC-GR RTL8111C-GR Version C Silicon Note: See page 3 for package ID information. www..com Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw Integrated Gigabit Ethernet Controller for PCI Express 41 Track ID: JATR-1076-21 Rev. 1.5 |
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