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W33D0001 SERIES 128-DOT LCD DRIVER WITH TIMER AND CLOCK FUNCTIONS
Table of ContentsGENERAL DESCRIPTION................................................................................................................. 2 FEATURES........................................................................................................................................ 2 PIN CONFIGURATION ...................................................................................................................... 3 PIN DESCRIPTION ........................................................................................................................... 3 BLOCK DIAGRAM ............................................................................................................................. 5 FUNCTIONAL DESCRIPTION ........................................................................................................... 6 1. Operating Mode.......................................................................................................................... 6 2. Reset Function ......................................................................................................................... 10 3. LCD Format.............................................................................................................................. 10 ABSOLUTE MAXIMUM RATINGS ................................................................................................... 11 ELECTRICAL CHARACTERISTICS................................................................................................. 11 DCharacteristics ........................................................................................................................... 11 AC Characteristics........................................................................................................................ 12 Table 1: Clock, Timer, and Normal Mode Function Table ............................................................. 13 Table 2: Clock Mode Address Mapping......................................................................................... 13 TIMING WAVEFORMS.................................................................................................................... 15 BONDING PAD DIAGRAM .............................................................................................................. 25 PACKAGE DIMENSIONS ................................................................................................................ 27 64-pin PQFP ................................................................................................................................ 27
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Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
GENERAL DESCRIPTION
This chip is an LCD driver for a telephone dialer number display or other equipment. A maximum of 16 digits or 128 dots can be displayed, with 1/3 bias, 1/4 duty, and 32 segments. In normal mode, a maximum of 128 dots (programmed by P transceiver function) can be displayed on the LCD panel. In clock mode, the LCD panel can display a built-in clock that can also be programmed through the P transceiver function. In timer mode, the LCD panel can display the conversation time. The timer mode cannot be programmed by the P. A VDD1 pin is used in different voltage system applications to implement a voltage level shift function to guarantee the transceiver data. This chip is fabricated using Winbond's high performance CMOS technology.
FEATURES
* * * * * *
Supply voltage: 1.5V or 3V by mask option Operating frequency: 32.768 KHz Built-in crystal oscillator circuit RC/Crystal mode selected by mask option Voltage level shift with a P Three operating modes - Normal mode (can be programmed by P) - Clock mode (can be programmed by P) - Timer mode. (can not be programmed by P)
* * * * * * * * * * *
Max. 16 (128 dots) digits with 8 dots/digit displayed in normal mode LCD (128 dots) can be programmed by P from any address between 0 and 127 Clock display include leap-year, month, date, hour, and minute Clock adjustable through MODE, SET pins or P Conversation time max. 11 hours 59 min 59 sec Clock 12 or 24 format by pin select 16, or 32 Hz LCD frequency select by mask option 1/3 bias, 1/4 duty 32-segment LCD panel Built-in VDD1 for different voltage system data transceiver application Built-in ATS pin to enable/disable timer mode Packaged in 64-pin PQFP
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W33D0001 SERIES
PIN CONFIGURATION
33
64 1
20
PIN DESCRIPTION
SYMBOL OSCI PIN 38 I/O I FUNCTION Oscillator input pin. Connect to a 32.768 KHz crystal. An external capacitor is needed. In RC mode an internal resistor must be added in circuit between the OSCI and OSCO pins. Oscillator output pin with internal capacitor. Positive power supply. For voltage level shift during data transceiver. Negative power supply. LCD voltage pins. CP is the voltage control capacitor positive pin. CN is the voltage control capacitor negative pin. A 0.1 F capacitor should be connected between these two pins. 36, 29 34 I I Test pins with pull-low resistor. Not used. Chip reset input pin. Active low with internal pull-high resistor.
OSCO VDD VDD1 VSS VLCD1, VLCD2 CN, CP TEST1 TEST2 RST
37 35 46 40 51, 50 54, 55
O I I I I I
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Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
Pin Description, continued
SYMBOL COM1- COM4 SEG1- SEG32 RDATA RCLK WDATA WCLK MS
PIN 56-59 60-64, 2-28 44 42 45 41 43
I/O O O O I I I I LCD panel common pins. (1/3 bias, 1/4 duty) LCD panel segment pins. (1/3 bias, 1/4 duty)
FUNCTION
Serial data output pin. It is H-Z when not active. Power source: VDD1 Synchronous read clock input pin. Power source: VDD1 Serial data/address input pin. Power source: VDD1 Synchronous write clock input pin. Power source: VDD1 Mode select input pin with floating status. Normal mode is active high or low by mask option. MS pin is high as normal mode through all the SPEC. Power source: VDD1 (Refer to functional description for more details)
12 / 24
47
I
12-hour (high) or 24-hour (low) clock select pin with floating status. Power source: VDD1 Waveform generator output pin. When RST = 0, 1 Hz or 1024 Hz (selected by mask option) will output from this pin. When RST = 1, the control bits (248, 249, 250) will output the square-wave from this pin. Power source: VDD1.
WFG
48
O
TIM MODE SET ATS
39 30 31 49
I I I I
Timer start/stop control pin with floating status. Clock mode-adjust pin with internal pull-low resistor. Clock digit-adjust pin with internal pull-low resistor. Auto Timer Select pin with floating status. ATS = 1, Auto timer disable. ATS = 0, Auto timer enable. (Refer to functional description for more details)
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W33D0001 SERIES
BLOCK DIAGRAM
WFG COM1 COM2 COM3 COM4 ATS OSCO OSCI TEST1 TEST2 MODE SET TIM MS 12/24 VDD1 VDD VSS RDATA RCLK WDATA WCLK RST SCAN CKT TIME BASE TIMER STATE CONTROL CONTROL CIRCUIT SHIFT REG LATCH REG. SEGMENT LATCH & DECODER & MUX SELECT 1/3 Bias 1/4 Duty SEG1 | SEG32 COMMON CIRCUIT
WATCH CLOCK
VOLTAGE DOUBLER
VLCD1 VLCD2 CN CP
W33D _ _ _ 1
supply voltage: 1 --- 1.5V, oscllate by crystal 2 --- 1.5V, oscllate by RC 3 --- 3V, oscllate by crystal 4 --- 3V, oscllate by RC 0: MS = low active, return to last state after 15 sec. "0" will not be shown in decimal digit of hour and min. 1: MS = high active, return to last state after 15 sec. "0" will not be shown in decimal digit of hour and min. 3: MS = high active, return to last state after 15 sec. "0" will be shown in decimal digit of hour and min.
COM. frequency / calibration frequency: 2 --- 16 Hz/1024 Hz 4 --- 32 Hz/1024 Hz
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Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
FUNCTIONAL DESCRIPTION
1. Operating Mode
The W33D0001 provides three operating modes: Normal mode, Clock mode, and Timer mode. Only the normal mode and clock mode can be programmed by the P. The address data corresponding to the mode is shown in Figure 1. In Figure 1 the address 0-127 range works as a working-loop. This means that the programmed address located in the 0-127 range will return to zero when the 127 address location is exceeded. The 128-255 range has the same function as the 0-127 range. Data in the 0-127 range are known as normal mode data. Data in the 192-227 range are known as clock mode data, and data in the 248-255 are known as function control bits. The following description shows the control functions, including the 8 control bits (248-255), the transceiver function controlled by a P in normal mode (0-127), and clock mode (192-227). 1.1 The Function Control Bits BIT 0-127 FUNCTION These addresses are for normal mode data display. This section functions as a working-loop. When you program data over address 127, the data will automatically start from the 0 address again. Reserved section area. Clock data area. Waveform Disable bit 0: Disable the waveform output from the WFG pin and keep the output to high. (Default value) 1: Enable the waveform output from the WFG pin. 249, 250 Determine which waveform will be generated on the WFG pin. The waveform can be determined by the following table:
249 0 0 1 1 250 0 1 0 1 Divid Time 1S (default) 1/2 1/16 1/256
128-191, 228-247 192-227 248
251
LCD panel ON/OFF control bit. (This bit will not affect the normal data in the chip, it just affects the LCD panel) 0: LCD panel light on. (Default value) 1: LCD panel light off.
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W33D0001 SERIES
1.1 The Function Control Bits, continued
BIT 252
FUNCTION Normal mode data reset control bit. (This bit will cause the 128 dots' data reset to "0"). 0: Non-reset the 128 dots' data. (Default value) 1: Resets the 128 dots' data to "0". (It is a level active signal)
253
RDATA pin output status control bit 0: RDATA pin with high impedance. 1: RDATA pin work as output pin in the read mode but H-Z in write mode.
254
Timer bit. (This bit can disable or enable the Timer mode) 0: Timer mode can be shown on the LCD panel. (Default value) 1: Timer mode cannot be shown on the LCD panel.
255
Clock bit. (This bit can disable or enable the Clock mode) 0: Clock mode can be shown on the LCD panel. (Default value) 1: Clock mode cannot be shown on the LCD panel.
1.2 The transceiver function controlled by a P: The W33D0001 can display the data on the LCD panel. These data are inputted by a serial transmission function from an external device such as a microprocessor. In normal mode and clock mode, the data can be read or written by a P with a transceiver function at the rising edge of RCLK or WCLK pin. The RCLK pin and WCLK pin must normally be set to a high state if there is no data reception and transmission. 1.2.1 Switch Read or Write Function If the W33D0001 is in write function mode, the first falling edge of RCLK will switch the write function to read function and the P can read data from the RCLK pin and RDATA pin, and vice versa. Refer to Figure 2. When the write function is reactivated (function changed from read to write or power on reset), the first 8 bits sent by the P sends through the WCLK pin and WDATA pin indicate the starting address of the desired read or write data. Refer to Figure 3 and Figure 4. 1.2.2 Serial Data Written by P A P can send serial data and clock to the W33D0001 through the WDATA pin and WCLK pin, respectively. When the P writes data to the W33D0001 in normal mode or clock mode, the P first does a dummy read before sending a serial starting address to the W33D0001 through the WDATA pin and WCLK pin. The serial starting address includes 8 bits which, from the first bit to the 8th bit, represent the LSB to the MSB of the starting address, respectively. Lastly, the P sends the serial data to the W33D0001 through the WDATA and WCLK pins. The serial data address stored in the W33D0001 is increased by one when the WCLK pin receives one clock form P. Refer to Figure 3.
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Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
1.2.3 Serial Data Read by P The P can read data from the W33D0001 in normal mode or clock mode. First, the P sends the starting address to the W33D0001. This addressing method is the same as the addressing method used in write functions. When the P sends a clock through the RCLK pin and the first falling edge on RCLK pin changes the write function to the read function, the W33D0001 can output the serial data from the RDATA pin when each rising edge of RCLK clock is input. Refer to Figure 4. Please note that the address 253 (RDATA status control bit) must be programmed to "1" before the read function is performed. The function of the three operating modes are described in the following section. 1.3 Normal mode: As shown in Table 1, the normal mode can be programmed only when the MS pin is high. If the Timer bit and Clock bit are both "1" (indicating a disabled clock mode and timer mode) the normal mode data can always be displayed on the LCD panel. In normal mode, the 128 dots (16 digits) are addressed from 0-127. The first digit is shown in the left most place in the LCD panel. When the P reads or writes data to or from the W33D0001 in normal mode, the P first arbitrarily sets any address between 0 to 127 as the starting address. The P will then read or write one bit to or from the W33D0001 while the RCLK or WCLK pin receives one clock from the P and the address is increased by one after every read or write clock input. The next address is reset to 0 when the 127 address is reached. If more than 128 dots are written by the P to the W33D0001 at a time, the 129th dot will replace the first dot, the 130th dot will replace the second dot, and so on until all the dots are written. Refer to Figure 1. The active operating mode is selected through the MS pin, Timer bit and Clock bit, where the Timer bit and Clock bit can be programmed through the P and stored in the 254 and 255 addresses, respectively. The default values of the two bits are both "0". Table 1 indicates the relationship between operating mode and the MS pin, Timer bit and the Clock bit. 1.3.1 Cascade function: More than two W33D0001 chips can be cascaded to expand the normal mode display data from 128 dots to 256 dots, 384 dots, ..etc. Only one MS pin in these chips can be pulled high to indicate the active chip. The data can then be written to the active W33D0001 chip. The application circuits are shown as Figure 14. When the cascade function is performed, the exact data in the timer bit and clock bit (254, 255) must be programmed. In most cases, both bits must be programmed to "0". 1.4 Clock mode: As shown in Table 2 the clock mode can display leap-year, month, date, hour, and minute. In this active clock mode, two LCD bars can flash every second. Refer to Figure 8. There are two methods for adjusting the data for clock mode. One method uses the transceiver function of the P to program the clock data. Another method is through the manual adjustment of the MODE and SET pins.
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W33D0001 SERIES
1.4.1 Using the transceiver function of P to program the clock data Programming the clock data through the transceiver function of the P is similar to programming in normal mode. Unlike normal mode, the programming addresses use the 192-227 range. When the MS pin is high and the clock bit is zero, the clock can be programmed by the P. When the clock setting is adjusted by the P, the clock function is stopped. After the clock's data is set, the clock time resets using the new data setting. However, the clock will not stop while the P is reading the clock data. In clock mode, the P can read or write the clock data with the addressing function. 192 is the starting address of clock mode. Moreover, the digit is displayed by means of an internal decoder in clock mode. Therefore, it needs only 4 bits to store a digit. The address of the digit corresponding to Month is 192-199. The address range for Date is 200-207. The P only reads or writes clock data in 24-hour format, however, the W33D0001 will automatically display the clock time in 12-hour format if the 12 / 24 pin is set high. The "P" symbol in the LCD panel is not programmed through the P. The appearance of the "P" symbol depends on the data in the Hour reg. (address = 208-215). The data in the 224-227 address indicate the leap-year. When the dot beside the symbol "P" is lighted, the data in the 224-227 will be (0000) in the leap-year. The data (0001) means the 1st year after the leap-year and the data (0010) means the 2nd year after the leap-year and so on. Refer to Figure 1, and the address mapping show in table 2. Any data not listed on Table 2 cannot be programmed in the clock mode. During programming (writing) of the data in clock mode, the clock is stopped. It is restarted when the read clock is input to the RCLK pin (or a dummy read is performed). This means that the built-in clock starts to work after the write function of the clock mode has ended. The built-in clock will not stop when clock mode data is being read. 1.4.2 Manual adjusting method through the MODE and SET pins. When clock mode is entered, the current time is displayed. Keeping the MODE pin depressed will cause the month digits to begin to flash. The SET pin can used to adjust the month setting; the setting will increase by one with each trigger. When the MODE pin is released, the month digits will continue the flash. At this time, a new input on the MODE pin will cause the date digits to begin flashing, and the date can be set. Successive inputs on the MODE pin will cause the hour, minute, and leap-year digits to flash, allowing the hour, minute, and leap-year to be adjusted. While the leap-year digits are flashing, a trigger on the MODE pin will return the system to clock mode. If there is no signal on the MODE pin for more than 15 seconds (or 30 seconds, by mask option), it will return to clock mode automatically. If the SET pin is depressed and held down for over 2 seconds, the clock setting will speed the P at an interval of 125 mS. When the SET pin is depressed during the clock adjusting mode, the clock will be restarted from the new data setting. The clock mode will automatically return to normal status from flash status if the flash status flashes for over 15 sec and no key is depressed. The MODE and SET pins are both high active. Refer to Figure 7.
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Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
1.5 Timer mode: The timer mode is controlled by the ATS pin with first priority. When the ATS pin is high, the timer function is inhibited meaning the timer data cannot display on the LCD panel. This timer function exists only when ATS pin is low, the MS pin is high, and Timer bit is equal to zero. Refer to Figure 9. In timer mode, the elapsed conversation time since the beginning of the call is displayed on the LCD panel. When the MS pin goes from low to high and the no data is transmitted, the LCD panel will show a flashing first digit (3 bars). When the MS pin is high, and no data transmission occur for more than 6 seconds, the timer will automatically start to count until the MS pin returns to a low state (in this case, the timer data will be kept for 5 sec. Befor being transferned to clock data). The maximum counting time is 11-59-59, and cycles to 00-00-00 to start again. The other method of starting and stopping the timer is by triggering the TIM pin. A high trigger input on the TIM pin will reverse the current condition of the timer; thus if the timer is counting, a high trigger on TIM will stop the counter, and vice versa. When the timer is in the initial state and the first trigger on the TIM pin occurs before the normal mode transmission data, the timer will display the previous counting number. Detailed flow charts depicting the above three operating modes are shown in Figure 5 and Figure 6.
2. Reset Function
There are two methods for initializing the chip: one is power-on reset, the other is pulling the RST pin low (low active). 2.1. Power-on reset At power on reset , the power-on reset circuit will generate a pulse to reset the chip. All LCD segments will flash momentarily for about 2 seconds and the built-in clock will start from 1-1 00-00 and the normal mode data of 128 dots will be reset to "0". 2.2. RST Pin function Pulling RST low will reset all of the chip's functions except for the clock. All LCD segments will flash momentarily for about 2 seconds and the 128 dots will be reset to "0".
3. LCD Format
The LCD panel is 1/3 bias, 1/4 duty. Refer to Figure 10 and Figure 11. The LCD format is shown in Figure 12.
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W33D0001 SERIES
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage temperature
of the device.
RATING -0.3 to +7.0 -0.3 to +7.0 120 -20 to +70 -55 to +155
UNIT V V mW C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
ELECTRICAL CHARACTERISTICS
DCharacteristics
VDD-VSS = 1.5V, FOSC = 32.768 KHz, TA = 25 C
PARAMETER Op. Voltage1 Op. Voltage2 Op. Current1 Op. Current2 Op. Current3 Op. Current4 SEG1 to SEG32 Source Current SEG1 to SEG32 Sink Current COM1 to COM4 Source Current COM1 to COM4 Sink Current WFG Source Current
SYM. VDD1 VDD2 IDD1 IDD2 IDD3 IDD4 ISH ISH ICH1 ICL1 ICH2
TEST CONDITIONS No load, VDD = 1.5V (Crystal mode) No load, VDD = 3.0V (Crystal mode) No load, VDD = 1.5V (RC Mode) No load VDD = 3.0V (RC Mode) VOH = 1.2V VOL = 0.3V VOH = 1.2V VOL = 0.3V VOH = 1.2V
MIN. 1.2 2.4 -0.4 0.4 -4 4 -
TYP. 1.5 3.0 5 20 30 60 500
MAX. 1.7 3.4 10 40 40 80 -
UNIT V V A A A A A A A A A
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W33D0001 SERIES
DC Characteristics, continued
PARAMETER WFG Sink Current Pull-high Resistor Pull-low Resistor Input Low Voltage Input High Voltage Oscillator Resistor RDATA Drive Current WDATA Sink Current
SYM. ICL2 RH RL VIL VIH ROSC IRDD
TEST CONDITIONS VOL = 0.3V RST MODE, SET RC Mode VDD = 3.0V VOH = 2.7V
MIN. 0 0.7 VDD -
TYP. 500 1.0 1.0 510 0.4
MAX. 2.0 2.0 0.3 VDD VDD -
UNIT A M M V V K mA
AC Characteristics
PARAMETER Op. Frequency Op. Frequency LCD Frequency Rising Debounce Time Falling Debounce Time Rising Debounce Time SYM. FOSC FOSC1 FLCD TRD TFD TRD TEST CONDITIONS Crystal, VDD = 1.5V RC mode, VDD = 1.5V Mask Option MODE, SET, TIM (Crystal Mode) MODE, SET, TIM (Crystal Mode) MODE, SET, TIM (RC Mode) MODE, SET, TIM (RC Mode) MIN. 35 35
35 * 32768 FOSC1 35 * 32768 FOSC1
TYP. 32.768 32.768 16 32 -
MAX. -
UNIT KHz KHz Hz Hz mS mS mS
Falling Debounce Time
TFD
-
-
mS
Mode to Set Effect Time Slow Adjust Effect Period Quick Set Data Time Quick Set-up Time RST Active Low Width Serial Transmit Data Setup Time Serial Transmit Data Hold Time
TMS TSPD TQD TQS TRWD TDS TDH
1 1 2 50 50
125 1 -
1999 -
mS mS mS S S nS nS
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W33D0001 SERIES
AC Characteristics, Continued
PARAMETER Serial Receive Data Access Time RCLK Period WCLK Period Transmit/Receive Time Oscillator Start Up Time WFG Duty Cycle
SYM. TAS TRCLK TWCLK TTRN TSTD TDCYL
TEST CONDITIONS -
MIN. 50 200 150 2 -
TYP. 3 50
MAX. -
UNIT nS nS nS mS S %
Table 1: Clock, Timer, and Normal Mode Function Table
MS Pin TIMER Bit CLOCK Bit CLOCK MODE Programmable Display-ed TIMER MODE Displayed NORMAL MODE Programable Display-ed
0 0 0 1 1 1 1
Notes:
x 0 1 0 1 0 1
0 1 1 0 0 1 1
x x x x x
x x x x x x
x x x x
x x x
x x
1. "x" represent "don't care". 2. "" represent "function existed". 3. "x" represent "function not existed". 4. "" represent "initial state displayed".
Table 2: Clock Mode Address Mapping
Mon. 1 0 Date Hour 1 0 Min. Leap Year 0 P
-
1
0
-
1
Address corresponding to digit
192-199 196 192 | | 199 195
200-207 204 200 | | 207 203
208-215 212 208 | | 215 211
216-223 220 216 | | 223 219
224-227 224 | 227
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W33D0001 SERIES
The address corresponding to the first displayed digit of Min./Hour/Date/Mon. Address 199-196 / 207-204/ 215-212 / 223-220 0000 0001 0010 0011 0100 0101 Others Displayed Digit
None (M/D), (H/Mi) 1 (M/D/H/Mi) 2 (D/Mi/H) 3 (D/Mi) 4 (Mi) 5 (Mi) (M/D/H/Mi)
The address corresponding to the 2nd displayed digit of Min./Hour/Date/Mon. Address 195-192 / 203-200/ 211-208 / 219-216 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Others 227-224 0000 0001 0010 0011 Others
Notes: 1. (M/D/H/Mi) means "for Mon. or Date or Hour or Min.". 2. " ": Displays "0" or none by mask option. 3. " ": Represent an illegal programming data. 4. "*" : Represent a leap year.
Displayed Digit
0 1 2 3 4 5 6 7 8 9
H Dot of 16th Digit * None None None
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W33D0001 SERIES
TIMING WAVEFORMS
0 128 DOTS
127 128 191 192 227 228 Reserved Clock
247 248 Control
255
Reserved
Read/Write Start
Read/Write Start address
Figure 1. Address Format
WRITE FUNCTION
READ FUNCTION
WRITE FUNCTION
WDATA
WCLK
change function
RDATA
RCLK
change function
Figure 2. Read/Write Change Function
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W33D0001 SERIES
Timing Waveforms, continued
dummy read write the starting address of written data WDATA
LSB MSB
write the serial data from the starting address
AE
Starting address
1st digit
Serial Data
16th digit
WCLK RDATA
TTRN
RCLK
TDS WDATA
Data Valid
TDH
A WCLK
B
C
D
E
F
G
H
TCLK
A
F
G
B
E
D
C H
seg n+1
seg n
Figure 3. Write Function Controlled By P
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W33D0001 SERIES
Timing Waveforms, continued
dummy read write the starting address of read data
LSB MSB
read the serial data from the starting address
WDATA
Starting address WCLK RDATA RCLK
TAS RDATA
TDH
A RCLK
B
G
H
TCLK
Figure 4. Read Function Controlled By P
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W33D0001 SERIES
Timing Waveforms, continued
Clock Mode MORE THAN 15 SEC
Mode switch controlled by MS pin If Timer bit = 0 & Clock bit = 0 (MS = 1: OFF Hook) (MS = 0: ON Hook)
Mode enter
12-31
2 3 - 5 9.
Mode enter
1 2 (Flash)
Mode enter
3 1 (Flash)
Mode enter
(Flash) 2 3
Mode enter
(Flash) 5 9
Mode enter
(Flash).
Mon. Date Hour Min.
ON HOOK OFF HOOK
MORE THAN 5 SEC.
ON HOOK
No digit accept
Timer Mode
ON HOOK
Normal Mode
Display Timer Last for 5 Sec.
DIGIT RECEIVED
LESS THAN 5 SEC. AND OFF HOOK AGAIN
Initial State (Flash)
7 77
ON HOOK
770
ATS = 0 NO DIGIT ENTER MORE THAN 6 SEC.
00-00-00 00-00-01
ATS = 1
7700 77006
00-00-02 Hour Min. Sec.
Max. 16 digits can be dispalyed
(TIMER RESTART -- FIRST 6 SEC. AFTER MS IS ENABLE) (TIMER CONTINUE -- IN THE OTHER CASE)
Figure 5. Mode Chart
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W33D0001 SERIES
Timing Waveforms, continued
Mode Check
NO MS = 0 ? NO
YES
Timer bit = 0 ? YES Timer mode initial state (flash) YES MS = 0 ? NO NO receive data ? YES
Timer bit = 0 ? NO
YES
NORMAL MODE (display receive data)
Clock bit = 0 ? NO Display data of normal mode only
YES
Clock bit = 0 ? YES
NO
display (flash)
CLOCK MODE (display real time clock)
display timer data NORMAL MODE (display receive data) NO display timer more than 5 sec NO YES MS = 0 ? NO YES
not receive data more than 6 YES sec ATS = 0 ? YES
NO
TIMER MODE 1.up count 2.dislplay timer
MS = 0 ? YES
NO
Figure 6. Flow Chart
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W33D0001 SERIES
Timing Waveforms, continued
TRD MODE SET
NORMAL MODE MON. flash
TSPD
TFD
TMS
MON. MON. adj. flash
MON. MON. adj. flash
DAT flash E
HOUR HOUR HOUR HOUR HOUR flash adj. flash adj. flash
MIN. flash
NORMAL MODE
SLOW ADJUSTING
TQS MODE SET
NORMAL MODE MON. flash MON. flash DAT flash E HOUR flash
TQS
HOUR flash
MIN. flash
NORMAL MODE
QUICK ADJUSTING
Figure 7. Clock Adjusting
flashes every second
flashes every second
Figure 8. LCD Clock Format
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W33D0001 SERIES
Timing Waveforms, continued
Figure 9. LCD Timer Format
digit 1
digit 2
digit 3
digit 4
digit 5
digit 6
digit 7
digit 8
digit 9
digit 10 digit 11
digit 12
digit 13 digit 14
digit 15 digit 16
SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2
SEG 1
COM1 COM2 COM3 COM4
Figure 10. LCD Layout
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W33D0001 SERIES
Timing Waveforms, continued
FLCD
(1/4 DUTY,1/3 BIAS)
COM1
V3 V2 V1 Vss V3 COM2 V2 V1 Vss V3 COM3 V2 V1 Vss V3 V2 COM4 V1 Vss V3 SEG1 V2 V1 Vss V3 V2 V1 Vss VLCD
V1 = 1/3 V LCD V2 = 2/3 V LCD V3 = VLCD
SEG2
COM1 - SEG1 (Selected Waveform)
1/3 V LCD Vss -1/3 V LCD
-V LCD 1/3 V LCD COM1 - SEG2 Vss -1/3 V LCD 1 Flame
(Non Selected Waveform)
Figure 11. LCD Waveform
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W33D0001 SERIES
Timing Waveforms, continued
SEG COM 1 2 3 4
Digit 1 32 F G E D 31 A B C H
Digit 2 30 F G E D 29 A B C H
Digit 3 28 F G E D 27 A B C H
Digit 4 26 F G E D 25 A B C H
Digit 5 24 F G E D 23 A B C H
Digit 6 22 F G E D 21 A B C H
Digit 7 20 F G E D 19 A B C H
Digit 8 18 F G E D 17 A B C H
SEG COM 1 2 3 4
Digit 9 16 F G E D 15 A B C H
Digit 10 14 F G E D 13 A B C H
Digit 11 12 F G E D 11 A B C H
Digit 12 10 F G E D 9 A B C H
Digit 13 8 F G E D 7 A B C H
Digit 14 6 F G E D 5 A B C H
Digit 15 4 F G E D 3 A B C H
Digit 16 2 F G E D 1 A B C H
Figure 12. LCD Panel Format
The diagram for the W33D0001 control is shown in Figure 13.
P VDD Mode select P Clock out Data in Clock out Data out
VDD1 MS RCLK RDATA WCLK WDATA
W33D0001 LCD driver
Figure 13. Application Suggestion Note: The condition, where normal mode is enabled by setting the MS pin high or low, is a mask option. Normal mode is enabled when the MS pin is high.
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Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
Timing Waveforms, continued
WCLK WDATA RCLK RDATA
W33D0001-1
P MS1 MS2
MS1
W33D0001-2
MS2
Figure 14. Normal Mode Cascade Application Circuit
VCC
1.5V
Mode select Clock out P Data in Clock out Data out
MS RCLK RDATA WCLK WDATA
VDD1
VDD
W33D0001 LCD driver
Figure 15. Application Circuit Notes: 1. VDD: W33D0001 SERIES Main power 2. VDD1: Voltage source come from P for level shift
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W33D0001 SERIES
BONDING PAD DIAGRAM
53 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 39 38 37 36 35 (0,0) X Y 4 3 2 1 59 58 57 56 55 54 52 51 50 49 48 47 46 45 44 43 42 41 40
PAD LIST
PAD NO. PAD NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 PIN# 60 61 62 63 64 2 3 4 5 6 7 8 9 10 X -406.8 -546.80 -715.80 -855.60 -1024.80 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 Y 1507.80 1507.80 1507.80 1507.80 1507.80 1246.20 1077.20 937.20 768.20 628.20 459.20 319.20 150.20 10.20 PAD NO. PAD NAME 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SEG 31 SEG 32 TEST2 MODE SET RST VDD TEST1 OSCO OSCI TIM VSS WCLK RCLK PIN# 27 28 29 30 31 34 35 36 37 38 39 40 41 42 X 155.30 295.30 648.45 883.20 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 Y -1542.80 -1542.80 -1542.80 -1542.80 -1350.10 -1381.10 -1241.10 -107810 -927.10 -321.00 -379.80 -221.50 -63.50 78.40
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Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
Pad List, continued
PAD NO. PAD NAME 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 SEG 29 SEG 30
PIN# 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
X -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1172.30 -1173.30 -940.70 -771.70 -631.70 -462.70 -322.70 -153.70 -13.70
Y -158.80 -298.80 -467.80 -607.80 -776.00 -916.80 -1085.80 -1225.80 -1394.80 -1542.30 -1542.30 -1542.30 -1542.30 -1542.30 -1542.30 -1542.30
PAD NO. PAD NAME 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 MS RDATA WDATA VDD1 12 / 24 WFG ATS VLCD2 VLCD1 CN CP COM1 COM2 COM3 COM4
PIN# 43 44 45 46 47 48 49 50 51 54 55 56 57 58 59
X 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 1164.40 788.40 619.40 302.90 162.90 -37.40 -177.40
Y 243.00 421.70 561.70 716.20 885.20 1039.70 1179.70 1358.10 1498.10 1507.80 1507.80 1507.80 1507.80 1507.80 1507.80
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W33D0001 SERIES
PACKAGE DIMENSIONS
64-pin PQFP
H D
64
D
52
1
51
E
HE
19
33
20
e
b
32
c
2
A See Detail F Seating Plane
1
A L L
1
y
A
Detail F
Dimension in inch
Dimension in mm
Symbol
Min.
0.004 0.107 0.014 0.004 0.546 0.782 0.033 0.728 0.964 0.039 0.087
Nom.
Max.
0.130
Min.
0.10
Nom.
Max.
3.30
A A1 A2 b c D E e HD HE L L1 y
0.112 0.016 0.006 0.551 0.787 0.039 0.740 0.976 0.047 0.094
0.117 0.020 0.010 0.556 0.792 0.045 0.752 0.988 0.055 0.103 0.004
2.73 0.35 0.10 13.87 19.87 0.85 18.49 24.49 1.00 2.21
2.85 0.40 0.15 14.00 20.00 1.00 18.80 24.80 1.20 2.40
2.97 0.50 0.25 14.13 20.13 1.15 19.10 25.10 1.40 2.62 0.10
0
12
0
12
- 27 -
Publication Release Date: July 1999 Revision A3
W33D0001 SERIES
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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