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TB62202AFG
TOSHIBA Bi-CMOS Processor IC Silicon Monolithic
TB62202AFG
Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type
The TB62202AFG is a dual-stepping motor driver driven by chopper micro-step pseudo sine wave. To drive two-phase stepping motors, Two pairs of 16-bit latch and shift registers are built in the IC. The IC is optimal for driving stepping motors at high efficiency and with low-torque ripple. The IC supports Mixed Decay mode for switching the attenuation ratio at chopping. The switching time for the attenuation ratio can be switched in four stages according to the load.
Features
Two stepping motors driven by micro-step pseudo sine wave are controlled by a single driver IC Monolithic Bi-CMOS IC Low ON-resistance of Ron = 1.2 (Tj = 25C @1.0 A: Typ.) Two pairs of built-in 16-bit shift and latch registers Two pairs of built-in 4-bit DA converters for micro steps Built-in ISD, TSD, VDD and VM power monitor (reset) circuit for protection Built-in charge pump circuit (two external capacitors) 36-pin power flat package (HSOP36-P-450-0.65) Output voltage: 40 V max Output current: 1.0 A/phase max Built-in Mixed Decay mode enables specification of four-stage attenuation ratio. (The attenuation ratio table can be overwritten externally.) Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at 100 kHz or higher. Note: When using the IC, pay attention to thermal conditions. These devices are easy damage by high static voltage. In regards to this, please handle with care. Weight: 0.79 g (typ.)
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Block Diagram
1. Overview (Power lines: A/B unit (C/D unit is the same as A/B unit))
RESET
Logic circuit
Current control data logic circuit DATA CLK STROBE Current setting Vref 4-bit DA (analog control) Waveform chapping circuit 16-bit shift register 16-bit latch Chopping reference circuit Chopping waveform generator circuit CR
Torque control
Current feedback circuit RS VRS
circuit
RS COMP
circuit
Output control circuit
VM
Ccp 2 Charge pump circuit Ccp 1 Output circuit (H-bridge)
ISD circuit
TSD circuit
VM
VDDR/VMR circuit
VDD
Protected circuit
Out X Stepping motor High voltage wiring (VM) Logic DATA Analog DATA IC terminal
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2. Logic unit A/B (C/D unit is the same as A/B unit)
Function
This circuit is used to input from the DATA pins micro-step current setting data and to transfer them to the subsequent stage. By switching the SETUP pin, the data in the mixed decay timing table can be overwritten.
SETUP
Micro-step current setting data logic circuit 16-bit shift register
MIXED DECAY TIMING
Output control circuit
DATA CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
STROBE
16-bit latch Data input selector
A unit side
TORQUE x 2 bits
DECAY x 2 bits B unit side
CURRENT x 4 bits B unit side
PHASE x 1 bit B
RESET
Current feedback circuit
D/A circuit
Output control circuit
Note: The RESET and SETUP pins are pulled down in the IC by 10-k resistor. When not using these pins, connect them to GND. Otherwise, malfunction may occur.
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3. Current feedback circuit and current setting circuit
(A/B unit (C/D unit is the same as A/B unit) Function
The current setting circuit is used to set the reference voltage of the output current using the micro-step current setting data input from the DATA pins. The current feedback circuit is used to output to the output control circuit the relation between the set current value and output current. This is done by comparing the reference voltage output to the current setting circuit with the potential difference generated when current flows through the current sense resistor connected between RS and VM. The chopping waveform generator circuit to which CR is connected is used to generate clock used as reference for the chopping frequency.
TORQUE 0, 1 LOGIC UNIT CURRENT 0~3
100% 85% 70% 50% Torque Control circuit
Current setting circuit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Micro-step current setting selector circuit
Vref
Chopping waveform generator circuit
CR
Waveform shaping circuit 4-bit D/A circuit Chopping reference circuit
Mixed decay timing circuit
Output stop signal (ALL OFF)
Use in Charge mode VRS circuit 1 (detects potential difference between RS and VM) VRS circuit 2 (detects potential difference between VM and RS) RS COMP circuit 1 (Note 1) Output control circuit
RS
NF (set current reached signal)
VM
RS COMP circuit 2 (Note 2)
RNF (set current monitor signal) Use in Fast mode
Current feedback circuit
Note 1: RS COMP 1: Compares the set current with the output current and outputs a signal when the output current reaches the set current. Note 2: RS COMP 2: Compares the set current with the output current at the end of Fast mode during chopping. www..com a signal when the set current is below the output current. Outputs
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4. Output control circuit, current feedback circuit and current setting circuit (A/B unit
(C/D unit is the same as A/B unit)
Micro-step current setting data logic circuit DECAY MODE Chopping reference circuit MIXED DECAY TIMING circuit CR COUNTER MIXED DECAY TIMING Charge start Current setting circuit Output stop signal Output control circuit U1 U2 L1 L2 Output circuit
Output control circuit NF set current reached signal RNF set current monitor signal
PHASE
Current feedback circuit
CR COUNTER
Output RESET signal
VDD
VM Power supply for upper output MOS transistors
RESET
Output pin
ISD (current shutdown) circuit VMR circuit Reset signal selector circuit
Charge pump halt signal Charge pump circuit
VH
Output circuit
VM
Ccp A
VDD
VDDR circuit Thermal shut down (TSD) circuit Protection circuit MICRO-STEP CURRENT SETUP LATCH CLEAR signal Charge pump circuit MIXED DECAY TIMING TABLE CLEAR signal LOGIC
Ccp B
Ccp C
VDDR: VDD power on Reset VMR: VM power on Reset ISD: Current shutdown circuit TSD: Thermal shutdown circuit
Note:
The RESET pins is pulled down in the IC by 10-k resistor. When not using the pin, connect it to GND. Otherwise, malfunction may occur.
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5. Output equivalent circuit (A/B unit (C/D unit is the same as A/B unit)
RS A Output driver circuit
To VM
RRS A
From output control circuit
U1 U2 L1 L2 Power supply for upper output MOS transistors (VH) Phase A
U1
U2
Output A
L1
L2
Output A
VM B
RS B Output driver circuit
RRS B
From output control circuit
U1 U2 L1 L2 Power supply for upper output MOS transistors (VH) Phase B
U1
U2
Output B L1 L2 Output B
M
PGND
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6. Input equivalent circuit
(1) Logic input circuit (CLK, DATA, STROBE)
VDD 27
IN To Logic IC 30/29/31 25/26/24 GND FIN 150
(2) Input circuit ( RESET )
VDD 27
IN 28
10 k
To Logic IC 150
GND FIN
(3) Vref input circuit
VDD 27 IN 4 9/10 To D/A circuit
GND FIN
Note: RESET pin is pulled down. Do not use them open. When not using these pins, connect them to GND.
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Pin Assignment
(top view) VM B OUT B RS B PGND OUT B NC Ccp A CR VREF AB VSS (FIN) VREF CD NC Ccp B Ccp C OUT D PGND RS D OUT D VM D 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 TB62202AFG 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 VM A OUT A RS A PGND OUT A STROBE AB CLK AB DATA AB
RESET
VSS (FIN) VDD DATA CD CLK CD STROBE CD OUT C PGND RS C OUT C
VM C
Note: [Important] If this IC is inserted reverse, voltages exceeding the voltages of standard may be applied to some pins, causing damage. Please confirm the pin assignment before mounting and using the IC.
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Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 FIN 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FIN 28 29 30 31 32 33 34 35 36 Pin Symbol VM B OUT B RS B PGND
OUT B
Description Voltage major for output B block Output B pin Channel B current pin Power GND pin Output B pin Non connection Capacitor pin for charge pump (Ccp1) External C/R (osc) pin (sets chopping frequency) Vref input pin AB FIN (VSS) : Logic GND pin Vref input pin CD Non connection Capacitor pin for charge pump (Ccp2) Capacitor pin for charge pump (Ccp2) Output D pin Power GND pin Channel D current pin Output D pin Voltage major for output D block Voltage major for output C block Output C pin Channel C current pin Power GND pin Output C pin CD STROBE (latch) signal input pin ( CD clock input pin CD serial data signal input pin Power pin for logic block FIN (VSS) : Logic GND pin Output reset signal input pin (L : RESET) AB serial data signal input pin AB clock input pin AB STROBE (latch) signal input pin ( Output A pin Power GND pin Channel A current pin Output A pin Voltage major for output A block : LATCH) : LATCH)
NC Ccp A CR VREF AB VSS VREF CD NC Ccp B Ccp C OUT D PGND RS D OUT D VM D VM C OUT C RS C PGND OUT C STROBE CD CLK CD DATA CD VDD VSS RESET DATA AB CLK AB STROBE AB OUT A PGND RS A OUT A VM A
Note: How to handle GND pins All power GND pins and FIN (VSS: signal GND) pins must be grounded. Since FIN also functions as a heat sink, take the heat dissipation into consideration when designing the board.
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Signal Functions
1. Serial input signals (for A/B. C/D is the same as A/B)
Data No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSB LSB Name TORQUE 0 TORQUE 1 DECAY MODE B0 DECAY MODE B1 Current B0 Current B1 Current B2 Current B3 PHASE B DECAY MODE A0 DECAY MODE A1 Current A0 Current A1 Current A2 Current A3 PHASE A Phase information (H : OUT A : H, OUT A : L) Phase information (H: OUT A: H, OUT A : L) 00: DECAY MODE 0, 01: DECAY MODE 1 10: DECAY MODE 2, 11: DECAY MODE 3 Functions DATA No.0, 1 = HH: 100%, LH: 85% HL: 70%, LL: 50% 00: DECAY MODE 0, 01: DECAY MODE 1 10: DECAY MODE 2, 11: DECAY MODE 3
Used for setting current. (LLLL = Output ALL OFF MODE) 4-bit current B data (Steps can be divided into 16 by 4-bit data) (Note 1)
Used for setting current. (LLLL = Output ALL OFF MODE) 4-bit current A data (Steps can be divided into 16 by 4-bit data)
Note 1: Serial data input order Serial data are input in the order LSB (DATA 0) MSB (DATA 15)
Role of Data
Data Name TORQUE DECAY MODE CURRENT PHASE Number of Bits 2 2 x 2 phases 4 x 2 phases 1 x 2 phases Functions Roughly regulates the current (four stages). Common to A and B units. Selects Decay mode. A and B units are set separately. Sets a 4-bit micro-step electrical angle. A and B units are set separately. Determines polarity (+ or -). A and B units are set separately.
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2. Serial input signal functions
Input CLK STROBE
x x x x x x x
Action VDDR (Note 1) or VMR H H H H H
x
DATA
x
RESET
H H H H H L
Operation of TSD/ISD L L L L L L
(Note 2) No change in shift register. H level is input to shift register. L level is input to shift register. Shift register data are latched. Qn Output off, charge pump halted (S/R DATA CLR) Output off (S/R DATA CLR) Charge pump halted Mixed decay timing table cleared (only VDDR) Output off (S/R DATA HOLD)
H L
x x x
x
x
x
x
L
L
x
x
x
H
H
H
Charge pump halted Restored when RESET goes from Low to High
x: Don't Care Qn: Latched output level when STROBE is . Note 1: VDDR and VMR H when the operable range (3 V typical) or higher and L when lower. When one of VDDR or VMR is operating, the system resets (OR relationship). Note 2: High when TSD is in operation. When one of TSD or ISD is operating, the system resets (OR relationship). Note: Function of overcurrent protection circuit Until the RESET signal is input after ISD is triggered, the overcurrent protection circuit remains in operation. During ISD, the charge pump stays halted. When TSD and ISD are operating, the charge pump halts.
3. PHASE functions
Input H L Function Positive polarity (A: H, : L) Negative polarity (A: L, : H)
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4. DECAY mode X0, X1 functions
DECAY Mode X1 L L H H DECAY Mode X0 L H L H Function Decay Mode 0 (Initial value: SLOW DECAY MODE) Decay Mode 1 (Initial value: MIXED DECAY MODE: 37.5%) Decay Mode 2 (Initial value: MIXED DECAY MODE: 75%) Decay Mode 3 (Initial value: FAST DECAY MODE)
5. TORQUE functions
TORQUE 0 H L H L TORQUE 1 H H L L Comparator Reference Voltage Ratio 100% 85% 70% 50%
6. Current AX (BX) functions
Step 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Set Angle 90.0 84.4 78.8 73.1 67.5 61.2 56.3 50.6 45.0 39.4 33.8 28.1 22.5 16.9 11.3 5.6 0.0 A3 H H H H H H H H H L L L L L L L L A2 H H H H H L L L L H H H H L L L L A1 H H H L L H H L L H H L L H H L L A0 H H L H L H L H L H L H L H L H L B3 L L L L L L L L H H H H H H H H H B2 L L L L H H H H L L L L H H H H H B1 L L H H L L H H L L H H L L H H H B0 L H L H L H L H L H L H L H L H H
By inputting the above current data (A: 4-bit, B: 4-bit), 17-microstep drive is possible. For 1 step fixed to 90 degrees, see the section on output current vector line (85 page).
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7. Serial data input setting
DATA CLK STROBE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Note: Data input to the DATA pin are 16-bit serial data. Data are transferred from DATA 0 (Torque 0) to DATA 15 (Phase A). Data are input and transferred at the following timings. At CLK falling edge: data input At CLK rising edge: data transfer After data are transferred, all data are latched on the rising edge of the STROBE signal. As long as STROBE is not rising, the signal can be either Low or High during data transfer.
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Maximum Ratings (Ta = 25C)
Characteristics Logic supply voltage Output voltage Output current Current detect pin voltage Charge pump pin maximum voltage (CCP1 pin) Logic input voltage Power dissipation Operating temperature Storage temperature Junction temperature Symbol VDD VM IOUT VRS VH VIN PD Topr Tstg Tj Rating 7 40 1.5 VM 4.5 VM + 7.0 to VDD + 0.4 1.4 3.2
-40 to 85 -50 to 150
Unit V V A/phase V V V W W C C C (Note 2) (Note 3) (Note 1)
150
Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.2 A or less per phase. Note 2: Input 7 V or less as VIN. Note 3: Measured for the IC only. (Ta = 25C) Note 4: Measured when mounted on the board. (Ta = 25C) Ta: IC ambient temperature Topr: IC ambient temperature when starting operation Tj: IC chip temperature during operation Tj (max) is controlled by TSD (thermal shut down circuit)
Recommended Operating Conditions (Ta = 0 to 85C)
Characteristics Power supply voltage Output voltage Symbol VDD VM IOUT (1) Output current IOUT (2) Logic input voltage Clock frequency Chopping frequency Reference voltage Current detect pin voltage VIN fCLK fchop Vref VRS VDD = 5.0 V VDD = 5.0 V VM = 24 V, Torque = 100% VDD = 5.0 V VDD = 5.0 V Ta = 25C, per phase (when one motor is driven) Ta = 25C, per phase (when two motors are driven)
Test Condition
Min 4.5 20

Typ. 5.0 24 0.6 0.6
Max 5.5 34 0.9 0.9 VDD 25 150 VDD
1.5
Unit V V A A V MHz KHz V V
GND 1.0 40 2.0 0
6.25 100 3.0
1.0
Note: Use the maximum junction temperature (Tj) at 120C or less
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Electrical Characteristics 1
Characteristics High Input voltage Low Input current 1 VIN (L) IIN1 (H) IIN1 (L) IIN2 (H) IIN2 (L) IDD1 Power dissipation (VDD pin) IDD2 2 2 RESET , SETUP pins VDD = 5 V (STROBE, RESET , DATA = L), RESET = L, Logic, output all off Output OPEN, fCLK = 6.25 MHz LOGIC ACTIVE, VDD = 5 V, Charge pump = charged Output OPEN (STROBE, RESET , DATA = L), RESET = L, Logic, output all off Charge Pump = no operation Output OPEN, fCLK = 6.25 MHz LOGIC ACTIVE, VDD = 5 V, VM = 24 V, Output off Charge Pump = charged Output OPEN, fCLK = 6.25 MHz LOGIC ACTIVE, 100 kHz chopping (emulation), Output OPEN, Charge Pump = charged Ccp1 = 0.22 F, Ccp2 = 0.01f VRS = VM = 24 V, Vout = 0 V, RESET = H, DATA = ALL L 5 VRS = VM = 24 V, Vout = 24 V, RESET = H, DATA = ALL L VRS = VM = CcpA = Vout = 24 V, RESET = L Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (H.H) = 100% set 6 Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (H.L) = 85% set Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (L.H) = 70% set Vref = 3.0 V, Vref (Gain) = 1/5.0 TORQUE = (L.L) = 50% set 7 7 8 Differences between output current channels Iout = 1000 mA Iout = 1000 mA VRS = 24 V, VM = 24 V, RESET = L (RESET status) CLK, STROBE, DATA pins
(Unless otherwise specified, Ta = 25C, VDD = 5 V, VM = 24 V)
Symbol VIN (H) 1 CLK, RESET , STROBE, DATA pins Test Circuit Test Condition Min 2.0 GND - 0.4 Typ. VDD GND 3.0 Max VDD + 0.4 0.8 1.0 1.0 700 700 6.0 mA 4.0 8.0
A
Unit
V
Input current 2
A
IM1 3 Power dissipation (VM pin) IM2
5.0
6.0
12
20
mA
IM3
4
30
40
Output standby current Output bias current Output leakage current
Upper Upper Lower High (Reference)
IOH IOB IOL VRS (H) VRS (MH) VRS (ML) VRS (L) Iout1 Iout2 IRS
-400 -200

1.0
A
100
Comparator reference voltage ratio
Mid High Mid Low LOw
83 68 48
85 70 50
87 72 52
%
Output current differential Output current setting differential RS pin current
-5 -5

5 5 10
% %
A
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Characteristics Symbol RON (D-S) 1 RON (D-S) 1 9 RON (D-S) 2 RON (D-S) 2 Test Circuit Test Condition Iout = 1.0 A, VDD = 5.0 V Tj = 25C, Drain-source Iout = 1.0 A, VDD = 5.0 V Tj = 25C, Source-drain Iout = 1.0 A, VDD = 5 V, Tj = 105C, Drain-source Iout = 1.0 A, VDD = 5 V, Tj = 105C, Source-drain Min Typ. 1.1 1.1 1.4 1.4 Max 1.3 1.3
Unit
Output transistor drain-source on-resistance
1.6 1.6
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Electrical Characteristics 2
Characteristics Vref input voltage Vref input current
(Unless otherwise specified, Ta = 25C, VDD = 5 V, VM = 24 V)
Symbol Vref Iref Test Circuit 10 Test Condition VM = 24 V, VDD = 5 V, RESET = H, Output on
RESET = H, Output off VM = 24 V, VDD = 5 V, Vref = 3.0 V
Min 2.0
Typ.

Max VDD 100
Unit V
10
0
A
Vref attenuation ratio TSD temperature TSD return temperature difference VDD return voltage VM return voltage Over current protected circuit operation current
Vref (GAIN) TjTSD (Note 1) TjTSD VDDR VMR ISD (Note 2)
6
VM = 24 V, VDD = 5 V, RESET = H, Output on, Vref = 2.0 to VDD - 1.0 V VDD = 5 V, VM = 24 V TjTSD = 130 to 170C VM = 24 V, RESET = H, STROBE = H VDD = 5 V, RESET = H, STROBE = H VDD = 5V, VM = 24V, fchop = 100 kHz set
1/4.8
1/5.0
1/5.2
11 11 12 13 14
130
170
C C V V A
TjTSD - 35

2.0 2.0
4.0 4.0
2.6
Note 1: Thermal shut down (TSD) circuit When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal reset circuit is activated switching the outputs of both motors to off. When the temperature is set between 130 (min) to 170C (max), the TSD circuit operates. When the TSD circuit is activated, the function data latched at that time are cleared. Output is halted until the reset is released. While the TSD circuit is in operation, the charge pump is halted. Even if the TSD circuit is activated and RESET goes H L H instantaneously, the IC is not reset until the IC junction temperature drops 35C (typ.) below the TSD operating temperature (hysteresis function). Note 2: Overcurrent protection circuit When current exceeding the specified value flows to the output, the internal reset circuit is activated switching the outputs of both shafts to off. When the ISD circuit is activated, the function data latched at that time are cleared. Until the RESET signal is input, the overcurrent protection circuit remains activated. During ISD, the charge pump halts. For failsafe operation, be sure to add a fuse to the power supply.
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Electrical Characteristics 3
Characteristics
(Ta = 25C, VDD = 5 V, VM = 24 V, Iout = 1.0 A)
SymboL Test Circuit Test Condition
A = 90 (16) A = 84 (15) A = 79 (14) A = 73 (13 A = 68 (12) A = 62 (11) A = 56 (10) A = 51 (9)
Min

Typ. 100 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 0
Max

Unit
93 91 87 83 78 72
97 93 88 82 76 68 61 52 43 34 25 15
Chopper current
Vector
15
A = 45 (8) A = 40 (7) A = 34 (6) A = 28 (5) A = 23 (4) A = 17 (3) A = 11 (2) A = 6 (1) A = 0 (0)
66 58 51 42 33 24 15 5
%
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AC Characteristics (Ta = 25C, VM = 24 V, VDD = 5 V, 6.8 mH/5.7 )
Characteristics Clock frequency SymboL fCLK tw (CLK) Minimum clock pulse width twp (CLK) twn (CLK) tSTROBE Minimum STROBE pulse width tSTROBE (H) tSTROBE (L) Data setup time tsuSIN-CLK tsuST-CLK thSIN-CLK thCLK-ST tr tf Output transistor switching characteristic tpLH (ST) tpHL (ST) tpLH (CR) tpHL (CR) Noise rejection dead band time CR reference signal oscillation frequency Chopping frequency range tBLNK fCR fchop (min) fchop (typ.) fchop (max) fchop tONG 21 19 20 18 16
Test Circuit 16
Test Condition
Min 1.0 40
Typ.

Max 25

Unit MHz
16
20 20 40
ns
16
20 20 20 20 20 20

ns
ns
Data hold time
16
ns
Output Load ; 6.8 mH/5.7 STROBE () to VOUT Output Load; 6.8 mH/5.7 CR to VOUT Output Load; 6.8 mH/5.7 Iout = 1.0 A Cosc = 560 pF, Rosc = 3.6 k Output active (Iout = 1.0 A) Step fixed, Ccp1 = 0.22 F, Ccp2 = 0.01F Output active (Iout = 1.0 A) CR CLK = 800 kHz Ccp2 = 0.22F, Ccp = 0.01 F VM = 24 V, VDD = 5 V, RESET = L H
0.1 0.1 15 10 1.2 2.5 300 800
s
200
400
ns kHz
40
100
150
kHz
20
Chopping frequency

100
kHz
Charge pump rise time
2
4
ms
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Test Waveforms (Timing waveforms and names)
tw (CLK) CLK 50% tsuST-CLK STROBE 50% tSTROBE (H) tSTROBE (L) tsuSIN-CLK DATA 50% DATA15 thSIN-CLK tSTROBE thCLK-ST twn twp
50%
DATA0
CR waveform (reference)
tpHL (CR) tpHL (ST) 90% OUTPUT voltage A 50% 10% tpLH (CR) tpLH (ST) 90% OUTPUT voltage A 50% 10% tr tf 90% 50% 10%
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Test Waveforms (Timing waveforms and names)
OSC-Charge Delay H OSC-Fast Delay
OSC (CR)
L T chop H OUTPUT voltage A 50% L H 50% L Set current 50%
OUTPUT voltage A
OUTPUT current
L Charge Slow Fast
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Calculation of Set Current
Determining RRS and Vref determines the set current value. Iout (Max) = Torque (Torque = 100, 85, 70, 50% : input serial data ) 1 x Vref (V) x R RS () Vref (GAIN)
1/5.0 is Vref (gain) : Vref attenuation ratio (typ.). For example, to input Vref = 3 V and Torque = 100% and to output Iout = 0.8 A, RRS = 0.75 (0.5 W or more) is required.
Formulas for Calculating CR Oscillation Frequency (Chopping reference frequency)
The CR oscillation frequency and fchop can be calculated by the following formulas: fCR = 1 [Hz] KA x (Cx Rx KB x C)
KA (constant): 0.523 KB (constant): 600
f fchop = CR [Hz] 8
Example : When Cosc = 1,000 pF and Rosc = 2.0 k are connected, fCR = 735 kHz. At this time, the chopping frequency fchop is : fchop = fCR/8 = 92 kHz. 1 Note: fCR = tCR tCR = t (Charge) + t (Dis - Charge) CR oscillation CR charge cycle time CR distance time
At this time, t (CR-discharge) is subject to the following condition: 600 ns > t (CR-discharge) > 400 ns. Be sure to set the CR value in accordance with this condition.
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CR Circuit Constants
OSC circuit oscillation waveform
t (CR-charge) t (CR-dis-charge)
E1
E2
t=0
t=1
t=2
The OSC circuit generates the chopping reference signal by charging and discharging the external capacitor Cosc through current supplied from the external resistor Rosc in the OSC block. Voltages E1 and E2 in the diagram are set by dividing the VDD by approximately 3/5 (E1) and 2/5 (E2). The actual current chopping time is 1/8 the CR frequency.
[Important: Setting the CR Circuit Constants]
The CR oscillation waveform is converted in the IC to the CLK waveform (CR-CLK signal) and used for control. If the CR waveform discharge time is set outside the range shown below, the operation of the IC is not guaranteed. Be sure to set the CR waveform discharge time within the following range. 600 ns > t (CR discharge) > 400 ns
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IC Power Dissipation
IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed by the logic block and the charge pump circuit.
(1) Power consumed by the Power Transistor (calculated with Ron = 1.3 )
In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower transistors of the H bridges. The following expression expresses the power consumed by the transistors of a H bridge. P (out) = 2 (Tr) x Iout (A) x VDS (V) = 2 x Iout^2 x Ron *************************(1) The average power dissipation for output under 4-bit micro step operation (phase difference between phases A and B is 90) is determined by expression (1). Thus, power dissipation for output per unit is determined as follows (2) under the conditions below. Ron = 1.3 (@1.0 A) Iout (Peak : Max) = 0.6 A VM = 24 V VDD = 5 V P (out) = 2 (Tr) x 0.6 (A)^2 x 1.3 () *************************************************(2) = 0.936 (W)
(2) Power consumed by the logic block and IM
The following standard values are used as power dissipation of the logic block and IM at operation. I (LOGIC) = 2 mA (Typ.): /unit I (IM3) = 12.5 mA (Typ.): operation/unit I (IM1) = 6.0 mA (Typ.): stop/unit The logic block is connected to VDD (5 V). IM (total of current consumed by the circuits connected to VM and current consumed by output switching) is connected to VM (24 V). Power dissipation is calculated as follows: P (Logic and IM) = 5 (V) x 0.002 (A) + 24 (V) x 0.0125 (A) ....................... (3) = 0.31 (W)
(3) Thus, power dissipation for 1 unit (P) is determined as follows by (2) and (3) above.
P = P (out) + P (Logic and IM) = 1.246 (W) Power dissipation for 1 unit at standby is determined as follows: P (standby) = 24 (V) x 0.006 (A) + 5 (V) x 0.002 (A) = 0.154 (W) When one motor driving = 100 %, power dissipation is determined as follows: P (all) = 1.246 (W) + 0.154 (W) = 1.4 (W) For thermal design on the board, evaluate by mounting the IC.
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TB62202AFG
MIXED DECAY Mode Waveforms (concept of mixed decay mode)
fchop CR pin input waveform DECAY MODE 0 SLOW DECAY MODE Set current value NF Slow
Charge
DECAY MODE 1 37.5% MIXED DECAY MODE Charge
NF
Slow
Set current value
MDT
Fast
Monitoring set current value RNF
DECAY MODE 2 75% MIXED DECAY MODE
NF Fast MDT
Set current value
Charge
Monitoring set current value RNF
DECAY MODE 3 NF FAST DECAY MODE Charge Fast Monitoring set current value RNF 100% 87.5% 75% 62.5% 50% 37.5% 25% 12.5% 0 Set current value
NF is the point where the output current reaches the set current value. RNF is the timing for monitoring the set current. In Mixed Decay and Fast Decay modes, where the condition RNF (set current monitor signal) < (output current) applies, Charge mode is cancelled at the next chopping cycle (charge cancel circuit). Therefore, at the next chopping cycle, the IC enters Slow + Fast modes (Slow Fast at MDT).
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TB62202AFG
Test Circuit (A/B unit only. C/D unit conforms to A/B unit.)
1. VIN (H), VIN (L)
Rosc AB = 3.6 k
Cosc AB = 560 pF
8 CR SGND
VM A 36 RRS A 34 RRS A
SGND
A 5V 0V 5V 0V 5V 0V
IDD1, IDD2
27 VDD 31 STROBE AB 30 CLK AB 29 DATA AB
A 32 A 35 B2 B 5
Vary VIN
RRS B 3 VM B 1
RRS B
IIN (H), IIN (L) A 28 RESET 0 V to 5 V No reset at testing RESET = 5 [V]
VSS (FIN) Ccp C 13
SGND
0.01 F
Ccp 2
24 V
A 6 SETUP P-GND
Ccp B 12 Ccp A 7
5V
VDD SGND
0.22 F
Ccp 1
: PGND : SGND (VSS)
Test method
VIN (H): Set RESET to High and vary the logic input voltage from 0 to 7 V. Monitor IDD and measure the change point (VM = 24 V). VIN (L): Set RESET to High and vary the logic input voltage from 5 to 0 V. Monitor IDD and measure the change point.
Setup data
DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Vref AB 9
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TB62202AFG
2. IIN (H), IIN (L), IDD1, IDD2 (A/B unit only. C/D unit conforms to A/B unit.)
Rosc AB = 3.6 k
Cosc AB = 560 pF
8 CR SGND
VM A 36 RRS A 34 RRS A
SGND
A 5V 0V 5V 0V 5V 0V
IDD1, IDD2
27 VDD 31 STROBE AB 30 CLK AB 29 DATA AB
A 32 A 35 B2 B 5
Vary VIN
RRS B 3 VM B 1
RRS B
IIN (H), IIN (L) A 28 RESET 0 V to 5 V No reset at testing RESET = 5 [V]
VSS (FIN) Ccp C 13
SGND
0.01 F
Ccp 2
24 V
A 6 SETUP P-GND
Ccp B 12 Ccp A 7
5V
VDD SGND
0.22 F
Ccp 1
: PGND : SGND (VSS)
Test method
IIN (H): IIN (H): IDD1: IDD2: Set RESET to High, set the the logic input voltage to 5 V, and measure the input current. Set RESET to High, set the the logic input voltage to 0 V, and measure the input current. Apply VDD, input RESET, and measure IDD. Input 6.25 MHz clock and measure the current when the logic is operating. Set output to OPEN.
Setup data
DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Vref AB 9
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TB62202AFG
3. IM1, IM2 (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
SGND
0.01 F
IM A
Ccp C 13 Ccp B 12
Ccp 2
24 V
0.22 F
At IM1 testing: RESET = L (0 V) At IM2 testing: RESET = H (5 V) VDD SGND
5V
P-GND SETUP 6
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Test method
IM1: Set the logic block to non-active (DATA = all 0), VDD = 5 V, VM = 24 V, and output to open. Measure the current input from VM supply. RESET = L IM2: Set the logic block only to active (CLK = 6.25 MHz), VM = 24 V, and output to open. Measure the current input from VM supply. RESET = H
Setup data
DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Vref AB 9
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TB62202AFG
4. IM3 (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
6
0.22 F
No reset at testing RESET = 5 [V]
5V
P-GND SETUP
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
This is the IM current when all of the circuits, including the output transistors, in the IC are operating. The IM current includes the current dissipation in the charge pump circuit, output gate loss, and output predriver. Because the IM current (IM3) is input from the RS pin, which is also used for the output current, IM3 cannot be measured by the normal testing methods. Use the method shown below.
Setup data
The serial data PHASE signal (both A and B) switch over to high or low.
DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Test method
Set output to open, change phase data from 1 0 1 0 and perform switching. When testing, input phase data at double the chopping frequency (if fchop = 100 kHz, fDATA = 200 kHz) and measure the current value of VM supply. fDATA = 200 kHz means that the phase switches at 200 kHz.
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Vref AB 9
A IM
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TB62202AFG
Number of switchings at phase switching Number of switchings at actual operation
Mode changes three times in one chopping cycle. To VM RRS
One phase switching (16-bit data input) Four transistors switching
To VM RRS
Chopping cycle U1 ON Load L1 OFF U2 OFF U1 OFF Load L2 OFF OFF
Four transistors switching
U2 ON ON
Two transistors switching
OFF
OFF
OFF
Switches by phase data L2 ON L1 ON
OFF Charge
ON
ON Slow
ON
Two transistors switching
Four transistors switching One phase switching (16-bit data input)
ON
PGND
PGND
Eight transistors switching in one chopping cycle
ON Fast
OFF
Four transistors are switched at one phase switching
Number of switchings at actual operation = 2 x number of switchings at phase switching. Therefore, switching the phase at 2 x chopping cycle matches the number of switchings at actual operation with the number of switchings at phase switching, and allows the actual current dissipation, IM3, to be measured.
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TB62202AFG
5. IOB, IOH, IOL (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc AB = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 A IOH, IOL A IOB
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
SGND
0.01 F
IOL
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Test method
IOH: IOB: IOL: With VM = 24 V, VDD = 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins to GND, and measure the supply current. With VM = 24 V, VDD = 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins to VM, and measure the supply current. With VM = 24 V, VDD = 5 V, and logic input all = 0 applied, set RESET = L, connect the output pins to GND, and measure the supply current.
Setup data
DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Vref AB 9
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TB62202AFG
6. VRS (H to L), Vref (GAIN) (when measuring phase A) after measurement
(A/B unit only. C/D unit conforms to A/B unit.)
Rosc AB = 3.6 k
Cosc AB = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 Oscilloscope
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
V
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
Vary between 0 and 1 V. SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
VRS (H to L): Input torque data = 100% (HH) and vary the voltage between VM and RS pins. Measure the voltage (VRS) when output changes from fixed Charge mode to another mode. Also measure VRS when torque data = 85% (HL), 70% (LH), or 50% (LL) as above and calculate the ratio using VRS value at 100% as reference. Vref (GAIN): Vref (GAIN) =
VRS (*) ((*) VRS: when torque data = 100%) Vref
Setup data
H L H L H L
DATA CLK STROBE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Vref AB 9
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TB62202AFG
7. Iout1, Iout2 (A/B unit only. C/D unit conforms to A/B unit.)
8 CR SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
Monitors current waveform.
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
RRS B
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and measure the various output currents at constant current operation.
Setup data
Set to100% DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MDT Current waveform Output current value (set current value) 0% Charge Slow 100% 0% Fast Slow
MDT
Fast
Measurement of peak current
Charge
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Vref AB 9
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TB62202AFG
8. IRS (when measuring phase A) (A/B unit only. C/D unit conforms to A/B unit)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD 31 STROBE AB 30 CLK AB 29 DATA AB A 32 A 35 B2 B 5 A
SGND
RRS B 3 VM B 1 VSS (FIN) 28 RESET
SGND
0.01 F
RESET = L
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
5V
0.22 F
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
With L input to RESET , connect VM and RRS to the power supply, and measure the current input to the RS pin. (Either drop all the input pins to GND level or input all Low data to the DATA pin, then perform measurement. At that time, leave all other output pins open.)
Setup data
H L H L H L
DATA CLK STROBE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Vref AB 9
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TB62202AFG
9. RON (D-S), RON (S-D) when measuring output A (A/B unit only. C/D unit conforms to A/B
unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 Curve tracer
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 Curve tracer VSS (FIN) 28 RESET
5V
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
0.22 F
SGND
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Input the current setting data (HHHH signal) to the DATA pin and measure the voltage between VM and OUT when Iout = 1000 mA or the voltage between OUT and GND. Then, change the phase and repeat measurement. At that time, leave the output pins which are not measured open.
Setup data (Vary the phase data during testing.)
H L H L H L
DATA CLK STROBE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Vref AB 9
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TB62202AFG
10. Vref, Iref (A/B unit only. C/D unit conforms to A/B unit.)
Rosc AB = 3.6 k
Oscilloscope
Cosc AB = 560 pF
8 CR AB SGND
Vref AB 9 VM A 36 RRS A 34
Monitor A Iref (*) Vary Vref = 2 to VDD - 1.0 V
*: When measuring Iref, fix Vref = 3 V and measure.
SGND
27 VDD 31 STROBE AB 30 CLK AB 29 DATA AB
A 32 A 35 B2 B 5
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V 0.01 F
SGND
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Vref: Vary Vref = 2 to VDD - 1 V and confirm that output is on. Iref: When VM = 24 V and VDD = 5 V, apply the specified voltage of 3 V to the Vref and monitor the current flow value.
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TB62202AFG
11. TjTSD, TjTSD (Measure in an environment such as an constant temperature chamber where
the temperature for the IC can be freely changed) (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 Curve tracer
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 Curve tracer VSS (FIN) 28 RESET
5V
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
0.22 F
SGND
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
TjTSD: Increase the ambient temperature. Measure the temperature when output stops. TjTSD: Gradually lower the temperature from the level when the TSD circuit was operating (output off). At that time, control the RESET input thus : H L H L. Output will begin at a certain temperature level. TjTSD is the difference between the temperature at which output begins and the temperature at which TSD is triggered.
Setup data
H L H L H L
DATA CLK STROBE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Vref AB 9
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TB62202AFG
12. VDDR (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Oscilloscope
Cosc = 560 pF
8 CR AB SGND
VDD SGND
5V
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V 0.01 F
RRS B
SGND
Ccp C 13 Ccp B 12 P-GND Ccp A 7
Ccp 2 VM
24 V
0.22 F
No reset at testing RESET = 5 [V] VDD SGND Vary from 0 V
Ccp 1
: PGND : SGND (VSS)
Monitor the output pins. Increase the VDD voltage from 0. Measure the VDD value when output starts. Next, decrease the VDD voltage and measure the VDD value when output stops.
Setup data
H L H L H L
DATA CLK STROBE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Vref AB 9
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TB62202AFG
13. VMR (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Oscilloscope
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V 0.01 F
RRS B
SGND
Ccp C 13 Ccp B 12 P-GND Ccp A 7
Ccp 2 Vary from 0 V
0.22 F
No reset at testing RESET = 5 [V]
5V
VDD SGND
Ccp 1
: PGND : SGND (VSS)
With the CLK signal and DATA (all High) input, increase the VM voltage from 0. Measure the VM value when output starts. Next, decrease the VM voltage and measure the VM value when output stops.
Setup data
H L H L H L
DATA CLK STROBE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Vref AB 9
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14. Overcurrent protector circuit (ISD) (To measure output A : )
(A/B unit only. C/D unit conforms to A/B unit.)
Rosc AB = 3.6 k
Cosc AB = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 Curve tracer
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 Curve tracer VSS (FIN) 28 RESET
5V
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
0.22 F
SGND
At measuring, non-reset RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Test method: To monitor operating current of the overcurrent protector circuit when output A is short-circuited to the power supply Input the current setting data (HHHH signal) to the DATA pin. If short-circuited to the supply, measure the lower output transistors. If short-circuited to ground, measure the upper output transistors (see how to measure RON). When measuring RON, increase the current flow. There is a current value at which output is switched off and RON cannot be measured. This value is the set current value for the overcurrent protector circuit. Make sure to leave open the output pins not being measured. Note that if the temperature changes, the value may fluctuate. Try to avoid applying power to the IC by one-shot measuring.
Setup data (Example : The phase signal must be changed depending on the pin.)
H L H L H L
DATA CLK STROBE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Vref AB 9
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TB62202AFG
15. Current vector (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
Monitor current waveform
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
RRS B
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
At measuring, non-reset RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Perform chopping in Mixed Decay mode with load L. Monitor the output current waveform and measure the output current at constant current operation. At this time, vary the 4-bit data for current setting and measure the current values. Using the set output current as 100%, calculate the output current ratio.
100%
Output current
(example) 71% 100%
0%
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Vref AB 9
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16. fCLK, tw (CLK), twp (CLK), twn (CLK), tSTROBE, tSTROBE (H), tSTOBE (L), tsuSIN-CLK, tsuST-CLK, thSIN-CLK, thCLK-ST (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V 0.01 F
RRS B
SGND
Ccp C 13 Ccp B 12 P-GND Ccp A 7
Ccp 2
24 V
0.22 F
No reset at testing RESET = 5 [V]
5V
VDD SGND
Ccp 1
: PGND : SGND (VSS)
Input any data at fCLK (max), perform chopping, and monitor the output waveform. For the measuring points, see the timing chart below.
Setup data
DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Measuring points
tw (CLK)
CLK
50% tsuST-CLK thCLK-ST twn (CLK) twp (CLK)
STROBE
50% tSTROBE (H) tSTROBE (L) tSTROBE thSIN-CLK 50%
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DATA
50% DATA15 DATA0
tsuSIN-CLK
42
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Vref AB 9
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17. OSC-fast delay, OSC-charge delay (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
RRS B
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Fix the output current value in Mixed Decay mode and turn the output on. Measure the time until the output switches from the CR pin waveform and the output voltage waveform.
Setup data
DATA CLK STROBE Top CR Bottom Osc-fast delay Vout A 50% 50% Osc-charge delay 50% H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
50% www..com Vout A (Mode) Charge Slow Fast Charge
50%
3V
Vref AB 9
50%
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18. tpHL (ST), tpLH (ST), tr, tf (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Monitor
3V
Cosc = 560 pF
8 CR AB SGND
Vref AB 9 VM A 36 RRS A 34 RRS A
SGND
27 VDD 5V 0V 5V 0V 5V 0V 31 STROBE AB 30 CLK AB 29 DATA AB
A 32 A 35 B2 B 5
L = 6.8 mH
RL = 5.7
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
RRS B
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Setup data
DATA CLK STROBE H L H L H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Switch PHASE every 130 s and measure the output pin voltage and the STROBE signal.
[Oscilloscope waveform (example)]
130 s STROBE 50% tpHL (ST) OUTPUT Voltage A tpLH (ST) OUTPUT Voltage A 90% 50% 10% tr tf 10% 90% 50%
50%
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19. tBRANK (A/B unit only. C/D unit conforms to A/B unit.)
Rosc AB = 3.6 k
Cosc AB = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
RRS B
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
0.22 F
SGND
No reset at testing RESET = 5 [V]
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
tBRANK is the dead time band for avoiding malfunction caused by noise. Apply sufficient differential voltage (when Vref = 3 V, 0.6 V or higher) to VM-RS and apply duty. When the pulse width reaches a certain value, triggering feedback and changing the output. Check the value.
Measure the pulse width where output changes.
VM
RS pin voltage
Apply pulse to the RS pin so that the RS pin = VM voltage - 1.0 V.
H Output operation L
Setup data
DATA CLK H L H L H 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
STROBE www..com L
45
3V
Vref AB 9
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20. fchop (fchop (min), fchop (max)) (A/B unit only. C/D unit conforms to A/B unit.)
Oscilloscope
Rosc AB = 3.6 k
Cosc AB = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD 31 STROBE AB 30 CLK AB 29 DATA AB A 32 A 35 B2 B 5 RRS A
SGND
RRS B 3 VM B 1 VSS (FIN) 28 RESET Ccp C 13 Ccp B 12 VDD SGND
5V
RRS B
SGND
0.01 F
Ccp 2
24 V
0.22 F
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Change the Rosc and Cosc values and measure the frequency on the CR pin using the oscilloscope. At this time, 1/8 of the frequency of the measured CR waveform is fchop.
Oscilloscope waveform (example)
1/8 fchop (SYNC) = fCR
t=0
t=1
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3V
Vref AB 9
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21. tONG (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR AB SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
RRS B
SGND
0.01 F
Ccp C 13 Ccp B 12
Ccp 2
24 V
VDD SGND
0.22 F
At measuring, change from reset to non-reset.
5V
P-GND
Ccp A 7
Ccp 1
: PGND : SGND (VSS)
Apply VM and VDD and change RESET from L to H. Measure the time until the CcpA pin becomes VM + VDD x 90%.
VDD + VM VM + (VDD x 90%)
VM
5V RESET 0V tONG 50%
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3V
Vref AB 9
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22. Mixed decay timing (A/B unit only. C/D unit conforms to A/B unit.)
Rosc = 3.6 k
Cosc = 560 pF
8 CR SGND
VM A 36 RRS A 34 27 VDD A 32 A 35 B2 B 5 RRS A
SGND
5V 0V 5V 0V 5V 0V
31 STROBE AB 30 CLK AB 29 DATA AB
RRS B 3 VM B 1 VSS (FIN) 28 RESET
5V
RRS B
SGND
0.01 F
Ccp C 13 Ccp B 12 6 SETUP P-GND Ccp A 7
Ccp 2
24 V
VDD SGND
5V
At measuring, non-reset RESET = 5 [V]
5V
0.22 F
Ccp 1
: PGND : SGND (VSS)
With VM = 24 V, VDD = 5 V, RESET = H, change the SETUP pin from L to H and overwrite the MIXED DECAY TIMING TABLE. Then change the SETUP pin from H to L. With load L, perform chopping and monitor the output current waveform at that time. Confirm that the switching timing from Slow Decay Mode to Fast Decay Mode within an fchop cycle is the specified MIXED DECAY TIMING. (Depending on the load L value and the test environment, chopping may be performed every two cycles or there may be no Slow Decay Mode. If so, conditions, for example, load condition, may need to be changed.
MDT 0% Slow Charge MDT 100% 0% Fast Charge Current waveform Slow MDT Fast MDT
Output current value (set current value)
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3V
Vref AB 9
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Waveforms in Various Current Modes (Ideal Waveform)
Normal MIXED DECAY MODE Waveform
NF is the point at which the output current reaches the set current value. fchop CR CLK signal Iout Set current value Set current value NF NF fchop
12.5% MIXED DECAY MODE
RNF MDT (MIXED DECAY TIMING) point
When NF is after MIXED DECAY Timing
Fast Decay mode after Charge mode. Iout Set current value MDT (MIXED DECAY TIMING) point NF
Set current value
37.5% MIXED DECAY MODE
NF
RNF
RNF
STROBE signal input
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In MIXED DECAY MODE, when the output current > the set current value
fchop Set current value Iout NF RNF NF fchop fchop fchop
CHARGE MODE for one fchop cycle after STROBE signal input
Because the set current value > the output current, no CHARGE MODE in the next cycle.
12.5% MIXED DECAY MODE
RNF
Set current value
NF RNF
MDT (MIXED DECAY TIMING) point
STROBE signal input
FAST DECAY MODE Waveform
fchop Set current value Iout NF is the point at which the output current reaches the set current value.
FAST DECAY MODE (0% MIXED DECAY MODE) RNF
Because the set current value > the output current, FAST DECAY MODE in the next cycle, too
Set current value
NF
RNF
Because the set current value > the output current, CHARGE MODE NF FAST DECAY MODE in the next cycle, too
RNF STROBE signal input Response delay time
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STROBE Signal, Internal CR CLK, and output Current Waveform
(When STROBE Signal is input in SLOW DECAY MODE)
fchop
fchop
fchop 37.5% MIXED DECAY MODE
Set current value Iout Set current value
MDT NF MDT RNF
RNF
STROBE signal input Reset CR-CLK counter here
Momentarily enters CHARGE MODE
When STROBE signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next CR-CLK timing. Because of this, compared with a method in which the counter is not reset, response to the input data is faster. (The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform: 1.25 S @100 kHz CHOPPING.) When the CR-CLK counter is reset due to STROBE signal input, CHARGE MODE is entered momentarily due to current comparison. Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison.
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STROBE Signal, Internal CR CLK, and output Current Waveform
(When STROBE signal is input in CHARGE MODE)
fchop
fchop
fchop
Set current value Iout Set current value
MDT NF
37.5% MIXED DECAY MODE
RNF
MDT
RNF
STROBE signal input
Momentarily enters CHARGE MODE
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(When STROBE Signal is input in FAST DECAY MODE)
fchop fchop 37.5% MIXED DECAY MODE
fchop
Set current value
NF MDT MDT
Iout Set current value
NF
MDT
RNF RNF
STROBE signal input
Momentarily enters CHARGE MODE
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(When PHASE Signal is input)
37.5% MIXED DECAY MODE fchop fchop fchop
Set current value Iout
0
RNF Set current value STROBE signal input NF NF
RNF MDT
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(When current point 0 control is included)
37.5% MIXED DECAY MODE fchop fchop fchop
Set current value Iout (1) (2)
0 (1) (2) (1)
Set current value STROBE signal input Reset CR-CLK counter here Reset CR-CLK counter here
(1)
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(When FAST DECAY MODE is included during the sequence)
fchop Set current value fchop fchop fchop fchop
37.5% MIXED DECAY MODE
FAST DECAY MODE
Set current value
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(When SLOW DECAY MODE is included during the sequence)
fchop Set current value fchop fchop fchop fchop fchop
SLOW DECAY MODE
37.5% MIXED DECAY MODE
fchop Set current value
37.5% MIXED DECAY MODE
In SLOW DECAY MODE, depending on the load, the set current cannot be accurately traced. Therefore, do not use SLOW DECAY MODE.
STROBE
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Current Modes
(MIXED (= SLOW + FAST) Decay Mode Effect)
Sine wave in increasing (Slow Decay Mode (Charge + Slow + Fast) normally used)
Slow Set current value Slow Set current value Charge Fast Charge Slow Fast Charge Fast Charge Slow
Fast
Sine wave in decreasing (When using MIXED DECAY Mode with large attenuation ratio (MDT%) at attenuation)
Slow Set current value Charge Fast Slow Set current value Fast Charge Fast Slow Charge Slow Fast Because current attenuates so quickly, the current immediately follows the set current value.
Sine wave in decreasing (When using MIXED DECAY Mode with small attenuation ratio (MDT%) at attenuation)
Because current attenuates slowly, it takes a long time for the current to follow the set current value (or the current does not follow). Fast Charge Fast Set current value Charge Fast
Set current value Charge
Slow Fast Charge
Slow
Note: The above charts are schematics. The actual current transient responses are curves.
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Output Transistor Operating Mode
To VM RRS RS pin U1 (Note) U2 U1 (Note) To VM RRS RS pin U2 U1 (Note) To VM RRS RS pin U2
Load L1 L2 L1
Load L2 L1
Load L2
PGND Charge mode (Charges coil power)
PGND Slow mode (Slightly attenuates coil power)
PGND Fast mode (Drastically attenuates coil power)
Output Transistor Operation Functions
CLK CHARGE SLOW FAST U1 ON OFF OFF U2 OFF OFF ON L1 OFF ON ON L2 ON ON OFF
Note: The above table is an example where current flows in the direction of the arrows in the above figures. When the current flows in the opposite direction of the arrows, see the table below.
CLK CHARGE SLOW FAST U1 OFF OFF ON U2 ON OFF OFF L1 ON ON OFF L2 OFF ON ON
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Output Transistor Operating Mode 2
(Sequence of MIXED DECAY MODE)
To VM RRS
To VM RRS
To VM RRS
U1
U2
U1
U2
U1
U2
OUT A L1
OUT A L2
OUT A L1
OUT A L2
OUT A L1
OUT A L2
PGND H OUTPUT voltage A L H OUTPUT voltage A L Set current 50%
PGND
PGND
50%
50%
OUPUT current
L Charge Mode Slow Mode Fast Mode
The constant current is controlled by changing mode from Charge Slow Fast.
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Current Discharge Path when Current Data = 0000 are input during operation
In Slow Decay Mode, when all output transistors are forced to switch off, coil energy is discharged in the following MODES : Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the parasitic diodes. However, when signal 0000 is input during operation, the current flows to them.
To VM RRS RS pin U1 ON (Note) U2 OFF U1 OFF (Note) To VM RRS RS pin U2 OFF U1 OFF (Note) To VM power supply RRS RS pin U2 OFF
Load L1 OFF L2 ON L1 ON
Load
Input Current DATA = 0000 L2 ON L1 OFF
Load L2 OFF
PGND Charge mode
PGND Slow Decay mode
PGND Forced OFF mode
As shown in the figure at right, an output transistor has parasitic diodes. To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to switch off, the energy of the coil is discharged via the parasitic diodes.
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PD-Ta (Package Power Dissipation)
PD - Ta
3.5 3.0 (2) (1) Rth (j-a) IC only (96C/W) (2) When mounted on the board (38C/W) Board size(100 x 200 x 1.6 mm) * Rth (j-c): 8.5C/W
(W) Power dissipation PD
2.5 2.0 1.5 1.0 0.5 0 0
(1)
25
50
75
100
125
150
Ambient temperature
Ta (C)
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Power Supply Sequence (Recommended)
VDD (max) VDD (min) VDD VDDR
GND VM VM (min) VMR GND NON-RESET Internal reset RESET
VM
RESET input *
H RESET L Takes up to tONG until operable. Non-operable area
t
Note 1: If the VDD drops to the level of the VDDR or below while the specified voltage is input to the VM pin, the IC is internally reset. This is a protective measure against malfunction. Likewise, if the VM drops to the level of the VMR or below while regulation voltage is input to the VDD, the IC is internally reset as a protective measure against malfunction. To avoid malfunction, when turning on VM or VDD, we recommend you input the RESET signal at the above timing. It takes time for the output control charge pump circuit to stabilize. Wait up to tONG time after power on before driving the motors. Note 2: When the VM value is between 3.3 to 5.5 V, the internal reset is released, thus output may be on. In such a case, the charge pump cannot drive stably because of insufficient voltage. We recommend the RESET state be maintained until VM reaches 20 V or more. Note 3: Since VDD = 0 V and VM = voltage within the rating are applied, output is turned off by internal reset. At that time, a current of several mA flows due to the Pass between VM and VDD.
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Relationship between VM and VH
VH is the voltage of the CcpA pin. It is the highest voltage in this IC (power supply for driving the upper gate of the H bridge).
VM - VH (& Vcharge up)
50
VH voltage VM voltage VDD = 5 V Ccp1 = 0.22 F Ccp2 = 0.02 F VH = VDD + VM (CcpA)
(V)
Charge up voltage
40
VH voltage, charge up voltage, VM voltage
Input RESET. 30 VMR ( RESET = 0 V) Maximum
20 Usable area
10
Recommended operation area
0 0
5
10
15
20
25
30
35
40
Supply voltage
VM
(V)
V charge Up is the voltage to boost VM to VH. Usually equivalent to VDD.
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Operation of Charge Pump Circuit
VM = 24 V VM 1/18/19/36 VH i2 Di2 Di1 Tr2 Comparator & Controller Output Output H switch Tr1 VZ Di3 R1 (1) (2) 13 i1 (2) 12 Ccp B
Ccp 2 = 0.01 F Ccp 1 = 0.22 F
27
VDD = 5 V
RS 3/16/21/34
RRS
Ccp A 7
Ccp C
VH = VM + VDD = charge pump voltage i1 = charge pump current i2 = gate block power dissipation Initial charging (1) When RESET is released, Tr1 is turned ON and Tr2 turned OFF. Ccp2 is charged from Ccp2 via Di1 (This is the same as when TSD and ISD are operating and the IC is restored from Reset state.) (2) Tr1 is turned OFF, Tr2 is turned ON, and Ccp1 is charged from Ccp2 via Di2. (3) When the voltage difference between VM and VH (CcpA pin voltage = charge pump voltage) reaches VDD or higher, operation halts (Steady state : Because the capacitor is naturally discharged, the IC is continually charging to the capacitor). Actual operation (4) Ccp1 charge is used at fchop switching and the VH potential drops. (5) Charges up by (1) and (2) above.
Output switching Initial charging
Charge pump voltage
Normal state
VH VM (1) (2) (3) t (4) (5) (4) (5)
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External Capacitors for Charge Pumps
When VDD = 5V, fchop = 100 kHz, and L = 10 mH is driven with VM = 24 V, Iout = 1100 mA, the theoretical values for Ccp1 and Ccp2 are as shown below:
Ccp 1 - Ccp 2
0.05 0.045 0.04 Usable area Ccp 1 = (NG) Ccp 2 = (OK)
(F) Ccp 2 capacitance
0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Recommended value Recommended area
Ccp 1 capacitance
(F)
Combine Ccp1 and Ccp2 as shown in the shaded area in the above graph. Select values 10: 1 or more for Ccp1: Ccp2. When making a setting, evaluate properly and set values with a margin.
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Charge Pump Rise Time
VDD + VM VM + (VDD x 90%)
VM
5V
RESET
0V
50%
tONG
tONG: Time taken for capacitor Ccp2 (charging capacitor) to fill up Ccp1 (capacitor used to save charge) to VM + VDD after a reset is released. The internal IC cannot drive the gates correctly until the voltage of Ccp1 reaches VM + VDD. Be sure to wait for tONG or longer before driving the motors. Basically, the larger the Ccp1 capacitance, the longer the initial charge-up time but the smaller the voltage fluctuation. The smaller the Ccp1 capacitance, the shorter the initial charge-up time but the larger the voltage fluctuation. Depending on the combination of capacitors (especially with small capacitance), voltage may not be sufficiently boosted. Thus, use the capacitors under the capacitor combination conditions (Ccp1 = 0.22 F, Ccp2 = 0.01 F) recommended by Toshiba.
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Operating Time for Overcurrent Protector Circuit
(ISD non-sensitivity time and ISD operating time)
CR oscillation (basic chopping waveform)
Output halts (Reset status)
MIN
MAX
(Non-sensitivity time) ISD BLANK time
MIN
MAX ISD operating time
Point where overcurrent flows to output transistors (overcurrent status start)
A non-sensitivity time is set for the overcurrent protector circuit to avoid misdetection of overcurrent due to spike current at irr or switching. The non-sensitivity time synchronizes with the frequency of the CR for setting the chopping frequency. The non-sensitivity time is set as follows : Non-sensitivity time = 4 x CR cycle The time required for the ISD to actually operate after the non-sensitivity time is as follows : Minimum: 5 x CR cycle Maximum: 8 x CR cycle Therefore, from the time overcurrent flows to the output transistors to the time output halts is as follows. Note that ideally, the operating time is the operating time when overcurrent flows. Depending on the output control mode timing, the overcurrent protector circuit may not be triggered. Therefore, to ensure safe operation, add a fuse to the VM power supply for protection. The fuse capacity would vary according to the use conditions. However, select a fuse whose capacity avoids any operating problems and does not exceed the power dissipation for the IC.
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Application Operation Input Data (Example: 2-Phase Excitation Mode)
TORQUE TORQUE DECAY 0 1 B0 Bit 1 2 3 4 0 1 1 1 1 1 1 1 1 1 2 1 1 1 1 DECAY B1 3 0 0 0 0 B0 4 1 1 1 1 B1 5 1 1 1 1 B2 6 1 1 1 1 B3 PHASE B DECAY A 7 1 1 1 1 8 1 0 0 1 9 1 1 1 1 DECAY A0 10 0 0 0 0 A0 11 1 1 1 1 A1 12 1 1 1 1 A2 13 1 1 1 1 A3 PHASE A 14 1 1 1 1 15 1 1 0 0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal. For the input conditions, see page 9, Functions. We recommend Mixed Decay mode (37.5%) as Decay mode. Set torque to 100%.
Output current waveform of 2-phase excitation sine wave
(%) 100
Phase B
0 Phase A
-100
Note: We recommended 2-phase excitation drive in 37.5% Mixed Decay mode. Please refer to the caution of 2-phase excitation mode on next page.
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Application Operation Input Data (Example: 1-2 Phase Excitation Mode Typ.A)
TORQUE TORQUE DECAY 0 1 B0 Bit 1 2 3 4 5 6 7 8 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 DECAY B1 3 0 0 0 0 0 0 0 0 B0 4 1 1 1 1 1 1 1 1 B1 5 1 0 1 1 1 0 1 1 B2 6 1 0 1 1 1 0 1 1 B3 PHASE B 7 1 0 1 1 1 0 1 1 8 1 1 1 0 0 0 0 1 DECAY A0 9 1 1 1 1 1 1 1 1 DECAY A1 10 0 0 0 0 0 0 0 0 A0 11 1 1 1 1 1 1 1 1 A1 12 1 1 1 0 1 1 1 0 A2 13 1 1 1 0 1 1 1 0 A3 PHASE A 14 1 1 1 0 1 1 1 0 15 1 1 1 0 0 0 0 1
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal. For the input conditions, see page 10, Functions. We recommend Mixed Decay Mode (37.5%) as Decay Mode. Set torque to 100%. When using this excitation mode, high efficiency can be achieved by setting the phase data to 10% (-10%). Set current values in the order +100% -10% -100% +10%.
Output Current Waveform of 1-2 Phase Excitation Sine Wave (Typ. A)
(%) 100
Phase A
10 0 -10
-100
(%) 100
Phase B
10 0 -10
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-100
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Points for Control that Includes Current of 0%
In modes other than 2-Phase Excitation mode (from 1-2 Phase Excitation mode to 4W1-2 Phase Excitation mode), when the current is controlled to 0%, the TB62201F's output transistors are all turned off. At the time, the coil's energy returns to the power supply through the parasitic diodes. If the same current is applied several times and is within the rated current, then : the power consumed by the on-resistance when current flows to the output MOS will be less than the power consumed when current is applied to the parasitic diodes. Therefore, when controlling the current, rather than setting 0%, set the current to the next step beyond 0% (the minimum step in the reverse direction) for better power dissipation results. However, if the 0% (actually 10%) current cycle is long, the power dissipation may be greater than in Off mode because of the need for constant-current control. Therefore, Toshiba recommend setting the current according to the actual operating pattern. (1-2 Phase Excitation mode is the most effective.)
Flyback diode mode
Charge
Constantcurrent control Output off period U1
OFF
[%] 100
RRS
To VM power supply
RS pin U2 OFF
The coil's energy returns through the parasitic diodes. Because VDS < VF, the power dissipation is large.
10 0 -10
L1 Constantcurrent control
OFF
Load
L2 OFF
-100
Forced Off mode PGND
Diode parasite
Non-flyback diode mode
Charge
RRS Constantcurrent control U1 ON 10 0 -10 To VM
[%] 100
RS pin U2 OFF
Constantcurrent control Constantcurrent control
OFF L1
Load
ON L2 Charge mode
The coil's energy returns through the MOS, which is turned on. Then the coil is charged to a level of 10%. The power dissipation is smaller than when the energy is returned via the parasitic diode. (However, the longer the 10% rated current control time, the longer the period of current dissipation.)
-100
Specifies a level of 10%, either side of 0.
Charge
PGND
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Application Operation Input Data (Example: 1-2 Phase Excitation mode Typ.B)
TORQUE TORQUE MDMB 0 1 Bit 1 2 3 4 5 6 7 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 DECAY B 3 0 0 0 0 0 0 0 B0 4 1 0 0 0 1 0 0 B1 5 1 0 0 0 1 0 0 B2 6 1 0 0 0 1 0 0 B3 7 1 1 0 1 1 1 0 PHASE B 8 1 1 1 0 0 0 0 MDM A 9 1 1 1 1 1 1 1 DECAY A 10 0 0 0 0 0 0 0 A0 11 0 0 1 0 0 0 1 A1 12 0 0 1 0 0 0 1 A2 13 0 0 1 0 0 0 1 A3 14 0 1 1 1 0 1 1 PHASE A 15 1 1 1 1 0 0 0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal. For the input conditions, see page 10, Functions. We recommend Mixed Decay Mode (37.5%) as Decay Mode. Set torque to 100%. Same as 1-2 phase excitation (typ. A) in the previous section, power dissipation can be reduced by changing 0% level to 10% or -10%.
Output Current Waveform of 1-2 Phase Excitation Sine Wave (Typ. B)
(%) 100
71
Phase A
0
Phase B
-71
-100
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TB62202AFG
Application Operation Input Data (Example: 4-bit micro steps) (4-bit micro steps = W1-2 phase excitation drive)
TORQUE TORQUE DECAY DECAY 0 1 B0 B1 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 4 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 B1 5 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 B2 6 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 0 1 0 1 1 B3 7 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 PHASE DECAY DECAY B A0 A1 8 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 A0 11 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 A1 12 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 A2 13 0 1 0 1 1 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 A3 14 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 PHASE A 15 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal. For the input conditions, see page 9, Functions. We recommend Slow Decay Mode in the ascending direction of the sine wave ; Mixed Decay Mode (37.5%) in the descending direction. Set torque to 100%.
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Output Current Waveform of Pseudo Sine Wave (4-bit micro steps)
(%) 100 92 71
Phase A
38
0 Phase B
-38
-71 -92 -100
STEP
5 micro-step from 0 to 90 drive is possible by combining Current DATA (AB & CD) and phase data. For input Current DATA at that time, see section on Current X in the list of the Functions. Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.
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TB62202AFG
Application Operation Input Data (Example: 3-bit micro steps) (3-bit micro steps = 2W1-2 phase excitation drive)
TORQUE TORQUE DECAY DECAY 0 1 B0 B1 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B1 5 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 B2 6 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 B3 7 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 PHASE B 8 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 DECAY DECAY A0 A1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 A0 11 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 A1 12 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 A2 13 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 A3 14 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 PHASE A 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal. For the input conditions, see page 10, Functions. We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the www..comto 100%. descending direction. Set torque
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Output Current Waveform of Pseudo Sine Wave (3-bit micro steps)
[%] 100 98 92 83 71 Phase A 56 38
20
0
-20
Phase B
-38 -56 -71 -83 -92 -98 -100
STEP
9 micro-step from 0 to 90 drive is possible by combining Current DATA (AB & CD) and phase data. For input Current DATA at that time, see section on Current X in the list of the Functions. Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.
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Application Operation Input Data (Example: 4-bit micro steps)
TORQUE TORQUE DECAY DECAY 0 1 B0 B1 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 4 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 B1 5 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 B2 6 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 B3 7 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 PHASE B 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DECAY DECAY A0 A1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A1 12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A2 13 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A3 14 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PHASE A 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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TORQUE TORQUE DECAY DECAY 0 1 B0 B1 Bit 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 4 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 B1 5 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 B2 6 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 B3 7 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 PHASE B 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DECAY DECAY A0 A1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A1 12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A2 13 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A3 14 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PHASE A 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal. For the input conditions, see page 10, Functions. In the above input data example, Decay mode has a Mixed Decay mode (37.5%) setting for both the rising and falling directions of the sine wave, and a torque setting of 100%.
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TB62202AFG
4W1-2 Output Current Waveform of Pseudo Sine Wave (4-bit micro steps)
[%] 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 Phase A
0
-10
Phase B
-20 -29 -38 -47 -56 -63 -71 -77 -83 -88 -92 -96 -98 -100
STEP
17 micro-step from 0 to 90 drive is possible by combining Current DATA (AB & CD) and phase data. For input Current DATA at that time, see section on Current X in the list of the Functions. Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.
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Output Current Vector Line
4W-1-2 phase excitation (4-bit micro steps)
100 98 96 92 X = 11 88 X = 10 83 X=9 77 X = 16 X = 15 X = 14 X = 13 X = 12
71
X=8 X=7
63
56
X=6
(%)
47
X=5
IA
38
X=4
29
X=3
20
X=2
X
10
X
X=1
X=0 0 10 20 29 38 47 56 63 71 77 83 88 92 96 98 100
IB
(%)
For data to be input, see the function of Current AX (BX) in the list of Functions (10 page).
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Output Current Vector Line 2 (Each mode: except 4W1-2 phase)
1-2 phase excitation (Typ. A)
100 100
1-2 phase excitation (Typ. B)
IA (%)
0
100
IA (%)
0
71
100
IB (%)
IB (%)
W 1-2 phase excitation
100 92 100 98 92 83 71 71 56
2W 1-2 phase excitation
IA (%)
38
IA (%)
38
38
20
0
71
92 100
0
20
38
56
71
83
92 100 98
IB (%)
IB (%)
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TB62202AFG
Recommended Application Circuit
The values for the devices are all recommended values. For values under each input condition, see the above-mentioned recommended operating conditions. (Example : fchop = 96 kHz, CR : Iout = 0.6 (A), LF : Iout = 0.6 (A) )
Rosc = 2.0 k CR Cosc = 1000 pF SGND VDD 5V 0V 5V 0V 5V 0V 5V 0V STEPUP CLK AB DATA AB STROBE AB
Vref AB Vref AB 2.63 V SGND VM A RRS A A A B B RRS B P-GND VM B VSS (FIN) RRS A 0.75 1 F
M MOTOR 1
STEPPING (CR: 6.8 mH/5.7 )
RRS B 0.75
5V 0V 5V 0V 5V 0V 5V 0V
CLK CD DATA CD STROBE CD
SGND VM C RRS C C RRS C 0.75
RESET
C
D D RRS D VM D
M MOTOR 2
STEPPING (LF: 6.8 mH/5.7 )
RRS D 0.75
Ccp A Ccp B 5V SGND 100 F Cop 1 0.22 F SGND
Vref CD Ccp C 4.13 V 1 F SGND 100 F 24 V
Ccp 2 0.015 F
Note: We recommend the user add bypass capacitors as required. Make sure as much as possible that GND wiring has only one contact point. Also, make sure that the VM pins are connected. For the data to be input, see the section on the recommended input data. Because there may be shorts between outputs, shorts to supply, or shorts to ground, be careful when designing output lines, VDD (VM) lines, and GND lines.
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TB62202AFG
Package Dimensions
HSOP36-P-450-0.65 Unit: mm
Weight: 0.79 g (typ.)
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About solderability, following conditions were confirmed * Solderability (1) Use of Sn-63Pb solder Bath * solder bath temperature = 230C * dipping time = 5 seconds * the number of times = once * use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath * solder bath temperature = 245C * dipping time = 5 seconds * the number of times = once * use of R-type flux
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
030619EBA
* The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations.
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