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RTL8186/RTL8186P
WIRELESS LAN ACCESS POINT/ GATEWAY CONTROLLER
Preliminary DATASHEET
Rev. 0.9 4 Aug 2004 Track ID: XXXXXXXXX
RTL8186
www..com
COPYRIGHT (c)2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engineer's reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY
Revision 0.9 Release Date 2004/8/4 Summary First preliminary release.
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Table of Contents
1. OVERVIEW .......................................................................................................................................4
2. PIN ASSIGNMENTS .........................................................................................................................6 3. PIN DESCRIPTION ..........................................................................................................................8 4. ADDRESS MAPPING...................................................................................................................... 16 5. REGISTER MAPPING.................................................................................................................... 18 6. SYSTEM CONFIGURATION......................................................................................................... 23 REGISTER SUMMARY ........................................................................................................................... 25 7. INTERRUPT CONTROLLER........................................................................................................ 27 REGISTER SUMMARY ........................................................................................................................... 27 8. MEMORY CONTROLLER ............................................................................................................ 29 REGISTER SUMMARY ........................................................................................................................... 29 TIMING DIAGRAM ............................................................................................................................... 34 9. ETHERNET NETWORK INTERFACE CONTROLLER ............................................................ 35 DESCRIPTOR DATA STRUCTURE............................................................................................................ 36 REGISTER SUMMARY ........................................................................................................................... 41 10. UART CONTROLLER.................................................................................................................. 55 REGISTER SUMMARY ........................................................................................................................... 55 11. TIMER & WATCHDOG ................................................................................................................ 60 REGISTER SUMMARY ........................................................................................................................... 60 12. GPIO CONTROL........................................................................................................................... 64 REGISTER SUMMARY ........................................................................................................................... 65 13. IPSEC CRYPTO ENGINE ............................................................................................................ 69 DESCRIPTOR DATA STRUCTURES USED IN CRYPTO ENGINE.................................................................... 70 REGISTER SUMMARY ........................................................................................................................... 76 14. MIC CALCULATOR ..................................................................................................................... 78 REGISTER SUMMARY ........................................................................................................................... 78 15. PCM CONTROLLER.................................................................................................................... 80 REGISTER SUMMARY ........................................................................................................................... 80 16. 802.11A/B/G WLAN CONTROLLER ........................................................................................... 88 17. CHARACTERISTICS ................................................................................................................. 110 18. DESIGN AND LAYOUT GUIDE ................................................................................................ 110 18. MECHANICAL DIMENSIONS .................................................................................................. 111
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1. Overview
The RTL8186 is a highly integrated system-on-a-chip (SoC), embedded with a high-performance 32-bit RISC processor, Ethernet, and WLAN controller. It is a cost-effective and high-performance solution for wireless LAN Access Point, wireless SOHO router, wireless Internet gateway systems, etc. System block diagram:
EJTAG PCM
Watchdog
Microprocessor w/ cache and MMU Timer
IPSEC crypto engine
802.11 b/g/a MAC/BB
MII
RF transceiver
Ethernet MAC0
MII
Ethernet PHY
LAN
UART GPIO Memory controller
Ethernet MAC1 PCI Bridge
Ethernet PHY
WAN
PCI device
Flash
SDRAM
The embedded processor is a Lexra LX5280 32-bit RISC CPU, with separate 8K instruction and 8K data caches. A Memory Management Unit (MMU) allows the memory to be segmented and protected. Such protection is a requirement of modern operating systems (e.g., Windows NT, 2000, XP, Linux). The processor pipeline is a dual-issue 6-stage architecture. The dual-issue CPU fetches two instructions per cycle, allowing two instructions to be executed concurrently in two pipes for an up to 30% improvement over uni-scalar architecture. It includes two Fast Ethernet MACs, one possibly used for the LAN interface and the other connected to a WAN port. An IEEE 802.11a/b/g WLAN MAC+Baseband processor is embedded. By interfacing with an external Realtek RF module, it could provide the total solution for 2.4GHz or 5G.Hz WLAN system. To support the emergence of VPN applications and the latest test criteria of ICSA, RTL8186 incorporates a full function SH1/MD5/DES/3DES/AES-128 crypto engine. The crypto engine offloads the packet authentication/encryption/decryption job with just a single pass of DMA, and thus it could achieve high performance when IPSEC is deployed in system. RTL8186 provides a glueless interface for external SDRAM and flash memory devices. It allows customers to use from 1M to 64M bytes SDRAM/flash memory with 16-bit or 32-bit variable length in great flexibility. RTL8186 can also support NOR and NAND type flash, and booting from NAND type flash could be fulfilled without extra cost. Additionally, RTL8186 provides UART, PCI and PCM interfaces as well as more than 60 GPIO (Programmable I/O) pins. With the PCM interface, the wireless VoIP applications are made possible. Realtek will provide turn-key solution in both hardware and software. Beside the evaluation board, we will provide hardware reference design kit, and software development kit for customization and adding new features.
Features
Core Processor
n n n LX5280 32-bit RISC architecture compatible to MIPS R3000 ISA-1 Superscalar architecture, containing 2 execution pipelines with better performance Embedded with 8K I-Cache, 8K D-Cache, 4K I-RAM and 4K D-RAM
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n 16-entry MMU www..com supported n Up to 200MHZ operating frequency
WLAN Controller
n n n n n n Integrated IEEE 802.11a/b/g complied MAC and DSSS Baseband processor Data rate of 54M, 48M, 36M, 24M, 18M, 12M, 9M, 6M, 11M, 5.5M, 2M and 1M Support antenna diversity and AGC Support 802.11h DFS and TPC Embedded with encryption/decryption engine for 64 bits/128 bits WEP, TKIP/MIC and AES RF interface to Realtek 2.4G and 5G RF module
Fast Ethernet Controller
n n n n n n Fully compliant with IEEE 802.3/802.3u Supports MII interface with full and half duplex capability Supports descriptor-based buffer management with scatter-gather capability Supports IP, TCP, and UDP checksum offload Supports IEEE 802.1Q VLAN tagging and 802.1P priority queue Supports full duplex flow control (IEEE 802.3X)
UART
n n n n 2 UART interfaces 16550 compatible 16 bytes FIFO size Auto CTS/RTS flow control
Memory Controller
n n n n Supports external 16/32-bit SDRAM with 2 banks access, up to 32M bytes for each bank Supports two external 16-bit NOR-type Flash memory, up to 8M bytes for each bank Supports two external 8-bit NAND-type Flash memory, up to 32M bytes for each bank Support boot from NAND type to reduce total bone cost
IPSEC Crypto Engine
n n n n n Supports DES, 3DES and AES-128 encryption/decryption algorithm for ESP encryption with throughput up to 120Mbps Supports HMAC-MD5 and HMAC-SHA-1 authentication algorithms Supports CBC or EBC mode with DES/3DES/AES algorithm A 32-bit PRNG (pseudo random number generator) Single pass for both authentication and encryption/decryption
PCI Bridge
n n n n n Complies with PCI 2.2. Supports four external PCI devices. Supports PCI master/slave mode with shared IRQ 3.3 and 5V I/O tolerance One of the PCI device supports memory mapping space up to 16M bytes, others up 1M bytes
GPIO
n n 11 dedicate programmable I/O ports and 58 shared GPIO ports Individually configurable to input, output and edge transition
Watchdog/Timer/Counter
n n Hardware watchdog timer, used to reset the processor if the system hangs. 4 sets of general timers/counter
EJTAG
n Use standard IEEE 1149.1 JTAG interface for software debugging
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PCM
n n n Supports 4 audio channels Supports bus master mode Supports G..711 u-law and a-law
Package
n n RTL8186 208-Pin QFP (Without PCI Interface). RTL8186P 292-Pin TFBGA (With PCI Interface).
2. Pin Assignments
RTL8186 208-Pin QFP Pin Assignments:
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1 32 M A8 www..com 13 3 1 34 135 1 36 1 37 1 38 13 9 14 0 14 1 1 42 143 144 14 5 14 6 147 148 149 150 1 51 152 153 1 54 155 1 56 MA9 M A1 0 M A 11 GND VDD33 M A1 2 MA13 MA14 MA15 M A1 6 MCS3 LE D 0 LE D 1 G PIO 8 AN T SE L + W LG P IO 5 C AS B R AS B MWEB AN T SE L M A 17 GND VD D 33 M A1 8 1 31 M A7 13 0 12 9 12 8 12 7 12 6 125 124 12 3 122 1 21 120 1 19 118 117 1 16 115 114 1 13 11 2 11 1 110 10 9 1 08 1 07 106 105 MA6 R FT XE N MA5 MA4 MA3 MA2 MA1 MA0 V D D 33 GND MCS2 W LG PIO 4 V D D 18 LNAHL G PIO 9 GND VD D 18 V R E FO VRP VRN R XI+ R X IAGND RXQ+ RXQAG N D
157 A P A PE 158 B P A PE 1 59 W LG PIO 3 160 M A 19 161 M A 20 162 M A 21 163 M D 0 164 M D 1 165 M D 2 166 M D 3 167 M D 4 168 G N D 169 M C L K 1 70 G N D 1 71 V D D 3 3 17 2 M D 5 1 73 M D 6 1 74 M D 7 175 VD D 18 1 76 M D 8 1 77 M D 9 1 78 M D 10 1 79 M D 11 180 M D 1 2 181 M D 1 3 182 G N D 18 3 M D 14 184 M D 1 5 185 V D D 33 186 M D 1 6 1 87 M D 17 1 88 G P IO 10 189 N AF AL E 1 90 G N D 1 91 M D 18 1 92 M D 19 1 93 M D 20 1 94 M D 21 1 95 M D 22 196 M D 2 3 1 97 M D 24 1 98 M D 25 199 M D 2 6 2 00 G N D 20 1 V D D 33 20 2 V D D 18 2 03 M D 27 2 04 M D 28 2 05 M D 29 2 06 M D 30 2 07 M D 31 2 08 G N D 1 V D D 18 2 N A FB U S Y B 3 LRXD0 4 LRXD1 5 GND 6 N A FW E B 7 N A FR E B 8 G P IO 7 9 V D D 18 1 0 LR X D V 11 L TX E 12 L M D C 1 3 LR X C 14 L C O L 15 L M D IO 16 G N D 17 W TX D 0 18 V D D 3 3 19 L TX D 1 2 0 LTX D 2 21 L TX D 3 22 G N D 23 WRXD1 24 W R XD 2 2 5 W R XD V 26 WRXC
R TL8186
1 04 X IC N L 1 03 A V D D 33 1 02 A V D D 33 1 01 A G N D 1 00 R 15K 99 A V D D 33 98 A G N D 97 RXAGC 96 TX A G C 95 R SS I 9 4 TS S I0 9 3 TS S I1 92 A V D 33 91 A G N D 90 T XQ + 8 9 TX Q 8 8 TX I8 7 TX I+ 8 6 TX Q T+ 8 5 TX Q T8 4 TX IT+ 8 3 TX IT8 2 W L G P IO 6 81 XI 80 U C T S0 7 9 U S IN 0 78 G P IO 1 77 G P IO 0 76 N A FC LE 75 TR SW 74 VCOPDN 73 U R TS0 72 GND 71 W LG P IO 2 7 0 W L G P IO 1 6 9 V D D 33 6 8 C A LE N 67 V D D 1 8 6 6 G PIO 3 6 5 G PIO 2 64 GND 6 3 R FL E 6 2 R IFS D 6 1 R IFS C K 6 0 V D D 18 5 9 C A LM O D E 58 U S O U T0 5 7 TR S W + 56 G N D 55 R F R XE N 54 M C S 4 53 GND 5 2 W L G P IO 0 5 1 V D D 33 50 L R XD 3 49 L R XD 2 4 8 G PIO 4 47 W R XD 0 4 6 W T XD 3 4 5 W T XD 2 44 W TX D 1 43 W R XD 3 4 2 W M D IO 41 W TX C 4 0 W T XE 3 9 M C S5 38 M C S 1 3 7 M C S0 3 6 V D D 33 35 G N D 34 L TX C 33 G P IO 6 32 G N D 3 1 LT XD 0 30 WMDC 29 G P IO 5 2 8 V D D 18 27 W C O L
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RTL8186P 292-Pin TFBGA Pin Assignments:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A B C D E F G H J K L M N P R T U V W Y
SE W LGPI 5 2 ANT S C L G P IO 1 M A 1 4 M A 1 M A 1 0 M A 8 O5 L+ SOUT 6 8 3 1 M A 15 M A 11 M A 9 1U LED G P IO M C S M A 1 B PA P
MA6 MA7
MA5 MA4 E
MA3 MA2
MA1 MA0
I C IC L L G P A H L P IO 9 O S S I0 B2 PA R P K W 4 LN G G NT VREF T O M CS 2 1 P C K G N T B G N T B 3 V R P R X Q + X IC N L T S S I1
A B C D E F G H J K L M N P R T U V W Y
X D RFTX E L E D 0 M W E B R A S B C A S B P IO 1 6 M A 1 3 0 G IN T B P R N
SE Y B FR A M E A 17 A N T 8 D 2 6 U S IN 1 S D A M M A 1 IR D L- A B ST 0 C IR 25 M A 2 P B A D 27 A D G PI A PE M D 0 M A 19 W L AP O3 MD2 MCL MD1 3 1 M A2 REQ B A D 29 A D 28 V 3 DD3 V D D 33 GND GND GND GND GND GND
G CA V D D 3 A G N D VRN AG ND RX Q TXA 3 AG GPI 3 3 R SSI W L P T X D V D D 3 V D D 3 V D D 3 3 V D D 1 8 R X I+ A G N D A G N D R 1 5 K R X C O6 3 DD3 D 0 AVD AV T X IT U S IN 3 3 2 P F S G P IO 1 V D D 1 8 R X ID3 T - X Q T + G P IO 1 AVD TXQ T 3 VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND V 33 TX Q TXQ + T X I- G P IO 0 T X I+ XI
K MD3 MD4
D D 33
MD5 MD6
A D 1 T X IT + U C T S 0 A D 0 L N A FC G N TB 0 W L G PI D 23 A E O2 PD S0 V C O 3 ALEN BC URT N CBE PI 9 W LG BEB2 TR SW A D 1 O1 C VDD 18 2 30 18 V D D G P IO A D
8 3 MD7 VDD1 VDD3 18 VDD 18
M D 8 M D 10 V D D
AL 1 3 2 NAF MD1 MD1 MD1 E MD1 MD1 MD2 MD2 4 MD1 6 MD1 5 MD9
7 M D 18 M D 22 M D 19 0 MD2 1 B 3 M D2 TRDY
C R IF S A D 3 1 G P IO 3 C B E B 0 K + D E 1 T R S W R F L C B E B R IF S PI W L G R F R X EU S O U T C A L M O0 ODE 0 N
4 M D 25 M D 26 M D 29
D L 1 1 FBU 28 7 1 7 A D 8 A D 2 V D D 3 3 V D D 3 3V D D 3 3 W T X C W T X A D 1 4 L R X D 3 A D 2 0 4 1 M D2 M D NA B LRXD LTXD L CO AD M CS AD2 GP 1 SY D W TX W RX D D 24 4 EQB0 XD2 PB M D 30 M D 31 N A FRE L TX E A D 3 RE Q B2 A D 10 A D 4 A D 9 V D D 18 D D 18 C S1 A B1 G P IO R ST O 2 V LR M REQ 0 B D W SE D NAF 7 IO A D 6 D E V W R X W R X L M D C G P IO 6 E D 1 5 W R X D A D 1 1 G P IO 1 4 D 2 2 W T X D 0 0 OW P IO L R X C L M D M CS W TX A A LRXD V WC EB G LB 1 3 3 D W TX RXD 2 5 A D 5 T X D 0 D 18 C 5 3 W M D I A D 16 A D 12 3 S AD1 D V L M D P IO 1 1 A 0 L T X D L T X D 3 A D 7 W 2 G P IO 1 W R X C G P IO L L TXC M C LRX G O IO 1 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
3. Pin Description
Memory Interface
Symbol Memory Interface MDPIN[0] MDPIN[1] MDPIN[2] MDPIN[3] Type 208 QFP 256 BGA Description Pin No Pin No I/O 163 164 165 166 F1 G2 G1 H2 Data for SDRAM, Nor-type and NAND-type Flash.
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MDPIN[4] www..com MDPIN[5] MDPIN[6] MDPIN[7] MDPIN[8] MDPIN[9] MDPIN[10] MDPIN[11] MDPIN[12] MDPIN[13] MDPIN[14] MDPIN[15] MDPIN[16] MDPIN[17] MDPIN[18] MDPIN[19] MDPIN[20] MDPIN[21] MDPIN[22] MDPIN[23] MDPIN[24] MDPIN[25] MDPIN[26] MDPIN[27] MDPIN[28] MDPIN[29] MDPIN[30] MDPIN[31] MAPIN[0] MAPIN[1] MAPIN[2] MAPIN[3] MAPIN[4] MAPIN[5] MAPIN[6] MAPIN[7] MAPIN[8] MAPIN[9] MAPIN[10] MAPIN[11] MAPIN[12] MAPIN[13] MAPIN[14] MAPIN[15] MAPIN[16] MAPIN[17] MAPIN[18] MAPIN[19] MAPIN[20] MAPIN[21] SDCLKPIN MCSPIN[0] MCSPIN[1] MCSPIN[2] MCSPIN[3] MCSPIN[4] MCSPIN[5] RASBPIN 167 172 173 174 176 177 178 179 180 181 183 184 186 187 191 192 193 194 195 196 197 198 199 203 204 205 206 207 123 124 125 126 127 128 130 131 132 133 134 135 138 139 140 141 142 153 156 160 161 162 169 37 38 120 143 54 39 150 J2 J1 K1 K2 L1 N4 L2 M1 M3 M2 N1 N3 N2 P1 P2 P4 R1 R2 P3 R3 T1 T2 T3 U2 U3 T4 V2 V3 B12 A12 B11 A11 B10 A10 A9 B9 A8 B8 A7 B7 A6 C7 A5 B6 B5 D4 D1 F2 E1 G3 H1 W13 V13 B13 B4 U19 Y16 C4
O
Address for SDRAM, Nor-type and NAND-type Flash. MAPIN[18-15] mapping to DQM[3-0] for SDRAM
O O O O O
SDRAM clock SDRAM chip select Nor-type Flash chip select NAND-type Flash chip select Raw address strobe for SDRAM, this pin is also the output enable pin for Nor-type Flash
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CASBPIN www..com MWEBPIN NAFBUSYBPIN NAFWEBPIN NAFREBPIN NAFCLEPIN NAFALEPIN UART0 Interface UCTS0PIN URTS0PIN O O I O O O O I O 149 151 2 6 7 76 189 80 73 C5 C3 U4 W2 V4 K17 M4 J19 L17 SDRAM column address strobe Write enable for SDRAM and Flash NAND-type flash ready/busy status indication. NAND-type flash Write Enable. NAND-type flash Read Enable. NAND-type flash Command Latch Enable. NAND-type flash Address Latch Enable. Uart0 Clear-to-Send signal. This pin mux-ed function with I2C SDAPIN at 208 QFP package. Uart0 Request-to-Send signal. This pin mux-ed function with I2C SCLPIN at 208 QFP package. Uart0 In data signal. Uart0 Out data signal. Uart1 In data signal. Uart1 Out data signal. I2C data signal. I2C clock signal. PCM clock signal. PCM FS signal. PCM TX data signal. PCM RX data signal. WLAN Tx/Rx traffic indicator. WLAN Tx/Rx traffic indicator. Not used in 8225 RF chipset. Not used in 8225 RF chipset. Not used in 8225 RF chipset. Receive (Rx) In-phase Analog Data. Receive (Rx) Quadrature-phase Analog Data. This pin must be pulled low by a 15K resistor. Not used in 8225 RF chipset. Not used in 8225 RF chipset. Analog Input to the Receive Power A/D Converter for Receive AGC Control. Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control. Not used in 8225 RF chipset. Not used in 8225 RF chipset. Not used in 8225 RF chipset. 40 MHz OSC Input. Operating frequency voltage selection between 3.3v and 1.8v. Transmit (TX) Quadrature-phase Analog Data. Transmit (TX) In-phase Analog Data. Serial Clock Output. All operation mode switching and register setting is done by 4-wire serial interface.
USIN0PIN I 79 E20 USOUT0PIN O 58 T19 UART1 Interface USIN1PIN I NA D7 USOUT1PIN O NA B2 I2C Interface SDAPIN I/O NA D8 SCLPIN O NA A3 PCM Interface PCKPIN I/O NA B14 PFSPIN O NA C11 PTXDPIN O NA D9 PRXDPIN O NA C9 WLAN Traffic LED Control WLLED0PIN[0] O 144 C2 WLLED0PIN[1] O 145 B1 RF Interface for Realtek 8225 [802.11 b/g RF] VREFO X 113 A19 VRP X 112 B17 VRN X 111 C15 RXIP I 110 D14 RXIN I 109 C14 RXQP I 107 B18 RXQN 106 C17 R15K I/O 100 D17 RXAGC O 97 D18 TXAGC O 96 C18 RSSI I 95 D19 TSSI0 TSSI1 TXQP TXQN TXIN TXIP XI XIPWRSEL TXQTP TXQTN TXITP TXITN RIFSCKPIN I I O O O O I I O O O O O 94 93 90 89 88 87 81 104 86 85 84 83 61 A20 B20 H18 G18 G19 H19 H20 B19 F19 F18 J18 E19 P17
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RIFSDPIN www..com RFLEPIN CALENPIN CALMODEPIN VCOPDNPIN TRSWPIN TRSWBPIN RFTXENPIN RFRXENPIN LNAHLPIN ANTSELPIN ANTSELBPIN I/O O O I/O O O O O O O O O 62 63 68 59 74 57 75 129 55 117 147 152 R20 R18 L20 T20 L18 R17 M17 C10 T18 A16 A1 D5 Serial Data Input/Output. Serial Enable control. Serial Read/Write control. Not used in 8225 RF chipset. This pin is used to turn on/off RF transceiver. Transmit/Receive path select. The TRSW select signal controls the direction of the Transmit/Receive switch. Not used in 8225 RF chipset. Not used in 8225 RF chipset. Not used in 8225 RF chipset. Antenna Select. The antenna detects signal change states as the receiver switches from antenna to antenna during the acquisition process in antenna diversity mode. 2.4GHz Transmit Power Amplifier Power Enable. Not used in 8225 RF chipset. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin.
A_PAPEPIN O 157 F4 B_PAPEPIN O 158 C1 WLGPIOPIN[0] I/O 52 T17 WLGPIOPIN[1] I/O 70 M19 WLGPIOPIN[2] I/O 71 K19 WLGPIOPIN[3] I/O 159 F3 WLGPIOPIN[4] I/O 119 A15 WLGPIOPIN[5] I/O 148 A2 WLGPIOPIN[6] I/O 82 D20 RF Interface for Realtek 8255 [802.11 a/b/g RF] VREFO X 113 A19 Not used in 8255 RF chipset. VRP X 112 B17 Not used in 8255 RF chipset. VRN X 111 C15 Not used in 8255 RF chipset. RXIP I 110 D14 Receive (Rx) In-phase Analog Data. RXIN I 109 C14 RXQP I 107 B18 Receive (Rx) Quadrature-phase Analog Data. RXQN 106 C17 R15K I/O 100 D17 This pin must be pulled low by a 15K resistor. RXAGC O 97 D18 Not used in 8255 RF chipset. TXAGC O 96 C18 Not used in 8255 RF chipset. RSSI I 95 D19 Analog Input to the Receive Power A/D Converter for Receive AGC Control. TSSI0 I 94 A20 Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control. TSSI1 I 93 B20 Input to the Transmit Power A/D Converter for 5GHz Transmit AGC Control. TXQP O 90 H18 Transmit (TX) Quadrature-phase Analog Data. TXQN O 89 G18 TXIN O 88 G19 Transmit (TX) In-phase Analog Data. TXIP O 87 H19 XI I 81 H20 40 MHz OSC Input. XIPWRSEL I 104 B19 Operating frequency voltage selection between 3.3v and 1.8v. TXQTP O 86 F19 Not used in 8255 RF chipset. TXQTN O 85 F18 TXITP O 84 J18 Not used in 8255 RF chipset. TXITN O 83 E19 RIFSCKPIN O 61 P17 Serial Clock Output. All operation mode switching and register setting is done by 3-wire serial interface. RIFSDPIN I/O 62 R20 Serial Data Input/Output. RFLEPIN O 63 R18 Serial Enable control. CALENPIN O 68 L20 Not used in 8255 RF chipset.
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CALMODEPIN www..com VCOPDNPIN TRSWPIN TRSWBPIN RFTXENPIN RFRXENPIN LNAHLPIN ANTSELPIN ANTSELBPIN I/O O O O O O O O O 59 74 57 75 129 55 117 147 152 T20 L18 R17 M17 C10 T18 A16 A1 D5 Not used in 8255 RF chipset. This pin is used to turn on/off RF transceiver. Transmit/Receive path select. The TRSW select signal controls the direction of the Transmit/Receive switch. Not used in 8255 RF chipset. Not used in 8255 RF chipset. Not used in 8255 RF chipset. Antenna Select. The antenna detects signal change states as the receiver switches from antenna to antenna during the acquisition process in antenna diversity mode. 2.4GHz Transmit Power Amplifier Power Enable. 5GHz Transmit Power Amplifier Power Enable. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. This is a continuous clock that is recovered from the incoming data. The RX clock is 25MHz in 100Mbps and 2.5Mhz in 10Mbs. This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RX clock by the external physical unit
A_PAPEPIN B_PAPEPIN WLGPIOPIN[0] WLGPIOPIN[1] WLGPIOPIN[2] WLGPIOPIN[3] WLGPIOPIN[4] WLGPIOPIN[5] WLGPIOPIN[6] LAN Interface LRXCPIN LRXDPIN[0] LRXDPIN[1] LRXDPIN[2] LRXDPIN[3] LRXDVPIN
O O I/O I/O I/O I/O I/O I/O I/O I I
157 158 52 70 71 159 119 148 82 13 3 4 49 50 10
F4 C1 T17 M19 K19 F3 A15 A2 D20 W4 W1 U5 V20 U17 Y1
I
LTXCPIN
I
34
Y15
LTXEPIN LTXDPIN[0] LTXDPIN[1] LTXDPIN[2] LTXDPIN[3] LCOLPIN
O O
I
11 31 19 20 21 14
V5 Y13 U6 Y5 Y6 U7
Data valid is asserted by an external PHY when receive data is present on the RXD[3:0] lines, and it is deasserted at the end of the packet. This signal is valid on the rising of the RXC. TXC is a continuous clock that provides a timing reference for the transfer of TXD[3:0], TXE. In MII mode, it uses the 25 MHz or 2.5 MHz supplied by the external PMD device. Indicates the presence of valid nibble data on TXD[3:0]. Four parallel transmit data lines which are driven synchronous to the TXC for transmission by the external physical layer chip.
LMDIOPIN LMDCPIN WAN Interface WRXCPIN WRXDPIN[0] WRXDPIN[1] WRXDPIN[2] WRXDPIN[3] WRXDVPIN
I/O O
15 12
W5 Y2
This signal is asserted high synchronously by the external physical unit upon detection of a collision on the medium. It will remain asserted as long as the collision condition persists. Management Data Input/Output: This pin provides the bi-directional signal used to transfer management information. Management Data Clock: This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks. This is a continuous clock that is recovered from the incoming data. The RX clock is 25MHz in 100Mbps and 2.5Mhz in 10Mbs. This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RX clock by the external physical unit
I I
26 47 23 24 43 25
Y10 V16 W8 Y8 W16 W9
I
WTXCPIN
I
41
U14
Data valid is asserted by an external PHY when receive data is present on the RXD[3:0] lines, and it is deasserted at the end of the packet. This signal is valid on the rising of the RXC. TXC is a continuous clock that provides a timing reference for the transfer of TXD[3:0], TXE. In MII mode, it uses the 25 MHz or 2.5 MHz supplied
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WTXEPIN WTXDPIN[0] WTXDPIN[1] WTXDPIN[2] WTXDPIN[3] WCOLPIN
O O
I
40 17 44 45 46 27
W14 Y4 U15 V15 W20 W10
by the external PMD device. Indicates the presence of valid nibble data on TXD[3:0]. Four parallel transmit data lines which are driven synchronous to the TXC for transmission by the external physical layer chip.
WMDIOPIN WMDCPIN GPIO Group A GPAPIN[0] GPAPIN[1] GPAPIN[2] GPAPIN[3] GPAPIN[4] GPAPIN[5] GPAPIN[6] GPAPIN[7] GPAPIN[8] GPAPIN[9] GPAPIN[10] GPIO Group F GPFPIN[0] GPFPIN[1] GPFPIN[2] GPFPIN[3] GPFPIN[4] GPFPIN[5] PCI Interface PCIADPIN[0] PCIADPIN[1] PCIADPIN[2] PCIADPIN[3] PCIADPIN[4] PCIADPIN[5] PCIADPIN[6] PCIADPIN[7] PCIADPIN[8] PCIADPIN[9] PCIADPIN[10] PCIADPIN[11] PCIADPIN[12] PCIADPIN[13] PCIADPIN[14] PCIADPIN[15] PCIADPIN[16] PCIADPIN[17] PCIADPIN[18] PCIADPIN[19] PCIADPIN[20] PCIADPIN[21] PCIADPIN[22] PCIADPIN[23] PCIADPIN[24]
I/O O
42 30
Y18 W11
This signal is asserted high synchronously by the external physical unit upon detection of a collision on the medium. It will remain asserted as long as the collision condition persists. Management Data Input/Output: This pin provides the bi-directional signal used to transfer management information. Management Data Clock: This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks.
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
77 78 65 66 48 29 33 8 146 116 188 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
G20 F20 N19 P19 V18 Y11 W12 W3 B3 A17 U1 Y3 C12 Y9 W18 A4 C6 J20 J17 U10 V6 V9 Y12 W6 Y7 U9 V10 V8 W17 Y20 Y17 U16 W15 Y19 U8 Y14 M18 U18 U20 W19 K20 V17
This pin also be JTAG_TDI when JTAG function is enabled. This pin also be JTAG_TMS when JTAG function is enabled. This pin also be JTAG_TRSTN when JTAG function is enabled. This pin also be JTAG_TDO when JTAG function is enabled. Reserved for internal use
PCI address and data multiplexed pins. The address phase is the first clock cycle in which FRAMEB is asserted. During the address phase, AD31-0 contains a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, it is a double-word address. Write data is stable and valid when IRDYB is asserted. Read data is stable and valid when TRDYB is asserted. Data I is transferred during those clocks where both IRDYB and TRDYB are asserted.
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PCIADPIN[25] www..com PCIADPIN[26] PCIADPIN[27] PCIADPIN[28] PCIADPIN[29] PCIADPIN[30] PCIADPIN[31] CBEBPIN[0] CBEBPIN[1] CBEBPIN[2] CBEBPIN[3] PCICLKPIN PCIRTSBPIN FRAMEBPIN I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O NA NA NA NA NA NA NA NA NA NA NA NA NA NA E4 D6 E3 H4 H3 N20 P18 P20 R19 M20 L19 A14 E2 D3
IRDYBPIN
I/O
NA
D2
TRDYBPIN
I/O
NA
R4
STOPBPIN DEVSELBPIN PARPIN
I/O I/O I/O
NA NA NA
V1 W7 A13
REQB0PIN GNTB0PIN REQB1PIN GNTB1PIN REQB2PIN GNTB2PIN REQB3PIN
I O I O I O I
NA NA NA NA NA NA NA
V19 K18 V14 B15 V7 A18 G4
PCI bus command and byte enables multiplexed pins. During the address phase of a transaction, C/BE3-0 define the bus command. During the data phase, C/BE3-0 are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE0 applies to byte 0, and C/BE3 applies to byte 3. PCI clock: This clock input provides timing for all PCI transactions and is input to the PCI device. Reset: Active low signal to reset the PCI device. Cycle Frame: As a bus master, this pin indicates the beginning and duration of an access. FRAMEB is asserted low to indicate the start of a bus transaction. While FRAMEB is asserted, data transfer continues. When FRAMEB is deasserted, the transaction is in the final data phase. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. Initiator Ready: This indicates the initiating agent's ability to complete the current data phase of the transaction. As a bus master, this signal will be asserted low when the RTL8186 is ready to complete the current data phase transaction. This signal is used in conjunction with the TRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. As a target, this signal indicates that the master has put data on the bus. Target Ready: This indicates the target agent's ability to complete the current phase of the transaction. As a bus master, this signal indicates that the target is ready for the data during write operations and with the data during read operations. As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. Stop: Indicates that the current target is requesting the master to stop the current transaction. Device Select: As a bus master, the RTL8186 samples this signal to insure that a PCI target recognizes the destination address for the data transfer. Parity: This signal indicates even parity across AD31-0 and C/BE3-0 including the PAR pin. PAR is stable and valid one clock after each address phase. For data phase, PAR is stable and valid one clock after either IRDYB is asserted on a write transaction or TRDYB is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. As a bus master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. Request: Request indicates to the arbiter that this agent desires use of the bus. Grant:Grant indicate to the agent that access to the bus has been granted. Request: Request indicates to the arbiter that this agent desires use of the bus. Grant:Grant indicate to the agent that access to the bus has been granted. Request: Request indicates to the arbiter that this agent desires use of the bus. Grant:Grant indicate to the agent that access to the bus has been granted. Request: Request indicates to the arbiter that this agent desires use of the
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GNTB3PIN INTB0PIN
O I
NA NA
B16 C8
bus. Grant:Grant indicate to the agent that access to the bus has been granted. Interrupt A: Used to request an interrupt. It is asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask. CPU power +3.3V (Digital),
Power & GND DVDD33
-
18 36 51 69 122 137 155 171 185 201 16 35 53 72 121 136 154 168 182 200 1 9 28 60 67 114 118 175 202 5 22 32 56 64 115 170 190 208
DGND33
-
DVDD18
-
DGND18
-
D10 D11 D12 G17 H17 J3 J4 K4 U11 U12 U13 H10 H11 H12 H13 H8 H9 J10 J11 J12 J13 C13 D13 K3 L3 L4 N17 N18 V11 V12 J8 J9 K10 K11 K12 K13 K8 K9 L10 L11 L12 L13 L8 L9 M10 M11 M12 N10 N11 N12 N13 N8 N9
CPU 3.3 GND (Digital)
CPU +1.8V (Digital)
CPU 1.8Ground (Digital)
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VDDA
-
102 103 101 105 108 99 98 92 91
GNDA
-
GNDSUB VDDBG GNDBG VDDPLL GNDPLL
-
M13 M8 M9 E17 E18 F17 C16 D15 D16 C20 C19
Wirless LAN power 3.3V(Analog)
Wirless LAN Ground (Analog)
Wirless LAN Ground (Analog), GA7 VSUB Analog VDD for WLAN Baseband. Analog GND for WLAN Baseband. PLL power(Analog) PLL Ground(Analog)
4. Address Mapping
The RTL8186 supports up to 4 gigabytes of logical address space, mapped to two kinds of memory device (SDRAM and ROM/FLASH). The memory address mapping is managed by MMU, which translates the virtual address to physical address. The memory is segmented into four regions by its access mode and caching capability as shown in following table. Segment Size KUSEG KSEG0 KSEG1 KSEG2 KSEG2 2048M 512M 512M 512M 512M Caching cacheable cacheable uncachable cacheable cacheable Virtual address range 0x0000_0000-0x7fff_ffff 0x8000_0000-0x9fff_ffff 0xa000_0000-0xbfff_ffff 0xc000_0000-0xfeff_ffff 0xff00_0000-0xffff_ffff Physical address range set in TLB 0x0000_0000-0x1fff_ffff 0x0000_0000-0x1fff_ffff set in TLB 0xff00_0000-0xffff_ffff Mode user/kernel kernel kernel kernel kernel
The RTL8186 has two memory mapping modes: direct memory mapping and TLB (Translation Look-aside Buffer) address mapping. When virtual address is located in the regions KSEG0, KSEG1 or higher half of KSEG2 segments, it physical address will be mapped directly from virtual address with an offset. If a virtual address is used in the region of KUSEG or lower half of KSEG2 segment, its physical address will be referred from TLB entry. RTL8186 contains 16 TLB entries, each of which maps to a page, with read/write access, cache-ability and process id. In RTL8186, SDRAM is mapped from physical address 0x0000_0000 to maximum 0x03ff_ffff (64M bytes). After reset, RTL8186 will start to fetch instructions from logical address 0xbfc0_0000, the starting address of first flash memory. The flash memory is mapped from physical address 0x1fc0_0000 to maximum 0x1fff_ffff (4M bytes). If flash size is greater than 4M, the physical address of flash memory more than 4M, will map from 0x1e40_0000 to 0x1eff_ffff.
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Memory Map (without TLB):
Virtual Address Physical Address 0x8000_0000
Cacheable
region
0x0000_0000
0x83ff_ffff 0xa000_0000
SDRAM (64Mbyte) None cacheable region
0x03ff_ffff
0xa3ff_ffff 0xbfc0_0000 0x1fc0_0000
None cacheable region None cacheable region
Flash (4Mbyte)
0xbfff_ffff 0xbe40_0000
0x1fff_ffff
Flash (12Mbyte)
0x1e40_0000
0xbeff_ffff
0x1eff_ffff
The memory map of RTL8186 I/O devices and registers are located in KSEG1 segment (uncacheable region). The following table illustrates the address map: Mapped device Special function registers (note) Memory controller registers IPSec Crypto Engine registers TKIP MIC calculator registers Ethernet0 PCM Ethernet1 WLAN controller IO map address of PCI device Memory map address of PCI device 0, 1 0xBD68_0000 - 0xBD68_FFFF 64K Memory map address of PCI device 2 0xB000_0000 - 0xBCFF_FFFF 208M Memory map address of PCI device 3 0xBD71_0000 - 0xBD71_FFFF 64K Configuration space of PCI device0 0xBD72_0000 - 0xBD72_FFFF 64K Configuration space of PCI device1 0xBD74_0000 - 0xBD74_FFFF 64K Configuration space of PCI device2 0xBD78_0000 - 0xBD78_FFFF 64K Configuration space of PCI device3 NOTE: The special function includes interrupt control, timer, watchdog, UART, and GPIO. Virtual address range 0xBD01_0000 - 0xBD01_0FFF 0xBD01_1000 - 0xBD01_1FFF 0xBD10_0000 - 0xBD17_FFFF 0xBD18_0000 - 0xBD1F_FFFF 0xBD20_0000 - 0xBD27_FFFF 0xBD28_0000 - 0xBD2F_FFFF 0xBD30_0000 - 0xBD3F_FFFF 0xBD40_0000 - 0xBD4F_FFFF 0xBD50_0000 - 0xBD5F_FFFF 0xBD60_0000 - 0xBD60_FFFF Size (bytes) 4K 4K 512K 512K 512K 512K 1M 1M 1M 64K
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5. Register Mapping
The following table displays the address mapping of the all registers: Virtual Address 0xBD01_0000 0xBD01_0004 0xBD01_0040 0xBD01_0044 0xBD01_0048 0xBD01_004C 0xBD01_0050 0xBD01_0054 0xBD01_0058 0xBD01_005C 0xBD01_0060 0xBD01_0064 0xBD01_0068 0xBD01_006C 0xBD01_0070 0xBD01_0074 0xBD01_0078 0xBD01_007C 0xBD01_00C3 0xBD01_00C3 0xBD01_00C3 0xBD01_00C7 0xBD01_00C7 0xBD01_00CB 0xBD01_00CB 0xBD01_00CF 0xBD01_00D3 0xBD01_00D7 0xBD01_00DB 0xBD01_00DF 0xBD01_00E3 0xBD01_00E3 0xBD01_00E3 0xBD01_00E7 0xBD01_00E7 0xBD01_00EB 0xBD01_00EB 0xBD01_00EF 0xBD01_00F3 0xBD01_00F7 0xBD01_00FB 0xBD01_00FF 0xBD01_0100 0xBD01_0104 0xBD01_0108 Register Name Interrupt Controller GIMR Global mask register GISR Global interrupt status register Scratch Registers SR0 Scratch register 0 SR1 Scratch register 1 SR2 Scratch register 2 SR3 Scratch register 3 Timer TCCNT Timer/Counter control register TCIR Timer/Counter interrupt register CBDR Clock division base register WDTCNR Watchdog timer control register TC0DATA Timer/Counter 0 data register TC1DATA Timer/Counter 1 data register TC2DATA Timer/Counter 2 data register TC3DATA Timer/Counter 3 data register TC0CNT Timer/Counter 0 count register TC1CNT Timer/Counter 1 count register TC2CNT Timer/Counter 2 count register TC3CNT Timer/Counter 3 count register UART0 UART0_RBR UART0 receiver buffer register UART0_THR UART0 transmitter holding register UART0_DLL UART0 divisor latch LSB UART0_DLM UART0 divisor latch MSB UART0_IER UART0 interrupt enable register UART0_IIR UART0 interrupt identification register UART0_FCR UART0 FIFO control register UART0_LCR UART0 line control register UART0_MCR UART0 modem control register UART0_LSR UART0 line status register UART0_MSR UART0 modem status register UART0_SCR UART0 scratch register UART1 UART1_RBR UART1 receiver buffer register UART1_THR UART1 transmitter holding register UART1_DLL UART1 divisor latch LSB UART1_DLM UART1 divisor latch MSB UART1_IER UART1 interrupt enable register UART1_IIR UART1 interrupt identification register UART1_FCR UART1 FIFO control register UART1_LCR UART1 line control register UART1_MCR UART1 modem control register UART1_LSR UART1 line status register UART1_MSR UART1 modem status register UART1_SCR UART1 scratch register System Configuration register BDGCR BDG0, BDG1 and PCI bridge configuration register PLLMNR DLL M ,N parameter register SYSCLKR System clock setting register Register Symbol
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0xBD01_0110 www..com TKNR 0xBD01_0114 0xBD01_0118 0xBD01_0120 0xBD01_0124 0xBD01_0128 0xBD01_012C 0xBD01_0130 0xBD01_0134 0xBD01_0138 0xBD01_013C 0xBD01_0140 0xBD01_0144 0xBD01_0148 0xBD01_014C 0xBD01_0150 0xBD01_0154 0xBD01_0158 0xBD01_015C 0xBD01_1000 0xBD01_1004 0xBD01_1008 0xBD01_100C 0xBD01_1010 0xBD01_1014 0xBD01_1018 0xBD10_0000 0xBD10_0004 0xBD10_0008 0xBD10_0009 0xBD10_000A 0xBD10_000B 0xBD10_000C 0xBD18_0000 0xBD18_0004 0xBD18_0008 0xBD18_000C 0xBD18_0010 0xBD18_0014 0xBD18_0018 0xBD20_0000 0xBD20_0008 0xBD20_0010 0xBD20_0012 0xBD20_0014 0xBD20_0016 0xBD20_0018 0xBD20_001A 0xBD20_001C Master token setting register Bridge master weight setting register PCI master weight setting register GPIO A/B GPABDATA Port A/B data register GPABDIR Port A/B direction register GPABIMR Port A/B interrupt mask register GPABISR Port A/B interrupt register GPIO C/D GPCDDATA Port C/D data register GPCDDIR Port C/D direction register GPCDIMR Port C/D interrupt mask register GPCDISR Port C/D interrupt register GPIO E/F GPEFDATA Port E/F data register GPEFDIR Port E/F direction register GPEFIMR Port E/F interrupt mask register GPEFISR Port E/F interrupt register GPIO G GPGDATA Port G data register GPGDIR Port G direction register GPGIMR Port G interrupt mask register GPGISR Port G interrupt register Memory controller MCR Memory configuration register MTCR0 Memory timing configuration register 0 MTCR1 Memory timing configuration register 1 NCR NAND flash Control Register NCAR NAND flash Command Register NADDR NAND flash Address Register NDR NAND flash Data Register IPSec Crypto Engine IPSSDAR IPSec Source Descriptor Starting Address Register IPSDDAR IPSec Destination Descriptor Starting Address Register IPSCFR IPSec Configuration Register IPSCR IPSec Command Register IPSIMR IPSec Interrupt Mast Register IPSISR IPSec Interrupt Status Register IPSCTR IPSec Control Register TKIP MIC Calculator MICLVAL MIC L value Register MICRVAL MIC R value Register MICSAR MIC Start Address Register MICLENR MIC Length Register MICDMAR MIC DMA Length Register MICCR MIC Control Register MICPSNR MIC Pseudo Random Number Register Ethernet0 ETH0_IDR Ethernet0 ID register ETH0_MAR Ethernet0 Multicast Register ETH0_TXOKCNT Ethernet0 Transmit OK Counter Register ETH0_RXOKCNT Ethernet0 Receive OK Counter Register ETH0_TXERR Ethernet0 Transmit Error Counter Register ETH0_RXERR Ethernet0 Receive Error Counter Register ETH0_MISSPKT Ethernet0 Missed Packet Counter Register ETH0_FAE Ethernet0 Frame Alignment Error Counter Register ETH0_TX1COL Ethernet0 Transmit 1st Collision Counter Register BDGWTR PCIWTR
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0xBD20_001E www..com ETH0_TXMCOL 0xBD20_0020 0xBD20_0022 0xBD20_0024 0xBD20_0026 0xBD20_0028 0xBD20_0034 0xBD20_003B 0xBD20_003C 0xBD20_003E 0xBD20_0040 0xBD20_0044 0xBD20_0058 0xBD20_005C 0xBD20_1300 0xBD20_1304 0xBD20_1380 0xBD20_1384 0xBD20_13F0 0xBD20_13F4 0xBD20_13F6 0xBD20_1430 0xBD20_1432 0xBD20_1434 0xBD28_0000 0xBD28_0004 0xBD28_0008 0xBD28_000C 0xBD28_0010 0xBD28_0014 0xBD28_0018 0xBD28_001C 0xBD28_0020 0xBD28_0024 0xBD28_0028 0xBD28_002C 0xBD28_0030 0xBD28_0034 0xBD30_0000 0xBD30_0008 0xBD30_0010 0xBD30_0012 0xBD30_0014 0xBD30_0016 0xBD30_0018 0xBD30_001A 0xBD30_001C 0xBD30_001E 0xBD30_0020 0xBD30_0022 0xBD30_0024 0xBD30_0026 0xBD30_0028 0xBD30_0034 0xBD30_003B Ethernet0 Transmit Multi-Collision Counter Register ETH0_RXOKPHY Ethernet0 RX Physical Address Matched Register ETH0_RXOKBRD Ethernet0 RX OK of Broadcast Matched Register ETH0_RXOKMUL Ethernet0 RX OK of Multicast Matched Register ETH0_TXABT Ethernet0 TX Abort Counter Register ETH0_TXUNDRN Ethernet0 TX under-run Counter Register ETH0_TRSR Ethernet0 Transmit/Receive Status Register ETH0_CR Ethernet0 Command Register ETH0_IMR Ethernet0 Interrupt Mask Register ETH0_ISR Ethernet0 Interrupt Status Register ETH0_TCR Ethernet0 Transmit Configuration Register ETH0_RCR Ethernet0 Receive Configuration Register ETH0_MSR Ethernet0 Media Status Register ETH0_MIIAR Ethernet0 MII Access Register ETH0_TXFDP1 Ethernet0 TX First Descriptor 1 Register ETH0_TXCDO1 Ethernet0 TX Current Descriptor Offset 1 Register ETH0_TXFDP2 Ethernet0 TX First Descriptor 2 Register ETH0_TXCDO2 Ethernet0 TX Current Descriptor Offset 2 Register ETH0_RXFDP Ethernet0 RX First Descriptor Register ETH0_RXCDO Ethernet0 RX Current Descriptor Offset Register ETH0_RXRINGSIZE Ethernet0 RX Descriptor Ring Size Register ETH0_RXCPUDESC Ethernet0 RX CPU's Descriptor Number Register ETH0_RXPSEDESC Ethernet0 RX Descriptor Number difference Register ETH0_IOCMD Ethernet0 I/O Command Register PCM Controller PCMCR PCM interface Control Register PCMCHCNR PCM Channel specific Control Register PCMTSR PCM Time Slot Assignment Register PCMBSIZE PCM Channels Buffer Size register CH0TXBSA PCM Channel 0 TX buffer starting address pointer CH1TXBSA PCM Channel 1 TX buffer starting address pointer CH2TXBSA PCM Channel 2 TX buffer starting address pointer CH3TXBSA PCM Channel 3 TX buffer starting address pointer CH0RXBSA PCM Channel 0 RX buffer starting address pointer CH1RXBSA PCM Channel 1 RX buffer starting address pointer CH2RXBSA PCM Channel 2 RX buffer starting address pointer CH3RXBSA PCM Channel 3 RX buffer starting address pointer PCMIMR PCM channels Interrupt Mask Register PCMISR PCM channels Interrupt Status Register Ethernet1 ETH1_IDR Ethernet1 ID register ETH1_MAR Ethernet1 Multicast Register ETH1_TXOKCNT Ethernet1 Transmit OK Counter Register ETH1_RXOKCNT Ethernet1 Receive OK Counter Register ETH1_TXERR Ethernet1 Transmit Error Counter Register ETH1_RXERR Ethernet1 Receive Error Counter Register ETH1_MISSPKT Ethernet1 Missed Packet Counter Register ETH1_FAE Ethernet1 Frame Alignment Error Counter Register ETH1_TX1COL Ethernet1 Transmit 1st Collision Counter Register ETH1_TXMCOL Ethernet1 Transmit Multi-Collision Counter Register ETH1_RXOKPHY Ethernet1 RX Physical Address Matched Register ETH1_RXOKBRD Ethernet1 RX OK of Broadcast Matched Register ETH1_RXOKMUL Ethernet1 RX OK of Multicast Matched Register ETH1_TXABT Ethernet1 TX Abort Counter Register ETH1_TXUNDRN Ethernet1 TX Underrun Counter Register ETH1_TRSR Ethernet1 Transmit/Receive Status Register ETH1_CR Ethernet1 Command Register
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0xBD30_003C www..com ETH1_IMR 0xBD30_003E 0xBD30_0040 0xBD30_0044 0xBD30_0058 0xBD30_005C 0xBD30_1300 0xBD30_1304 0xBD30_1380 0xBD30_1384 0xBD30_13F0 0xBD30_13F4 0xBD30_13F6 0xBD30_1430 0xBD30_1432 0xBD30_1434 0xBD40_0000 0xBD40_0008 0xBD40_0018 0xBD40_0020 0xBD40_0024 0xBD40_0028 0xBD40_002C 0xBD40_002E 0xBD40_0034 0xBD40_0035 0xBD40_0037 0xBD40_003C 0xBD40_003E 0xBD40_0040 0xBD40_0044 0xBD40_0048 0xBD40_004C 0xBD40_0050 0xBD40_0051 0xBD40_0052 0xBD40_0053 0xBD40_0054 0xBD40_0058 0xBD40_0059 0xBD40_005A 0xBD40_005B 0xBD40_0070 0xBD40_0072 0xBD40_0074 0xBD40_0076 0xBD40_007C 0xBD40_007D 0xBD40_007E 0xBD40_0080 0xBD40_0082 0xBD40_0084 0xBD40_0086 0xBD40_0088 0xBD40_008C Ethernet1 Interrupt Mask Register ETH1_ISR Ethernet1 Interrupt Status Register ETH1_TCR Ethernet1 Transmit Configuration Register ETH1_RCR Ethernet1 Receive Configuration Register ETH1_MSR Ethernet1 Media Status Register ETH1_MIIAR Ethernet1 MII Access Register ETH1_TXFDP1 Ethernet1 TX First Descriptor 1 Register ETH1_TXCDO1 Ethernet1 TX Current Descriptor Offset 1 Register ETH1_TXFDP2 Ethernet1 TX First Descriptor 2 Register ETH1_TXCDO2 Ethernet1 TX Current Descriptor Offset 2 Register ETH1_RXFDP Ethernet1 RX First Descriptor Register ETH1_RXCDO Ethernet1 RX Current Descriptor Offset Register ETH1_RXRINGSIZE Ethernet1 RX Descriptor Ring Size Register ETH1_RXCPUDESC Ethernet1 RX CPU's Descriptor Number Register ETH1_RXPSEDESC Ethernet1 RX Descriptor Number difference Register ETH1_IOCMD Ethernet1 I/O Command Register WLAN controller WLAN_ID WLAN ID WLAN_MAR WLAN multicast register WLAN_TSFTR WLAN timing synchronization function timer register WLAN_TLPDA WLAN transmit low priority descriptors start address WLAN_TNPDA WLAN transmit normal priority descriptors start address WLAN_THPDA WLAN transmit high priority descriptors start address WLAN_BRSR WLAN basic rate set register WLAN_BSSID WLAN basic service set ID WLAN_RR WLAN response rate WLAN_EIFS WLAN EIFS register WLAN_CR WLAN command register WLAN_IMR WLAN interrupt mask register WLAN_ISR WLAN interrupt status register WLAN_TCR WLAN transmit configuration register WLAN_RCR WLAN receive configuration register WLAN_TINT WLAN timer interrupt register WLAN_TBDA WLAN transmit beacon descriptor start address WLAN_CR WLAN command register WLAN_CONFIG0 WLAN configuration register 0 WLAN_CONFIG1 WLAN configuration register 1 WLAN_CONFIG2 WLAN configuration register 2 WLAN_ANAPARM WLAN analog parameter WLAN_MSR WLAN media status register WLAN_CONFIG3 WLAN configuration register 3 WLAN_CONFIG4 WLAN configuration register 4 WLAN_TESTR WLAN test mode register WLAN_BCNITV WLAN beacon interval register WLAN_ATIMWND WLAN ATIM window register WLAN_BINTRITV WLAN beacon interrupt interval register WLAN_ATIMTRITV WLAN ATIM interrupt interval register WLAN_PHYADDR WLAN PHY address register WLAN_PHYDATAW WLAN write data to PHY WLAN_PHYDATAR WLAN read data from PHY WLAN_RFPINOUT WLAN RF Pins output register WLAN_RFPINEN WLAN RF Pins enable register WLAN_RFPINSEL WLAN RF Pins select register WLAN_RFPININPU WLAN RF Pins input register T WLAN_RFPARA WLAN RF parameter register WLAN_RFTIMING WLAN RF timing register
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0xBD40_009C www..com WLAN_TXAGC 0xBD40_009D 0xBD40_009E 0xBD40_009F 0xBD40_00A0 0xBD40_00A4 0xBD40_00A8 0xBD40_00AC 0xBD40_00B0 0xBD40_00B2 0xBD40_00B4 0xBD40_00B5 0xBD40_00B6 0xBD40_00B7 0xBD40_00BC 0xBD40_00BD 0xBD40_00BE 0xBD40_00D8 0xBD40_00D9 0xBD40_00DC 0xBD40_00DE 0xBD40_00E4 0xBD40_0100 0xBD40_0104 0xBD40_0100 0xBD40_0104 0xBD40_0108 0xBD40_010C 0xBD40_0110 0xBD40_0114 0xBD40_0118 0xBD40_011C 0xBD40_0120 0xBD40_0124 0xBD40_0128 0xBD40_012C 0xBD40_0130 0xBD40_0134 0xBD40_0138 0xBD40_013C 0xBD40_0140 0xBD40_0144 0xBD40_0148 0xBD40_014C 0xBD40_0150 0xBD40_0154 0xBD40_0158 0xBD40_015C WLAN auto TX AGC control WLAN_CCKTXAGC WLAN auto TX AGC control for CCK WLAN_OFDMTXA WLAN auto TX AGC control for OFDM GC WLAN_ANTSEL WLAN TX Antenna select WLAN_CAMRW WLAN CAM (Content Access Memory) read/write register WLAN_CAMOUTP WLAN data written to CAM UT WLAN_CAMINPUT WLAN data read from DMA WLAN_CAMDEBU WLAN CAM debug interface G WLAN_WPACONFI WLAN WPA (WiFi Protected Access) configuration G register WLAN_AESMASK WLAN AES (Advanced Encryption Standard) mask register WLAN_SIFS WLAN SIFS setting register WLAN_DIFS WLAN DIFS setting register WLAN_SLOTTIME WLAN slot setting register WLAN_USTUNE WLAN micro-second fine tune register WLAN_CWCONFIG WLAN contention window config register WLAN_CWVALUE WLAN contention window value register WLAN_RATECTRL WLAN auto rate fallback control register WLAN_CONFIG5 WLAN configuration register 5 WLAN_TPPOLL WLAN transmit priority polling register WLAN_CWR WLAN contention window register WLAN_RETRYCTR WLAN retry count register WLAN_RDSAR WLAN receive descriptor start address register WLAN_DFSCR WLAN DFS control register WLAN_ DFSSLR WLAN DFS Schmitt trigger low-threshold setting register WLAN_DFSCR WLAN DFS control register WLAN_DFSCR WLAN DFS control register WLAN_DFSSHR WLAN DFS Schmitt trigger high-threshold setting register WLAN_DFSDLR WLAN DFS Pulse-duration low-threshold setting register WLAN_ DFSDHR DFS Pulse-duration high-threshold setting register WLAN_ DFSPCR WLAN DFS valid pulse count register WLAN_ DFSTS0R WLAN DFS Time Stamp 0 register WLAN_ DFSTS1R WLAN DFS Time Stamp 1 register WLAN_ DFSTS2R WLAN DFS Time Stamp 2 register WLAN_ DFSTS3R WLAN DFS Time Stamp 3 register WLAN_ DFSTS4R WLAN DFS Time Stamp 4 register WLAN_ DFSTS5R WLAN DFS Time Stamp 5 register WLAN_ DFSTS6R WLAN DFS Time Stamp 6 register WLAN_ DFSTS7R WLAN DFS Time Stamp 7 register WLAN_ DFSTS8R WLAN DFS Time Stamp 8 register WLAN_ DFSTS9R WLAN DFS Time Stamp 9 register WLAN_ DFSTSAR WLAN DFS Time Stamp A register WLAN_ DFSTSBR WLAN DFS Time Stamp B register WLAN_ DFSTSCR WLAN DFS Time Stamp C register WLAN_ DFSTSDR WLAN DFS Time Stamp D register WLAN_ DFSTSER WLAN DFS Time Stamp E register WLAN_ DFSTSFR WLAN DFS Time Stamp F register WLAN_ DFSTSGR WLAN DFS Time Stamp G register WLAN_ DFSTSHR WLAN DFS Time Stamp H register
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0xBD40_0160 www..com WLAN_ DFSTSIR 0xBD40_0164 0xBD40_0168 WLAN_ DFSTSJR WLAN_ DFSCTSR WLAN DFS Time Stamp I register WLAN DFS Time Stamp J register WLAN DFS Current Time Stamp register
6. System Configuration
In RTL8186, several system parameters are loaded from hardware settings rather than software configuration. The signal group ICFG controls the default setting for memory width and system clock. The values of ICFG signals are strapped from GPIO pins. The mapping relationship is illustrated as following table: ICFG Bit field 0 1 2 3 4 Strapping Pin Name RFLEPIN CALENPIN CALMODEPIN VCOPDNPIN GPAPIN[4] Default State N/A N/A N/A N/A N/A Function Description CPU clock rate select. ICFG[3:0]. See the table below for detailed CPU and SDRAM clock setting combination.
5 6
GPAPIN[5] GPAPIN[9]
1 0
7 8
WTXDPIN[0] WTXDPIN[1]
0 0
9
WTXDPIN[2]
0
10
WTXDPIN[3]
0
11
SOUT0PIN
0
12
MAPIN[19]
N/A
13
MAPIN[20]
N/A
14
MAPIN[21]
N/A
15
TRSWPIN
0
16
TRSWBPIN
1
17
ANTSELPIN
0
SDRAM clock synchronous/asynchronous select. 1: Synchronous (identical to system bus clock) 0: Asynchronous NOR-type flash data bus width select ICFG[6:5] = 00: 8-bit data bus 01: 16-bit data bus 10: 32-bit data bus 11: Reserved SDRAM clock delay parameter ICFG[8:7] = 00: No delay 01: Delay 1 unit 10: Delay 2 units 11: Delay 3 units Boot device select ICFG[9] = 0: Boot from NOR-type flash 1: Boot from NAND-type flash Function switch of PCM and WAN in 208 QFP package ICFG[10] = 0: Select WAN function at WAN pin-out in 208 QFP package 1: Select PCM function at WAN pin-out in 208 QFP package Function switch of I2C and UART0 in 208 QFP package ICFG[11] = 0: Select UART0 function at UART0 pin-out in 208 QFP package 1: Select I2C function at UART0 pin-out in 208 QFP package Function switch of GPIOB and UART0 ICFG[12] = 0: Select UART0 function at UART0 pin-out 1: Select GPIO B function at UART0 pin-out Function switch of GPIO C and Memory data upper 16 pins ICFG[13] = 0: Select Memory Data function at memory data pin-out 1: Select GPIO C function at memory data pin-out Function switch of GPIO D and WAN function at WAN pin-out. Notice that the WAN also has function switch with PCM, the GPIO D function is selected at WAN pin-out only when PCM function is not selected. ICFG[14] = 0: Select WAN function or PCM function at WAN pin-out 1: Select GPIO D function at WAN pin-out Function switch of GPIO E and NAND flash control pin-out ICFG[15] = 0: Select NAND flash control function at NAND flash pin-out 1: Select GPIO E function at NAND flash pin-out Function switch of GPIO F and PCI AD bus pin-out ICFG[16] = 0: Select GPIO F function at PCI AD bus pin-out 1: Select PCI AD function at PCI AD bus pin-out JTAG function enable ICFG[17] = 0: JTAG function disabled
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18
ANTSELBPIN
1
19
LTXDPIN[0]
N/A
20
LTXDPIN[1]
N/A
21
LTXDPIN[2]
N/A
22
LTXDPIN[3]
N/A
1: JTAG function enabled System bus grant control by external pin ICFG[18] = 0: Enable external control of system bus grant 1: Disable external control system bus grant External clock enable. Notice than this bit is effective only when ICFG[3:0] = 0001. ICFG[19] = 0: System clock comes from internal PLL 1: System clock comes from external pin input. CPU Scan test enable ICFG[20] = 0: Disable Scan test of CPU 1: Enable Scan test of CPU CP test enable ICFG[21] = 0: Disable CP test 1: Enable CP test Lexra mode CP test enable ICFG[22] = 0: Disable Lexra mode CP test 1: Enable Lexra mode CP test
The operation rate of CPU/System Bus and SDRAM is determined by the signal ICFG[3-0] as follows. ICFG[3-0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU/System Bus clock rate SDRAM clock rate (unit: MHz) (unit: MHz) 200.0 133.3 200.0 133.3 200.0 100.0 200.0 160.0 200.0 125.0 220.0 146.7 213.3 142.2 213.3 106.7 192.0 128.0 192.0 115.2 190.0 95.0 180.0 120.0 180.0 90.0 100.0 100.0 100.0 50.0 66.7 33.3
Please note, the CPU clock will be synchronous to system bus clock. Besides the signal group, there is a set of registers provided for software to control the internal bridge or clock module. Also there is another set of registers to control the Lexra bus arbitration. The RTL8186 has three bridges attached to system bus, thus it will have four master devices including CPU, and which needs an arbiter for bus access arbitration. The system arbiter provides a dynamic adjustable priority. Through setting of ARB_PRIREG register, the weight of bus master device can be changed in software according to the need of different applications. The three bridges contains 9 bus masters devices, each of them are: Bridge name BDG0 BDG1 PCI Bridge Attached Bus Master Devices IPSec engine, TKIP-MIC engine, Ethernet0 Ethernet1, WLAN controller PCI device 0,1,2,3
The bus clocks under each bridge also can be configurable through register BDGCR. Note that the clock divider at BDGCR cannot be odd number or zero. Arbitration of each bus masters under certain bridge can be configured through corresponding bridge priority setting register. For example, setting BDG0_PRIREG can prioritize the three bus masters of bridge0. Please note, the priority weight of any
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bus master cannot be www..com zero; otherwise the master will never gain the bus grant. These system-configuration related registers are defined as follow:
Register Summary
Virtual address Size (byte) Name 0xBD01_0100 4 BDGCR 0xBD01_0104 0xBD01_0108 0xBD01_0110 0xBD01_0114 0xBD01_0118 4 4 4 4 4 PLLMNR SYSCLKR TKNR BDGWTR PCIWTR Description BDG0, BDG1 and PCI bridge configuration register RTL8186 DPLL M, N parameter register RTL8186 System clock setting register RTL8186 master token setting register RTL8186 bridge weight setting register RTL8186 PCI bridge weight setting register
0xBD01_0100 Bridge Configuration Register (BDGCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) PDIV B1DIV B0DIV Reset: 0x0000_0511. Bit Bit Name 11-8 PDIV Description Bus clock to PCI Bridge clock ratio. 0001= 2:1, 0011= 4:1, 0101= 6:1, 0111= 8:1, Other values are reserved. Bus clock to Bridge1 clock ratio. 0001= 2:1, 0011= 4:1, 0101= 6:1, 0111= 8:1, Other values are reserved. Bus clock to Bridge0 clock ratio. 0001= 2:1, 0011= 4:1, 0101= 6:1, 0111= 8:1, Other values are reserved. R/W R/W InitVal 0101
7-4
B1DIV
R/W
0001
3-0
B0DIV
R/W
0001
0xBD01_0104 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 (Reserved) A R B W S Reset: 0x0003_1703 Bit Bit Name Description 17-16 ARBWS Arbiter Wait Parameter Setting. 14 MNEN MDIV and NDIV write enable, 0: disable, 1: enable. 13-8 MDIV DPLL M parameter 4-0 NDIV DPLL N parameter
15 R S V D
DPLL M,N parameter Register (PLLMNR) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M MDIV R NDIV N S E V N D
R/W R/W R/W
InitVal 11 0
R/W R/W
010111 00011
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Note: The equation www..comof DPLL clock rate is: 40MHz*(M+1)/(N+1) 0xBD01_0108 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 C P C P I U I E O N S Reset: 0x00 Bit Bit Name Description 23-22 PCIIOS PCI IO map control register. 00 - use PCI IO map for 16 bits 11 - use PCI IO map for 32 bits 15 CPUEN Write enable control for CPU setting register. 11-8 CPUS CPU setting register 7 MEMEN Write enable control for memory setting register 3-0 MEMS Memory setting register System Clock Setting Register (SYSCLKR) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPUS M MEMS R R S E S V V M D D E N
R/W R/W
InitVal 00
R/W R/W R/W R/W
0 0000 0 0000
The relation among CPUS/MEMS value, CPU/System-bus clock, SDRAM timing and signal ICFG[3-0] are defined as follows. ICFG[3-0] CPUS MEMS CPU/System Bus clock SDRAM clock rate rate (unit: MHz) (unit: MHz) 0000 2 4 200.0 133.3 0001 2 4 200.0 133.3 0010 2 5 200.0 100.0 0011 2 5 200.0 160.0 0100 3 5 200.0 125.0 0101 2 4 220.0 146.7 0110 2 4 213.3 142.2 0111 2 5 213.3 106.7 1000 2 4 192.0 128.0 1001 1 3 192.0 115.2 1010 2 5 190.0 95.0 1011 2 4 180.0 120.0 1100 1 4 180.0 90.0 1101 5 5 100.0 100.0 1110 4 6 100.0 50.0 1111 4 6 66.7 33.3
0xBD01_0110 Master Token Register (TKNR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPUTKN BDG0TKN BDG1TKN PCIBTKN Reset: 0x0F01_0101 Bit Bit Name 31-24 CPUTKN 23-16 BDG0TKN 15-8 BDG1TKN 7-0 PCIBTKN Description CPU Token setting BDG0 Token setting BDG1 Token setting PCI Bridge Token setting R/W R/W R/W R/W R/W InitVal 00001111 00000001 00000001 00000001
0xBD01_0114 Bridge Weight Setting Register (BDGWTR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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B1R3 www..com B1R2 B1R1 B1R0 B0R3 B0R2 B0R1 B0R0
Reset: 0x1111_1111 Bit Bit Name 31-28 B1R3 27-24 B1R2 23-20 B1R1 19-16 B1R0 15-12 B0R3 11-8 B0R2 7-4 B0R1 3-0 B0R0
Description BDG1 Master 3 request weight setting BDG1 Master 2 request weight setting BDG1 Master 1 request weight setting BDG1 Master 0 request weight setting BDG0 Master 3 request weight setting BDG0 Master 2 request weight setting BDG0 Master 1 request weight setting BDG0 Master 0 request weight setting
R/W R/W R/W R/W R/W R/W R/W R/W R/W
InitVal 0001 0001 0001 0001 0001 0001 0001 0001
0xBD01_0118 PCI Master Weight Setting Register (PCIWTR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) PBR3 PBR2 PBR1 PBR0
Reset: 0x0000_2222 Bit Bit Name 15-12 PBR3 11-8 PBR2 7-4 PBR1 3-0 PBR0
Description PCI Bridge Master 3 request weight setting PCI Bridge Master 2 request weight setting PCI Bridge Master 1 request weight setting PCI Bridge Master 0 request weight setting
R/W R/W R/W R/W R/W
InitVal 0001 0001 0001 0001
7. Interrupt Controller
The RTL8186 provides six internal hardware-interrupt inputs (IRQ0-IRQ5). Some devices share the same IRQ signal. The following table displays the IRQ map used by devices. IRQ Number 0 1 2 3 4 5 Interrupt Source Timer/Counter interrupt. GPIO/LBC interrupt. WLAN interrupt. UART/PCI interrupt. Ethernet0 interrupt. Ethernet1/MIC/IPSEC interrupt.
When any one of above IRQ is happened, RTL8186 will assert the corresponding bit in CPU coprocessor cause and status register. Besides, it has two additional registers for the interrupt control. The GIMR register can enable/disable the peripheral interrupt source. The GISR shows the pending peripheral interrupt status.
Register Summary
Virtual address Size (byte) Name 0xBD01_0000 2 GIMR 0xBD01_0004 2 GISR Description Global interrupt mask register Global interrupt status register
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0xBD01_0000 31
Global Interrupt Mask Register (GIMR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) M I L P P E EUWGT I PBCCTTALPC C SCMI HHRA I I I I I I I 1 0TNOE EEEEEI I I I I EEEEE Description MIC calculator interrupt enable. 0: Disable, 1: Enable IPSec engine interrupt enable. 0: Disable, 1: Enable LBC time-out interrupt enable. 0: Disable, 1: Enable PCM interrupt enable. 0: Disable, 1: Enable PCI interrupt enable. 0: Disable, 1: Enable Ethernet1 interrupt enable. 0: Disable, 1: Enable Ethernet0 interrupt enable. 0: Disable, 1: Enable UART interrupt enable. 0: Disable 1: Enable WLAN controller interrupt enable. 0: Disable, 1: Enable GPIO interrupt enable. 0: Disable, 1: Enable Timers/Counters interrupt enable. 0: Disable, 1: Enable R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W InitVal 0 0 0 0 0 0 0 0 0 0 0
Reset: 0x0000_0000 Bit Bit Name 10 MICIE 9 8 7 6 5 4 3 2 1 0 IPSIE LBC1E PCMIE PCIIE ETH1IE ETH0IE UARTIE WLANIE GPIOIE TCIE
0xBD01_0004 31
Global Interrupt Status Register (GISR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) M I L P P E EUWGT I PBCCTTALPC C SCMI HHRA I I I I I I I 1 0TNOP PPPPPIIIII PPPPP Description MIC calculator interrupt pending flag. 0: no pending, 1: pending IPSec engine interrupt pending flag. 0: no pending, 1: pending LBC time-out interrupt pending flag. 0: no pending, 1: pending PCM interrupt pending flag. 0: no pending, 1: pending PCI interrupt pending flag. 0: no pending, 1: pending Ethernet1 interrupt pending flag. 0: no pending, 1: pending Ethernet0 interrupt pending flag. R/W R R R R R R R InitVal 0 0 0 0 0 0 0
Reset: 0x0000_0000 Bit Bit Name 10 MICIP 9 8 7 6 5 4 IPSIP LBCIP PCMIP PCIIP ETH1IP ETH0IP
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3 2 1 0
UARTIP WLANIP GPIOIP TCIP
0: no pending, 1: pending UARTI interrupt pending flag. 0: no pending, 1: pending WLAN controller interrupt pending flag. 0: no pending, 1: pending GPIO interrupt pending flag. 0: no pending, 1: pending Timers/Counters interrupt pending flag. 0: no pending, 1: pending
R R R R
0 0 0 0
8. Memory Controller
RTL8186 integrates a memory control module to access external SDRAM and flash memory. The interface is designed to PC100 or PC133-compliant SDRAM, supports auto-refresh mode, which requires 4096 refresh cycle within 64 ms. The SDRAM interface supports two chips (CS0#, and CS1#), and the SDRAM size and timing is configurable in registers. The data width of SDRAM could be chosen as 16-bit or 32-bit in register as well. If 32-bit is configured, 2 16-bit SDRAM chips may be used to expand the data bus width to 32 bits or use one 32-bit SDRAM chip is allowable. Besides, RTL8186 could also supports two flash memory chips (F_CS0# and F_CS1#). The interface could support only 16-bit NOR-type flash memory. Another flash memory type, NAND flash, is also support by this interface. The system can be configured to boot from NOR type flash or NAND. When NOR type is used, the system will boot from KSEG1 at virtual address 0xBFC0_0000 (physical address: 0x1FC0_0000). Chip1 flash memory will be mapped to the address "0x1FC0_000 + flash size". The flash size is configurable from 1M to 8M bytes for each chip. If flash size set to 4M or 8M the 0xBFC0_0000 still map the first 4M bytes of flash. There will have a new memory mapping from 0xBE00_0000. The 0xBE00_0000 mapped to the chip0 byte 0. If NAND type flash is selected in signal group ICFG[9], the memory controller will move first block of NAND flash (16K byte long) to SDRAM at virtual address 0x8000_00000, and then it will run the system software from there. The first 3 rd and 4th bytes of the image will be referred for SDRAM configuration setting, please refer the paragraph `NAND flash layout' below for detail.
Register Summary
Virtual address Size (byte) Name Description 0xBD01_1000 4 MCR Memory Configuration Register 0xBD01_1004 4 MTCR0 Memory Timing Configuration Register 0 0xBD01_1008 4 MTCR1 Memory Timing Configuration Register 1 0xBD01_100C 4 NCR NAND Flash Control Register 0xBD01_1010 4 NCAR NAND Flash Command Register 0xBD01_1014 4 NADDR NAND Flash Address Register 0xBD01_1018 4 NDR NAND Flash Data Register Note: These registers should be accessed in double word.
0xBD01_1000 31 30 29 28 F S L D S R S I Z I E Z E
Memory Configuration Register (MCR) 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C R SM B (Reserved) A S DC U S V BK S L D U2 C SL L K WC IK D
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Reset: 0xB290_0000 www..com Bit 31-30 Bit Name FLSIZE Description Flash size respective to one bank (byte). 00: 1M 01: 2M 10: 4M 11: 8M SDRAM size respective to one bank (bit). 00: 512Kx16x2 01: 1Mx16x4 10: 2Mx16x4 11: Reserved CAS Latency 0: Latency=2 1: Latency=3 Reserved SDRAM bus width 0: 16 bit 1: 32 bit Memory clock to Lexra bus clock ratio. Cooperates with ICFG[3-0] for initialization ICFG[3-0]=1111 CPU=200 MEM=100 ICFG[3-0]=1110 CPU=100 MEM=100 ICFG[3-0]=0101 CPU=166 MEM=133 18-16 BUSCLK Bus Clock to control auto-refresh timing 000: 200 MHz 001: 100 MHz 010: 50 MHz 011: 25 MHz 100: 12.5 MHz 101: 6.25 MHz 110: 3.125 MHz 111: 1.5625 MHz Must be set to bit value 00. R/W 000 R/W R/W InitVal 11
29-28
SDRSIZE
R/W
01
27
CASL
R/W
0
26-21 20
RSVD SDBUSWID
R R/W
0 1
19
MCK2LCK
R
15-0
Reserved
R/W
00
0xBD01_1004 Memory Timing Configuration Register 0 (MTCR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE0T_CS CE0T_WP CE1T_CS CE1T_WP EXCS0T_CS EXCS0T_WP (Reserved)
Reset: 0xFFFF_FF00 Bit Bit Name 31-28 CE0T_CS
27-24
CE0T_WP
23-20
CE1T_CS
19-16
CE1T_WP
Description The timing interval between F_CE0# to WR# Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) The timing interval for WR# to be pulled-low Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) The timing interval between F_CE1# to WR# Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) The timing interval for WR# to be pulled-low Basic unit, 2*clock cycle
R/W R/W
InitVal 1111
R/W
1111
R/W
1111
R/W
1111
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"0000" means 1 unit (2 clock cycles) The timing interval between EXT_CE0# to WR# Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) 11-8 EXCS0T_WP The timing interval for WR# to be pulled-low Basic unit, 2*clock cycle "0000" means 1 unit (2 clock cycles) Note: The clock cycle is based on memory clock. 15-12 EXCS0T_CS
R/W
1111
R/W
1111
0xBD01_1008 Memory Timing Configuration Register 1 (MTCR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) CE23T_RP CE23T_RAS CE23T_RFC (T_RCD)
Reset: 0x0000_1FFF Bit Bit Name 12-10 CE23T_RP (T_RCD)
Description T_RP and T_RCD timing parameter Basic unit, 1*clock cycle "000" means 1 unit (1 clock cycle) Only "001" and "010" are valid for correct operation. 9-5 CE23T_RAS T_RAS timing parameter Basic unit, 1*clock cycle "0000" means 1 unit (1 clock cycle) 4-0 CE23T_RFC T_RFC timing parameter for refresh interval Basic unit, 1*clock cycle "0000" means 1 unit (1 clock cycle) Note: The clock cycle is based on memory clock.
R/W R/W
InitVal 111
R/W
11111
R/W
11111
0xBD01_100C NAND Flash Control Register (NCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N R R W (Reserved) CE_TWP CE_TWB CE_TRR CE_TREA CE_TH CE_TS FSBB RVSS BD Reset: 0xB0FF_FFFF Bit Bit Name 31 NFRB
30 29
RSVD RBS
28
WBS
23-20 19-16 15-12 11-8 7-4 3-0
CE_TWP CE_TWB CE_TRR CE_TREA CE_TH CE_TS
Description Nand flash Ready/Busy status indication bit 0: Busy 1: Ready Reserved Read Byte Swapping. 0: The byte order of NDR register read is {0, 1, 2, 3} 1: The byte order of NDR register read is {3, 2, 1, 0} Write Byte Swapping. 0: The byte order of NDR register write is {0, 1, 2, 3} 1: The byte order of NDR register write is {3, 2, 1, 0} Write pulse width. Base unit: 1 * clock cycle WE high to busy. Base unit: 1 * clock cycle Ready to RE falling edge. Base unit: 1 * clock cycle RE access time. Base unit: 1 * clock cycle CLE, CE, ALE, DATA and WE hold time. Base unit: 1* clock cycle CLE, CE, ALE and DATA setup time. Base unit: 1 * clock cycle
R/W R
InitVal 1
R R/W
0 1
R/W
1
R/W R/W R/W R/W R/W R/W
1111 1111 1111 1111 1111 1111
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0xBD01_1010 NAND Flash Command Register (NCAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC (Reserved) CE_CMD EE CC SS 45 Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal W 1 31 CECS4 Command enable to CS4 connected NAND flash `1': Command Enable `0': No command enabled W 0 30 CECS5 Command enable to CS5 connected NAND flash `1': Command Enable `0': No command enabled 7-0 CE_CMD Command port to NAND flash memory W 0
0xBD01_1014 31 30 29 28 27 26 (Reserved) A D 2 E N Reset: 0x0000_0000 Bit Bit Name 26 AD2EN
25 A D 1 E N
NAND Flash Address Register (NADDR) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A CE_ADD2 CE_ADD1 CE_ADDR0 D 0 E N R/W W InitVal 0
25
AD1EN
24
AD0EN
23-16 15-8 7-0
CE_ADDR2 CE_ADDR1 CE_ADDR0
Description Address port 2 enable `1': Address port 2 is valid to output to NAND flash `0': Address port 2 is not output to NAND flash Address port 1 enable `1': Address port 1 is valid to output to NAND flash `0': Address port 1 is not output to NAND flash Address port 0 enable `1': Address port 0 is valid to output to NAND flash `0': Address port 0 is not output to NAND flash Address2 port to NAND flash memory. Address1 port to NAND flash memory. Address0 port to NAND flash memory.
W
0
W
0
W W W
0 0 0
0xBD01_1018 NAND Flash Data Register (NDR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA3 DATA2 DATA1 DATA0
Reset: 0x0000_0000 Bit Bit Name 31-24 DATA3
Description R/W NAND flash DATA0 port. Read/Write this field during data phase will R/W reflects to external NAND flash I/O ports. When bit RBS or bit WBS in NCR register is `1', this data byte is the highest address of the register word. Else this byte is the lowest address byte of the register word.
InitVal 0
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23-16 DATA2 www..com NAND flash DATA1 port. Read/Write this field during data phase will R/W reflects to external NAND flash I/O ports. When bit RBS or bit WBS in NCR register is `1', this data byte is the 3rd address of the register word. Else this byte is the 2nd address byte of the register word. NAND flash DATA1 port. Read/Write this field during data phase will R/W reflects to external NAND flash I/O ports. When bit RBS or bit WBS in NCR register is `1', this data byte is the 2nd address of the register word. Else this byte is the 3rd address byte of the register word. NAND flash DATA0 port. Read/Write this field during data phase will R/W reflects to external NAND flash I/O ports. When bit RBS or bit WBS in NCR register is `1', this data byte is the lowest address of the register word. Else this byte is the highest address byte of the register word. 0
15-8
DATA1
0
7-0
DATA0
0
NAND flash layout
Address Address Address ... 0x0 - 0x1 0x2 - 0x3 0x4 - ... NAND flash Header NAND flash boot image Address 0x4000 Address 0x4001 Data Address End
NAND flash header format
Byte Address 3 Byte Address 2 Byte Address 1 Byte Address 0 543210765432107654321076543210 B T_RAS T_RFC OPCODE CS T_RCD AD U SB S LU C S L W K I D Byte Address 3 Bit Bit Name Description R/W InitVal 7-6 SDRSZ SDRAM size respective to one bank (bit). R/W 10 00: 512Kx16x2 01: 1Mx16x4 10: 2Mx16x4 11: Reserved 5 CASL CAS Latency R/W 0 0: Latency=2 1: Latency=3 4 SDBUSWID SDRAM bus width R/W 0 0: 16 bit 1: 32 bit 3-1 BUSCLK Bus Clock to control auto-refresh timing R/W 000 000: 200 MHz 001: 100 MHz 010: 50 MHz 011: 25 MHz 100: 12.5 MHz 101: 6.25 MHz 7 6 S D R S Z
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0 T_RCD Byte Address 2 Bit Bit Name 0-7-6 T_RCD
110: 3.125 MHz 111: 1.5625 MHz Combined with 1st field of next table. Description T_RP and T_RCD timing parameter Basic unit, 4*clock cycle "000" means 1 unit (4 clock cycle) T_RAS timing parameter Basic unit, 4*clock cycle "000" means 1 unit (4 clock cycle) T_RFC timing parameter for refresh interval Basic unit, 4*clock cycle "000" means 1 unit (4 clock cycle) Description The OPCODE of first instruction in big endian format. R/W R/W InitVal 111
5-3
T_RAS
R/W
111
2-0
T_RFC
R/W
111
Byte Address 1-0 Bit Bit Name 7-0 OPCODE
R/W R/W
InitVal x
Timing Diagram
The SDRAM timing:
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The write access timing of flash memory: www..com
A[20..0] F_CE0# OE# Twp Tcs WR# D[n..0]
The read access timing of flash memory:
A[20..0] F_CE0# WE# OE# D[n..0]
9. Ethernet Network Interface Controller
There are two 10/100M Ethernet NIC modules embedded in RTL8186. The Ethernet device has bus master capability and moves packets between SDRAM and the Ethernet controller through a DMA mechanism, lessening the CPU loading and giving better performance. Both the Ethernet controller support the following feature: l l l l l Supports 10/100 Full/Half (collision) Flow control (control frame transmission). Supports IEEE802.1P/Q VLAN handling. TCP, UDP, IP receiving checksum offload Hardware Priority queue with one receive descriptor ring and two transmit descriptor rings. Unicast Address Recognition.
The Ethernet controller supports up to 64 consecutive descriptors for transmit and receive separately. Besides, it includes 3 descriptor rings, one high priority transmit ring, one normal priority transmit ring and the other is for receive descriptor ring. Each descriptor ring may consist of up to 64 consecutive descriptors, and each descriptor is consisted of 4 consecutive words. The starting address of each descriptor group should be 256-byte alignment. Software must pre-allocate enough buffers and configures all descriptor rings before transmitting and/or receiving packets. Descriptors can be chained for both transmitting and receiving packet. Any transmit buffer pointed by one of transmit descriptor should be at least 4 bytes. And for transmit packet padding; the Ethernet controller will automatically pad any packet less than 64 bytes (including 4 bytes CRC) to 64-byte long (including 4-byte CRC) before transmitting that packet into network medium. Also the Ethernet controller offloads the calculation of IP/TCP/UDP checksum at the receiving path FIFO. The packet parser insides the controller can identify: l l l l 802.3 Ethernet packets RFC894 Ethernet II packets PPPOE packets VLAN packets
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Inside the IP payload, the packet parser determines whether the packet is TCP/UDP or neither of the two. For TCP/UDP checksum, the IP pseudo header must be included in the checksum one's complement summation. The Ethernet NIC also identifies fragmented packets and handles TCP/UDP checksum by performing one's complement summation per IP packet, recording the sum/packet in the last descriptor and reporting fragmentation on status descriptor. For non-fragmented packets, Ethernet NIC module checks the calculated TCP/UDP checksum and reports the status in the descriptor.
Descriptor Data Structure
The descriptors in the queuing rings serve to exchange messages between CPU and the Ethernet Controller. A transmit descriptor changes form before and after transmit. Also the receive descriptor changes form before and after receive. The descriptor data structures are illustrated as follow:
n
Normal Tx Descriptor Format (before transmitting, OWN=1, Tx command mode 1)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 54 3 21 0
31 330 29 28
OEFL WOS S NR = 1
RSVD (4 bits)
C R C
Offset 0 RSVD (11 bits) Data_Length (12 bits)
Offset 4 TX_BUFFER_ADDRESS (32 bits)
RSVD (15 bits)
T A G C
VIDL
VLAN_TAG PRIO C F I
Offset 8 VIDH
Offset 12 RSVD
Offset# 0
Bit# 31
Symbol OWN
Description When set, indicates that the descriptor is owned by NIC, and the data relative to this descriptor is ready to be transmitted. When cleared, indicates that the descriptor is owned by host system. NIC clears this bit when the relative buffer data is transmitted. In this case, OWN=1. Value Meaning 0 Descriptor own by host system 1 Descriptor own by NIC End of descriptor Ring. When set, indicates that this is the last descriptor in descriptor ring. When NIC's internal transmit pointer reaches here, the pointer will return to the first descriptor of the descriptor ring after transmitting the data associates with this descriptor. First segment descriptor. When set, indicates that this is the first descriptor of a segmented Tx packet, and this descriptor is pointing to the first segment of the packet. Last segment descriptor. When set, indicates that this is the last descriptor of a segmented Tx packet, and this descriptor is pointing to the last segment of the packet. Reserved bits.
0
30
EOR
0
29
FS
0
28
LS
0
27-24
RSVD
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0 23 CRC www..com If this bit is set then append CRC at the end of Ethernet frame. Value 0 1 Reserved bits. Meaning No CRC appended CRC appended
0 0 4 8 8
22-12 11-0 31-0 31-17 16
RSVD Frame_Length TxBuff RSVD TAGC
Transmit frame length. This field indicates the length in TX buffer page, in byte, to be transmitted Physical 32-bit address of transmit buffer. Reserved bits. VLAN tag control bit. 1: Enable. 0: Disable. Meaning Packet remains unchanged when transmitting. I.e., the packet transmitted is the same as upper layer passed it down. 1 Insert TAG 0x8100 (Ethernet encoded tag protocol ID) after source address, indicating that this is a IEEE 802.1Q VLAN packet. And 2 bytes are inserted after the TAG that copied from VLAN_TAG field in Tx descriptor. The 2-byte VLAN_TAG contains information, from upper layer, of user priority, canoethernetal format indicator, and VLAN ID. Please refer to IEEE 802.1Q for more VLAN tag information. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canoethernetal Format Indicator. Reserved Value 0
8
15-0
VLAN_TAG
12
31-0
RSVD
n
Tx Status Descriptor (after transmitting, OWN=0, Tx status mode)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7654 3210
31 30 29 28
OEFL WO S S NR = 0
Offset 0 RSVD (16bits) Data_Length (12 bits)
Offset 4 TX_BUFFER_ADDRESS (32 bits)
RSVD (15 bits)
T A VIDL G C
VLAN_TAG PRIO C VIDH F I
Offset 8
Offset 12 RSVD
Offset# 0
Bit# 31
Symbol OWN
Description When set, indicates that the descriptor is owned by NIC. When clear indicates that the descriptor is owned by host system. NIC clears this bit 37
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indicates that the descriptor is owned by host system. NIC clears this bit when the relative buffer data is already transmitted. In this case, OWN=0. Value Meaning 0 Descriptor own by host system 1 Descriptor own by NIC End of descriptor Ring. When set, indicates that this is the last descriptor in descriptor ring. When NIC's internal transmit pointer reaches here, the pointer will return to the first descriptor of the descriptor ring after transmitting the data associates with this descriptor. First segment descriptor. When set, indicates that this is the first descriptor of a segmented Tx packet, and this descriptor is pointing to the first segment of the packet. Last segment descriptor. When set, indicates that this is the last descriptor of a segmented Tx packet, and this descriptor is pointing to the last segment of the packet. Reserved. Transmit data length. This field indicates the length in TX buffer page, in byte, transmitted The physical 32-bit address of transmit buffer. Reserved bits. Record of previous VLAN information: VLAN tag control bit. 1: Tag was inserted. 0: Tag was not inserted Record of previous VLAN information: The 2-byte VLAN_TAG contains information, from upper layer, of user priority, canoethernetal format indicator, and VLAN ID. Please refer to IEEE 802.1Q for more VLAN tag information. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canoethernetal Format Indicator. Reserved
0
30
EOR
0
29
FS
0
28
LS
0 0 4 8 8
27-12 11-0 31-0 31-17 16
RSVD Data_Length TxBuff RSVD TAGC
8
15-0
VLAN_TAG
12
31-0
RSVD
n
OE WO NR = 1
Rx Command Descriptor (OWN=1)
10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
Offset 0 RSVD (18 bits) Buffer_Size (12 bits)
Offset 8 RX_BUFFER_ADDRESS (32 bits)
Offset 8 RSVD
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Offset 12 RSVD
Offset# 0
Bit# 31
Symbol OWN
Description When set, indicates that the descriptor is owned by NIC, and is ready to receive packet. The OWN bit is set by driver after having pre-allocated buffer at initialization, or the host has released the buffer to driver. In this case, OWN=1. Value Meaning 0 Descriptor own by host system 1 Descriptor own by NIC End of Rx descriptor Ring. Set to 1 indicates that this descriptor is the last descriptor of Rx descriptor ring. Once NIC's internal receive descriptor pointer reaches here, it will return to the first descriptor of Rx descriptor ring after this descriptor is used by packet reception. Reserved bits. This field indicate the receive buffer size in bytes. The NIC purges all data after 4K bytes if the packet is larger than 4K-byte long. The 32-bit physical address of receive buffer. Reserved bits. Reserved bits.
0
30
EOR
0 0 4 8 12
29-12 11-0 31-0 31-0 31-0
RSVD Buffer_Size Rx_Buff_addr RSVD RSVD
n
Rx Status Descriptor (OWN=0)
10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
O E FL FMPBP E WO S SAAAAP 8 E RMR P 0 NR O 2. = E3 0
LRRCP PEUR I KSNCD T T 1
P IUT I I PDCP DFPPS 0 FFE G
R S V D
Data_Length (11 bits)
Offset 0
Offset 8 RX_BUFFER_ADDRESS (32 bits)
O F F S T
F R A G
RSVD (13 bits)
T A V A
VLAN_TAG VIDL (8 bits) PRIO C (3 bits) F I
Offset 8 VIDH (4 bits) Offset 12
RSVD (16 bits)
PARTIAL_CHECKSUM (16 bits)
Offset# 0
Bit# 31
Symbol OWN
Description When set, indicates that the descriptor is owned by NIC. When cleared, indicates that the descriptor is owned by host system. NIC clears this bit when NIC has filled up this Rx buffer with a packet or part of a packet. In
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this case, OWN=0. Value Meaning 0 Descriptor own by host system 1 Descriptor own by NIC End of Rx descriptor Ring. Set to 1 indicates that this descriptor is the last descriptor of Rx descriptor ring. Once NIC's internal receive descriptor pointer reaches here, it will return to the first descriptor of Rx descriptor ring after this descriptor is used by packet reception. First segment descriptor. When set, indicates that this is the first descriptor of a received packet, and this descriptor is pointing to the first segment of the packet. Last segment descriptor. When set, indicates that this is the last descriptor of a received packet, and this descriptor is pointing to the last segment of the packet. Frame Alignment Error. When set, indicates a frame alignment error has occurred on the received packet. The FAE packet can be received only when AER bit at RCR register is set. Multicast Address packet Received. When set, indicates that a multicast packet is received Physical Address Matched. When set, indicates that the destination address of this Rx packet matches to the value in Ethernet's ID registers. Use to address packets to gateway. Broadcast Address Received. When set, indicates that a broadcast packet is received. BAR and MAR will not be set simultaneously. Identifies if current packet is PPPOE packet Identifies if current packet is of Ethernet 802.3 format Receive Watchdog Timer expired. When set, indicates that the received packet length exceeds 4096 bytes, the receive watchdog timer will expire and stop receive engine. Receive Error Summary. When set, indicates at least one of the following errors occurred: CRC, RUNT, RWT, FAE. This bit is valid only when LS (Last segment bit) is set Runt packet. When set, indicates that the received packet length is smaller than 64 bytes. RUNT packet can be received only when AR bit at RCR register is set. CRC error. When set, indicates that a CRC error has occurred on the received packet. A CRC packet can be received only when AER bit at RCR register is set. Protocol ID1, Protocol ID0: These 2 bits indicate the protocol type of the packet received. PID1 PID0 Non-IP 0 0 TCP/IP 0 1 UDP/IP 1 0 IP 1 1 When set, indicates IP checksum failure. When set, indicates UDP checksum failure. When set, indicates TCP checksum failure. Reserved This indicates the number of bytes of data on the page pointed by the descriptor. The content of the page should start with no reserve at the start of the page (unless offset bit is set) The 32-bit physical address of receive buffer.
0
30
EOR
0
29
FS
0
28
LS
0
27
FAE
0 0
26 25
MAR PAM
0 0 0 0
24 23 22 21
BAR PPPOE E802.3 RWT
0
20
RES
0
19
RUNT
0
18
CRC
0
17, 16
PID1, PID0
0 0 0 0 0
15 14 13 12 11-0
IPF UDPF TCPF RSVD Data_Length
4
31-0
RxBuff
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8 31 OFFST www..com 8 8 8 8 30 29-17 16 15-0 FRAG RSVD TAVA VLAN_TAG Defines if a 2-byte offset exists on this page before valid data. Indicates the fragmentation flag is set Reserved bits. Tag Available. When set, the received packet is an IEEE802.1Q VLAN TAG (0x8100) available packet. If the packet `s TAG (EtherType field) is 0x8100, The NIC extracts four bytes from after source ID, sets TAVA bit to1, and moves the TAG value to this field in Rx descriptor. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canoethernetal Format Indicator. Reserved bits.
12 12
31-0 15-0
RSVD
PARTIAL_CHEC In the case of IP packet with no fragmentation: KSUM This field is the non-inverted accumulate sum for this IP PDU including Pseudo Header. Result should be 0xFFFF if there are no errors. In the case of IP fragmentation: This field is the non-inverted accumulate sum for this IP PDU excluding Pseudo Header. Summing all partial sums of packets crossing multiple IP PDU's and performing One's complement' inversion is done by software). If the TCP/UDP packet is fragment and carried over 2 more IP packets, only the accumulate sum and not the pseudo header is included in the summation. This value is valid in descriptor with LS=1.
Register Summary
Virtual Address Size (byte) Name 0xBD20_0000 6 ETH0_IDR Description Access ID Register. The ID register is only permitted R/W to write by 4-byte access. Read access can be byte, word, or double word access. The initial value is autoloaded from Flash. Multicast Register. The MAR register is only R/W permitted to write by 4-byte access. Read access can be byte, word, or double word access. Driver is responsible for initializing these registers. The MAR defines 64 bits that is a bit wise index of the multicast function of multicast addresses. The hash function of multicast address is the upper 6 MSB's of the CRC32 of the address (destination). The index then is the numerical representation of those 6 bits in hex format. 16-bit counter of Tx DMA Ok packets. R/W 16-bit counter of Rx Ok packets. R/W 16-bit packet counter of Tx errors including R/W Tx abort, carrier lost, Tx underrun (should be happened only on jumbo frames), and out of window collision. 16-bit packet counter of Rx errors including R/W CRC error packets (should be larger than 8 bytes) and missed packets. 16-bit counter of missed packets resulting R/W from Rx FIFO full.
0xBD20_0008
8
ETH0_MAR
0xBD20_0010 0xBD20_0012 0xBD20_0014
2 2 2
ETH0_TXOKCNT ETH0_RXOKCNT ETH0_TXERR
0xBD20_0016
2
ETH0_RXERR
0xBD20_0018
2
ETH0_MISSPKT
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0xBD20_001A 2 www..com 0xBD20_001C 0xBD20_001E 2 2 16-bit counter of Frame Alignment Error packets. ETH0_TX1COL 16-bit counter of those Tx Ok packets with only 1 collision happened before Tx Ok. ETH0_TXMCOL 16-bit counter of those Tx Ok packets with more than 1, and less than 16 collisions happened before Tx Ok. ETH0_RXOKPHY 16-bit counter of all Rx Ok packets with physical address matched destination ID. ETH0_RXOKBRD 16-bit counter of all Rx Ok packets with broadcast destination ID. ETH0_RXOKMUL 16-bit counter of all Rx Ok packets with multicast destination ID. ETH0_TXABT 16-bit counter of Tx abort packets. ETH0_TXUNDRN 16-bit counter of Tx underrun and discarded packets. ETH0_TRSR Tx/Rx Status Register. ETH0_CR Command Register. ETH0_IMR Interrupt Mask Register. ETH0_ISR Interrupt Status Register. ETH0_TCR Transmit (Tx) Configuration Register. ETH0_RCR Receive (Rx) Configuration Register. ETH0_MSR Media Status Register. ETH0_MIIAR MII Access Register. ETH0_ TXFDP1 Tx First Descriptor Pointer (FDP) for high priority queue. ETH0_ TXCDO1 Tx Current Descriptor Offset (CDO) for high priority queue. ETH0_ TXFDP2 Tx First Descriptor Pointer (FDP) for low priority queue. ETH0_ TXCDO2 Tx Current Descriptor Offset (CDO) for low priority queue. ETH0_ RXFDP Rx First Descriptor Pointer (FDP). ETH0_ CDO Rx Current Descriptor Offset (CDO). ETH0_ RXRINGSIZE Rx Ring Size (in number of Descriptors). ETH0_ RXCPUDESC This is the descriptor number which the CPU has finished processing and returned to IO. CPU needs to update this. ETH0_ RXPSEDESC Specifies the difference between ETH0_ RXCPUDESC and the descriptor number currently in use by NIC in which flow control will be assert. ETH0_ IOCMD ETHER_IO_CMD. ETH0_FAE R/W R/W R/W
0xBD20_0020 0xBD20_0022 0xBD20_0024 0xBD20_0026 0xBD20_0028 0xBD20_0034 0xBD20_003B 0xBD20_003C 0xBD20_003E 0xBD20_0040 0xBD20_0044 0xBD20_0058 0xBD20_005C 0xBD20_1300 0xBD20_1304 0xBD20_1380 0xBD20_1384 0xBD20_13F0 0xBD20_13F4 0xBD20_13F6 0xBD20_1430
2 2 2 2 2 4 1 2 2 4 4 4 4 4 2 4 2 4 2 1 2
R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0xBD20_1432
2
R/W
0xBD20_1434
4
R/W
Virtual Address Size (byte) Name 0xBD30_0000 6 ETH1_IDR
Description Access ID Register. The ID register is only permitted R/W to write by 4-byte access. Read access can be byte, word, or double word access. The initial value is autoloaded from Flash.
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0xBD30_0008 8 www..com Multicast Register. The MAR register is only permitted to write by 4-byte access. Read access can be byte, word, or double word access. Driver is responsible for initializing these registers. The MAR defines 64 bits that is a bit wise index of the multicast function of multicast addresses. The hash function of multicast address is the upper 6 MSB's of the CRC32 of the address (destination). The index then is the numerical representation of those 6 bits in hex format. ETH1_TXOKCNT 16-bit counter of Tx DMA Ok packets. ETH1_RXOKCNT 16-bit counter of Rx Ok packets. ETH1_TXERR 16-bit packet counter of Tx errors including Tx abort, carrier lost, Tx underrun (should be happened only on jumbo frames), and out of window collision. ETH1_RXERR 16-bit packet counter of Rx errors including CRC error packets (should be larger than 8 bytes) and missed packets. ETH1_MISSPKT 16-bit counter of missed packets resulting from Rx FIFO full. ETH1_FAE 16-bit counter of Frame Alignment Error packets. ETH1_TX1COL 16-bit counter of those Tx Ok packets with only 1 collision happened before Tx Ok. ETH1_TXMCOL 16-bit counter of those Tx Ok packets with more than 1, and less than 16 collisions happened before Tx Ok. ETH1_RXOKPHY 16-bit counter of all Rx Ok packets with physical address matched destination ID. ETH1_RXOKBRD 16-bit counter of all Rx Ok packets with broadcast destination ID. ETH1_RXOKMUL 16-bit counter of all Rx Ok packets with multicast destination ID. ETH1_TXABT 16-bit counter of Tx abort packets. ETH1_TXUNDRN 16-bit counter of Tx underrun and discarded packets. ETH1_TRSR Tx/Rx Status Register. ETH1_CR Command Register. ETH1_IMR Interrupt Mask Register. ETH1_ISR Interrupt Status Register. ETH1_TCR Transmit (Tx) Configuration Register. ETH1_RCR Receive (Rx) Configuration Register. ETH1_MSR Media Status Register. ETH1_MIIAR MII Access Register. ETH1_ TXFDP1 Tx First Descriptor Pointer (FDP) for high priority queue. ETH1_ TXCDO1 Tx Current Descriptor Offset (CDO) for high priority queue. ETH1_ TXFDP2 Tx First Descriptor Pointer (FDP) for low priority queue. ETH1_ TXCDO2 Tx Current Descriptor Offset (CDO) for low priority queue. ETH1_ RXFDP Rx First Descriptor Pointer (FDP). ETH1_ CDO Rx Current Descriptor Offset (CDO). ETH1_ RXRINGSIZE Rx Ring Size (in number of Descriptors). ETH1_MAR R/W
0xBD30_0010 0xBD30_0012 0xBD30_0014
2 2 2
R/W R/W R/W
0xBD30_0016
2
R/W
0xBD30_0018 0xBD30_001A 0xBD30_001C 0xBD30_001E
2 2 2 2
R/W R/W R/W R/W
0xBD30_0020 0xBD30_0022 0xBD30_0024 0xBD30_0026 0xBD30_0028 0xBD30_0034 0xBD30_003B 0xBD30_003C 0xBD30_003E 0xBD30_0040 0xBD30_0044 0xBD30_0058 0xBD30_005C 0xBD30_1300 0xBD30_1304 0xBD30_1380 0xBD30_1384 0xBD30_13F0 0xBD30_13F4 0xBD30_13F6
2 2 2 2 2 4 1 2 2 4 4 4 4 4 2 4 2 4 2 1
R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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0xBD30_1430 2 www..com 0xBD30_1432 2 ETH1_ RXCPUDESC This is the descriptor number which the CPU R/W has finished processing and returned to IO. CPU needs to update this. R/W ETH1_ RXPSEDESC Specifies the difference between ETH1_ RXCPUDESC and the descriptor number currently in use by NIC in which flow control will be assert. ETH1_ IOCMD ETHER_IO_CMD. R/W
0xBD30_1434
4
0xBD20_0000 Ethernet0 ID Register (ETH0_IDR) 0xBD30_0000 Ethernet1 ID Register (ETH1_IDR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID3 ID2 ID1 ID0
0xBD20_0004 0xBD30_0004 31
cont. of Ethernet0 ID Register (ETH0_IDR) cont. of Ethernet1 ID Register (ETH1_IDR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID5 ID4
Reset: 0x0 Bit Bit Name 7-0 ID0 15-8 ID1 23-16 ID2 31-0 ID3 7-0 ID4 15-8 ID5
Description R/W InitVal ID Register. The ID register0-5 are only permitted R/W ? to write by 4-byte access. Read access can be byte, word, or double word access. The initial value is autoloaded from Flash.
0xBD20_0008 Ethernet0 Multicast Register (ETH0_MAR) 0xBD30_0008 Ethernet1 Multicast Register (ETH1_MAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR3 MAR2 MAR1 MAR0
0xBD20_000C cont. of Ethernet0 Multicast Register (ETH0_MAR) 0xBD30_000C cont. of Ethernet1 Multicast Register (ETH1_MAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR7 MAR6 MAR5 MAR4 Reset: 0x? Bit Bit Name 7-0 MAR0 15-8 MAR1 23-16 MAR2 31-0 MAR3 7-0 MAR4 15-8 MAR5 23-16 MAR6 31-24 MAR7
Description R/W InitVal Multicast Register. The MAR register0-7 is only R/W ? permitted to write by 4-byte access. Read access can be byte, word, or double word access. Driver is responsible for initializing these registers. The MAR7-0 defined a 64-bits, which is a bit wise index of the multicast function of multicast addresses. The hash function of multicast address is the upper 6 MSB's of the CRC32 of the address (destination). The index then is the numerical representation of those 6 bits in hex format.
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0xBD20_0010 0xBD30_0010 31
Ethernet0 TX DMA OK Counter Register (ETH0_TXOKCNT) Ethernet1 TX DMA OK Counter Register (ETH1_TXOKCNT) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxOkCnt
Reset: 0x00 Bit Bit Name 15-0 TxOkCnt
Description R/W InitVal 16-bit counter of Tx DMA Ok packets. Rolls over R/W 0 automatically. Write to clear.
0xBD20_0012 0xBD30_0012 31
Ethernet0 RX DMA OK Counter Register (ETH0_RXOKCNT) Ethernet1 RX DMA OK Counter Register (ETH1_RXOKCNT) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxOkCnt
Reset: 0x00 Bit Bit Name 15-0 RxOkCnt
Description R/W InitVal 16-bit counter of Rx DMA Ok packets. Rolls over R/W 0 automatically. Write to clear.
0xBD20_0014 0xBD30_0014 31
Ethernet0 TX Error Counter Register (ETH0_TXERR) Ethernet1 TX Error Counter Register (ETH1_TXERR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxErrCnt
Reset: 0x00 Bit Bit Name 15-0 TxErrCnt
Description 16-bit counter of Tx error packets. Rolls over automatically. Write to clear.
R/W InitVal R/W 0
0xBD20_0016 0xBD30_0016 31
Ethernet0 RX Error Counter Register (ETH0_RXERR) Ethernet1 RX Error Counter Register (ETH1_RXERR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxErrCnt
Reset: 0x01 Bit Bit Name 15-0 RxErrCnt
Description 16-bit counter of Rx error packets. Rolls over automatically. Write to clear.
R/W InitVal R/W 1
0xBD20_0018 0xBD30_0018 31
Ethernet0 Miss Packet Counter Register (ETH0_MISSPKT) Ethernet1 Miss Packet Counter Register (ETH1_MISSPKT) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MissPkt
Reset: 0x00 Bit Bit Name 15-0 MissPkt
Description 16-bit counter missed packets. Rolls over automatically. Write to clear.
R/W InitVal R/W 0
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0xBD20_001A 0xBD30_001A 31
Ethernet0 FAE Counter Register (ETH0_FAE) Ethernet1 FAE Counter Register (ETH1_FAE) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FAECnt
Reset: 0x00 Bit Bit Name 15-0 FAECnt
Description 16-bit counter of Fragment Alignment Error packets. Rolls over automatically. Write to clear.
R/W InitVal R/W 0
0xBD20_001C 0xBD30_001C 31
Ethernet0 Tx 1st Collision Counter Register (ETH0_TX1COL) Ethernet1 Tx 1st Collision Counter Register (ETH1_TX1COL) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tx1Col
Reset: 0x00 Bit Bit Name 15-0 Tx1Col
Description 16-bit counter of TxCol packets. Rolls over automatically. Write to clear. This only records which have entered just one collision before Tx OK.
R/W InitVal R/W 0
0xBD20_001E 0xBD30_001E 31
Ethernet0 Tx Multi Collision Counter Register (ETH0_TXMCOL) Ethernet1 Tx Multi Collision Counter Register (ETH1_TXMCOL) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxMCol
Reset: 0x00 Bit Bit Name 15-0 TxMCol
Description R/W InitVal 16-bit counter of Tx Multi Collision packets. Rolls R/W 0 over automatically. Write to clear. This keeps track of those packets with less than 16 collisions (or the configured retry count) before Tx Ok.
0xBD20_0020 0xBD30_0020 31
Ethernet0 Rx Ok Physical addr matched Counter Register (ETH0_RXPHY) Ethernet1 Rx Ok Physical addr matched Counter Register (ETH1_RXPHY) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxPhyAddM
Reset: 0x00 Bit Bit Name 15-0 RxPhyAddM
Description 16-bit counter of Rx Ok packets with physical address matching destination address. Rolls over automatically. Write to clear.
R/W InitVal R/W 0
0xBD20_0022 0xBD30_0022 31
Ethernet0 Rx Ok Broadcast addr matched Counter Register (ETH0_RXBRD) Ethernet1 Rx Ok Broadcast addr matched Counter Register (ETH1_RXBRD) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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RxBrdAddM
Reset: 0x00 Bit Bit Name 15-0 RxBrdAddM
Description 16-bit counter of Rx Ok packets with broadcast destination address. Rolls over automatically. Write to clear.
R/W InitVal R/W 0
0xBD20_0024 0xBD30_0024 31
Ethernet0 Rx Ok Multicast addr matched Counter Register (ETH0_RXMUL) Ethernet1 Rx Ok Multicast addr matched Counter Register (ETH1_RXMUL) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxMulAddM
Reset: 0x00 Bit Bit Name 15-0 RxMulAddM
Description 16-bit counter of Rx Ok packets with multicast destination address. Rolls over automatically. Write to clear.
R/W InitVal R/W 0
0xBD20_0026 0xBD30_0026 31
Ethernet0 Tx Abort Counter Register (ETH0_TXABT) Ethernet1 Tx Abort Counter Register (ETH1_TXABT) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxAbt
Reset: 0x00 Bit Bit Name 15-0 TxAbt
Description 16-bit counter of Tx aborted packets. Rolls over automatically. Write to clear. This accounts for over collision, underrun, LNK failure conditions.
R/W InitVal R/W 0
0xBD20_0028 0xBD30_0028 31
Ethernet0 Tx Underrun Counter Register (ETH0_TXUNDRN) Ethernet1 Tx Underrun Counter Register (ETH1_TXUNDRN) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxUndrn
Reset: 0x00 Bit Bit Name 15-0 TxUndrn
Description R/W InitVal 16-bit counter of Tx Underrun packets. Rolls over R/W 0 automatically. Write to clear. (Only possible for jumbo frame which may not be allowed in RTL8186)
0xBD20_0034 Ethernet0 Tx/Rx Status Register (ETH0_TRSR) 0xBD30_0034 Ethernet1 Tx/Rx Status Register (ETH1_TRSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) TTRR OUXS KNFV ED Reset: 0x0000_0000
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Bit Bit Name www..com 3 TOK Description Transmit OK: Set to 1 indicates that the transmission of a packet was completed successfully and no transmit underrun occurs. Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted during the transmission of a packet. The NIC can re-transfer data if the Tx FIFO underruns and can also transmit the packet to the wire successfully even though the Tx FIFO underruns. That is, when TSD=1, TSD=0 and ISR=1 (or ISR=1). Handle underrun transmit with care. Rx FIFO is Empty. Reserved. R/W InitVal R 0
2
TUN
R
0
1 0
RXFE RSVD
R -
0 -
0xBD20_003B 0xBD30_003B 31
Ethernet0 Command Register (ETH0_CR) Ethernet1 Command Register (ETH1_CR) 876543210 (Reserved) RRR XXS VCT LS AE N Description Receive VLAN de-tagging enable. 1: Enable. 0: Disable. Receive checksum offload enable. 1: Enable. 0: Disable. Reset: Setting to 1 to force the NIC enters a software reset state which disables the transmitter and receiver, reinitializes the FIFOs, triggers interrupt Swint for RISC to reset the system buffer pointer to the initial value Tx/Rx FDP. The values of IDR0-5 and MAR0-7 will have no changes. This bit is 1 during the reset operation, and is cleared to 0 by the NIC when the reset operation is complete. R/W InitVal R/W 0 R/W 0 R/W 0
Reset: 0x0000_0000 Bit Bit Name 2 RXVLAN 1 0 RXCSE RST
0xBD20_003C 0xBD30_003C 31
Ethernet0 Interrupt Mask Register (ETH0_IMR) Ethernet1 Interrupt Mask Register (ETH1_IMR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) STLTTRRRRRR WDNEODXSXSO I UKRKUFVRVK n C UDUD t H L N G L T Description 1: enable interrupt 0: disable interrupt 1: enable interrupt R/W InitVal R/W 0 R/W 0
Reset: 0x0000_0000 Bit Bit Name 10 SWInt 9 TDU
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8 7 6 5 4 3, 1 2 0
LNKCHG TER TOK RDU RXFULL RSVD RXRUNT ROK
0: disable interrupt 1: enable interrupt 0: disable interrupt 1: enable interrupt 0: disable interrupt 1: enable interrupt 0: disable interrupt 1: enable interrupt 0: disable interrupt 1: enable interrupt 0: disable interrupt Reserved. 1: enable interrupt 0: disable interrupt 1: enable interrupt 0: disable interrupt
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
0xBD20_003E 0xBD30_003E 31
Ethernet0 Interrupt Status Register (ETH0_ISR) Ethernet1 Interrupt Status Register (ETH1_ISR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) STLTTRRRRRR WDNEODXSXSO I UKRKUFVRVK n C UDUD t H L N G L T Description Software Interrupt pending: When set to 1 indicates a software interrupt was forced. Write 1 to clear. Tx Descriptor Unavailable: When set, indicates Tx descriptor is unavailable. Link Change: Set to 1 when link status is changed. Write 1 to clear. Transmit (Tx) Error: Indicates that a packet transmission was aborted, due to excessive collisions, according to the TXRR's setting. Write 1 to clear. Transmit Interrupt: Indicates that the DMA of the last descriptor of RxIntMitigation number of Tx packet has completed and the last descriptor has been closed. Write 1 to clear. Rx Descriptor Unavailable: When set, indicates Rx descriptor is unavailable or Rx_Pse_Des_Thres was broken. Rx FIFO Overflow, caused by RBO/RDU, poor system bus (Lexra bus) performance, or overloaded Lexra bus traffic. Reserved. Rx error caused by runt error characterized by the frame length in bytes being less than 64 bytes. Write 1 to clear. Receive (Rx) OK: This interrupt is set either when RxIntMitigation R/W InitVal R/W 0
Reset: 0x0000_0000 Bit Bit Name 10 SWInt
9 8
TDU LNKCHG
R/W 0 R/W 0
7
TER
R/W 0
6
TOK
R/W 0
5
RDU
R/W 0
4
RXFULL
R/W 0
3, 1 2
RSVD RXRUNT
R/W 0
0
RXOK
R/W 0
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packet is met or RxPktTimer expires. clear.
Write 1 to
0xBD20_0040 Ethernet0 Transmit Configuration Register (ETH0_TCR) 0xBD30_0040 Ethernet1 Transmit Configuration Register (ETH1_TCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) IFG LBK (Reserved) Reset: 0x0000_0C00 Bit Bit Name 12-10 IFG
Description R/W InitVal InterFrameGap Time: This field allows the user to R/W 3 adjust the interframe gap time longer than the standard: 9.6 us for 10Mbps, 960 ns for 100Mbps. The time can be programmed from 9.6 us to 14.4 us (10Mbps) and 960ns to 1440ns (100Mbps). The formula for the inter frame gap is: IFG 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 IFG@100MHz (nS) 960 960 + 8 * 10 960 + 16 * 10 960 + 24 * 10 960 + 32 * 10 960 + 40 * 10 960 + 48 * 10 960 + 96 * 10 IFG@10MHz (uS) 9.6 9.6 +8 * 0.1 9.6 +16 * 0.1 9.6 +24 * 0.1 9.6 +32 * 0.1 9.6 +40 * 0.1 9.6 +48 * 0.1 9.6 +96 * 0.1
9-8
LBK
Loopback test. There will be no packet on the R/W 0 TX+/- lines under the Loopback test condition. The loopback function must be independent of the link state. 00 : normal operation 01 : Reserved 10 : Reserved 11 : Loopback mode
0xBD20_0044 Ethernet0 Receive Configuration Register (ETH0_RCR) 0xBD30_0044 Ethernet1 Receive Configuration Register (ETH1_RCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) AAAAAAA FERBMPA LR MP O W Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 6 AFLOW Set 1 to accept flow control packets R/W 0 5 AER Accept Error Packet: When set to 1, all packets R/W 0 with CRC error, alignment error, and/or collided fragments will be accepted. When set to 0, all packets with CRC error, alignment error, and/or collided fragments will be rejected. 4 AR Accept Runt: This bit allows the receiver to accept R/W 0
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3 2 1 0
AB AM APM AAP
packets that are smaller than 64 bytes. The packet must be at least 8 bytes long to be accepted as a runt. Set to 1 to accept runt packets. Set to 1 to accept broadcast packets, 0 to reject. Set to 1 to accept multicast packets, 0 to reject. Set to 1 to accept physical match packets, 0 to reject. Set to 1 to accept all packets with physical destination address, 0 to reject.
R/W 0 R/W 0 R/W 0 R/W 0
0xBD20_0058 Ethernet0 Media Status Register (ETH0_MSR) 0xBD30_0058 Ethernet1 Media Status Register (ETH1_MSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) FRTRSLTR TXXSP IXX XFFVENPP FCCDEKFF CEE DB Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 7 FTXFC Force Tx Flow Control: R/W 0 1 = enabled Flow control in the absence of NWAY. 0 = disables Flow control in the absence of NWAY. 6 RXFCE RX Flow control Enable: The flow control is R/W 0 enabled in full-duplex mode only. Packets are dropped if buffer is exhausted. Default is 0. 1 = Rx Flow Control Enabled. 0 = Rx Flow Control Disabled. 5 TXFCE Tx Flow Control Enable: R/W 0 1 = enable flow control ACCEPT ERRORS MUST NOT BE ENABLED 4 RSVD Reserved. R/W 0 3 SPEED Media Mode: 1 = 10 Mbps. 0 = 100Mbps. R/W 0 2 LINKB Inverse of Link status. 0 = Link OK. 1 = Link Fail. R/W 0 1 TXPF Tx Pause frame: R/W 0 1: Ethernet NIC has sent a pause packet. 0: Ethernet NIC has sent a timer done packet. 0 RXPF Pause Flag: R/W 0 1 = Ethernet NIC is in backoff state because a pause packet received. 0: pause state is clear.
0xBD20_005C Ethernet0 MII Access Register (ETH0_MIIAR) 0xBD30_005C Ethernet1 MII Access Register (ETH1_MIIAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F PHYADDR (Reserved) REGADDR DATA L A G Reset: 0x0400_0000 Bit Bit Name 31 FLAG
Description Flag bit, used to identify access to MII register: 1: Write data to MII register. Turns to 0
R/W InitVal R/W 0
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30-26 20-16 15-0
PHYADDR REGADDR DATA
automatically upon completion of MAC writing to the specified MII register. 0: Read data from MII register. Turns to 1 automatically upon completion of MAC reading the specified MII register. Read write turn around time I s about 64 us. Defines the Phy address for the MII. R/W 0x1 5-bit MII register address. R/W 0 16 bit MII resgister data. R/W 0
0xBD20_1300 Ethernet0 TX First Descriptor Pointer 1 Register (ETH0_TXFDP1) 0xBD30_1300 Ethernet1 TX First Descriptor Pointer 1 Register (ETH1_TXFDP1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxFDP1 Reset: 0x0000_0000 Bit Bit Name 31-0 TxFDP1
Description R/W InitVal High priority Tx First Descriptor Pointer to the Tx R/W 0 Ring.
0xBD20_1304 0xBD30_1304 31
Ethernet0 TX Current Descriptor Offset 1 Register (ETH0_TXCDO1) Ethernet1 TX Current Descriptor Offset 1 Register (ETH1_TXCDO1) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) TxCDO1
Reset: 0x0000_0000 Bit Bit Name 5-0 TxCDO1
Description High priority Tx Current Descriptor Offset: FDP+CDO = current descriptor pointer. CDO increments by 16 bytes each time.
R/W InitVal R/W 0
0xBD20_1380 Ethernet0 TX First Descriptor Pointer 2 Register (ETH0_TXFDP2) 0xBD30_1380 Ethernet1 TX First Descriptor Pointer 2 Register (ETH1_TXFDP2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxFDP2 Reset: 0x0000_0000 Bit Bit Name 31-0 TxFDP2
Description Tx First Descriptor Pointer to the low priority Tx Ring.
R/W InitVal R/W 0
0xBD20_1384 0xBD30_1384 31
Ethernet0 TX Current Descriptor Offset 2 Register (ETH0_TXCDO2) Ethernet1 TX Current Descriptor Offset 2 Register (ETH1_TXCDO2) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) TxCDO2
Reset: 0x0000_0000 Bit Bit Name 5-0 TxCDO2
Description Low priority Tx Current Descriptor Offset: FDP+CDO = current descriptor pointer. CDO
R/W InitVal R/W 0
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increments by 16 bytes each time.
0xBD20_13F0 Ethernet0 RX First Descriptor Pointer Register (ETH0_RXFDP) 0xBD30_13F0 Ethernet1 RX First Descriptor Pointer Register (ETH1_RXFDP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxFDP Reset: 0x0000_0000 Bit Bit Name 31-0 RxFDP
Description Rx First Descriptor Pointer to the Rx Descriptor Ring.
R/W InitVal R/W 0
0xBD20_13F4 0xBD30_13F4 31
Ethernet0 RX Current Descriptor Offset Register (ETH0_RXCDO) Ethernet1 RX Current Descriptor Offset Register (ETH1_RXCDO) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) RxCDO
Reset: 0x0000_0000 Bit Bit Name 5-0 RxCDO
Description R/W InitVal Rx Current Descriptor Offset: RxFDP+RxCDO = R/W 0 current descriptor pointer. CDO increments by 16 each time (each increment is one byte).
0xBD20_13F6 0xBD30_13F6 31
Ethernet0 RX Descriptor Ring Size Register (ETH0_RXRINGSIZE) Ethernet1 RX Descriptor Ring Size Register (ETH1_RXRINGSIZE) 876543210 (Reserved) SIZE
Reset: 0x0000_0000 Bit Bit Name 1-0 SIZE
Description This is the total number of descriptors in the Rx descriptor ring. 00: 16 descriptors 01: 32 descriptors 10: 64 descriptors
R/W InitVal R/W 0
0xBD20_1430 0xBD30_1430 31
Ethernet0 RX CPU Descriptor Number Register (ETH0_RXCPUDESC) Ethernet1 RX CPU Descriptor Number Register (ETH1_RXCPUDESC) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) W RSVD Rx_CPU_Des_Num R A P
Reset: 0x0000_0000 Bit Bit Name 8 WRAP
5-0
Description R/W InitVal This indicates to Ethernet NIC that Ethernet driver R/W 0 has allocated free RX CMD descriptors past End Of Ring. Ethernet NIC module will clear this bit when it wraps around the RX CMD descriptor ring. Rx_CPU_Des_N This is the descriptor # which the CPU has R/W 0
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um www..com finished processing and returned to IO. CPU needs to update this. When Ethernet descriptor processing reaches End Of Ring, Ethernet driver must set "WRAP" (1431h) bit to high. This will indicate to Ethernet NIC module that descriptors have been allocated past end of ring descriptor.
0xBD20_1432 0xBD30_1432 31
Ethernet0 RX PSE Descriptor Threshold Register (ETH0_RXPSEDESC) Ethernet1 RX PSE Descriptor Threshold Register (ETH1_RXPSEDESC) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) Rx_PSE_Des_Num
Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 5-0 Rx_PSE_Des_N Tx Threshold: Specifies the threshold level in the R/W 0 um Tx FIFO to begin the transmission. When the byte count of the data in the Tx FIFO reaches this level, (or the FIFO contains at least one complete packet or the end of a packet) the Ethernet NIC module will transmit this packet.
0xBD20_1434 Ethernet0 I/O Command Register (ETH0_IOCMD) 0xBD30_1434 Ethernet1 I/O Command Register (ETH1_IOCMD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) T RXPkt R (Reserved) R T T T TxInt RxInt X Timer X EEXX Mitigation Mitigation T F FF NN H T LH H Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 20-19 TXTH Tx Threshold: Specifies the threshold level in the R/W 0 Tx FIFO to begin the transmission. When the byte count of the data in the Tx FIFO reaches this level, (or the FIFO contains at least one complete packet or the end of a packet) the NIC will transmit this packet. 00: 64 bytes 01: 128 bytes 10: 256 bytes 11: Reserved TxIntMitigation This sets the number of packets received before TxOK interrupt is triggered. 000- 1 pkt 010- 3 pkt 100- 5 pkt 110- 7 pkt 001- 2 pkts 011- 4 pkts 101- 6 pkts 111- 8 pkts
18-16
R/W 0
15-13
RXPktTimer
Timer to trigger RxOK interrupt after receipt of RxIntMitigation pkts. 000 - no timer set 001 ~ 111 : the timer interval defining a multiple
R/W 0
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of 82us ex: 011 = timer interval set to 3 x 82us or 246us This only applies to packets of size larger than 128 bytes. Once RxOK is asserted the timer mechanism is reinitialized.
12-11
RXFTH
10-8
Rx FIFO Threshold: Specifies Rx FIFO Threshold R/W 0 level. When the number of the received data bytes from a packet, which is being received into the Rx FIFO, has reached to this level (or the FIFO has contained a complete packet), the Lexra bus master function will begin to transfer the data from the FIFO to the host memory. This field sets the threshold level according to the following table: 00 = no rx threshold. The NIC begins the transfer of data after having received a whole packet in the FIFO. 01 = 32 bytes 10 = 64 bytes 11 = 128 bytes RxIntMitigation This sets the number of packets received before R/W 0 RxOK interrupt is triggered. This only applies to packets of size larger than 128 bytes. Once RxOK is asserted the mitigation mechanism is reinitialized. 000- 1 pkt 001- 2 pkts 010- 3 pkts 011- 4 pkts 100- 5 pkts 101- 6 pkts 110- 7 pkts 111- 8 pkts MII Rx Enable MII Tx Enable Low Priority DMA-Ethernet Transmit enable. 1: Enable. 0: Disable. High Priority DMA-Ethernet Transmit enable. 1: Enable. 0: Disable.
3 2 1
RE TE TXFNL
R/W 0 R/W 0 R/W 0
0
TXFNH
R/W 0
10. UART Controller
RTL8186 features two 16C550 compatible UART, containing a 16-bytes FIFO on each. In addition, auto flow control is provided, in which, auto-CTS mode (CTS controls transmitter) and auto-RTS mode (Receiver FIFO contents and threshold control RTS) are both supported. The baud rate is programmable and allows division of any input reference clock by 1 to (2^16-1) and generates an internal 16x clock. RTL8186 provides fully programmable serial interface, which can be configured to support 7,8 bit characters, even, odd, no parity generation and detection, and 1 or 2 stop bit generation. Also, fully prioritized interrupt control and loopback functionality for diagnostic capability are provided.
Register Summary
Virtual address 0xBD01_00C3 0xBD01_00C3 0xBD01_00C3 Size (byte) 1 1 1 Name UART0_RBR UART0_THR UART0_DLL Description Receiver buffer register. (DLAB=0) Transmitter holding register. (DLAB=0) Divisor latch LSB. (DLAB=1) Access R W R/W
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0xBD01_00C7 1 www..com 0xBD01_00C7 0xBD01_00CB 0xBD01_00CB 0xBD01_00CF 0xBD01_00D3 0xBD01_00D7 0xBD01_00DB 0xBD01_00DF 0xBD01_00E3 0xBD01_00E3 0xBD01_00E3 0xBD01_00E7 0xBD01_00E7 0xBD01_00EB 0xBD01_00EB 0xBD01_00EF 0xBD01_00F3 0xBD01_00F7 0xBD01_00FB 0xBD01_00FF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 UART0_IER UART0_DLM UART0_IIR UART0_FCR UART0_LCR UART0_MCR UART0_LSR UART0_MSR UART0_SCR UART1_RBR UART1_THR UART1_DLL UART1_IER UART1_DLM UART1_IIR UART1_FCR UART1_LCR UART1_MCR UART1_LSR UART1_MSR UART1_SCR Interrupt enable register. (DLAB=0) Divisor latch MSB. (DLAB=1) Interrupt identification register. FIFO control register Line control register Modem control register Line status register Modem status register Scratch register Receiver buffer register. (DLAB=0) Transmitter holding register. (DLAB=0) Divisor latch LSB. (DLAB=1) Interrupt enable register. (DLAB=0) Divisor latch MSB. (DLAB=1) Interrupt identification register. FIFO control register Line control register Modem control register Line status register Modem status register Scratch register R/W R/W R W R/W R/W R/W R/W R/W R W R/W R/W R/W R W R/W R/W R/W R/W R/W
0xBD01_00C3 (DLAB = 0, Read_Mode) 0xBD01_00E3 (DLAB = 0, Read_Mode) 31
UART0 Receive Buffer Register (UART0_RBR) UART1 Receive Buffer Register (UART1_RBR) 876543210 RDATA
Reset: 0x00 0xBD01_00C3 (DLAB = 0, Write_Mode) 0xBD01_00E3 (DLAB = 0, Write_Mode) 31
UART0 Transmitter Holding Register (UART0_THR) UART1 Transmitter Holding Register (UART1_THR) 876543210 WDATA
Reset: 0x00 0xBD01_00C3 (DLAB = 1) 0xBD01_00E3 (DLAB = 1) 31
UART0 Divisor Latch LSB Register (UART0_DLL) UART1 Divisor Latch LSB Register (UART1_DLL) 876543210 DLLB
Reset: 0x00 Bit Bit Name 7-0 RDATA Bit Bit Name 7-0 WDATA Bit Bit Name 7-0 DLLB
Description Receive Data Description Write Transmit Holding Data Description Divisor Latch LSB
R/W R R/W W R/W R/W
InitVal 0 InitVal 0 InitVal 0
0xBD01_00C7 (DLAB = 0) 0xBD01_00E7 (DLAB = 0) 31
UART0 Interrupt Enable Register (UART0_IER) UART1 Interrupt Enable Register (UART1_IER) 876543210
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R S V D
EEEE LSDL PLSS PSI I
E T B E I
E R B I
Reset: 0x00 0xBD01_00C7 (DLAB = 1) 0xBD01_00E7 (DLAB = 1) 31
UART0 Divisor Latch MSB Register (UART0_DLM) UART1 Divisor Latch MSB Register (UART1_DLM) 876543210 DLMB
Reset: 0x00 Bit Bit Name 7-6 RSVD 5 ELP 4 ESLP 3 EDSSI 2 ELSI 1 ETBEI 0 ERBI Bit Bit Name 7-0 DLMB
Description Reserved Low power mode enable Sleep mode enable Enable modem status register interrupt Enable receiver line status interrupt Enable transmitter holding register empty interrupt Enable received data available interrupt Description Divisor Latch MSB
R/W R/W R/W R/W R/W R/W R/W R/W R/W
InitVal 0 0 0 0 0 0 InitVal 0
0xBD01_00CB 0xBD01_00EB 31
UART0 Interrupt Identification Register (UART0_IIR) UART1 Interrupt Identification Register (UART1_IIR) 876543210 F I I R I S I P F V D N O D D 6 4 Description 000 = no FIFO 110 = 16-byte FIFO Reserved Interrupt ID. IID[1:0] indicates the interrupt priority. Illustrated at following table: Interrupt pending 0 = interrupt pending R/W R R R R InitVal 110 0 000 0
Reset: 0xC0 Bit Bit Name 7-5 FIFO64 4 3-1 0 RSVD IID IPND
Interrupt Priority Interrupt Identification Register Bit3 Bit2 Bit1 Bit0 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 0
Priority level None 1 2 2
Interrupt type
Interrupt source
Interrupt reset method None Read LSR Read RBR.
None Receiver line status Received data available Character time-out indication
None Overrun, parity, framing errors or break DR bit is set.
No characters have been Read RBR removed from or input to FIFO during the last character times and at 1 character in it.
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0 0 1 0 www..com 0 0 0 0 3 THRE bit set. Transmitter holding register empty Modem status CTS#,DSR#,RI#,DCD# Reading IIR or write THR Reading MSR
4
0xBD01_00CB 0xBD01_00EB 31
UART0 FIFO Control Register (UART0_FCR) UART1 FIFO Control Register (UART1_FCR) 876543210 TRE R R S T FFF V R RRI D G SSF TTO Description Receiver trigger level Trigger level: 16-byte 00 = 01 01 = 04 10 = 08 11 = 14 Reserved R/W W InitVal 11
Reset: 0xC0 Bit Bit Name 7-6 RTRG
3-5 2 1 0
RSVD TFRST RFRST EFIFO
Transmitter FIFO reset. Writes 1 to clear the W transmitter FIFO. Receiver FIFO reset. Writes 1 to clear the receiver W FIFO. Enable FIFO. When this bit is set, enable the W transmitter and receiver FIFO. Changing this bit clears the FIFO.
0 0 0
0xBD01_00CF 0xBD01_00EF 31
UART0 Line Control Register (UART0_LCR) UART1 Line Control Register (UART1_LCR) 876543210 DB E PS W LR P ET L AK S NB S B Description Divisor latch access bit. Break control. Set this bit force TXD to the spacing (low) state.(break) Clear this bit to disable break condition. Even parity select 00 = odd parity 01 = even parity 10 = mark parity 11 = space parity Parity enable Number of stop bits 0 = 1 bit 1 = 2 bits Word length select 10 = 7 bits R/W R/W R/W InitVal 0 0
Reset: 0x03 Bit Bit Name 7 DLAB 6 BRK
5-4
EPS[1:0]
R/W
0
3 2
PEN STB
R/W R/W
0 0
1-0
WLS[1:0]
R/W
11
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11 = 8 bits
0xBD01_00D3 0xBD01_00F3 31
UART0 Modem Control Register (UART0_MCR) UART1 Modem Control Register (UART1_MCR) 876543210 R AL R RR S FO S TS V EO V SV D D P D Description Reserved Auto flow control enable Loopback Reserved Request to send 0 = Set RTS# high 1 = Set RTS# low Reserved R/W R/W R/W R/W InitVal 0 0 0
Reset: 0x00 Bit Bit Name 7-6 RSVD 5 AFE 4 LOOP 2-3 RSVD 1 RTS
0
RSVD
0xBD01_00D7 0xBD01_00F7 31
UART0 Line Status Register (UART0_LSR) UART1 Line Status Register (UART1_LSR) 876543210 RTTBFPOD FEHIEEER EMR TE Description Errors in receiver FIFO. At least one parity, framing and break error in the FIFO. Transmitter empty Character mode: both THR and TSR are empty. FIFO mode: both transmitter FIFO and TSR are empty Transmitter holding register empty. Character mode: THR is empty. FIFO mode: transmitter FIFO is empty Break interrupt indicator Framing error Parity error Overrun error. An overrun occurs when the receiver FIFO is full and the next character is completely received in the receiver shift register. An OE is indicated. The character in the shift register will be overwritten. Data ready. Character mode: data ready in RBR FIFO mode: receiver FIFO is not empty. R/W R R InitVal 0 0
Reset: 0x00 Bit Bit Name 7 RFE 6 TEMT
5
THRE
R
0
4 3 2 1
BI FE PE OE
R R R R
0 0 0 0
0
DR
R
0
0xBD01_00DB 0xBD01_00FB 31
UART0 Modem Status Register (UART0_MSR) UART1 Modem Status Register (UART1_MSR) 876543210
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DRDC CIST D RS
R S V D
C T S
Reset: 0x00 Bit Bit Name 7 DCD 6 5 4 RI DSR CTS
3-1 0
RSVD CTS
Description In loopback mode, returns the bit 2 of MCR. In normal mode, returns 1. In loopback mode, returns the bit 3 of MCR. In normal mode, returns 0. In loopback mode, returns the bit 0 of MCR In normal mode, returns 1. Clear to send. 0 = CTS# detected high 1 = CTS# detected low Reserved Delta clear to send. CTS# signal transits.
R/W R R R R
InitVal 1 0 1 0
R
0
11. Timer & Watchdog
There are four sets of hardware timers and one watchdog timer. Each timer can be configured as timer mode or counter mode. In both counter and timer mode, the time value is counted down from the initial value to zero (the value is reduced one for every timer clock). When the value reaches zero, the timer stops and an interrupt is issued. When an interrupt is issued in timer mode, the time value will be reset to its initial value and the count down will restart. An interrupt will be issued whenever the count down value reaches zero. The source clock of timer could be configured to use base clock directly, or based on the base clock divided by a configurable register value - CDBR. When watchdog timer is enabled, it will cause a system reset when a time-out occurs. The time-out interval may be set in the registers. The time unit value is based on the base clock divided by the base value, which is the same used by all timer.
Register Summary
Virtual address 0xBD01_0050 0xBD01_0054 0xBD01_0058 0xBD01_005C 0xBD01_0060 0xBD01_0064 0xBD01_0068 0xBD01_006C 0xBD01_0070 0xBD01_0074 0xBD01_0078 0xBD01_007C Size (byte) 2 1 2 2 3 3 4 4 3 3 4 4 Name TCCNR TCIR CDBR WDTCNR TC0DATA TC1DATA TC2DATA TC3DATA TC0CNT TC1CNT TC2CNT TC3CNT Description Timer/Counter control register Timer/Counter interrupt register Clock division base register Watchdog timer control register Timer/Counter 0 data register. It specifies the time-out duration. Timer/Counter 1 data register. It specifies the time-out duration. Timer/Counter 2 data register. It specifies the time-out duration. Timer/Counter 3 data register. It specifies the time-out duration. Timer/Counter 0 count register Timer/Counter 1 count register Timer/Counter 2 count register Timer/Counter 3 count register Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R
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0xBD01_0050 www..com 31 Timer/Counter Control register (TCCNR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) TTTTTTTTTTTT CCCCCCCCCCCC 321033221100 S S S SMEMEMEME R RRRONONONON CCCCD D D D E E E E Description Timer/Counter 3 clock source 0=Base clock 1=Basic timer Timer/Counter 2 clock source 0=Base clock 1=Basic timer Timer/Counter 1 clock source 0=Base clock 1=Basic timer Timer/Counter 0 clock source 0=Base clock 1=Basic timer Timer/Counter 3 mode 0=counter mode 1=timer mode Timer/Counter 3 enable Timer/Counter 2 mode 0=counter mode 1=timer mode Timer/Counter 2 enable Timer/Counter 1 mode 0=counter mode 1=timer mode Timer/Counter 1 enable Timer/Counter 0 mode 0=counter mode 1=timer mode Timer/Counter 0 enable R/W R/W InitVal 0
Reset: 0x0000_0000 Bit Bit Name 11 TC3SRC
10
TC2SRC
R/W
0
9
TC1SRC
R/W
0
8
TC0SRC
R/W
0
7
TC3MODE
R/W
0
6 5
TC3EN TC2MODE
R/W R/W
0 0
4 3
TC2EN TC1MODE
R/W R/W
0 0
2 1
TC1EN TC0MODE
R/W R/W
0 0
0
TC0EN
R/W
0
0xBD01_0054 31
Timer/Counter Interrupt Register (TCIR) 876543210 TTTTTTTT CCCCCCCC 32103210 IIIIIIII PPPPEEEE Description Timer/Counter 3 interrupt pending. Write "1" to clear the interrupt. Timer/Counter 2 interrupt pending. Write "1" to clear the interrupt. Timer/Counter 1 interrupt pending. Write "1" to clear the interrupt. Timer/Counter 0 interrupt pending. Write "1" to clear the interrupt. R/W R/W R/W R/W R/W InitVal 0 0 0 0
Reset: 0x00 Bit Bit Name 7 TC3IP 6 5 4 TC2IP TC1IP TC0IP
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3 TC3IE www..com 2 1 0 TC2IE TC1IE TC0IE Timer/Counter 3 interrupt enable Timer/Counter 2 interrupt enable Timer/Counter 1 interrupt enable Timer/Counter 0 interrupt enable R/W R/W R/W R/W 0 0 0 0
0xBD01_0058 31
Clock Division Base Register (CDBR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DivFactor
Reset: 0x0000_0000 Bit Bit Name 15-0 DivFactor
Description R/W The divide factor of clock source. If the DivFactor R/W is N, the watchdog timer is divided by N+1. This value cannot be 0 in timer or watchdog mode. The clock source is 22MHz.
InitVal 0
0xBD01_005C 31
Watchdog Control Register (WDTCNR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) OW WDTE V D S T C E L L R Description Overflow select. These bits specify the overflow condition when the watchdog timer counts to the value. 00 = 213 01 = 214 10 = 215 11 = 216 Watchdog clear. Write a 1 to clear the watchdog counter. It is auto cleared after the write. Watchdog enable. When these bits are set to 0xA5, the watchdog timer stops. Other value can enable the watchdog timer and cause a system reset when an overflow signal occurs. R/W R/W InitVal 00
Reset: 0x00A5 Bit Bit Name 10-9 OVSEL
8 7-0
WDTCLR WDTE
W W
0 0xA5
0xBD01_0060 Timer/Counter 0 Data register (TC0DATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) TC0Data Reset: 0x0000_0000 Bit Bit Name 23-0 TC0Data
Description Timer/Counter 0 data register. It specifies the time-out duration.
R/W R/W
InitVal 0
0xBD01_0064 Timer/Counter 1 Data register (TC1DATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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(Reserved) www..com Reset: 0x0000_0000 Bit Bit Name 23-0 TC1Data TC1Data
Description Timer/Counter 1 data register. It specifies the time-out duration.
R/W R/W
InitVal 0
0xBD01_0068 Timer/Counter 2 Data register (TC2DATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2Data Reset: 0x0000_0000 Bit Bit Name 31-0 TC2Data
Description Timer/Counter 2 data register. It specifies the time-out duration.
R/W R/W
InitVal 0
0xBD01_006C Timer/Counter 3 Data register (TC3DATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC3Data Reset: 0x0000_0000 Bit Bit Name 31-0 TC3Data
Description Timer/Counter 3 data register. It specifies the time-out duration.
R/W R/W
InitVal 0
0xBD01_0070 Timer/Counter 0 Counter register (TC0CNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) TC0Value Reset: 0x0000_0000 Bit Bit Name 23-0 TC0Value
Description The timer or counter initial value
R/W R/W
InitVal 0
0xBD01_0074 Timer/Counter 1 Counter register (TC1CNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) TC1Value Reset: 0x0000_0000 Bit Bit Name 23-0 TC1Value
Description The timer or counter initial value
R/W R/W
InitVal 0
0xBD01_0078 Timer/Counter 2 Counter register (TC2CNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2Value Reset: 0x0000_0000 Bit Bit Name 31-0 TC2Value
Description The timer or counter initial value
R/W R/W
InitVal 0
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0xBD01_007C Timer/Counter 3 Counter register (TC3CNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC3Value Reset: 0x0000_0000 Bit Bit Name 31-0 TC3Value
Description The timer or counter initial value
R/W R/W
InitVal 0
12. GPIO Control
RTL8186 provides seven sets of GPIO pins - PortA , PortB, PortC, PortD, PortE, PortF, and PortG. Every GPIO pin can be configured as input or output pins via register PxDIR. Register PxDATA could be used to control the signals (high or low) of GPIO pins. Only the GPIO PortA and PortF have dedicated pins, the others are shared pins with other functions. Following table illustrates the GPIO PortX pin-out and their mux-ed function pins. GPIO Group Pins Shared Function Pins Available Package GPBPIN[0] CTS0PIN Both GPBPIN[1] RTS0PIN Control Mechanism In 208 QFP package: ICFG[12] = 1 and ICFG[11] = 0 to enable the GPIOB function, else disable GPIOB. In 256 BGA package: ICFG[12] = 1 to enable the GPIOB function, else disable GPIOB. In both package, ICFG[12] = 1 to enable the GPIOB function, else disable GPIOB. In both package, ICFG[13] = 1 to enable the GPIOC function, else disable GPIOC.
GPBPIN[2] GPBPIN[3] GPCPIN[0] GPCPIN[1] GPCPIN[2] GPCPIN[3] GPCPIN[4] GPCPIN[5] GPCPIN[6] GPCPIN[7] GPCPIN[8] GPCPIN[9] GPCPIN[10] GPCPIN[11] GPCPIN[12] GPCPIN[13] GPCPIN[14] GPCPIN[15] GPDPIN[0] GPDPIN[1] GPDPIN[2] GPDPIN[3] GPDPIN[4]
SIN0PIN SOUT0PIN MDPIN[16] MDPIN[17] MDPIN[18] MDPIN[19] MDPIN[20] MDPIN[21] MDPIN[22] MDPIN[23] MDPIN[24] MDPIN[25] MDPIN[26] MDPIN[27] MDPIN[28] MDPIN[29] MDPIN[30] MDPIN[31] WRXCPIN WRXDPIN[0] WRXDPIN[1] WRXDPIN[2] WRXDPIN[3]
Both Both
Both Both
GPDPIN[5] GPDPIN[6] GPDPIN[7] GPDPIN[8] GPDPIN[9]
WRXDVPIN WTXCPIN WTXEPIN WTXDPIN[0] WTXDPIN[1]
Both
In both package, SYSCFG[14] = 1 to enable GPIOD function, else disable GPIOD In 208 QFP package: SYSCFG[14] = 1 and SYSCFG[10] = 0 to enable GPIOD function, else disable GPIOD. In 256 BGA package: SYSCFG[14] = 1 to enable GPIOD function, else disable GPIOD. In both package, SYSCFG[14] = 1 to enable GPIOD function, else disable GPIOD
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GPDPIN[10] www..com WTXDPIN[2] GPDPIN[11] GPDPIN[12] GPDPIN[13] GPDPIN[14] GPEPIN[0] GPEPIN[1] GPEPIN[2] GPEPIN[3] GPEPIN[4] GPEPIN[5] GPEPIN[6] GPGPIN[0] GPGPIN[1] GPGPIN[2] GPGPIN[3] GPGPIN[4] GPGPIN[5] GPGPIN[6] GPGPIN[7] GPGPIN[8] GPGPIN[9] GPGPIN[10] GPGPIN[11] GPGPIN[12] GPGPIN[13] GPGPIN[14] GPGPIN[15] GPGPIN[16] GPGPIN[17] GPGPIN[18] GPGPIN[19] GPGPIN[20] GPGPIN[21] GPGPIN[22] GPGPIN[23] GPGPIN[24] GPGPIN[25] GPGPIN[26] GPGPIN[27] GPGPIN[28] GPGPIN[29] GPGPIN[30] GPGPIN[31] WTXDPIN[3] WCOLPIN WMDIOPIN WMDCPIN NAFBUSYBPIN NAFCLEPIN NAFALEPIN MCSPIN[4] MCSPIN[5] NAFWEBPIN NAFREBPIN PCIADPIN[0] PCIADPIN[1] PCIADPIN[2] PCIADPIN[3] PCIADPIN[4] PCIADPIN[5] PCIADPIN[6] PCIADPIN[7] PCIADPIN[8] PCIADPIN[9] PCIADPIN[10] PCIADPIN[11] PCIADPIN[12] PCIADPIN[13] PCIADPIN[14] PCIADPIN[15] PCIADPIN[16] PCIADPIN[17] PCIADPIN[18] PCIADPIN[19] PCIADPIN[20] PCIADPIN[21] PCIADPIN[22] PCIADPIN[23] PCIADPIN[24] PCIADPIN[25] PCIADPIN[26] PCIADPIN[27] PCIADPIN[28] PCIADPIN[29] PCIADPIN[30] PCIADPIN[31]
Both
In both package, SYSCFG[15] = 1 to enable GPIOE function, else disable GPIOE
256 BGA
In 256 BGA package, SYSCFG[16] = 1 to enable GPIOG, else disable GPIOG.
Register Summary
Virtual address 0xBD01_0120 0xBD01_0124 0xBD01_0128 0xBD01_012C 0xBD01_0130 0xBD01_0134 0xBD01_0138 0xBD01_013C 0xBD01_0140 Size (byte) 4 4 4 4 4 4 4 4 4 Name GPABDATA GPABDIR GPABIMR GPABISR GPCDDATA GPCDDIR GPCDIMR GPCDISR GPEFDATA Description Port A/B data register Port A/B direction register Port A/B interrupt mask register Port A/B interrupt status register Port C/D data register Port C/D direction register Port C/D interrupt mask register Port C/D interrupt status register Port E/F data register Access R/W R/W R/W R/W R/W R/W R/W R/W R/W
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0xBD01_0144 4 www..com 0xBD01_0148 0xBD01_014C 0xBD01_0150 0xBD01_0154 0xBD01_0158 0xBD01_015C 4 4 4 4 4 4 GPEFDIR GPEFIMR GPEFISR GPGDATA GPGDIR GPGIMR GPGISR Port E/F direction register Port E/F interrupt mask register Port E/F interrupt status register Port G data register Port G direction register Port G interrupt mask register Port G interrupt status register R/W R/W R/W R/W R/W R/W R/W
0xBD01_0120 GPIO Port A/B DATA Register (GPABDATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) DATAB (Reserved) DATAA Reset: 0x0000_0000 Bit Bit Name 19-16 DATAB 10-0 DATAA
Description Pin data of Port B Pin data of Port A
R/W R/W R/W
InitVal 00 00
0xBD01_0124 GPIO Port A/B Direction Register (GPABDIR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) DRCB (Reserved) DRCA Reset: 0x0000_0000 Bit Bit Name 19-16 DRCB
10-0
DRCA
Description Pin direction configuration of Port B 0 = configured as input pin 1 = configured as output pin Pin direction configuration of Port A 0 = configured as input pin 1 = configured as output pin
R/W R/W
InitVal 00
R/W
00
0xBD01_0128 GPIO Port A/B Interrupt Mask Register (GPABIMR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) BIMR (Reserved) AIMR Reset: 0x0000_0000 Bit Bit Name Description 19-16 BIMR PortB interrupt enable 0 = disable interrupt 1 = enable interrupt 10-0 AIMR PortA interrupt enable 0 = disable interrupt 1 = enable interrupt
R/W R/W
InitVal 00
R/W
00
0xBD01_012C GPIO Port A/B Interrupt Status Register (GPABISR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) BISR (Reserved) AISR Reset: 0x0000_0000 Bit Bit Name Description 19-16 BISR GPIO B interrupt pending status. Write `1' to clear interrupt pending status.
R/W R/W
InitVal 0
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15-0 AISR www..com GPIO A interrupt pending status. Write `1' to clear interrupt pending status. R/W 0
0xBD01_0130 31 30 29 28 27 26 R S V D Reset: 0x0000_0000 Bit Bit Name 30-16 DATAD 15-0 DATAC
GPIO Port C/D DATA Register (GPCDDATA) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAD DATAC
Description Pin data of Port D Pin data of Port C
R/W R/W R/W
InitVal 00 00
0xBD01_0134 GPIO Port C/D Direction Register (GPCDDIR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DRCD DRCC S V D Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 30-16 DRCD Pin direction configuration of Port D R/W 00 0 = configured as input pin 1 = configured as output pin 15-0 DRCC Pin direction configuration of Port C R/W 00 0 = configured as input pin 1 = configured as output pin
0xBD01_0138 GPIO Port C/D Interrupt Mask Register (GPCDIMR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DIMR CIMR S V D Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 30-16 DIMR PortD interrupt enable R/W 0 0 = disable interrupt 1 = enable interrupt 15-0 CIMR PortC interrupt enable R/W 0 0 = disable interrupt 1 = enable interrupt
0xBD01_013C GPIO Port C/D Interrupt Status Register (GPCDISR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DISR CISR Reset: 0x0000_0000 Bit Bit Name Description 30-16 DISR GPIO D interrupt pending status. Write `1' to clear interrupt pending status. 15-0 CISR GPIO C interrupt pending status. Write `1' to clear
R/W R/W R/W
InitVal 0 0
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interrupt pending status.
0xBD01_0140 GPIO Port E/F DATA Register (GPEFDATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) DATAF (Reserved) DATAE Reset: 0x0000_0000 Bit Bit Name 21-16 DATAF 6-0 DATAE
Description Pin data of Port F Pin data of Port E
R/W R/W R/W
InitVal 00 00
0xBD01_0144 GPIO Port E/F Direction Register (GPEFDIR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) DRCF (Reserved) DRCE Reset: 0x0000_0000 Bit Bit Name 21-16 DRCF
6-0
DRCE
Description Pin direction configuration of Port F 0 = configured as input pin 1 = configured as output pin Pin direction configuration of Port E 0 = configured as input pin 1 = configured as output pin
R/W R/W
InitVal 00
R/W
00
0xBD01_0148 GPIO Port E/F Interrupt Mask Register (GPEFIMR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) FIMR (Reserved) EIMR Reset: 0x0000_0000 Bit Bit Name Description 21-16 FIMR PortF interrupt enable 0 = disable interrupt 1 = enable interrupt 6-0 EIMR PortE interrupt enable 0 = disable interrupt 1 = enable interrupt
R/W R/W
InitVal 00
R/W
00
0xBD01_014C GPIO Port E/F Interrupt Status Register (GPEFISR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (Reserved) FISR (Reserved) EISR Reset: 0x0000_0000 Bit Bit Name Description 21-16 BISR GPIO F interrupt pending status. Write `1' to clear interrupt pending status. 6-0 AISR GPIO E interrupt pending status. Write `1' to clear interrupt pending status.
R/W R/W R/W
InitVal 0 0
0xBD01_0150 GPIO Port G DATA Register (GPGDATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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DATAG
Reset: 0x0000_0000 Bit Bit Name 31-0 DATAG
Description Pin data of Port G
R/W R/W
InitVal 00
0xBD01_0154 GPIO Port G Direction Register (GPGDIR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRCG Reset: 0x0000_0000 Bit Bit Name 31-0 DRCG
Description Pin direction configuration of Port G 0 = configured as input pin 1 = configured as output pin
R/W R/W
InitVal 0
0xBD01_0158 GPIO Port G Interrupt Mask Register (GPGIMR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GIMR Reset: 0x0000_0000 Bit Bit Name Description 31-0 GIMR PortG interrupt enable 0 = disable interrupt 1 = enable interrupt
R/W R/W
InitVal 00
0xBD01_015C GPIO Port G Interrupt Status Register (GPGISR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GISR Reset: 0x0000_0000 Bit Bit Name Description 31-0 GISR GPIO G interrupt pending status. Write `1' to clear interrupt pending status.
R/W R/W
InitVal 0
13. IPSec Crypto Engine
The RTL8186 implements an AES/DES/3DES/HMAC-SHA-1/HMAC-MD5 crypto engine to accelerate the packet processing speed when IPSec is enabled within communication protocol. These crypto algorithms can be applied to AH or ESP protocol according to the requirement of security policy. The security engine uses descriptor based access mechanism to service software request. Two descriptor rings are implemented, one called as Source Crypto Descriptors, specifying the source data for encryption/ decryption, and the other one is Destination Crypto Descriptor, defining the output data of encryption/decryption. The Crypto Engine supports AES/DES/3DES algorithm to operate in both of the two modes: Electronic Code Block (ECB) and Cipher Block Chaining (CBC). The mode applied to the algorithm was specified at descriptor field. The Crypto Engine supports IV and Key management in descriptor-based manner, these IV and keys are well-organized data structure named Key Array Element. The Crypto Engine loads the keys and IV from the first descriptor of the packet, which the FS field is `1'. The key array resided at system memory and has no alignment limitation.
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To accommodate the fragmentation in IP standard, the Destination Crypto Descriptor supports fragment gathering DMA behavior. The cipher text can overwrite plaintext by setting DDBP field in Destination Crypto Descriptor identical to the SDBP in Source Crypto Descriptor. Number of the Destination Crypto Descriptors is limited to 64, but it is unlimited in the descriptor number of Source Crypto Descriptor.
Descriptor Data Structures used in Crypto Engine n
Payload format diagram
SBDL = sum of each (SBL) AUL (Max 1720) ENL Key Array Element
K1 K2 K3 IV OPAD IPAD
IPSec Header
Encryption Data
HMAC Padding
A2EO
DDL
n
Source Crypto Descriptor
10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
ORFLR WS SSS NV V D D
Authentication Length, AUL (11 bits)
MS M 3 A (2 D D E bit) 5 E S S KAM C R (3 bits) B S CV D
Destination DMA Length, DDL (11 bits)
Offset 0
Destination Descriptor Index, DDI (8 bits)
Authentication to Encryption Offset, A2EO (8 bits)
Encryption Length, ENL (11 bits)
Offset 4
Offset 8 Source Data Buffer Pointer, SDBP
RSVD (5 bits)
Source Buffer DMA Length, SBDL (11 bits)
RSVD (5 bits)
Source Buffer Length, SBL (11 bits)
Offset 12
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Next Descriptor Address Pointer, NDAP
Offset 16
Offset# 0
Bit# 31
Symbol OWN
Description When set, indicates that the Source Crypto Descriptor is owned by IPSec Crypto Engine. When cleared, indicates that the Source Crypto Descriptor is owned by host system. IPSec Crypto Engine clears this bit when the relative buffer data is already encrypted or decrypted. Value 0 1 Reserved. Meaning Descriptor own by host system Descriptor own by IPSec
0 0
30 29
RSVD FS
First Segment. Value 1 Meaning This is the first Source Crypto Descriptor of an IP packet; the SDBP pointes to the physical address of Key Array Element of this packet. This is NOT the first Source Crypto Descriptor of an IP Packet.
0
0
28
LS
Last Segments. Meaning This is the last Source Crypto Descriptor of the packet. 0 This is NOT the last Source Crypto Descriptor of the packet. Authentication Length. If authentication algorithm such as SHA-1/MD5 is applied, this is the byte length that the authentication algorithm should process. Mode Select. Value Meaning 00 Use DES or 3DES ESP algorithm. 01 Use SHA-1 or MD5 AH algorithm. 10 SHA-1/MD5 then DES/3DES 11 DES/3DES then SHA-1/MD5 MD5 algorithm selected. `1': Use MD5 in AH algorithm. `0': Use SHA-1 in AH algorithm. 3DES algorithm selected. Effective only when AES bit is `0'. `1': Use 3DES in ESP algorithm. `0': Use DES in ESP algorithm. AES algorithm selected. Apply Encrypt/Decrypt (depends on AESAG) algorithm to do ESP. `1': Use AES in ESP algorithm. `0': Use DES or 3DES (depends on 3DES filed) in ESP algorithm. Destination Data Length. This value is the length of the write-back packet that processed by the crypto engine. Destination Descriptor Index. This is an index value used to identify the relationship of Source Crypto Descriptor and Destination Crypto Value 1
0
26-16
AUL
0
15-14
MS
0
13
MD5
0
12
3DES
0
11
AES
0 4
10-0 31-24
DDL DDI
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4
23-16
A2EO
4
15-13
KAM
Descriptor. When the crypto engine processed the Source Crypto Descriptor, it would write this index value back to the current Destination Crypto Descriptor that crypto engine consumed. Authentication to Encryption Offset. This is the byte-offset value between the data applied to authentication and encryption. This value must be 4-byte aligned. Key Applied Mechanism. This field specified the mechanism used when 3DES encryption is selected. Value Meaning 000 Decrypt with K1, K2, K3 010 Decrypt with K1, encrypt with K2, decrypt with K3 101 Encrypt with K1, decrypt with K2, encrypt with K3 111 Encrypt with K1, K2, K3 K1, K2, and K3 are Key1, Key2, Key3 used in 3DES algorithm. CBC mode in 3DES algorithm selected. `1': Use CBC mode in 3DES ESP algorithm. `0': Use EBC in 3DES ESP algorithm. Reserved.. Encryption data Length. This is the length of encryption data in byte. Source Data Buffer Pointer. This pointer points to the physical address of source data buffer. If FS = `1', this pointer points to the Key Array Element of the packet. Source Buffer DMA Length. This field takes effect only when FS field is set to `1'. SBDL is the DMA byte count of a packet, which may comprise from several descriptors. Source Buffer Length. This is the length of source data buffer in byte in each descriptor. Next Descriptor Address. This is the physical address pointer to next descriptor. If This field contains all zero, then this is the end of the descriptor list.
2
12
CBC
2 4 8
11 10-0 31-0
RSVD ENL SDBP
12
26-16
SBDL
12
10-0
SBL
16
31-0
NXTDA
n
Destination Crypto Descriptor (OWN = 1)
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OE WO NR = 1
Reserved (19 bits)
Destination Buffer Length, DBL (11 bits)
Offset 0
Reserved
Offset 4
Offset 8 Destination Data Buffer Pointer, DDBP
Reserved
Offset 12
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Reserved Reserved Reserved Reserved
Offset 16 Offset 20 Offset 24 Offset 28
Offset# 0
Bit# 31
Symbol OWN
Description When set, indicates that the Destination Crypto Descriptor is owned by IPSec Crypto Engine. When cleared, indicates that the Destination Crypto Descriptor is owned by host system. IPSec Crypto Engine clears this bit when the destination buffer is filled with encrypted or decrypted data. End Of Ring. When set, indicates this descriptor is at the end of the descriptor ring. Destination Buffer Length. This is the available length of destination buffer in this descriptor. Destination Data Buffer Pointer. This is the destination data buffer physical starting address.
0 0 8
30 10-0 31-0
EOR DBL DDBP
n
Destination Crypto Descriptor (OWN = 0)
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OEFLR WO S S S NR V D
Authentication Length, AUL (11 bits)
MS M 3 R (2 D D S bit) 5 E V SD KAM C R (3 bits) B S CV D
Destination DMA Length, DDL (11 bits)
Offset 0
Destination Descriptor Index, DDI (8 bits)
Authentication to Encryption Offset, A2EO (8 bits)
Encryption Length, ENL (11 bits)
Offset 4
Offset 8 Destination Data Buffer Pointer, DDBP
ICV (for SHA-1, ICV = 160 bits; for MD5, ICV = 128 bits)
Offset 12 Offset 16 Offset 20 Offset 24 Offset 28
Offset#
Bit#
Symbol
Description
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0 31 OWN www..com When set, indicates that the Destination Crypto Descriptor is owned by IPSec Crypto Engine. When cleared, indicates that the Destination Crypto Descriptor is owned by host system. IPSec Crypto Engine clears this bit when the relative buffer data is already encrypted or decrypted. Value Meaning 0 Descriptor own by host system 1 Descriptor own by IPSec End of descriptor Ring. When set, this is the last descriptor of the ring. First Segment. Value 1 0 Meaning This is the first Destination Crypto Descriptor of an IP packet. This is NOT the first Destination Crypto Descriptor of an IP Packet.
0 0
30 29
EOR FS
0
28
LS
Last Segments. Meaning This is the last Destination Crypto Descriptor of the packet. 0 This is NOT the last Destination Crypto Descriptor of the packet. Authentication Length. If authentication algorithm such as SHA-1/MD5 is applied, this is the byte length that the authentication algorithm had processed. Mode Select. Value Meaning 00 Use DES or 3DES ESP algorithm. 01 Use SHA-1 or MD5 AH algorithm. 10 SHA-1/MD5 then DES/3DES 11 DES/3DES then SHA-1/MD5 MD5 algorithm selected. `1': Use MD5 in AH algorithm. `0': Use SHA-1 in AH algorithm. 3DES algorithm selected. `1': Use 3DES in ESP algorithm. `0': Use DES in ESP algorithm. Destination Data Length. This value is the length of the write-back packet that processed by the crypto engine. Destination Descriptor Index. This value is copied from Source Crypto Descriptor that output to this destination descriptor. Authentication to Encryption Offset. This is the byte-offset value between the data applied to authentication and encryption. This value must be 4-byte aligned. Key Applied Mechanism. This field specified the mechanism used when 3DES encryption is selected. Value Meaning 000 Decrypt with K1, K2, K3 010 Decrypt with K1, encrypt with K2, decrypt with K3 101 Encrypt with K1, decrypt with K2, encrypt with K3 111 Encrypt with K1, K2, K3 K1, K2, and K3 are Key1, Key2, Key3 used in 3DES algorithm. Value 1
0
26-16
AUL
0
15-14
MS
0
13
MD5
0
12
3DES
0 4 4
10-0 31-24 23-16
DDL DDI A2EO
4
15-13
KAM
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4 12 CBC www..com CBC mode in 3DES algorithm selected. `1': Use CBC mode in 3DES ESP algorithm. `0': Use EBC in 3DES ESP algorithm. Encryption data Length. This is the length of encrypted data in byte. Destination Data Buffer Pointer. This pointer points to the physical address of destination data buffer. Integrity Check Value. This is the result of HMAC-SHA-1 or HMAC-MD5. If SHA-1 is used, the length of ICV is 160 bits. If MD5 is used, the length of ICV is 128 bits.
4 8 12-31
10-0 31-0 31-0
ENL DDBP ICV
n
Key Array Element
K1L, Key 1 Left Part K1R, Key 1 Right Part K2L, Key 2 Left Part K2R, Key 2 Right Part K3L, Key 3 Left Part K3R, Key 3 Right Part IVL, IV Left Part IVR, IV Right Part OPAD IPAD Offset 0 Offset 4 Offset 8 Offset 12 Offset 16 Offset 20 Offset 24 Offset 28 Offset 32-95 Offset 96-159
Offset# 0
Bit# 31-0
Symbol K1L
Description 3DES/DES: Key 1 Left Part. AES: First four bytes of the key Note: For AES decryption, the key is the decryption round 1 key. 3DES/DES: Key 1 Right Part. AES: Second four bytes of the key. Note: For AES decryption, the key is the decryption round 1 key. 3DES: Key 2 Left Part. AES: Third four bytes of the key. Note: For AES decryption, the key is the decryption round 1 key. 3DES: Key 2 Right Part. AES: Fourth four bytes of the key. Note: For AES decryption, the key is the decryption round 1 key. 3DES: Key 3 Left Part. AES: First four bytes of the IV. 3DES: Key 3 Right Part. AES: Second four bytes of the IV.
4
31-0
K1R
8
31-0
K2L
12
31-0
K2R
16 20
31-0 31-0
K3L K3R
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24 31-0 IVL www..com 28 32-95 96-159 31-0 31-0 31-0 IVR OPAD IPAD 3DES/DES: IV Left Part. AES: Third four bytes of the IV. 3DES/DES: IV Right Part. AES: Fourth four bytes of the IV. In SHA-1/MD5, these 64 bytes are output padding XOR-ed with key. In SHA-1/MD5, these 64 bytes are input padding XOR-ed with key.
Register Summary
Virtual address 0xBD10_0000 0xBD10_0004 0xBD10_0008 0xBD10_0009 0xBD10_000A 0xBD10_000B 0xBD10_000C Size (byte) 4 4 1 1 1 1 4 Name IPSSDAR IPSDDAR IPSCFR IPSCR IPSIMR IPSISR IPSCTR Description IPSec Source Descriptor Starting Address Register IPSec Destination Descriptor Starting Address Register IPSec Configuration Register IPSec Command Register IPSec Interrupt Mast Register IPSec Interrupt Status Register IPSec Control Register Access R/W R/W R/W R/W R/W R/W R/W
0xBD10_0000 IPSec Source Descriptor Starting Address Register (IPSSDAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDSA Reset: 0x0000_0000 Bit Bit Name 31-0 SDSA
Description Source Descriptor Starting Address. This is the physical address of first available Source Crypto Descriptor. The address should be 256 byte aligned.
R/W InitVal R/W 0
0xBD10_0004 IPSec Destination Descriptor Starting Address Register (IPSDDAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDSA Reset: 0x0000_0000 Bit Bit Name 31-0 DDSA
Description Destination Descriptor Starting Address. This is the physical address of first available Destination Crypto Descriptor.
R/W InitVal R/W 0
0xBD10_0008 31
IPSec Configuration Register (IPSCFR) 876543210 R CLCC S FBKE V EKEE D M Description Configuration Register Enable. Set `1' to enable the configuration to IPSCTR register. Loopback mode enable. Set `1' to enable loop R/W InitVal R/W 0 R/W 0
Reset: 0x00 Bit Bit Name 3 CFE 2 LBKM
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1 0
CKE CEE
mode of the crypto engine. This will override the command setting in the descriptor. Clock Enable. Set `1' to enable the crypto engine R/W 0 clock. Crypto Engine Enable. Set `1' to enable the crypto R/W 0 engine.
0xBD10_0009 31
IPSec Command Register (IPSCR) 876543210 Reserved P O L L Description R/W InitVal Descriptor Polling. Set this bit to `1' will kick the R/W 0 crypto engine to fetch the first Source Descriptor pointed by IPSSDAR register.
Reset: 0x00 Bit Bit Name 0 POLL
0xBD10_000A 31
IPSec Interrupt Mask Register (IPSIMR) 876543210 SDD BDD FUO EEK Description Source Buffer Full Error Interrupt Mask. 1: Enable 0: Disable Destination Descriptor Unavailable Error Interrupt Mask. 1: Enable 0: Disable Destination Descriptor OK Interrupt Mask. 1: Enable 0: Disable R/W InitVal R/W 0
Reset: 0x00 Bit Bit Name 2 SBFE
1
DDUE
R/W 0
0
DDOK
R/W 0
0xBD10_000B 31
IPSec Interrupt Status Register (IPSISR) 876543210 SDD BDD FUO EEK Description Source Buffer Full Error Interrupt. Write `1' to clear. Destination Descriptor Unavailable Error Interrupt. Write `1' to clear. Destination Descriptor OK Interrupt. Write `1' to clear. R/W InitVal R/W 0 R/W 0 R/W 0
Reset: 0x00 Bit Bit Name 2 SBFE 1 0 DDUE DDOK
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0xBD10_000C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 Reserved BBR Reserved C DETS R RIS S K S SV V TD D Reset: 0x0300_0000 Bit Bit Name Description R/W R/W 25-24 CKS Crypto engine Clock Source Select. 00: 80 MHz crypto clock 01: 100 MHz crypto clock 10: 120 MHz crypto clock 11: Bus clock crypto clock 17 BR BIST Result. `1': BIST success. `0': BIST fail. R/W 16 BIST Crypto engine internal RAM BIST enable. Set `1' R/W to enable BIST, when BIST complete, this bit will cleared to `0' and the BR bit indicates the result. 14-12 DETS Destination Early DMA Threshold Size. R/W 10-8 DMBS Destination DMA Maximum Burst Size. R/W 000: 16 Byte 001: 32 Byte 010: 64 Byte 011: 128 Byte 1XX: Reserved. 2-0 SMBS Source DMA Maximum Burst Size. R/W 000: 16 Byte 001: 32 Byte 010: 64 Byte 011: 128 Byte 1XX: Reserved.
IPSec Control Register (IPSCTR) 10 9 8 7 6 5 4 3 2 1 0 DMBS Reserved SMBS
InitVal 11
0 0
111 010
010
14. MIC Calculator
To offload the computation task of CPU, RTL8186 integrates a TKIP-Michael hardware calculator. Register MICLVAL and MICRVAL are used to set the key of TKIP-Michael. After calculated, these two registers will store the output MIC value. Beside the MIC engine, the calculator also embedded with a PRNG (Pseudo Random Number Generator) to provide uniform distributed random number. To use the PRNG, you may write an initial number into MICPRNR register as a seed number, and then read back the MICPRNR value as the output random number.
Register Summary
Virtual address 0xBD18_0000 0xBD18_0004 0xBD18_0008 0xBD18_000C 0xBD18_0010 0xBD18_0014 0xBD18_0018 Size (byte) 4 4 4 4 4 4 4 Name MICLVAL MICRVAL MICSAR MICLENR MICDMAR MICCR MICPRNR Description MIC L value register MIC R value register MIC calculation starting address register MIC calculation length register MIC calculation DMA length register MIC control register MIC Pseudo Random Number Generator register Access R/W R/W R/W R/W R/W R/W R/W
0xBD18_0000 MIC L Value Register (MICLVAL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Lval
Reset: 0x0000_0000 Bit Bit Name 31-0 LVal
Description R/W InitVal MIC L value register. The initial L value is written R/W 0 to this register; when calculation done, read this register for new L value.
0xBD18_0004 MIC R Value Register (MICRVAL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RVal Reset: 0x0000_0000 Bit Bit Name 31-0 RVal
Description R/W InitVal MIC R value register. The initial R value is written R/W 0 to this register; when calculation done, read this register for new R value.
0xBD18_0008 MIC Starting Address Register (MICSAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SADDR Reset: 0x0000_0000 Bit Bit Name 31-0 SADDR
Description The physical address of the data that MIC calculator is going to do calculation. The address has no alignment restriction.
R/W InitVal R/W 0
0xBD18_000C MIC Calculation Length Register (MICLENR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TLEN Reset: 0x0000_0000 Bit Bit Name 31-0 TLEN
Description R/W InitVal The data length that MIC calculator is going to do R/W 0 calculation.
0xBD18_0010 MIC Calculation DMA Length Register (MICDMAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DLEN Reset: 0x0000_0000 Bit Bit Name 31-0 DLEN
Description The DMA length that MIC calculator is going to do calculation. The relation between data length (LEN) and DMA length (DLEN) is: DLEN = (TLEN/4 + 2)*4
R/W InitVal R/W 0
0xBD18_0014
MIC Control Register (MICCR)
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31 30 29 28 27 www..com 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reserved) 87654321 I (Reserved) I S E N 0 R U N
Reset: 0x0000_0000 Bit Bit Name 8 IS 1 IEN
0
RUN
Description Interrupt Status. When MIC calculation is done, this bit is set to `1'. Write `1' to clear the status. Interrupt Enable. When MIC calculation is done and this bit is set to `1', the MIC calculator will assert interrupt to CPU. If this bit is not set, only the IS bit is set while calculation done. MIC Calculator run. Write this bit `1' will trigger the hardware start calculation. When calculation done, this bit auto reset to `0'.
R/W InitVal R/W 0 R/W 0
R/W 0
0xBD18_0018 MIC PRNG Register (MICPRNR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRNG Reset: 0x5412_3333 Bit Bit Name 31-0 PRNG
Description R/W InitVal The Pseudo Random Number Generator. Notice R/W 0x54123333 that if write 0 to this register, the PRNG will fail to generate random number.
15. PCM Controller
The RTL8186 integrates a PCM controller, which supports four channels of voice application and both A-law and u-low compression.
Register Summary
Virtual address 0xBD28_0000 0xBD28_0004 0xBD28_0008 0xBD28_000C 0xBD28_0010 0xBD28_0014 0xBD28_0018 0xBD28_001C 0xBD28_0020 0xBD28_0024 0xBD28_0028 0xBD28_002C 0xBD28_0030 0xBD28_0034 Size (byte) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Name PCMCR PCMCHCNR PCMTSR PCMBSIZE CH0TXBSA CH1TXBSA CH2TXBSA CH3TXBSA CH0RXBSA CH1RXBSA CH2RXBSA CH3RXBSA PCMIMR PCMISR Description PCM interface Control Register PCM Channel specific Control Register PCM Time Slot Assignment Register PCM Channels Buffer Size register PCM Channel 0 TX buffer starting address pointer PCM Channel 1 TX buffer starting address pointer PCM Channel 2 TX buffer starting address pointer PCM Channel 3 TX buffer starting address pointer PCM Channel 0 RX buffer starting address pointer PCM Channel 1 RX buffer starting address pointer PCM Channel 2 RX buffer starting address pointer PCM Channel 3 RX buffer starting address pointer PCM channels Interrupt Mask Register PCM channels Interrupt Status Register Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0xBD28_0000 PCM interface Control Register (PCMCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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(Reserved)
PCPF CKXS MDDI EISN REV R/W InitVal R/W 0
(Reserved)
ICC
Reset: 0x0000_0000 Bit Bit Name 12 PCME
11
CKDIR
10
PXDSE
9
FSINV
3-0
ICC
Description PCM interface Enable. While PCM interface is disabled, all logic and registers will reset to initial state. 0: Disable 1: Enable CLK and FS signal source select of PCM interface. 0: External source from Codec 1: From internal PLL (output to Codec) PCM interface extra data strobe enable. 0: Disable extra data strobe 1: Enable extra data strobe PCM interface frame synchronization polarity invert. 0: PCMFS set to high active 1: PCMFS set to low active PCM interface channels inter change control. When two channels was set as interchange mode, the channel data received from one channel will auto transfer to another for output, without pass through the internal FIFO. 0001: Channel 0, 1 talk 0010: Channel 0, 2 talk 0011: Channel 0, 3 talk 0100: Channel 1, 2 talk 0101: Channel 1, 3 talk 0110: Channel 2, 3 talk 1001: Channel 0, 1 talk and channel 2, 3 talk 1010: Channel 0, 2 talk and channel 1, 3 talk 1011: Channel 0, 3 talk and channel 1, 2 talk others: No interchange talk function enabled.
R/W 0
R/W 0
R/W 0
R/W 0
0xBD28_0004 31 30 29 28 27 26 R CCC S 00H V IC0 D LMU BPA EE Reset: 0x0000_0000 Bit Bit Name 28 C0ILBE
25 C H 0 T E
24 23 22 21 20 19 18 17 C R CCC H S 1HH 0 V C11 R D MUT E PAE E
PCM Channel Control Register (PCMCHCNR) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C R CCCC R CCCC H S 2 HHH S 3HHH 1 V C222 V C333 R D MUTR D MUTR E PAEE PAEE E E R/W InitVal R/W 0
27
C0CMPE
Description Channel 0 Internal Loop-back Enable. When loop-back function enabled, the data in TX FIFO transmits to TXD and also the RX FIFO. 0: Disable loop-back 1: Enable loop-back Channel 0 Compander Enable. When channel compander enabled, the 8-bit data from RXD expands to 16 bits and sent to RX FIFO. In the
R/W 0
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26
CH0UA
25
CH0TE
24
CH0RE
19
C1CMPE
18
CH1UA
17
CH1TE
16
CH1RE
11
C1CMPE
10
CH2UA
9
CH2TE
8
CH2RE
3
C3CMPE
2
CH3UA
1
CH3TE
other direction, the compander suppresses 16 bit data from TX FIFO to 8 bits and sent to TXD. 0: Disable 1: Enable Channel 0 u-law/A-law select. 0: u-law 1: A-law Channel 0 Transmitter Enable. 0: Disable 1: Enable Channel 0 Receiver Enable. 0: Disable 1: Enable Channel 1 Compander Enable. When channel compander enabled, the 8-bit data from RXD expands to 16 bits and sent to RX FIFO. In the other direction, the compander suppresses 16 bit data from TX FIFO to 8 bits and sent to TXD. 0: Disable 1: Enable Channel 1 u-law/A-law select. 0: u-law 1: A-law Channel 1 Transmitter Enable. 0: Disable 1: Enable Channel 1 Receiver Enable. 0: Disable 1: Enable Channel 1 Compander Enable. When channel compander enabled, the 8-bit data from RXD expands to 16 bits and sent to RX FIFO. In the other direction, the compander suppresses 16 bit data from TX FIFO to 8 bits and sent to TXD. 0: Disable 1: Enable Channel 2 u-law/A-law select. 0: u-law 1: A-law Channel 2 Transmitter Enable. 0: Disable 1: Enable Channel 2 Receiver Enable. 0: Disable 1: Enable Channel 3 Compander Enable. When channel compander enabled, the 8-bit data from RXD expands to 16 bits and sent to RX FIFO. In the other direction, the compander suppresses 16 bit data from TX FIFO to 8 bits and sent to TXD. 0: Disable 1: Enable Channel 3 u-law/A-law select. 0: u-law 1: A-law Channel 3 Transmitter Enable. 0: Disable 1: Enable
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
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0 CH3RE www..com Channel 3 Receiver Enable. 0: Disable 1: Enable R/W 0
0xBD28_0008 PCM Time Slot Assignment Register (PCMTSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3TSA CH2TSA R CH1TSA R CH0TSA R R S S S S V V V V D D D D Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 28-24 CH0TSA Channel 0 Time Slot Assignment. R/W 0 CH0TSA[4:0] mapping to Slot 0 .. Slot 31. 20-16 CH1TSA Channel 1 Time Slot Assignment. R/W 0 CH1TSA[4:0] mapping to Slot 0 .. Slot 31. 12-8 CH2TSA Channel 2 Time Slot Assignment. R/W 0 CH2TSA[4:0] mapping to Slot 0 .. Slot 31. 4-0 CH3TSA Channel 3 Time Slot Assignment. R/W 0 CH3TSA[4:0] mapping to Slot 0 .. Slot 31.
0xBD28_001C PCM Buffer Size Register (PCMBSIZE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0BSIZE CH1BSIZE CH2BSIZE CH3BSIZE Reset: 0x0000_0000 Bit Bit Name 31-24 CH0BSIZE 23-16 CH1BSIZE 15-8 CH2BSIZE 7-0 CH3BSIZE
Description Channel 0 buffer size in unit of 4(n+1) bytes. Channel 1 buffer size in unit of 4(n+1) bytes. Channel 2 buffer size in unit of 4(n+1) bytes. Channel 3 buffer size in unit of 4(n+1) bytes.
R/W R/W R/W R/W R/W
InitVal 0x0 0x0 0x0 0x0
0xBD28_0010 PCM Channel 0 TX Base Address Register (CH0TXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXBUFPR PP 10 OO WW NN Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 31-2 TXBUFPR TX Buffer Pointer. This is a physical address with R/W 0x0 word-align limitation. 1 P1OWN Page 1 Own bit R/W 0x0 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller 0 P0OWN Page 0 Own bit R/W 0x0 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
0xBD28_0014 PCM Channel 1 TX Base Address Register (CH1TXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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TXBUFPR
P 1 O W N R/W InitVal R/W 0x0 R/W 0x0
P 0 O W N
Reset: 0x0000_0000 Bit Bit Name 31-2 TXBUFPR 1 P1OWN
0
P0OWN
Description TX Buffer Pointer. This is a physical address with word-align limitation. Page 1 Own bit 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller Page 0 Own bit 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
R/W 0x0
0xBD28_0018 PCM Channel 2 TX Base Address Register (CH2TXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXBUFPR PP 10 OO WW NN Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 31-2 TXBUFPR TX Buffer Pointer. This is a physical address with R/W 0x0 word-align limitation. 1 P1OWN Page 1 Own bit R/W 0x0 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller 0 P0OWN Page 0 Own bit R/W 0x0 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
0xBD28_001C PCM Channel 3 TX Base Address Register (CH3TXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXBUFPR PP 10 OO WW NN Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 31-2 TXBUFPR TX Buffer Pointer. This is a physical address with R/W 0x0 word-align limitation. 1 P1OWN Page 1 Own bit R/W 0x0 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller 0 P0OWN Page 0 Own bit R/W 0x0 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
0xBD28_0020 PCM Channel 0 RX Base Address Register (CH0RXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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RXBUFPR
P 1 O W N R/W InitVal R/W 0x0 R/W 0x0
P 0 O W N
Reset: 0x0000_0000 Bit Bit Name 31-2 RXBUFPR 1 P1OWN
0
P0OWN
Description RX Buffer Pointer. This is a physical address with word-align limitation. Page 1 Own bit 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller Page 0 Own bit 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
R/W 0x0
0xBD28_0024 PCM Channel 1 RX Base Address Register (CH1RXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXBUFPR PP 10 OO WW NN Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 31-2 RXBUFPR RX Buffer Pointer. This is a physical address with R/W 0x0 word-align limitation. 1 P1OWN Page 1 Own bit R/W 0x0 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller 0 P0OWN Page 0 Own bit R/W 0x0 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
0xBD28_0028 PCM Channel 2 RX Base Address Register (CH2RXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXBUFPR PP 10 OO WW NN Reset: 0x0000_0000 Bit Bit Name Description R/W InitVal 31-2 RXBUFPR RX Buffer Pointer. This is a physical address with R/W 0x0 word-align limitation. 1 P1OWN Page 1 Own bit R/W 0x0 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller 0 P0OWN Page 0 Own bit R/W 0x0 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
0xBD28_002C PCM Channel 3 RX Base Address Register (CH3RXBSA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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RXBUFPR
P 1 O W N R/W InitVal R/W 0x0 R/W 0x0
P 0 O W N
Reset: 0x0000_0000 Bit Bit Name 31-2 RXBUFPR 1 P1OWN
0
P0OWN
Description RX Buffer Pointer. This is a physical address with word-align limitation. Page 1 Own bit 0: Page 1 owned by CPU 1: Page 1 owned by PCM controller Page 0 Own bit 0: Page 0 owned by CPU 1: Page 0 owned by PCM controller
R/W 0x0
0xBD28_0030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 (Reserved) CCC HHH 000 PPT 01B OOU KKA III EEE Reset: 0x0000_0000 Bit Bit Name Description 15 CH0P0OKIE Channel 0 Page 0 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt 14 CH0P1OKIE Channel 0 Page 1 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt 13 CH0TBUAIE Channel 0 Transmit Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt 12 CH0RBUAIE Channel 0 Receive Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt 11 CH1P0OKIE Channel 1 Page 0 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt 10 CH1P1OKIE Channel 1 Page 1 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt 9 CH1TBUAIE Channel 1 Transmit Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt 8 CH1RBUAIE Channel 1 Receive Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt
PCM Interrupt Mask Register (PCMIMR) 12 11 10 9 8 7 6 5 4 3 2 1 0 CCCCCCCCCCCCC HHHHHHHHHHHHH 0111122223333 RP PTRPPTRPPTR B 0 1BB01BB01BB UOOUUOOUUOOUU AKKAAKKAAKKAA IIIIIIIIIIIII EEEEEEEEEEEEE R/W InitVal R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
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7 CH2P0OKIE www..com 6 CH2P1OKIE Channel 2 Page 0 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt Channel 2 Page 1 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt Channel 2 Transmit Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt Channel 2 Receive Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt Channel 3 Page 0 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt Channel 3 Page 1 OK Interrupt Enable. 0: Disable interrupt 1: Enable interrupt Channel 3 Transmit Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt Channel 3 Receive Buffer Unavailable Interrupt Enable. 0: Disable interrupt 1: Enable interrupt R/W 0
R/W 0
5
CH2TBUAIE
R/W 0
4
CH2RBUAIE
R/W 0
3
CH3P0OKIE
R/W 0
2
CH3P1OKIE
R/W 0
1
CH3TBUAIE
R/W 0
0
CH3RBUAIE
R/W 0
0xBD28_0034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 (Reserved) CCC HHH 000 PPT 01B OOU KKA III PPP Reset: 0x0000_0000 Bit Bit Name Description 15 CH0P0OKIP Channel 0 Page 0 OK Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. 14 CH0P1OKIP Channel 0 Page 1 OK Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. 13 CH0TBUAIP Channel 0 Transmit Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. 12 CH0RBUAIP Channel 0 Receive Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. 11 CH1P0OKIP Channel 1 Page 0 OK Interrupt Pending. 0: No interrupt
PCM Interrupt Status Register (PCMISR) 12 11 10 9 8 7 6 5 4 3 2 1 0 CCCCCCCCCCCCC HHHHHHHHHHHHH 0111122223333 RP PTRPPTRPPTR B 0 1BB01BB01BB UOOUUOOUUOOUU AKKAAKKAAKKAA IIIIIIIIIIIII PPPPPPPPPPPPP R/W InitVal R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
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10
CH1P1OKIP
9
CH1TBUAIP
8
CH1RBUAIP
7
CH2P0OKIP
6
CH2P1OKIP
5
CH2TBUAIP
4
CH2RBUAIP
3
CH3P0OKIP
2
CH3P1OKIP
1
CH3TBUAIP
0
CH3RBUAIP
1: Interrupt pending, write `1' to clear. Channel 1 Page 1 OK Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 1 Transmit Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 1 Receive Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 2 Page 0 OK Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 2 Page 1 OK Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 2 Transmit Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 2 Receive Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 3 Page 0 OK Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 3 Page 1 OK Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 3 Transmit Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear. Channel 3 Receive Buffer Unavailable Interrupt Pending. 0: No interrupt 1: Interrupt pending, write `1' to clear.
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
16. 802.11a/b/g WLAN Controller
RTL8186 integrates with a wireless LAN MAC and a direct sequence spread spectrum baseband processor. The WLAN controller implements Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK) and Orthogonal Frequency Division Multiplexing (OFDM) baseband processing to support all IEEE 802.11a, 802.11b and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability, are available along with complementary code keying to provide data rates of 1, 2, 5.5 and 11Mbps, with long or short preamble. A high speed Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM modulation of the individual subcarriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with rate compatible punctured convolutional coding with a coding rate of 1/2, 2/3 and 3/4. The WLAN controller also builds in an enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder to alleviate the severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset and timing offset compensation are provided for the radio frequency front-end impairments. Selectable digital transmit and receiver FIR filters are provided to meet the requirement of transmit spectrum mask and to reject the adjacent channel
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interference, respectively. Both in the transmitter and receiver, programmable scaling in digital domain trades the quantization www..com noise against the increasing probability of clipping. Furthermore, robust signal detection, symbol boundary detection and channel estimation are performed well at the minimum sensitivity. Besides, it supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions, and adaptive transmit power control function to obtain better performance in the analog portions of the transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I and Q inputs and outputs, transmit TSSI and receiver RSSI input, and transmit and receiver AGC outputs. To support 802.11h, RTL8186 implements a dynamic frequency selection (DFS) and transmit power control (TPC) that could be used to satisfy regulator requirements for operation in the 5GHz band in Europe. For security issues, RTL8186 has implemented a high performance security engine to support WEP, TKIP and AES encryption/decryption for transmitting and receiving packet. The WLAN controller is a DMA bus-master device, and uses descriptor-based buffer structure for packet transmission and reception. These features will definitely offload much CPU loading. RTL8186 provides interfaces for external RF module. Now Realtek RTL8225 (802.11 b/g) and RFL8255 (802.11 a/b/g) RF chipset are supported.
Register Summary
Virtual Address 0xBD40_0000 Size (byte) 8 Name WLAN_ID Description ID Register. The ID register is only permitted to write via 4-byte access. Read access can be byte, word, or double word access. Multicast Register. The MAR register is only permitted to write via 4-byte access. Read access can be byte, word, or double word access. Timing Synchronization Function Timer Register. Transmit Low Priority Descriptors Start Address (32-bit) (256-byte alignment). Transmit Normal Priority Descriptors Start Address (32-bit). (256-byte alignment). Transmit High Priority Descriptors Start Address (32-bit). (256-byte alignment). Basic Rate Set Register. Basic Service Set ID. Response Rate. Extended InterFrame Space Time. The value is in units of 4s. Command Register. Interrupt Mask Register. Interrupt Status Register. Transmit (Tx) Configuration Register. Receive (Rx) Configuration Register. Timer Interrupt Register. Once having written a non-zero value to this register, the Timeout bit of the WLAN_ISR register will be set whenever the least 32 bits of the WLAN_TSFTR reaches this value. The Timeout bit will not be set as long as the WLAN_TINT register is zero. Transmit Beacon Descriptor start Address (32-bit) (256-byte alignment). RW RW
0xBD40_0008
8
WLAN_MAR
RW
0xBD40_0018 0xBD40_0020 0xBD40_0024 0xBD40_0028 0xBD40_002C 0xBD40_002E 0xBD40_0034 0xBD40_0035 0xBD40_0037 0xBD40_003C 0xBD40_003E 0xBD40_0040 0xBD40_0044 0xBD40_0048
8 4 4 4 4 6 1 1 1 2 2 4 4 4
WLAN_TSFTR WLAN_TLPDA WLAN_TNPDA WLAN_THPDA WLAN_BRSR WLAN_BSSID WLAN_RR WLAN_EIFS WLAN_CR WLAN_IMR WLAN_ISR WLAN_TCR WLAN_RCR WLAN_TINT
R RW RW RW RW RW RW RW RW RW RW RW RW RW
0xBD40_004C
4
WLAN_TBDA
RW
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Virtual www..com Address 0xBD40_0050 0xBD40_0051 0xBD40_0052 0xBD40_0053 0xBD40_0054 0xBD40_0058 0xBD40_0059 0xBD40_005A 0xBD40_005B 0xBD40_0070 0xBD40_0072 0xBD40_0074 0xBD40_0076 0xBD40_007C 0xBD40_007D 0xBD40_007E 0xBD40_0080 0xBD40_0082 0xBD40_0084 0xBD40_0086 0xBD40_0088 0xBD40_008C 0xBD40_009C 0xBD40_009D 0xBD40_009E 0xBD40_009F 0xBD40_00A0 0xBD40_00A4 0xBD40_00A8 0xBD40_00AC 0xBD40_00B0 0xBD40_00B2 0xBD40_00B4 0xBD40_00B5 0xBD40_00B6 0xBD40_00B7 0xBD40_00BC 0xBD40_00BD 0xBD40_00BE 0xBD40_00D8 0xBD40_00D9 0xBD40_00DC 0xBD40_00DE 0xBD40_00E4 0xBD40_0100 0xBD40_0104 0xBD40_0108 0xBD40_010C 0xBD40_0110 0xBD40_0114 Size (byte) 1 1 1 1 4 1 1 1 1 2 2 2 2 1 1 1 2 2 2 2 4 4 1 1 1 1 4 4 4 4 2 2 1 1 1 1 1 1 1 1 1 2 1 4 4 4 4 4 4 4 Name WLAN_CR WLAN_CONFIG0 WLAN_CONFIG1 WLAN_CONFIG2 WLAN_ANAPARM WLAN_MSR WLAN_CONFIG3 WLAN_CONFIG4 WLAN_TESTR WLAN_BCNITV WLAN_ATIMWND WLAN_BINTRITV WLAN_ATIMTRITV WLAN_PHYADDR WLAN_PHYDATAW WLAN_PHYDATAR WLAN_RFPINOUT WLAN_RFPINEN WLAN_RFPINSEL WLAN_RFPININPUT WLAN_RFPARA WLAN_RFTIMING WLAN_TXAGC WLAN_CCKTXAGC WLAN_OFDMTXAG C WLAN_ANTSEL WLAN_CAMRW WLAN_CAMOUTPU T WLAN_CAMINPUT WLAN_CAMDEBUG WLAN_WPACONFIG WLAN_AESMASK WLAN_SIFS WLAN_DIFS WLAN_SLOTTIME WLAN_USTUNE WLAN_CWCONFIG WLAN_CWVALUE WLAN_RATECTRL WLAN_ CONFIG5 WLAN_TPPOLL WLAN_ CWR WLAN_RETRYCTR WLAN_RDSAR WLAN_DFSCR WLAN_DFSSLR WLAN_DFSSHR WLAN_DFSDLR WLAN_DFSDHR WLAN_DFSPCR Description Command Register. Configuration Register 0. Configuration Register 1. Configuration Register 2. Analog Parameter. Media Status Register. Configuration Register 3. Configuration Register 4. Test mode Register. Beacon Interval Register. Atim Window Register. Beacon interrupt Interval Register. Atim Interrupt Interval Register. PHY interface Address Register. Write Data to PHY. Read Data from PHY. RF Pins Output RF Pins Enable RF Pins Select RF Pins Input RF Parameter RF Timing Auto TXAGC Control. Complementary Code Keying TX Automatic Gain Control. Orthogonal Frequency Division Multiplexing TX Automatic Gain Control. TX Antenna Select. Content Access Memory Read/Write. Date written to Content Access Memory. Date read from Content Access Memory. Content Access Memory Debug Interface. Wi-Fi Protected Access Config. Advanced Encryption Standard Mask. Short InterFrame Spacing Timer Setting. Distributed InterFrame Spacing Timer Setting. Slot Time Setting. Micro-second Fine Tune Config. Contention Window Config. Contention Window Value. Auto Rate Fallback Control. Configuration Register 5. Transmit Priority Polling register. Contention Window Register. Retry Count Register. Receive Descriptor Start Address Register (32-bit). (256-byte alignment). DFS control register DFS Schmitt trigger low-threshold setting register DFS Schmitt trigger high-threshold setting register DFS Pulse-duration low-threshold setting register DFS Pulse-duration high-threshold setting register DFS valid pulse count register RW RW R RW RW RW RW RW RW RW RW RW RW RW RW W R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W R R RW RW RW RW RW RW R
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Virtual www..com Address 0xBD40_0118 0xBD40_011C 0xBD40_0120 0xBD40_0124 0xBD40_0128 0xBD40_012C 0xBD40_0130 0xBD40_0134 0xBD40_0138 0xBD40_013C 0xBD40_0140 0xBD40_0144 0xBD40_0148 0xBD40_014C 0xBD40_0150 0xBD40_0154 0xBD40_0158 0xBD40_015C 0xBD40_0160 0xBD40_0164 0xBD40_0168 Size (byte) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Name WLAN_DFSTS0R WLAN_DFSTS1R WLAN_DFSTS2R WLAN_DFSTS3R WLAN_DFSTS4R WLAN_DFSTS5R WLAN_DFSTS6R WLAN_DFSTS7R WLAN_DFSTS8R WLAN_DFSTS9R WLAN_DFSTSAR WLAN_DFSTSBR WLAN_DFSTSCR WLAN_DFSTSDR WLAN_DFSTSER WLAN_DFSTSFR WLAN_DFSTSGR WLAN_DFSTSHR WLAN_DFSTSIR WLAN_DFSTSJR WLAN_DFSCTSR Description DFS Time Stamp 0 register DFS Time Stamp 1 register DFS Time Stamp 2 register DFS Time Stamp 3 register DFS Time Stamp 4 register DFS Time Stamp 5 register DFS Time Stamp 6 register DFS Time Stamp 7 register DFS Time Stamp 8 register DFS Time Stamp 9 register DFS Time Stamp A register DFS Time Stamp B register DFS Time Stamp C register DFS Time Stamp D register DFS Time Stamp E register DFS Time Stamp F register DFS Time Stamp G register DFS Time Stamp H register DFS Time Stamp I register DFS Time Stamp J register DFS Current Time Stamp register RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R
0xBD40_0018 Bit Bit Name 63-0 TSFT
TSF Timer Register (WLAN_TSFTR) Description RW Timing Synchronization Function Timer. R The RTL8186/RTL8186P maintains a TSF timer with modules 2^64 counting in increments of microseconds. The 8 octets are the timestamp field of beacon and probe response frames. Basic Rate Set Register (WLAN_BRSR) R/W R/W Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11
0xBD40_002C Bit 15-12 11-0
Bit Name BRSR
Description Reserved. Basic Rate Set Register. 1Mbps 2Mbps 5.5Mbps 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps
0xBD40_002E Bit Bit Name 47-0 BSSID
Basic Service Set ID Register (WLAN_BSSID) Description RW Basic Service Set Identification. RW The driver writes to this register to set BSSID after a NIC joins a network or creates a BSS/IBSS network.
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0xBD40_0034 Response Rate (WLAN_RR) Bit Bit Name Description RW 7-4 MAX_RESPO Maximum Response Rate. RW NSE_RATE If the rate of the received unicast packet/RTS is larger than the Maximum Response Rate, the hardware uses the Maximum Response Rate to respond to the received packet. 3-0 MIN_RESPO Minimum Response Rate. NSE_RATE If the rate of the received unicast packet/RTS is not larger than the Maximum Response Rate and is not one of the basic rates shown below, the hardware uses the Minimum Response Rate to respond to the received packet. Bit 3 Bit 2 Bit 1 Bit 0 1Mbps 0 0 0 0 2Mbps 0 0 0 1 5.5Mbps 0 0 1 0 11Mbps 0 0 1 1 6Mbps 0 1 0 0 9Mbps 0 1 0 1 12Mbps 0 1 1 0 18Mbps 0 1 1 1 24Mbps 1 0 0 0 36Mbps 1 0 0 1 48Mbps 1 0 1 0 54Mbps 1 0 1 1 RW
0xBD40_0037 Bit Bit Name 7-5 4 RST
3
RE
2
TE
1 0
MULRW
Command Register (WLAN_CR) Description RW Reserved. Reset. RW Setting this bit to 1 forces the RTL8186/RTL8186P perform a WLAN MAC reset. During the reset state, it disables the transmitter and receiver and reinitializes the FIFOs. The values of WLAN_IDR and WLAN_MAR are not changed. This bit is 1 during the reset operation, and is cleared to 0 when the reset operation is complete. Receiver Enable. RW When set to 1 whilst the receive state machine is idle, the receive machine becomes active. This bit will read back as 1 whenever the receive state machine is active. After initial power-up, software must insure that the receiver has completely reset before setting this bit. 1: Enable 0: Disable Transmitter Enable. RW When set to 1 whilst the transmit state machine is idle, the transmit state machine becomes active. This bit will read back as 1 whenever the transmit state machine is active. After initial power-up, software must insure that the transmitter has completely reset before setting this bit. 1: Enable 0: Disable Reserved. Multiple Bus Read/Write Enable. RW 1: Enable 0: Disable Interrupt Mask Register (WLAN_IMR) RW
0xBD40_003C Bit Bit Name
Description
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Bit Bit Name www..com 15 TXFOVW Description Tx FIFO Overflow Interrupt. 1: Enable 0: Disable Time Out interrupt. 1: Enable 0: Disable Beacon Time out Interrupt. 1: Enable 0: Disable ATIM Time Out Interrupt. 1: Enable 0: Disable Tx Beacon Descriptor Error interrupt. 1: Enable 0: Disable Tx Beacon Descriptor OK interrupt. 1: Enable 0: Disable Tx High Priority Descriptor Error interrupt. 1: Enable 0: Disable Tx High Priority Descriptor OK interrupt. 1: Enable 0: Disable Tx Normal Priority Descriptor Error interrupt. 1: Enable 0: Disable Tx Normal Priority Descriptor OK interrupt. 1: Enable 0: Disable Rx FIFO Overflow interrupt. 1: Enable 0: Disable Rx Descriptor Unavailable interrupt. 1: Enable 0: Disable Tx Low Priority Descriptor Error interrupt. 1: Enable 0: Disable Tx Low Priority Descriptor OK interrupt. 1: Enable 0: Disable Rx Error interrupt. 1: Enable 0: Disable Rx OK interrupt. 1: Enable 0: Disable RW RW
14
TimeOut
RW
13
BcnInt
RW
12
ATIMInt
RW
11
TBDER
RW
10
TBDOK
RW
9
THPDER
RW
8
THPDOK
RW
7
TNPDER
RW
6
TNPDOK
RW
5
RXFOVW
RW
4
RDU
RW
3
TLPDER
RW
2
TLPDOK
RW
1
RER
RW
0
ROK
RW
0xBD40_003E Bit Bit Name 15 TXFOVW 14 TimeOut
Interrupt Status Register (WLAN_ISR) Description RW Tx FIFO Overflow. RW Time Out. RW This bit is set to 1 when the least 32 bits of the TSFTR register reaches the value of the TimerInt register.
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Bit Bit Name www..com 13 BcnInt Description Beacon time out Interrupt. When set, this bit indicates that the TBTT (Target Beacon Transmission Time) has reached the value set in the Beacon Interrupt Interval Register. ATIM Time Out Interrupt. When set, this bit indicates that the ATIM window has reached the value set in the Atim Interrupt Interval Register. Transmit Beacon priority Descriptor Error. Indicates that a beacon priority descriptor transmission was aborted due to reception of a beacon frame. Transmit Beacon priority Descriptor OK. Indicates that a beacon priority descriptor exchange sequence has been successfully completed. Transmit High Priority Descriptor Error. Indicates that a high priority descriptor transmission was aborted due to an SSRC (Station Short Retry Count) having reached SRL (Short Retry Limit), or an SLRC (Station Long Retry Count) having reached LRL (Long Retry Limit). Transmit High Priority Descriptor OK. Indicates that a high priority descriptor exchange sequence has been successfully completed. Transmit Normal Priority Descriptor Error. Indicates that a normal priority descriptor transmission was aborted due to an SSRC (Station Short Retry Count) having reached SRL (Short Retry Limit), or an SLRC (Station Long Retry Count) having reached LRL (Long Retry Limit). Transmit Normal Priority Descriptor OK. Indicates that a normal priority descriptor exchange sequence has been successfully completed. Rx FIFO Overflow. This bit set to 1 is caused by Receive Descriptor Unavailable (RDU), poor PCI performance, or overloaded PCI traffic. Rx Descriptor Unavailable. When set, this bit indicates that the Rx descriptor is currently unavailable. Transmit Low Priority Descriptor Error. Indicates that a low priority descriptor transmission was aborted due to an SSRC (Station Short Retry Count) having reached SRL (Short Retry Limit), or an SLRC (Station Long Retry Count) having reached LRL (Long Retry Limit). Transmit Low Priority Descriptor OK. Indicates that a low priority descriptor exchange sequence has been successfully completed. Receive Error. Indicates that a packet has a CRC32 or ICV error. Receive OK. In normal mode, indicates the successful completion of a packet reception. RW RW
12
ATIMInt
RW
11
TBDER
RW
10
TBDOK
RW
9
THPDER
RW
8
THPDOK
RW
7
TNPDER
RW
6
TNPDOK
RW
5
FOVW
RW
4 3
_RDU TLPDER
RW RW
2
TLPDOK
RW
1 0
RER ROK
RW RW
0xBD40_0040 Bit Bit Name 31-30 29 NO_PROBE_R SP_TIMESTA MP 28 24 PLCP_LENGT H
Transmit Configuration Register (WLAN_TCR) Description RW Reserved Disable tagging a timestamp onto probe response frames. RW
Reserved. HW/SW Physical Layer Convergence Procedure Length Mechanism. 1: Software provides the PLCP length and LENGEXT. 0: Hardware provides the PLCP length and LENGEXT.
RW
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Bit Bit Name www..com 23-21 MXDMA2, 1, 0 Description Max DMA burst size per Tx DMA burst. This field sets the maximum size of transmit DMA data bursts according to the following: 000: 16 bytes, 001: 32 bytes, 010: 64 bytes, 011: 128 bytes, 100: 256 bytes, 101: 512 bytes, 110: 1024 bytes, 111: 2048 bytes Disable Contention Window Backoff. This bit indicates the existence of a backoff procedure during packet transmission. 0: Uses IEEE 802.11 random backoff procedure 1: No random backoff procedure Append ICV (Integrity Check Value). This bit indicates the existence of an ICV appended at the end of an encipherment packet. 0: ICV appended 1: No ICV appended Loopback Test. There are no packets on the TXI+/- and TXQ+/- lines under the Loopback test condition. The loopback function must be independent of the link state. 00: Normal operation, 01: MAC Loopback 10: Baseband Loopback, 11: Continue TX. Append CRC32. This bit indicates the existence of a CRC32 appended at the end of a packet. 0: A CRC32 is appended 1: No CRC32 appended Short Retry Limit RTS Retry Limit. Indicates the maximum retry time for frames of length less than or equal to the RTSThreshold. Long Retry Limit: Data Packet Retry Limit. Indicates the maximum retransmission times for Data or Management frames of length greater than RTSThreshold. RW RW
20
DISCW
RW
19
ICV
RW
18-17
LBK1, LBK0
RW
16
CRC
RW
15-8
SRL
RW
7-0
LRL
RW
0xBD40_0044 Bit Bit Name 31 ONLYERLPKT 30 29 28 27-24 23 ENCS2 ENCS1 ENMARP CBSSID
22
APWRMGT
21
ADD3
Receive Configuration Register (WLAN_RCR) Description RW Early Receiving based on Packet Size. RW Early Receiving is only performed for packets with a size greater than 1536 bytes. Enable Carrier Sense Detection Method 2. RW Enable Carrier Sense Detection Method 1. RW Enable MAC Auto-reset PHY. RW Reserved. Check BSSID `To DS' and `From DS' Match Packet. RW When set to 1, the RTL8186/RTL8186P will check the Rx data type frame's BSSID `To DS' and `From DS' fields, according to NETYPE (bits 3:2, MSR), to determine if it is set to Link ok. Accept Power Management packet. RW This bit determines whether the RTL8186/RTL8186P will accept or reject packets with the power management bit set. 0: Reject 1: Accept Accept Address 3 match packets. RW Set this bit to 1 to accept broadcast/multicast data type frames that Address 3 match the RTL8186/RTL8186P's MAC address. This bit is valid only when NETYPE (bits 3:2, MSR) is set to Link ok in an Infrastructure network.
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Bit Bit Name www..com 20 AMF Description Accept Management Frame. This bit determines whether the RTL8186/RTL8186P will accept or reject a management frame. 0: Reject 1: Accept Accept Control Frame. This bit determines whether the RTL8186/RTL8186P will accept or reject a control frame. 0: Reject 1: Accept Accept Data Frame. This bit determines whether the RTL8186/RTL8186P will accept or reject a data frame. 0: Reject 1: Accept Reserved. Rx FIFO Threshold. This bit specifies the Rx FIFO Threshold level. When the number of the received data bytes from a packet being received into the Rx FIFO of the RTL8186/RTL8186P has reached the set level (or the FIFO contains a complete packet), the receive PCI bus master function will begin to transfer the data from the FIFO to the host memory. This field sets the threshold level according to the following: 000: Reserved, 001: Reserved, 010: 64 bytes, 011: 128 bytes 100: 256 bytes, 101: 512 bytes, 110: 1024 bytes, 111: No Rx threshold. The RTL8186/RTL8186P begins the transfer of data after receiving a whole packet into the FIFO. Accept ICV error packets. This bit determines whether packets with ICV (Integrity Check Value) errors will be accepted or rejected. 1: Accept 0: Reject Reserved. Max. DMA burst size per Rx DMA burst. This field sets the maximum size of the receive DMA data bursts according to the following: 000: 16 bytes, 001: 32 bytes, 010: 64 bytes, 011: 128 bytes 100: 256 bytes, 101: 512 bytes, 110: 1024 bytes, 111: Unlimited Reserved. Accept CRC32 error packets. This bit determines whether packets with CRC32 errors will be accepted or rejected. 0: Reject 1: Accept Reserved. Accept Broadcast packets. This bit determines whether broadcast packets will be accepted or rejected. 0: Reject 1: Accept Accept Multicast packets. This bit determines whether multicast packets will be accepted or rejected. 0: Reject 1: Accept Accept Physical Match packets. This bit determines whether physical match packets will be accepted or rejected. 0: Reject 1: Accept RW RW
19
ACF
RW
18
ADF
RW
17-16 15-13
RXFTH2, 1, 0
12
AICV
11 10-8
MXDMA2, 1, 0
7-6 5
ACRC32
4 3
AB
2
AM
1
APM
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PRELIMINARY v0.9
RTL8186
Bit Bit Name www..com 0 AAP Description Accept destination Address Packets. This bit determines whether packets with a destination address will be accepted or rejected. 0: Reject 1: Accept RW
0xBD40_0050 Bit Bit Name 7-6 EEM
5-0
Command Register (WLAN_CR) Description RW RW These 2 bits select the operating mode. 00: Operating in network/host communication mode. 11: Before writing to the WLAN_CONFIG0, 1, 2, and 3 registers, the RTL8186/RTL8186P must be placed in this mode. This prevents accidental changes to the WLAN controller configurations. Reserved.
0xBD40_0051 Bit Bit Name 7-4 3 Aux_Status
2 1-0
GL
Configuration Register 0 (WLAN_CONFIG0) Description RW Reserved. Auxiliary power present Status. RW This bit indicates the existence of auxiliary power. The value of this bit is fixed after each reset. 1: Auxiliary power is present 0: Auxiliary power is absent Reserved. Geographic Location. RW These bits indicate the current operational region in which the RTL8186/RTL8186P transmits and receives packets. 11: USA, 10: Europe, 0: Japan Configuration Register 1 (WLAN_CONFIG1) Description RW WLAN LED indicator, which bit values are defined as: RW LED0-1 LED0 LED1 00 TX/RX Infrastructure 01 TX/RX LINK 10 TX RX 11 LINK/ACT Infrastructure
0xBD40_0052 Bit Bit Name 7-6 LED
5-0
Reserved.
0xBD40_0053 Bit Bit Name 7 LCK
6
ANT
5-4 3
DPS
Configuration Register 2 (WLAN_CONFIG2) Description RW Locked Clocks. RW Set this bit to 1 to lock the transmit frequency and symbol clocks to the same oscillator. Antenna diversity. RW 0: Disable 1: Enable Reserved. Descriptor Polling State. Test mode. RW 0: Normal working state. This is also the power-on default value 1: Test mode
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RTL8186
Bit Bit Name www..com 2 PAPE_sign Description Power Amplifier Enable timing. 1: The RTL8186/RTL8186P will advance PAPE_time to enable the PAPE pin when transmitting data 0: The RTL8186/RTL8186P will delay PAPE_time to enable the PAPE pin when transmitting data These two bits indicate that the RTL8186/RTL8186P has enabled the PAPE pin (in s). RW RW
1-0
PAPE_time
RW
0xBD40_0058 Bit Bit Name 7-4 3-2 NETTYPE
1-0 0xBD40_0059 Bit Bit Name 7 6 PARM_En
Media Status Register (WLAN_MSR) Description RW Reserved. RW Network Type and Link Status. The values of these bits are written by the driver. 10: Infrastructure client, 01: Ad-hoc, 11: Access Point, 00: No link Reserved. Configuration Register 3 (WLAN_CONFIG3) Description RW Reserved. Parameter write Enable. RW Setting this bit to 1 and asserting WLAN_CR register bit EEM1 and EEM0 at the same time will enable the WLAN_ANAPARM register to be written via software. Reserved. Fast Back to Back Enable. RW 0: Disable 1: Enable Configuration Register 4 (WLAN_CONFIG4) Description RW VCO Power Down. RW 0: Normal working state. This is the power-on default value 1: VCO power down mode. Setting this bit enables the VCOPDN pin and turns off the external RF front end power (including VCO) and most of the internal power of the RTL8186/RTL8186P Power Off. RW 0: Normal working state. This is the power-on default value 1: Power Off mode. Turn off the external RF front end power (excluding VCO) and most of the internal power of the RTL8186/RTL8186P Power Management. RW 0: Normal working state. This is the power-on default value 1: Power management mode. Sets a Tx packet's power management bit to 1 to include a control type frame Reserved. Beacon Interval Register (WLAN_BCNITV) Description RW Beacon Interval. RW The Beacon Interval represents the number of time units (1 TU = 1024s) between target beacon transmissions (TBTTs). This register is written by the driver after starting a BSS/IBSS or joining an IBSS network. ATIM Window Register (WLAN_ATIMWND) RW
4-1 0
FBtBEn
0xBD40_005A Bit Bit Name 7 VCOPDN
6
PWROFF
5
PWRMGT
4-0 0xBD40_0070 Bit Bit Name 15-0 BCNITV
0xBD40_0072 Bit Bit Name
Description
CONFIDENTIAL
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Bit Bit Name www..com 15-0 ATIMWND Description This register indicates the ATIM Window length in Time Units (TU). It is written by the driver after the NIC joins or creates an ad-hoc network. RW RW
0xBD40_0074 Bit Bit Name 15-0 BINTRITV
Beacon Interrupt Interval Register (WLAN_BINTRITV) Description RW RW This timer register generates BcnInt (bit 13, ISR) at a set time interval before TBTT to prompt the host to prepare the beacon. The unit of this register is microseconds. It is written by the driver after the NIC joins a network or creates an ad-hoc network. ATIM Interrupt Interval Register (WLAN_ATIMTRITV) Description RW RW This timer register generates ATIMInt (bit 12, ISR) at a set time interval before the end of the ATIM window in an ad-hoc network. The unit of this register is microseconds. It is written by the driver after the NIC joins a network or creates an ad-hoc network. PHY Delay Register (WLAN_PHYDELAY) Description RW Reserved. Physical layer Delay. RW These three bits represent the delay time in s between the wireless MAC and RF front end when transmitting data. Read/Write CAM (WLAN_CAMRW) RW RW RW
0xBD40_0076 Bit Bit Name 15-0 ATIMTRIT V
0xBD40_0078 Bit Bit Name 7-3 2-0 PHYDELAY
0xBD40_00A0 Bit Bit Name 31 POLLING 30-17 16 WRITE_EN ABLE 15-7 6-0 CAM_ADD RESS 0xBD40_00AC Bit Bit Name 31 SEL_TX_C AM_INFO 30 KEY_FOUN D 29-24 WPA_CONFI G 23-0 CAM_KEY 0xBD40_00B0 Bit Bit Name 31-9 8 RX_WPA_D UMMY 7-4 3 DISABLE_R X_AES_MI C 2 RX_DECRY PT
Description Polling bit Reserved Write Enabled Reserved CAM Address
RW
Description Select TX/RX CAM Information TX/RX Security Key is Found. TX/RX WPA Config CAM Key.
CAM Debug Interface (WLAN_CAMDEBUG) RW RW
RW RW WPA Config (WLAN_WPACONFIG) RW RW
Description Reserved. Enable RX Dummy Function. Reserved. Disable RX AES MIC.
RW
Enable RX Decryption.
RW
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Bit Bit Name www..com 1 0 TX_ENCRY PTION USING_DEF AULT_KET Description Enable Tx Encryption Force HW Using Default Key. RW RW RW
0xBD40_00BC Bit Bit Name 7-2 1 PER_PACKET_ RETRY_LIMIT 0 PER_PACKET_ CW 0xBD40_00BD Bit Bit Name 7-4 CWMAX 3-0 CWMIN
Description Reserved. Enable Per-packet Retry Limit.
Contention Window Config (WLAN_CWCONFIG) RW RW RW
Enable Per-Packet Contention Window.
Description Maximum Contention Window. CWMax = 2n-1. Minimum Contention Window. CWMin = 2n-1.
Contention Window Value (WLAN_CWVALUE) RW RW RW
0xBD40_00BE Bit Bit Name 7 ENABL_RATE_ FALLBACK 6-2 1-0 FALLBACK_ST EP 0xBD40_00D8 Bit Bit Name 7 TX_FIFI_OK
Description Enable Auto Rate Fallback.. Reserved Auto Rate Fallback Step. Auto rate fallback per 2n retry.
Auto Rate Fallback Control (WLAN_RATECTRL) RW RW
6
RX_FIFO_OK
5-0 0xBD40_00D9 Bit Bit Name 7 BQ
Description Built in Self-Test for TX FIFO. 1: OK 0: Fail Built in Self-Test for RX FIFO. 1: OK 0: Fail Reserved.
Configuration Register 5 (WLAN_CONFIG5) RW R
R
6
HPQ
Transmit Priority Polling Register (WLAN_TPPOLL) Description RW Beacon Queue Polling. W The RTL8186 will clear this bit automatically after a beacon packet has been transmitted or received. Writing to this bit has no effect High Priority Queue Polling. W Write a 1 to this bit by software to notify the RTL8186 that there is a high priority packet(s) waiting to be transmitted. The RTL8186 will clear this bit automatically after all high priority packets have been transmitted. Writing a 0 to this bit has no effect.
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Bit Bit Name www..com 5 NPQ Description Normal Priority Queue Polling. DPS (bit3, Config 2) set to 0: The RTL8186 will clear this bit automatically after all normal priority packets have been transmitted or received. Writing to this bit has no effect. DPS (bit3, Config 2) set to 1: Write a 1 to this bit via software to notify the RTL8186 that there is a normal priority packet(s) waiting to be transmitted. The RTL8186 will clear this bit automatically after all normal priority packets have been transmitted. Writing a 0 to this bit has no effect. Low Priority Queue Polling. Write a 1 to this bit via software to notify the RTL8186 that there is a low priority packet(s) waiting to be transmitted. The RTL8186 will clear this bit automatically after all low priority packets have been transmitted. Writing a 0 to this bit has no effect. Stop High Priority Queue. Write a 1 to this bit via software to notify the RTL8186 to stop the DMA mechanism of the High Priority Queue. Stop High Priority Queue. Write a 1 to this bit via software to notify the RTL8186 to stop the DMA mechanism of the High Priority Queue. Stop Normal Priority Queue. Write a 1 to this bit via software to notify the RTL8186 to stop the DMA mechanism of the Normal Priority Queue. This bit is invalid when DPS (bit3, Config 2) is set to 1. Stop Low Priority Queue. Write a 1 to this bit via software to notify the RTL8186 to stop the DMA mechanism of the Low Priority Queue. RW W
4
LPQ
W
3
SBQ
2
SHPQ
1
SNPQ
0
SLPQ
0xBD40_00DC Bit Bit Name 15-10 9-0 CW
Contention Window Register (WLAN_CWR) Description RW Reserved Contention Window. R This register indicates the number of contention windows before transmitting a packet. Retry Count Register (WLAN_RETRYCTR) Description RW Retry Count. R This register indicates the number of retry counts when a packet transmit is completed. Receive Descriptor Start Address Register (WLAN_RDSAR) Description RW Receive Descriptor Start Address. RW This is a 32-bit address. DFS Control Register (DFSCR) R/W
0xBD40_00DE Bit Bit Name 7-0 RETRYCT
0xBD40_00E4 Bit Bit Name 31-0 RDSA
0xBD40_0100 Bit Bit Name
Description
CONFIDENTIAL
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RTL8186
7 TSFS www..com Time Stamp Format select. When this bit is set, the time stamp registers use LSb for recording the CCA status, else the time stamp registers recording the current time while detecting valid pulse. `1': Record CCA status at LSb of time stamp registers `0': Record current time at time stamp registers CCA filter enable. When this bit is set, the CCA signal will filter the valid pulse during CCA on. `1': Enable CCA filtering `0': Disable CCA filtering Time Stamp clock divider select. `1': 5/64 MHz clock selected `0': 5/128 MHz clock selected TX on filter enable. When this bit is set, the DFS detection will stop while TX is on, else disable the TX on filter. `1': Enable TX ON filtering `0': Disable TX ON filtering I-Q sample clock phase select. When this bit is set, the IQ sample clock use falling edge of the clock, else the IQ sample clock use rising clock edge. `1': falling clock edge `0': rising clock edge I-Q power detection mechanism enable. When this bit set, the DFS module use I-Q power detection mechanism to detect radar pulse, else the DFS module use RSSI threshold mechanism. `1': Enable I-Q power detection. `0': Enable RSSI threshold detection. Delay CCA mechanism enable. When this bit is set, the Delay CCA signal will mask the RSSI input. Else the Delay CCA signal has no effect at all. `1': Enable Delay CCA filtering `0': Disable Delay CCA filtering. DFS module enable. When the DFS module is enabled, the Time Stamp registers are updated when valid pulse is detected. When the DFS module is disabled, the Time Stamp registers are reset to default state. `1': Enable DFS function `0': Disable DFS function R/W
6
CCAEN
R/W
5
TDS
R/W
4
TXONE
R/W
3
IQCKS
R/W
2
IQEN
R/W
1
DCCAEN
R/W
0
DFSEN
R/W
0xBD40_0104 Bit Bit Name 31-7 6-0 LT
DFS Schmitt trigger Low Threshold Register (DFSSLR) Description R/W Reserved Low Threshold value of Schmitt trigger R/W
0xBD40_0108 Bit Bit Name 31-7 6-0 HT
DFS Schmitt trigger High Threshold Register (DFSSHR) Description R/W Reserved High Threshold value of Schmitt trigger R/W
0xBD40_010C Bit Bit Name 31-6 5-0 LT
Pulse Duration Low Threshold Register (DFSDLR) Description R/W Reserved Low Threshold value of Pulse Duration (unit: 0.2 us) R/W
0xBD40_0110 Bit Bit Name
Description
Pulse Duration High Threshold Register (DFSDHR) R/W
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31-6 www..com 5-0 HT Reserved High Threshold value of Pulse Duration (unit: 0.2 us)
R/W
0xBD40_0114 Bit Bit Name 31-5 4-0 PC
Pulse Count Register (DFSPCR) Description R/W Reserved R Valid Pulse Count. While DFS is enabled, the number of valid pulse detected is show at this register. This value also indicates who many time stamp registers are valid. Disable DFS module will reset this register.
0xBD40_0118 0xBD40_011C 0xBD40_0120 0xBD40_0124 0xBD40_0128 0xBD40_012C 0xBD40_0130 0xBD40_0134 0xBD40_0138 0xBD40_013C 0xBD40_0140 0xBD40_0144 0xBD40_0148 0xBD40_014C 0xBD40_0150 0xBD40_0154 0xBD40_0158 0xBD40_015C 0xBD40_0160 0xBD40_0164 Bit Bit Name 31-16 15-1 TS 0 CCA
Description Reserved The time stamp of detected valid pulse. This value will reset while DFS module is disabled. When TSFS of DFSCR register is set, this bit is the CCA signal status of the time that time stamp register is updated. Else this bit indicates the LSb of TS.
Time Stamp 0 Register (DFSTS0R) Time Stamp 1 Register (DFSTS1R) Time Stamp 2 Register (DFSTS2R) Time Stamp 3 Register (DFSTS3R) Time Stamp 4 Register (DFSTS4R) Time Stamp 5 Register (DFSTS5R) Time Stamp 6 Register (DFSTS6R) Time Stamp 7 Register (DFSTS7R) Time Stamp 8 Register (DFSTS8R) Time Stamp 9 Register (DFSTS9R) Time Stamp A Register (DFSTSAR) Time Stamp B Register (DFSTSBR) Time Stamp C Register (DFSTSCR) Time Stamp D Register (DFSTSDR) Time Stamp E Register (DFSTSER) Time Stamp F Register (DFSTSFR) Time Stamp G Register DFSTSGR) Time Stamp H Register (DFSTSHR) Time Stamp I Register (DFSTSIR) Time Stamp J Register (DFSTSJR) R/W R R
0xBD40_0168 Bit Bit Name 31-16 15-0 TS
Current Time Stamp Register (DFSCTSR) Description R/W Reserved Current real-time stamp. The real-time time stamp will reset to 0 while DFS module R is disabled.
Packet Buffering RTL8186 WLAN controller incorporates two independent FIFOs for transferring data to/from the system interface and from/to the network. The FIFOs, providing temporary storage of data freeing the host system from the real-time demands of the network. The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the Receive Configuration registers. These values determine how full or empty the FIFOs must be before the device requests the bus. Once RTL8186 requests the bus, it will attempt to empty or fill the FIFOs as allowed by the respective MXDMA settings in the Transmit Configuration and Receive Configuration registers.
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Transmit Buffer Manager The buffer management scheme used on the WLAN controller allows quick, simple and efficient use of the frame buffer memory. The buffer management scheme uses separate buffers and descriptors for packet information. This allows effective transfers of data to the transmit buffer manager by simply transferring the descriptor information to the transmit queue. The Tx Buffer Manager DMAs packet data from system memory and places it in the 4KB transmit FIFO, and pulls data from the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO, allowing packets to be transmitted with short interframe space. Additionally, once RTL8186 requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA setting. The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by drawing from two separate descriptor lists to fill the internal FIFO. If packets are available in the high priority queues, they will be loaded into the FIFO before those of low priority. Receive Buffer Manager The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer Manager retrieves packet data from the Rx MAC and places it in the 2KB receive data FIFO, and pulls data from the FIFO for DMA to system memory. The receive FIFO is controlled by the FIFO threshold value in RXFTH. This value determines the number of long words written into the FIFO from the MAC unit before a DMA request for system memory occurs. Once the RTL8186 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached, as set in MXDMA.
Transmit & Receive Operation The RTL8186 supports descriptor-based buffer management that will significantly lower host CPU utilization. The RTL8186 supports unlimited consecutive transmit descriptors and up to 64 consecutive descriptors for receive. There are four transmission descriptor rings for beacon, high priority packet, normal priority packet and low priority packet respectively. Besides, it includes another descriptor ring for receiving packet. Each transmit descriptor ring may consist of up to infinite 8-double-word consecutive descriptors and the receive descriptor array may consist of up to 64 4-double-word consecutive descriptors. The start address of each descriptor group should be in 256-byte alignment. Transmit Descriptor The following describes what the Tx descriptor may look like, depending on different states in each Tx descriptor.
Tx Descriptor Format (before transmitting, OWN=1, Tx command mode 1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10
O W N = 1
R C M S N RSVD DFL M S S TXRATE T RTSRATE T O P O A (4 bits) S (4 bits) S R L _ E EECE O N NFPN K R C A R G Y P T
TPKTSIZE (12 bits)
Offset 0
L E N G E X T
Length (15 bits)
RTSDUR (16 bits)
Offset 4
TX_BUFFER_ADDRESS RSVD Frame_Length (12 bits) NEXT_TX_DESCRIPTOR_ADDRESS
Offset 8 Offset 12 Offset 16
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31 30 29 28 27 www..com 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10
RATE_FALL BACK_LIMIT (4 bits)
R S V D (3 bits)
A N T E N N A
AGC (8 bits)
RETRY_LIMIT (8 bits) CWMAX CWMIN Offset 20 (4 bits) (4 bits)
RSVD RSVD
Offset 24 Offset 28
Offset# 0
Bit# 31
Symbol OWN
0
30
DMA OK
0
29
FS
0
28
LS
0
27:24
TXRATE
Description Ownership. When set, this bit indicates that the descriptor is owned by the NIC, and the data relative to this descriptor is ready to be transmitted. When cleared, it indicates that the descriptor is owned by the host system. The NIC clears this bit when the relative buffer data is transmitted. In this case, OWN=1. DMA OK. Set by the driver, reset by the RTL8186 when TX DMA OK. If IMR's corresponding bit is set and the driver sets this bit, the RTL8186 resets this bit and issues an interrupt right after DMA OK of the last segment (LS). If not, the RTL8186 just resets this bit without asserting an interrupt. First Segment Descriptor. When set, this bit indicates that this is the first descriptor of a Tx packet, and that this descriptor is pointing to the first segment of the packet. Last Segment Descriptor. When set, indicates that this is the last descriptor of a Tx packet, and this descriptor is pointing to the last segment of the packet. Tx Rate. These four bits indicate the current frame's transmission rate. Bit 27 Bit 26 Bit 25 Bit 24 1Mbps 0 0 0 0 2Mbps 0 0 0 1 5.5Mbps 0 0 1 0 11Mbps 0 0 1 1 6Mbps 0 1 0 0 9Mbps 0 1 0 1 12Mbps 0 1 1 0 18Mbps 0 1 1 1 24Mbps 1 0 0 0 36Mbps 1 0 0 1 48Mbps 1 0 1 0 54Mbps 1 0 1 1 Reserved All other combinations RTS Enable. Set to 1 indicates that an RTS/CTS handshake shall be performed at the beginning of any frame exchange sequence where the frame is of type Data or Management, the frame has an unicast address in the Address1 field, and the length of the frame is greater than RTSThreshold. RTS Rate. These four bits indicate the RTS frame's transmission rate before transmitting the current frame and will be ignored if the RTSEN bit is set to 0. Bit 22 Bit 21 Bit 20 Bit 19 1Mbps 0 0 0 0 2Mbps 0 0 0 1 5.5Mbps 0 0 1 0
0
23
RTSEN
0
22:19
RTSRATE
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Offset# www..com Bit# Symbol Description 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps Reserved
0 0 0 0 0 1 1 1 1
0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 All other combinations
1 0 1 0 1 0 1 0 1
0
18
CTSEN
0
17
MOREFRAG
0
16
SPLCP
0
15
NO_ENCRYP T RSVD TPKTSIZE LENGEXT
0 0 4
14:12 11:0 31
CTS Enable. Both RTSEN and CTSEN set to 1 indicates that the CTS-to-self protection mechanism will be used. More Fragment. This bit is set to 1 in all data type frames that have another fragment of the current packet to follow. Short Physical Layer Convergence Protocol format. When set, this bit indicates that a short PLCP preamble will be added to the header before transmitting the frame. No Encryption. This packet will be sent out without encryption even if Tx encryption is enabled. Reserved. Transmit Packet Size. This field indicates the number of bytes required to transmit the frame. Length Extension. This bit is used to supplement the Length field (bits 30:16, offset 4). This bit will be ignored if the TXRATE is set to 1Mbps, 2Mbps, or 5.5Mbps. PLCP Length: The PLCP length field indicates the number of microseconds required to transmit the frame. RTS Duration: These bits indicate the RTS frame's duration field before transmitting the current frame and will be ignored if the RTSEN bit is set to 0. 32-bit Transmit Buffer Address. Reserved. Reserved. Transmit Frame Length. This field indicates the length in the Tx buffer, in bytes, to be transmitted. 32-bit Address of the Next Transmit Descriptor. Data Rate Auto Fallback Limit. Reserved. Tx Antenna. Tx AGC. Retry Count Limit. Maximum Contention Window. Minimum Contention Window. Reserved. Reserved.
4 4 8 12 12 12 16 20 20 20 20 20 20 20 24 28
30:16 15:0 31:0 31:28 15:12 11:0 31:0 31:28 27:25 24 23:16 15:8 7:4 3:0 31:0 31:0
Length RTSDUR TxBuff RSVD RSVD Frame_Length NTDA RATE_FALL BACK_LIMIT RSVD ANTENNA AGC RETRY_LIMI T CWMAX CWMIN RSVD RSVD
CONFIDENTIAL
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www..com Tx Status Descriptor
31 30 29 28
(after transmitting, OWN=0, Tx status mode)
6 5 4 3 2 10
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
O W N = 0
DFL MSS A _ O K
RSVD (11 bits)
UT DO RK
Offset 0 RTS RC (7 bits) Packet RC (8 bits)
RSVD TX_BUFFER_ADDRESS RSVD (20 bits) Frame_Length (12 bits) NEXT_TX_ DESCRIPTOR _ADDRESS RSVD RSVD RSVD
Offset 4 Offset 8 Offset 12 Offset 16 Offset 20 Offset 24 Offset 28
Offset# 0
Bit# 31
Symbol OWN
0 0
30 29
DMA_OK FS
Description Ownership. When set, this bit indicates that the descriptor is owned by the NIC. When clear, it indicates that the descriptor is owned by the host system. The NIC clears this bit when the related buffer data has been transmitted. In this case, OWN=0. DMA Okay. First Segment Descriptor. When set, this bit indicates that this is the first descriptor of a Tx packet, and that this descriptor is pointing to the first segment of the packet. Last Segment Descriptor. When set, this bit indicates that this is the last descriptor of a Tx packet, and that this descriptor is pointing to the last segment of the packet. Reserved. FIFO under run during transmission of this packet. Transmit (Tx) OK. Indicates that a packet exchange sequence has completed successfully. RTS Retry Count. The RTS RC's initial value is 0. It indicates the number of retries of RTS. Packet Retry Count. The RC's initial value is 0. It indicates the number of retries before a packet was transmitted properly. Reserved. 32-bit Transmit Buffer Address. Reserved. Transmit Frame Length. This field indicates the length in the Tx buffer, in bytes, to be transmitted. 32-bit Address of Next Transmit Descriptor. Reserved. Reserved. Reserved.
0
28
LS
0 0 0 0 0
27:17 16 15 14:8 7:0
RSVD UDR TOK RTS RC Packet RC
4 8 12 12 16 20 24 28
31:0 31:0 31:12 11:0 31:0 31:0 31:0 31:0
RSVD TxBuff RSVD Frame_Length NTDA RSVD RSVD RSVD
Receive
This section describes what an Rx descriptor could look like, depending on different states in each Rx descriptor. An Rx buffer pointed to by one of the Rx descriptors should be at least 4 bytes.
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Rx Command Descriptor (OWN=1) www..com
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 210
OE WO NR = 1
Offset 0 RSVD (17 bits) Buffer_Size (12 bits)
RSVD (32 bits) RX_BUFFER_ADDRESS RSVD Offset# 0 Bit# 31 Symbol OWN
Offset 4 Offset 8 Offset 12
0
30
EOR
0 0 4 8 12
29:12 11:0 31:0 31:0 31:0
RSVD Buffer_Size RSVD RxBuff RSVD
Description Ownership. When set, this bit indicates that the descriptor is owned by the RTL8186, and is ready to receive a packet. The OWN bit is set by the driver after having pre-allocated a buffer at initialization, or the host has released the buffer to the driver. In this case, OWN=1. End of Rx Descriptor Ring. This bit set to 1 indicates that this descriptor is the last descriptor of the Rx descriptor ring. Once the RTL8186 internal receive descriptor pointer reaches here, it will return to the first descriptor of the Rx descriptor ring after this descriptor is used by packet reception. Reserved. Buffer Size. This field indicates the receive buffer size in bytes. Reserved. 32-bit Receive Buffer Address. Reserved.
Rx Status Descriptor (OWN=0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OEFLDFS WO S SMO P NR AVL = FFC 0 P W A K E U P
RSVD (6 bits)
R RMPBR P C S RXRATE S A A A E W R V (4 bits) V R M R S R C D D M3 G2 T D AGC (8 bits) A E N C T R E Y N P N T A E D TSFTL TSFTH
I C V
Offset 0 Frame_Length (12 bits)
Offset 4 RSSI (7 bits) SQ (8 bits)
Offset 8 Offset 12
Offset#
Bit#
Symbol
Description
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Offset# Bit# www..com 0 31 Symbol OWN Description Ownership. When set, this bit indicates that the descriptor is owned by the RTL8186. When cleared, it indicates that the descriptor is owned by the host system. The RTL8186 clears this bit when the NIC has filled this Rx buffer with a packet or part of a packet. In this case, OWN=0. End Of Rx Descriptor Ring. This bit set to 1 indicates that this descriptor is the last descriptor of the Rx descriptor ring. Once the RTL8186 internal receive descriptor pointer reaches here, it will return to the first descriptor of the Rx descriptor ring after this descriptor is used by packet reception. First Segment Descriptor. When set, this bit indicates that this is the first descriptor of a received packet, and that this descriptor is pointing to the first segment of the packet. Last Segment Descriptor. When set, this bit indicates that this is the last descriptor of a received packet, and this descriptor is pointing to the last segment of the packet. RX DMA Fail. When set, it indicates this packet is wrong in DMA, and it should be discarded by driver. FIFO Overflow. When set, this bit indicates that the receive FIFO was exhausted before this packet was fully received. Short Physical Layer Convergence Protocol format. When set, this bit indicates that a short PLCP preamble was added to the current received frame. Reserved. Rx Rate. These four bits indicate the current frame's receiving rate. Bit 23 Bit 22 Bit 21 Bit 20 1Mbps 0 0 0 0 2Mbps 0 0 0 1 5.5Mbps 0 0 1 0 11Mbps 0 0 1 1 6Mbps 0 1 0 0 9Mbps 0 1 0 1 12Mbps 0 1 1 0 18Mbps 0 1 1 1 24Mbps 1 0 0 0 36Mbps 1 0 0 1 48Mbps 1 0 1 0 54Mbps 1 0 1 1 Reserved All other combinations Reserved. Multicast Address Packet Received. When set, this bit indicates that a multicast packet was received. Physical Address Matched. When set, this bit indicates that the destination address of this Rx packet matches the value in the WLAN ID registers. Broadcast Address Received. When set, this bit indicates that a broadcast packet was received. BAR and MAR will not be set simultaneously. Receive Error. Valid if DMAF=0 Receive Power Management Packet. When set, this bit indicates that the Power Management bit is set on the received packet.
0
30
EOR
0
29
FS
0
28
LS
0
27
DMAF
0
26
FOVF
0
25
SPLCP
0 0
24 23:20
RSVD RXRATE
0 0 0
19 18 17
RSVD MAR PAM
0
16
BAR
0 0
15 14
RES PWRMGT
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Offset# Bit# www..com 0 13 Symbol CRC32 Description CRC32 Error. When set, this bit indicates that a CRC32 error has occurred on the received packet. A CRC32 packet can be received only when RCR_ACRC32 is set. Integrity Check Value Error. When set, this bit indicates that an ICV error has occurred on the received packet. A ICV packet can be received only when RCR_AICV is set. When OWN=0 and LS =1, this bit indicates the received packet length including CRC32, in bytes. Reserved. The received packet is a unicast wakeup packet. The received packet has been decrypted. The received packet is received through this antenna. The AGC of the received packet. Received Signal Strength Indicator. The RSSI is a measure of the RF energy received by the PHY. Signal Quality. The SQ is a measure of the quality of BAKER code lock, providing an effective measure during the full reception of a PLCP preamble and header. A snapshot of the TSFTR's least significant 32 bits. Valid only when LS is set. A snapshot of the TSFTR's most significant 32 bits. Valid only when LS is set.
0
12
ICV
0 4 4 4 4 4 4 4
11:0 31:27 26 25 24 23:16 15:8 7:0
Frame_Length RSVD WAKEUP DECRYPTED ANTENNA AGC RSSI SQ
8 12
31:0 31:0
TSFTL TSFTH
17. Characteristics 18. Design and Layout Guide
In order to achieve maximum performance using the RTL8186/RTL8186P, good design attention is required throughout the design and layout process. The following are some recommendations on how to implement a high performance system. General Guidelines l Provide a good power source, minimizing noise from switching power supply circuits (<50mV). l Keep power and ground noise levels below 50mV. l Use bulk capacitors (4.7F-10F) between the power and ground planes. l Use 0.1F de-coupling capacitors to reduce high-frequency noise on the power and ground planes. l Keep de-coupling capacitors as close as possible to the RTL8186/RTL8186P chip. Differential Signal Layout Guidelines l Keep differential pairs as close as possible and route both traces as identically as possible. l Avoid vias and layer changes if possible. l Keep transmit and receive pairs away from each other. Run orthogonally or separate by a ground plane. Clock Circuit l If possible, surround the clock by ground trace to minimize high-frequency emissions. l Keep the crystal or oscillator as close to the RTL8186/RTL8186P as possible. Power Plane l Divide the power plane into 1.8V digital, 3.3V analog, and 3.3V digital. l Use 0.1F decoupling capacitors and bulk capacitors between each power plane and the ground plane. Ground Plane l Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to the rest of the board.
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l Place a moat (gap) between the system ground and chassis ground. www..com RF Interface l As the RF interface is complex and power noise sensitive, we strongly recommend customers to hard copy the RF design from Realtek. Memory Interface l Keep the SDRAM as close as possible to the RTL8186/RTL8186P. The FLASH timing is slower than SDRAM so place the SDRAM closer than FLASH if space considerations prevent placing both components equally close to the RTL8186/RTL8186P. l Where two banks of SDRAM are used, the memory clock trace should have the same length.
18. Mechanical Dimensions
Package Outline for 208 LQFP (28*28*1.4mm)
Notes for 208 LQFP
Symbol A A1 Dimension in inch Dimension Min Typ Max Min Typ 0.136 0.144 0.152 3.45 3.65 0.004 0.010 0.036 0.10 0.25 in mm Max 3.85 0.91 Notes: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion.
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A2 0.119 0.128 www..com b c D E e HD HE L L1 y 0.004 0.002 1.093 1.093 0.012 1.169 1.169 0.010 0.041 0 0.008 0.006 1.102 1.102 0.020 1.205 1.205 0.020 0.051 0.136 0.012 0.010 1.112 1.112 0.031 1.240 1.240 0.030 0.061 0.004 12 3.02 0.10 0.04 27.75 27.75 0.30 29.70 29.70 0.25 1.05 0 3.24 0.20 0.15 28.00 28.00 0.50 30.60 30.60 0.50 1.30 3.46 0.30 0.26 28.25 28.25 0.80 31.50 31.50 0.75 1.55 0.10 12 3.Controlling dimension: Millimeter 4.General appearance spec. should be based on final visual inspection spec. TITLE : 208L QFP ( 28x28 mm*2 ) FOOTPRINT 2.6mm PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: APPROVE DOC. NO. VERSION PAGE CHECK DWG NO. DATE REALTEK SEMICONDUCTOR CORP.
Package Outline for TFBGA 292 BALL (17*17 mm)
Notes for TFBGA 292 BALL
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Symbol A A1 A2 c D E D1 E1 e b aaa bbb ccc ddd eee MD/ME
Dimension Min --0.25 0.84 0.32 16.90 16.90 ------0.35 Nom --0.30 0.89
in
mm Dimension Max 1.30 0.35 0.94
in inch
Notes:
1. CONTROLLING DIMENSION: MILLIMETER 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 5. REFERENCE DOCUMENT: JEDEC MO-205. 6. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY. TITLE : 292LD TFBGA ( 17x17mm) PACKAGE OUTLINE SUBSTRATE MATERIAL: BT RESIN APPR. ENG. QM. CHK. DWG. REALTEK SEMICONDUCTOR CORP.
Min Nom Max ----- 0.051 0.010 0.012 0.014 0.033 0.035 0.037
0.36 0.40 013 0.014 0.016 17.00 17.10 0.665 0.669 0.673 17.00 17.10 0.665 0.669 0.673 15.20 ----- 0.598 --15.20 ----- 0.598 --0.80 ----- 0.031 --0.40 0.45 0.014 0.016 0.018 0.10 0.004 0.10 0.004 0.12 0.005 0.15 0.006 0.08 0.003 20/20 20/20
DWG NO. Rev NO PRODUCT CODE DATE. SHT No.
Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw
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