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INTEGRATED CIRCUITS
DATA SHEET
SAA7705H Car radio Digital Signal Processor (DSP)
Preliminary specification File under Integrated Circuits, IC01 1999 Aug 16
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
CONTENTS 1 1.1 1.2 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.5 8.5.1 8.5.2 8.5.3 FEATURES Hardware Software APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION FM and level information processing Signal path for level information Signal path from FMMPX input to IAC and stereo decoder Input sensitivity for FM and RDS signals AD input selection switch Interference absorption circuit Analog source selection and analog-to-digital conversion Input selection switches Signal flow of the AM, analog CD and TAPE inputs The analog CD block Pin VREFAD Pins VDACN1, VDACN2 and VDACP Supply of the analog inputs Analog outputs DACs Upsample filter Volume control Function of pin POM Power-off plop suppression The internal pin VREFDA Internal DAC current reference Supply of the analog outputs Clock circuit and oscillator Supply of the crystal oscillator The phase-locked loop circuit to generate the DSP clock and other derived clocks The clock block Synchronization with the core Equalizer accelerator circuit Introduction EQ circuit overview Controller and programming circuit 8.6 8.7 8.8 8.9 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.11 9 10 11 12 12.1 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.3 12.4 12.5 13 13.1 13.2 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18
SAA7705H
The DSP core External control pins and status register I2C-bus interface (pins SCL and SDA) I2S-bus inputs and outputs RDS decoder (pins RDSCLK and RDSDAT) Clock and data recovery Timing of clock and data signals Buffering of RDS data Buffer interface DSP reset LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2C-BUS INTERFACE AND PROGRAMMING I2C-bus interface Characteristics of the I2C-bus Bit transfer Start and stop conditions Data transfer Acknowledge I2C-bus protocol Addressing Slave address Write cycles Read cycles Memory map specification and register overview Register description Detailed register description APPLICATION INFORMATION Software description Power supply connection and EMC PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
1 1.1 FEATURES Hardware
SAA7705H
* Three 3rd-order Switched Capacitor Analog-to-Digital converters (SCADs) * Digital-to-Analog Converters (DACs) with four times oversampling and noise shaping * Digital stereo decoder for the FM multiplex signal * Improved digital Interference Absorption Circuit (IAC) for FM * Radio Data System (RDS) processing with an optional 16-bit buffer via a separate channel (two tuners possible) * Auxiliary high Common-Mode Rejection Ratio (CMRR) analog CD input (CD-walkman, speech, economic CD-changer, etc.) * I2C-bus controlled * Four channel 5-band I2C-bus controlled parametric equalizer * Two separate full I2S-bus and LSB-justified formats high performance input interfaces * Audio output short-circuit protected * Separate AM left and right inputs * Phase-Locked Loop (PLL) to generate the high frequency DSP clock from a common fundamental oscillator crystal * Analog single-ended tape inputs * I2S-bus subwoofer output (mono or stereo) * Expandable with additional DSPs for sophisticated features through an I2S-bus gateway * Operating ambient temperature from -40 to +85 C. 1.2 Software * Music Search System (MSS) detection for tape * Dolby-B tape noise reduction * Adjustable dynamics compressor * CD de-emphasis processing * Improved AM reception * Soft audio mute * AM IAC * Pause detection for RDS updates * Signal level, noise and multipath detection for AM/FM signal quality information. 2 APPLICATIONS
* Car radio systems. 3 GENERAL DESCRIPTION
The SAA7705H performs all the signal functions in front of the power amplifiers and behind the AM and FM multiplex demodulation of a car radio or the tape input. These functions are: * Interference absorption * Stereo decoding * RDS decoding * FM and AM weak signal processing (soft mute, sliding stereo, etc.) * Dolby-B tape noise reduction * Audio controls (volume, balance, fader and tone). Some functions have been implemented in the hardware (stereo decoder, RDS decoding and IAC for FM multiplex) and are not freely programmable. Digital audio signals from external sources with the Philips I2S-bus format or the LSB-justified 16, 18 or 20 bits format are accepted. There are four independent analog output channels. The channels have a hardware implemented 5-band parametric equalizer, controlled via the I2C-bus.
* Improved FM weak signal processing * Integrated 19 kHz MPX filter and de-emphasis * Electronic adjustments: FM/AM level, FM channel separation and Dolby level * Baseband audio processing (treble, bass, balance, fader and volume) * Dynamic loudness or bass boost * Audio level meter * Tape equalisation (tape analog playback)
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
The DSP contains a basic program that enables a set with: * AM/FM reception * Sophisticated FM weak signal functions * Music Search System (MSS) detection for tape 4 QUICK REFERENCE DATA SYMBOL Supply VDDD3V IDDD3V VDDD5V IDDD5V VDDA IDDA digital supply voltage 3.3 V for DSP core supply current of the 3.3 V digital DSP core supply voltage 5 V for periphery supply current of the 5 V digital periphery analog supply voltage 3.3 V analog supply current VDDAx pins with respect to VSS zero input and output signal VDDD3Vx pins with respect to VSS 3 high activity of the DSP at 27 MHz DSP frequency - 3.3 80 5 3 3.3 40 PARAMETER CONDITIONS MIN. TYP.
SAA7705H
* Dolby-B tape noise reduction system * CD play with compressor function * Separate bass and treble tone control and fader or balance control additional to the equalizers.
MAX.
UNIT
3.6 110 5.5 5 3.6 50 -
V mA V mA V mA
VDDDV5x pins with respect to VSS 4.5 - 3 -
Analog level inputs (AML and FML); Tamb = 25 C; VDDA1 = 3.3 V; unless otherwise specified S/NLAD level-ADC signal-to-noise 0 to 29 kHz bandwidth; ratio maximum input level; unweighted input voltage level-ADC for full-scale 48 54 dB
Vi(LAD)
0
-
VDDA1
V
Analog inputs; Tamb = 25 C; VDDA1 = 3.3 V; unless otherwise specified THDFMMPX total harmonic distortion FMMPX input signal-to-noise ratio FMMPX input mono signal-to-noise ratio FMMPX input stereo total harmonic distortion CD inputs signal-to-noise ratio CD inputs total harmonic distortion AM inputs input signal 0.35 V (RMS) at 1 kHz; bandwidth = 19 kHz; note 1 input signal at 1 kHz; 0 dB reference = 0.35 V (RMS); bandwidth = 19 kHz; note 1 input signal at 1 kHz; 0 dB reference = 0.35 V (RMS); bandwidth = 40 kHz; note 1 input signal 0.55 V (RMS) at 1 kHz; input gain = 1; bandwidth = 20 kHz input signal at 1 kHz; 0 dB reference = 0.55 V (RMS); bandwidth = 20 kHz input signal 0.55 V (RMS) at 1 kHz; bandwidth = 5 kHz - - 80 -70 0.03 83 -65 0.056 - dB % dB
S/NFMMPX(m)
S/NFMMPX(s)
74
77
-
dB
THDCD
- - 81
-83 0.007 84
-78 0.013 -
dB % dB
S/NCD
THDAM
- -
-80 0.01
-76 0.016
dB %
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL S/NAM
PARAMETER signal-to-noise ratio AM inputs total harmonic distortion TAPE inputs signal-to-noise ratio TAPE inputs maximum conversion input level at analog inputs (RMS value)
CONDITIONS input signal at 1 kHz; 0 dB reference = 0.55 V (RMS); bandwidth = 5 kHz input signal 0.55 V (RMS) at 1 kHz; bandwidth = 20 kHz; input signal at 1 kHz; 0 dB reference = 0.55 V (RMS); bandwidth = 20 kHz THD < 1%
MIN. 83
TYP. 88 -
MAX.
UNIT dB
THDTAPE S/NTAPE
- - 81
-80 0.01 83
-76 0.016 -
dB % dB
Vi(con)(max)(rms)
0.6
0.66
-
V
Analog outputs; Tamb = 25 C; VDDA2 = 3.3 V; unless otherwise specified (THD + N)/S total harmonic distortion-plus-noise to signal ratio dynamic range output signal 0.72 V (RMS) at f = 1 kHz; RL > 5 k (AC); A-weighted output signal -60 dB at 1 kHz; 0 dB reference = 0.77 V (RMS); A-weighted output signal at 20 Hz to 17 kHz; 0 dB reference = 0.77 V (RMS); A-weighted - -75 -65 dBA
DR
92
102
-
dBA
DS
digital silence
-
-108
-102
dBA
Oscillator (fosc = 11.2896 MHz) fxtal fclk(DSP) Note 1. FMRDS and FMMPX input sensitivity setting `000' (see Table 17). 5 ORDERING INFORMATION TYPE NUMBER SAA7705H PACKAGE NAME QFP80 DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT318-2 crystal frequency clock frequency DSP core - - 11.2896 - 27.1656 - MHz MHz
1999 Aug 16
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VDACP VDACN1 1 2 AML FML 4 3 LEVEL-ADC SIGNAL LEVEL 5 POM CDLB CDLI CDRB CDRI CDGND VREFAD 73 72 71 70 77 78 INPUT STAGE 16 15 SIGNAL QUALITY DSP CORE QUAD DIGITAL TO ANALOG CONVERTER (QDAC) 13 14 9 8 6 AMAFR TAPEL TAPER FMMPX FMRDS 66 69 68 80 SCAD3 79 ANALOG SOURCE SELECTOR DIGITAL SOURCE SELECTOR SCAD2 7 12 34 35 30 33 RDS DECODER I2C-BUS INTERFACE 31 32 59 RDSCLK 65 VDD(OSC) 63 OSCIN 64 OSCOUT 62 VSS(OSC) 29 CD1CL 27 CD1WS 28 CD1DATA 25 CD2DATA 24 CD2WS 26 CD2CL 57 SCL 58 SDA 56 A0 42 DSPRESET FLV FLI FRV FRI RLV RLI RRV RRI VREFDA IISOUT1 IISOUT2 IISCLK IISWS IISIN1 RTCB
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Philips Semiconductors
handbook, full pagewidth
Car radio Digital Signal Processor (DSP)
BLOCK DIAGRAM
DSPOUT1
74
76
75
21
22
36
46
49
50
53
54
23
37
47
48
51
52
55
38
39
40
DSPOUT2 41 11 VDDA2
VDDD5V1
VDDD5V2
VDDD5V3
VDDD3V1
VDDD3V2
VDDD3V3
VDDD3V4
VSSD3V1
VSSD3V2
VSSD3V3
VSSD3V4
VSSD5V1
VSSD5V2
VSSD5V3
VDACN2
DSPIN1
SAA7705H
EQUALIZER 10 VSSA2
AMAFL
67
SCAD1
IAC
STEREO DECODER
SELFR
61
OSCILLATOR
DSPIN2
VDDA1
VSSA1
TP5
TP1
TP2
TP3
SHTCB
TSCAN
TP4
RDSDAT
6
43 44 45 17 18 19 20 60
Preliminary specification
IISIN2
SAA7705H
MGM119
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
7 PINNING SYMBOL VDACP VDACN1 FML AML POM RRV RRI RLI RLV VSSA2 VDDA2 VREFDA FRV FRI FLI FLV TP1 TP2 TP3 TP4 TP5 VDDD5V1 VSSD5V1 CD2WS CD2DATA CD2CL CD1WS CD1DATA CD1CL IISCLK IISIN1 IISIN2 IISWS IISOUT1 IISOUT2 VDDD5V2 VSSD5V2 DSPIN1 DSPIN2 1999 Aug 16 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 PIN TYPE AP2D AP2D AP2D AP2D AP2D AP2D AP2D AP2D AP2D APVSS APVDD AP2D AP2D AP2D AP2D AP2D BT4CR BT4CR BT4CR BT4CR IBUFD VDDE5 VSSE5 IBUFD IBUFD IBUFD IBUFD IBUFD IBUFD BT4CR IBUFD IBUFD BD4CR BD4CR BD4CR VDDE5 VSSE5 IBUFD IBUFD DESCRIPTION
SAA7705H
positive reference voltage for SCAD1, SCAD2, SCAD3 and level-ADC ground reference voltage 1 for SCAD1, SCAD2, SCAD3 and level-ADC FM level input; via this pin the level of the FM signal is fed to the SAA7705H; the level information is needed for a correct functioning of the weak signal behaviour AM level input; via this pin the level of the AM signal is fed to the SAA7705H power-on mute of the QDAC; timing is determined by an external capacitor rear right audio voltage output of the QDAC rear right audio current output of the QDAC rear left audio current output of the QDAC rear left audio voltage output of the QDAC ground supply for the analog part of the QDAC positive supply for the analog part of the QDAC decoupling for voltage reference of the analog part of the QDAC front right audio voltage output of the QDAC front right audio current output of the QDAC front left audio current output of the QDAC front left audio voltage output of the QDAC test pin, used in factory test mode, must not be connected test pin, used in factory test mode, must not be connected test pin, used in factory test mode, must not be connected test pin, used in factory test mode, must not be connected test pin, used in factory test mode, must be connected to VDDD5V positive supply 1 for peripheral cells ground supply 1 for peripheral cells word select input 2 from a digital audio source (I2S-bus or LSB-justified format) left or right data input 2 from a digital audio source (I2S-bus or LSB-justified format) clock input 2 from a digital audio source (I2S-bus or LSB-justified format) word select input 1 from a digital audio source (I2S-bus or LSB-justified format) left or right data input 1 from a digital audio source (I2S-bus or LSB-justified format) clock input 1 from a digital audio source (I2S-bus or LSB-justified format) clock output to extra DSP chip (I2S-bus) data input channel 1 (front) from extra DSP chip (I2S-bus) data input channel 2 (rear) from extra DSP chip (I2S-bus) word select input or output for extra DSP chip (I2S-bus) data output to extra DSP chip (I2S-bus) subwoofer output (I2S-bus) positive supply 2 for peripheral cells ground supply 2 for peripheral cells digital input 1 of the DSP core (flag F0 of the status register) digital input 2 of the DSP core (flag F1 of the status register) 7
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL DSPOUT1 DSPOUT2 DSPRESET RTCB SHTCB TSCAN VDDD5V3 VSSD5V3 VDDD3V1 VSSD3V1 VSSD3V2 VDDD3V2 VDDD3V3 VSSD3V3 VSSD3V4 VDDD3V4 A0 SCL SDA RDSCLK RDSDAT SELFR
PIN 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
PIN TYPE B4CR B4CR IBUFU IBUFD IBUFD IBUFD VDDE5 VSSE5 VDDI3 VSSI3 VSSI3 VDDI3 VDDI3 VSSI3 VSSI3 VDDI3 IBUFD BD4SCI4 BD4CR BT4CR IBUFD
DESCRIPTION digital output 1 of the DSP core (flag F2 of the status register) digital output 2 of the DSP core (flag F3 of the status register) reset input to the DSP core (active LOW) asynchronous reset test control block, connect to ground shift clock test control block, connect to ground scan control (active HIGH), connect to ground positive supply 3 for peripheral cells ground supply 3 for peripheral cells positive supply 1 for DSP core ground supply 1 for DSP core ground supply 2 for DSP core positive supply 2 for DSP core positive supply 3 for DSP core ground supply 3 for DSP core ground supply 4 for DSP core positive supply 4 for DSP core I2C-bus address selection serial data input/output (I2C-bus) RDS bit clock output or RDS external clock input RDS data output AD input selection switch; to enable high-ohmic FMMPX input at fast tuner search on pin FMRDS; if SELFR is HIGH, the input at pin FMRDS is put through to SCAD1 and FMRDS gets high-ohmic; this pin works together with the AD register bit SELTWOTUN (see Table 9) ground supply for crystal oscillator circuit crystal oscillator input: crystal oscillator sense for gain control or forced input in slave mode crystal oscillator output: drive output to 11.2896 MHz crystal positive supply for crystal oscillator circuit AM audio frequency analog input (right channel) AM audio frequency analog input (left channel) tape analog input (right channel) tape analog input (left channel) CD analog input (right channel) feedback input of the CD analog input (right channel) CD analog input (left channel) feedback input of the CD analog input (left channel) analog positive supply for SCAD1, SCAD2, SCAD3 and level-ADC analog ground supply SCAD1, SCAD2, SCAD3 and level-ADC ground reference voltage 2 for SCAD1, SCAD2, SCAD3 and level-ADC
SCHMITCD serial clock input (I2C-bus)
VSS(OSC) OSCIN OSCOUT VDD(OSC) AMAFR AMAFL TAPER TAPEL CDRI CDRB CDLI CDLB VDDA1 VSSA1 VDACN2
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
APVSS AP2D AP2D APVDD AP2D AP2D AP2D AP2D AP2D AP2D AP2D AP2D APVDD APVSS AP2D
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL CDGND VREFAD FMRDS FMMPX Table 1
PIN 77 78 79 80
PIN TYPE AP2D AP2D AP2D AP2D
DESCRIPTION positive reference for analog CD block common-mode reference voltage SCAD1, SCAD2, SCAD3 and level-ADC FM RDS analog input FM multiplex analog input
Explanation of pin types DESCRIPTION analog input/output analog supply analog ground 5 V peripheral supply 5 V peripheral ground connection, no connection to the substrate 3.3 V supply to digital core and internal I/O pads 3.3 V ground to digital core and internal I/O pads, no connection to the substrate CMOS, Schmitt trigger input with active pull-down CMOS, active pull-up to all VDDE5 pads CMOS, active pull-down to all VSSE5 pads bidirectional CMOS I/O buffer, 4 mA, slew rate control 4 mA CMOS 3-state output buffer, slew rate control 4 mA CMOS output buffer, slew rate control CMOS I/O pad with open-drain output
PIN TYPE AP2D APVDD APVSS VDDE5 VSSE5 VDDI3 VSSI3 SCHMITCD IBUFU IBUFD BD4CR BT4CR B4CR BD4SCI4
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
76 VDACN2
78 VREFAD
handbook, full pagewidth
VDACP VDACN1 FML
65 VDD(OSC) 64 OSCOUT 63 OSCIN 62 VSS(OSC) 61 SELFR 60 RDSDAT 59 RDSCLK 58 SDA 57 SCL 56 A0 55 VDDD3V4 54 VSSD3V4 53 VSSD3V3 52 VDDD3V3 51 VDDD3V2 50 VSSD3V2 49 VSSD3V1 48 VDDD3V1 47 VSSD5V3 46 VDDD5V3 45 TSCAN 44 SHTCB 43 RTCB 42 DSPRESET 41 DSPOUT2 DSPOUT1 40
77 CDGND
80 FMMPX
79 FMRDS
1 2 3
AML 4 POM RRV RRI RLI RLV 5 6 7 8 9
VSSA2 10 VDDA2 11 VREFDA 12
SAA7705H
FRV 13 FRI 14 FLI 15 FLV 16 TP1 17 TP2 18 TP3 19 TP4 20 TP5 21 VDDD5V1 22 VSSD5V1 23 CD2WS 24 CD2DATA 25 CD2CL 26 CD1WS 27 CD1DATA 28 CD1CL 29 IISCLK 30 IISIN1 31 IISIN2 32 IISWS 33 IISOUT1 34 IISOUT2 35 VDDD5V2 36 VSSD5V2 37 DSPIN1 38 DSPIN2 39
66 AMAFR
74 VDDA1
67 AMAFL
68 TAPER
75 VSSA1
69 TAPEL
73 CDLB
71 CDRB
70 CDRI
72 CDLI
MGM118
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
8 FUNCTIONAL DESCRIPTION
SAA7705H
The SAA7705H consists of a DSP core and periphery. The DSP core is described in Sections 8.6, 8.7 and 8.11. The periphery handles the following tasks: * FM and level information processing (see Section 8.1) * Analog source selection and analog-to-digital conversion of the analog audio sources (see Section 8.2) * Digital-to-analog conversion of the DSP output QDAC (see Section 8.3) * Clock circuit and oscillator (see Section 8.4) * Equalizer accelerator circuit (see Section 8.5) * I2C-bus interface (see Section 8.8 and Chapter 12) * RDS decoder (see Section 8.10). 8.1 8.1.1 FM and level information processing SIGNAL PATH FOR LEVEL INFORMATION
of FM reception, it must be in the narrow position. The FMMPX path is followed by the sample-and-hold switch of the IAC (see Section 8.1.5) and the 19 kHz pilot signal regeneration circuit. A second decimation filter reduces the output of the IAC to a lower sample rate. One of the two filter outputs contains the multiplexed signal with a frequency range of 0 to 60 kHz. The outputs of this signal path to the DSP (which are all running on a sample frequency of 38 kHz) are: * Pilot presence indication: Pilot-I. This one bit signal is LOW for a pilot frequency deviation <4 kHz and HIGH for a pilot frequency deviation >4 kHz and locked on a pilot tone. * FM reception stereo signal. This is the 18-bit output of the stereo decoder after the matrix decoding in Information System Network (ISN) I2S-bus format. This signal is fed via a multiplexer to a general I2S-bus interface block that communicates with the DSP core. * A noise level indication. This signal is derived from the first MPX decimation filter via a wide band noise filter. Detection is done with an envelope detector. This noise level is filtered in the DSP core and is used to optimize the FM weak signal processing. 8.1.3 INPUT SENSITIVITY FOR FM AND RDS SIGNALS
For FM weak signal processing and for AM and FM purposes (absolute level and multipath), an FM level and an AM level input is implemented (pins FML and AML). In the case of radio reception clocking of the filters and the level-ADC is based on a 38 kHz sample frequency. The DC input signal is converted by a bitstream first-order Sigma-Delta ADC followed by a decimation filter. The input signal has to be obtained from the radio part. Two different configurations for AM and FM reception are possible: * A circuit with two separate level signals: one for FM level and one for AM level * A combined circuit with AM and FM level information on the FM level input. The level input is selected with bit LEVAM-FM of the SEL register (see Table 12 and Chapter 12). 8.1.2 SIGNAL PATH FROM FMMPX INPUT TO IAC AND
STEREO DECODER
The FM and RDS input sensitivity is designed for tuner front ends which deliver an output voltage varying from 65 to 225 mV (RMS) at a sweep of 22.5 kHz for a 1 kHz tone. The intermediate standard input sensitivities can be reached in steps of 1.6 dB, to be programmed with the AD register bits VOLFM and VOLRDS (see Tables 9 and 17). The volume control of the FMMPX and the FMRDS input can be controlled separately. VOLFM and VOLRDS = 000 is the most sensitive position, VOLFM and VOLRDS = 111 the least sensitive position. Due to the analog circuit control of the volume gain, the input impedance of pin FMMPX or pin FMRDS changes with the volume setting. 8.1.4 AD INPUT SELECTION SWITCH
The SAA7705H has four analog audio source channels. One of the analog inputs is the FM multiplex signal. Selection of this signal can be achieved by the SEL register bits AUX-FM and CD-TAPE (see Table 12). The multiplexed FM signal is converted to the digital domain in SCAD1, a bitstream third-order SCAD. The first decimation with a factor of 16 takes place in down sample filter ADF1. This decimation filter can be switched by means of the SEL register bit WIDE-NARROW (see Table 12) in the wide or narrow band position. In case
Pin SELFR makes it possible to change to another transmitter frequency with the same radio program to assess the quality of that signal. In case of a stronger transmitter signal the decision can be made by the software to switch to the new transmitter. The FMMPX input is normally used to process the FM signal. This FMMPX input is connected via a relative large capacitor to the MPX tuner output. Switching the tuner to another transmitter frequency means another DC voltage level on the MPX output of the tuner and a charging of the 11
1999 Aug 16
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
series capacitor (because the FMMPX input of the SAA7705H is low-ohmic). Pulling SELFR HIGH during such an update, causes the FMMPX input to become high-ohmic, preventing charging of the capacitor. The signal probing of the new transmitter quality is done via the FMRDS input. 8.1.5 INTERFERENCE ABSORPTION CIRCUIT
SAA7705H
based on probability calculations. This detector performs optimally with higher antenna voltages. On detection of ignition interference, this logic will send appropriate pulses to the MPX mute switch. * Level detector: The input signal of the second detector is the FM level signal (the output of the level-ADC). This detector performs optimally with lower antenna voltages. It is therefore complementary to the first detector. The characteristics of both ignition interference pulse detectors can be adapted to the properties of different FM front ends by means of the coefficients in the IAC register and the level-IAC register (see Section 12.4). Both IAC detectors can be switched on or off independently. Both IAC detectors can mute the MPX signal independently. * Dynamic detector: The third detector is the dynamic IAC circuit. This detector switches off the IAC completely if the frequency deviation of the FM multiplex signal is too high. The use of narrow band IF filters can result in AM modulation. This AM modulation could be interpreted by the IAC circuitry as interference caused by the car's engine.
The Interference Absorption Circuit (IAC) detects and suppresses ignition interference. This hardware IAC is a modified, digitized and extended version of the analog circuit which is in use for many years already. The IAC consists of an MPX mute function switched by mute pulses from two ignition interference pulse detectors. A third detector inhibits muting. The three detectors are: * Interference detector: The input signal of the first detector is the output signal of SCAD1. This interference detector analyses the high frequency contents of the MPX signal. The discrimination between interference pulses and other signals is performed by a special Philips patented fuzzy logic such as algorithm and is
handbook, full pagewidth
FML AML
3 4 LEVEL-ADC
AMAFR TAPER CDRB CDRI CDGND AMAFL TAPEL CDLB CDLI FMMPX
66 68 71 70 77 67 69 73 72 80 GAIN CONTROL SCAD3 INPUT SELECTOR ROUTER SCAD1 SCAD2
FMRDS
79
SELFR
61
MGM123
Fig.3 Analog input switching circuit.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Parameter setting for the IAC detectors is done by means of 5 different coefficients. Upon reset, the nominal setting for a good performing IAC detector is selected.
SAA7705H
8.1.5.1
AGC set point (1 bit)
In case the sensitivity and feed-forward factor are out of range in a certain application, the set point of the AGC can be shifted. The set point controls the sensitivity of the other IAC control parameters. See bit 11 of the IAC register (Table 11).
8.1.5.2
Threshold sensitivity offset (3 bits)
via the FM demodulator and MPX conversion and filtering. These differences depend on the front end used in the car radio. With a simultaneous appearance of a peak disturbance at the FM level input and the MPX ADC input of the IC, a zero delay setting takes care for the level-IAC mute pulse to coincide with the passage of the disturbance in the MPX mute circuit. The setting for the level-IAC feed-forward allows to advance the mute pulse by 1 sample period or to delay it by 1 or 2 sample periods of the 304 kHz clock, with respect to the default value. The appropriate register bits for each setting are given in Table 20.
With this parameter the threshold sensitivity of the comparator in the interfering pulse detectors can be set. It also influences the amount of unwanted triggering. Settings are according to Table 25.
8.1.5.8
Level-IAC suppression stretch time (2 bits)
8.1.5.3
Deviation feed-forward factor (3 bits)
This parameter sets the time that the mute pulse is stretched when the FM level input has stopped exceeding the threshold. The duration can be selected in steps of one period of the 304 kHz (3.3 s) sample frequency. In Table 19 the possible values are given.
This parameter determines the reduction of the sensitivity of the detector by the absolute value of the MPX signal. This mechanism prevents the detector from unwanted triggering at noise with modulation peaks. In Table 24 the possible values are given.
8.1.5.9
Dynamic IAC threshold levels
8.1.5.4
Suppression stretch time (3 bits)
This parameter sets the duration of the pulse suppression after the detector has stopped sending a trigger pulse. It can be switched off by setting the value `000'. The duration can be selected in steps of one period of the 304 kHz (3.3 s) sample frequency. In Table 23 the possible values are given.
If enabled by bit 15 of the LEVELIAC register, this block will disable temporarily all IAC actions if the MPX mono signal exceeds a threshold deviation (threshold 1) for a given time with a given excess amount (threshold 2). This MPX mono signal is separated from the MPX signal with a low-pass filter with the -3 dB corner point at 15 kHz. The possible values of this threshold are given in Table 18.
8.1.5.10
IAC testing mode
8.1.5.5
MPX delay (2 bits)
With this parameter the delay time between 2 and 5 samples of the 304 kHz sample frequency can be selected. The needed value depends on the used front end of the car radio. Settings are according to Table 22.
The internal IAC trigger signal is visible on pin DSPOUT2 if bit IACTRIGGER of the IAC register is set. In this mode the effect of the parameter settings on the IAC performance can be verified. 8.2 8.2.1 Analog source selection and analog-to-digital conversion INPUT SELECTION SWITCHES
8.1.5.6
Level-IAC threshold (4 bits)
With this parameter the sensitivity of the comparator in the ignition interference pulse detector can be set. It also influences the amount of unwanted triggering. The possible values are given in Table 21. The prefix value `0000' switches off the level-IAC function.
In Fig.3 the block diagram of the input is shown. The input selection is controlled by bits in the input selector control register and the input selection pin SELFR. The relationship between these bits and the switches is indicated in Table 26. 8.2.2 SIGNAL FLOW OF THE AM, ANALOG CD AND TAPE
INPUTS
8.1.5.7
Level-IAC feed-forward setting (2 bits)
This parameter allows for adjusting delay differences in the signal paths from the FM antenna to the MPX mute, namely, via the FM level-ADC and level-IAC detection and 1999 Aug 16 13
The signal of the two single-ended stereo AM inputs can be selected by the correct values of the SEL register bits according to Table 26.
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
The AM and the TAPE inputs are buffered with an operational amplifier to ensure a high-impedance input which enables the use of an external resistor divider for signal reduction. For correct biasing of the first operational amplifier a resistor must be connected between the input and pin VREFAD, which acts as a virtual ground (see Fig.21). The analog input switching circuit is shown in Fig.3. The input for an analog CD player is explained in more detail in Section 8.2.3. 8.2.3 THE ANALOG CD BLOCK
SAA7705H
Which part of the common-mode signal is processed as the real input signal depends on the ratio of the CDGND resistor and the series resistor in the cable and the difference in input offset of the operational amplifiers. The induced signals on the CDLI and CDRI lines are of the same amplitude and therefore rejected as common-mode signals in the SCADs. 8.2.4 PIN VREFAD
Special precautions are taken to realize a high Common-Mode Rejection Ratio (CMRR) in case of the use of a CD player output processed via analog inputs. The block diagram is shown in Fig.4. The operational amplifiers OAR and OAL are used as buffers. The gain of these operational amplifiers can be adjusted via the external resistors and is in this case 0.54 by using a 8.2 k and a 15 k resistor. The reference inputs of these operational amplifiers are connected to a separate pin CDGND. This pin is on one side AC connected to the ground shielding of the cable coming from the CD player and via a resistor >1 M to pin VREFAD. In this configuration the common-mode signal propagates all the way to the SCAD block inputs of SCAD1 and SCAD2. The SCADs themselves have a good rejection ratio for in-phase common-mode signals.
The middle reference voltage of the SCAD1, SCAD2, SCAD3 and level-ADC can be filtered via this pin. This voltage is used as half the supply reference of the SCAD1, SCAD2, SCAD3 and as the positive reference for the level-ADC and buffers. External capacitors (connected to VSSA1) prevent crosstalk between the SCADs and buffers and improve the power supply rejection ratio of all blocks. This pin must also be used as a reference for the inputs AMAFL, AMAFR, TAPEL, TAPER and CDGND. 8.2.5 PINS VDACN1, VDACN2 AND VDACP
These pins are used as ground and positive supply reference for the SCAD1, SCAD2, SCAD3 and the level-ADC. For optimal performance, pins VDACN1 and VDACN2 must be directly connected to the VSSA1 and pin VDACP to the filtered VDDA1.
handbook, full pagewidth
8.2 k
CDLB 73
15 k LEFT
CDLI 72 to SCAD2 via router CDGND 77 1 M OAL
GROUND
CD-player analog output 8.2 k
VREFAD 78
to SCADs and level-ADC
CDRB 71
15 k RIGHT
CDRI 70 to SCAD1 via router OAR
off-chip
on-chip
MGM124
Fig.4 Analog CD block.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
8.2.6 SUPPLY OF THE ANALOG INPUTS
SAA7705H
The analog input circuit has separate power supply connections to allow maximum filtering of the analog supply voltages: VSSA1 for the analog ground and VDDA1 for the analog supply. 8.3 8.3.1 Analog outputs DACS
signal-to-noise ratio larger then 105 dB. The word clock for the upsample filter (4 x fs) is derived from the audio source timing. If the internal audio source is selected, the sample frequency can be either 44.1 or 38 kHz. In case of external digital sources (CD1 and CD2), a sample frequency from 32 to 48 kHz is possible. 8.3.3 VOLUME CONTROL
Each of the four low noise high dynamic range DACs consists of a 15-bit signed magnitude DAC with current output, followed by a buffer operational amplifier. For each of the four audio output channels a separate convertor is used. Each converter output is connected to the inverting input of one of the four internal CMOS operational amplifiers. The non-inverting input of this operational amplifier is connected to the internal reference voltage. Together with an internal resistor the conversion of current-to-voltage of the audio output is achieved. 8.3.2 UPSAMPLE FILTER
The total volume control has a dynamic range of more than 100 dB (0 dB being maximal input on the I2S-bus input). With the signed magnitude noise shaped 15-bit DAC and the internal 18-bit registers (these registers provide the digital data communication between the DSP and the QDAC) of the DSP core a useful digital volume control range of 100 dB is possible by calculating the corresponding coefficients. The step size is freely programmable and an additional analog volume control is not needed in this design. The SNR of the audio output at full-scale is determined by the total 15 bits of the converter. The noise at low outputs is fully determined by the noise performance of the DAC. Since it is a signed magnitude type, the noise at digital silence is also low. The disadvantage is that the total THD is higher than conventional DACs. The typical THD-plus-noise versus output level is shown in Fig.5.
To reduce spectral components above the audio band, a fixed 4 times oversampling and interpolating 18-bit digital IIR filter is used. It is realized as a bit serial design and consists of two consecutive filters. The data path in these filters is 22 bits to prevent overflow and to maintain a
handbook, full pagewidth
0 THD + N (dB) -20 -30 -40 -50 -60 -70 -80
MGM125
-90 -80
-70
-60
-50
-40
-30
-20
-10 output level (dB)
0
Fig.5 Typical THD + N curve versus output level.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
8.3.4 FUNCTION OF PIN POM 8.3.8
SAA7705H
SUPPLY OF THE ANALOG OUTPUTS
With pin POM it is possible to switch-off the reference current of the DAC. The capacitor on pin POM (see Fig.21) determines the time after which this current has a soft switch-on. At power-on, the current audio signal outputs are always muted. The external capacitor is loaded in two stages via two different current sources. The loading starts at a current level that is 9 times lower than the load current after the voltage on pin POM has risen above 1 V. This results in an almost dB-linear behaviour. However, the DAC has an asymmetrical supply and the DC output voltage will be half the supply voltage under functional conditions. During start-up the output voltage is not defined as long as the supply voltage is below the threshold voltages of the transistors. A small jump in DC is possible at start up. In this DC jump audio components can be present. 8.3.5 POWER-OFF PLOP SUPPRESSION
All the analog circuitry of the DACs and the operational amplifiers are powered by 2 pins: VDDA2 and VSSA2. VDDA2 must have sufficient decoupling to prevent high THD and to ensure a good Power Supply Rejection Ratio (PSRR). The digital part of the DAC is fully supplied from the DSP core supply. 8.4 Clock circuit and oscillator
To avoid plops in a power amplifier, the supply voltage (3.3 V) for the analog part of the DAC can be supplied from the 5 V supply via a transistor. A capacitor is connected to VDDA2 to maintain power to the analog part if the 5 V supply is switched off fast. In this case the output voltage will decrease gradually allowing the power amplifier some extra time to switch-off without audible plops. 8.3.6 THE INTERNAL PIN VREFDA
The device has an on-chip oscillator. The block diagram of this Pierce oscillator is shown in Fig.6. The active element needed to compensate for the loss resistance of the crystal is the block Gm. This block is placed between the external pins OSCIN and OSCOUT. The gain of the oscillator is internally controlled by the AGC block. A sine wave with a peak-to-peak voltage close to the oscillator power supply voltage is generated. The AGC block prevents clipping of the sine wave and therefore the generation of harmonics as much as possible. At the same time the voltage of the sine wave is as high as possible which reduces the jitter going from the sine wave to the clock signal. 8.4.1 SUPPLY OF THE CRYSTAL OSCILLATOR
The supply of the oscillator is separated from the other supplies. This minimizes the feedback from the ground bounce of the chip to the oscillator circuit. Pin VSS(OSC) is used as ground and pin VDD(OSC) as positive supply. 8.4.2 THE PHASE-LOCKED LOOP CIRCUIT TO GENERATE DSP CLOCK AND OTHER DERIVED CLOCKS
Using two internal resistors, half of the supply voltage VDDA2 is obtained and coupled to an internal buffer. This reference voltage is used as a DC voltage for the output operational amplifiers and as a reference for the DAC. In order to obtain the lowest noise and to have the best ripple rejection, a capacitor has to be connected between this pin and ground. 8.3.7 INTERNAL DAC CURRENT REFERENCE
THE
A PLL circuit is used to generate the DSP clock and other derived clocks. The minimum equalizer clock frequency is 480fs. If fs equals 44.1 kHz, this results in a minimum oscillator frequency of 21.1687 MHz. Crystals for the crystal oscillator in the range of twice the required DSP clock frequency (approximately 40 MHz) are always third-overtone crystals and must be manufactured on customer demand. This makes these crystals expensive. The PLL enables the use of a commonly available crystal operating in fundamental mode. For this circuit a 11.2896 MHz (256 x 44.1 kHz) crystal is chosen. This type of crystal is widely used.
As a reference for the internal DAC current and also for the DAC current source output, a current is drawn from pin VREFDA to VSSA2 (ground) via an internal resistor. The value of this resistor determines also the DAC current (absolute value). Consequently, the absolute value of the current varies from device to device due to the spread of the reference resistor value. This, however, has no influence on the absolute output voltages because these voltages are derived from a conversion of the DAC current to the actual output voltage via internal resistors.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
handbook, full pagewidth
AGC
Gm clock to circuit
on-chip
63 OSCIN
Rbias 64 OSCOUT 65 VDD(OSC) 62 VSS(OSC)
off-chip
Cx1 Cx2
MGM126
Fig.6 Block diagram of the oscillator circuit.
Although multiples of the crystal frequency of 11.2896 MHz fall within the FM reception band, this will not disturb the reception. The relatively low frequency crystal is driven in a controlled way and the resonating crystal produces harmonics of a very low amplitude in the FM reception band. The block diagram of the programmable PLL is shown in Fig.7. The oscillator is used in a fundamental mode. The 11.2896 MHz oscillator frequency is divided by 256 and the resulting signal is fed to the phase detector as a reference signal. The base for the clock signal is a current controlled oscillator (free running frequency 70 to 130 MHz). After having been divided by 4, the required clock frequency for the DSP core is available. To close the loop this signal is further divided by 4 and by the PLL clock division factor N. N can be programmed with the DCSCTR register bits PLL-DIV (see Tables 7 and 15) in the range from 93 to 181. This provides some flexibility in the choice of the crystal frequency. With the recommended crystal, N = 154 and the DSP clock frequency (fDSP) equals 27.1656 MHz. N = 154 is the default position at start-up. By setting the AD register bit DSPTURBO (see Tables 9 and 15), the PLL output frequency, and consequently fDSP, can be doubled. This feature is not used in the proposed application.
The clock frequency of the PLL oscillator divided by two (2fDSP) is also used as the clock for the DCS block. 8.4.3 THE CLOCK BLOCK
For the digital stereo decoder a clock signal is needed which is the 512-multiple of the pilot tone frequency of the FM multiplex signal. This is done by the Digitally Controlled Sampling (DCS) block, which generates this 512 x 19 kHz = 9.728 MHz clock, the DCS clock, by locking to the pilot frequency. This block is also able to generate other frequencies. It is controlled by the DCSCTR and DCSDIV registers (see Tables 7 and 8). Default settings of the DCS and the PLL guarantee correct functioning of the DCS block. 8.4.4 SYNCHRONIZATION WITH THE CORE
In case of I2S-bus input the system can run on audio sample frequencies of fs = 32 kHz, 38 kHz, 44.1 kHz or 48 kHz. After processing of an input sample, the Input flag (I-flag) of the status register (see Section 8.7) of the DSP core is set to logic 1 during 4 clock cycles on the falling edge of the internal or external I2S-bus WS pulses. This flag can be tested with a conditional branch instruction in the DSP. This synchronisation starts in parallel with the input signal due to the short period that the I-flag is set. It is obvious that the higher fs the lower the number of cycles available in the DSP program.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
handbook, full pagewidth
Iref 44.1 kHz
Idelay
OSCIN OSCOUT VDD(OSC) VSS(OSC) 11.2896 MHz OSCILLATOR
/256
x
70 to 130 MHz LOOP FILTER CURRENT CONTROLLED OSCILLATOR
PHASE DETECTOR
/2
PLL-DIV(0)
/2
/2
/2
from DCSCTR register
PLL-DIV(1) PLL-DIV(2) PLL-DIV(3)
/N
N = 154 clock 27.1656 MHz clock 54.3312 MHz
MGM127
Fig.7 Programmable PLL for DSP clock generation.
8.5 8.5.1
Equalizer accelerator circuit INTRODUCTION
8.5.2
EQ CIRCUIT OVERVIEW
This EQ circuit contains the following parts: * A second-order filter data path, with programmable coefficients and with 40 state registers, supporting storage of the two filter states for 20 multiplexed filters; this part is clocked by a gated clock * Signal routing around this filter data path, consisting of: - buses and selectors to configure the 20 filter sections for two or four channels; - input and output registers, with proper interfacing with the DSP core and with conversions between parallel and serial formats. * A coefficient memory, to be loaded via the I2C-bus interface * A controller, started by the write pulse for input and output registers, that controls the signal routing, controls the clock for the filter data path, addresses the coefficient memory and controls its programming.
The Equalizer accelerator (EQ) circuit is an equalizer circuit used as a hardware accelerator to the DSP core. Its inputs and outputs are stored in registers of the DSP core (these registers provide the digital data communication between the equalizer and the DSP core). The flag that starts the DSP program, refreshes the EQ input and output registers and starts the EQ controller. The EQ circuit contains one second-order filter data path that is twenty-fold multiplexed. With this circuit, a two-channel equalizer of 10 second-order sections per channel or a four-channel equalizer of 5 second-order sections per channel can be realized. The centre frequency, gain and Q-factor of all 20 second-order sections can be set independently from each other. Every section is followed by a variable attenuation of 0 or 6 dB. Per section, 4 bytes are needed to store the settings. During an audio sample period, all settings are read as 16-bit words in 80 read accesses to the coefficient memory.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 2 Equalizer port list DESCRIPTION
SAA7705H
NAME Data to/from DSP core IN FL IN FR IN RL IN RR OUT FL OUT FR OUT RL OUT RR
Front Left input bus, 18 bits Front Right input bus, 18 bits Rear Left input bus, 18 bits Rear Right input bus, 18 bits Front Left output bus, 18 bits Front Right output bus, 18 bits Rear Left output bus, 18 bits Rear Right output bus, 18 bits
In Table 2 the port pinning is depicted. This equalizer accelerator circuit (EQ) can make a two-channel equalizer of 10 second-order sections per channel or a four-channel equalizer of 5 second-order sections per channel depending on the value of AD register bit TWO-FOUR (see Table 9). It takes an input sample set of 2 (stereo) samples or 4 (stereo front and rear) samples via 4 input registers. It delivers an output sample set of 2 or 4 samples via 4 output registers. All input and output registers are 18 bits wide. A pulse of three clock cycles long of the signal start based on the word select of the used signal path refreshes the EQ input and output registers and starts up the EQ controller. This sequence is shown in Fig.8. 8.5.3 CONTROLLER AND PROGRAMMING CIRCUIT
From EQ register TWO-FOUR two or four channel configuration switch, I2C-bus controlled; see Table 9
Control from DSP clkCORE start data-valid acknowledge new-address new-coefword DSP core clock, at least 480fs new sample start pulse, input and output registers written new coefficient word available new coefficient word loaded in coefficient memory address for new coefficient word, 6 bits, range is from 0 to 39 new coefficient word, 16 bits
A controller is used to generate the bit control and word control signals for the filter section data path, the addresses for the coefficient memory and the control signals for the input and output selections and conversions. Depending on the AD register bit TWO-FOUR (see Table 9), control signals for a two- or four-channel equalizer are generated. The 40 coefficient words should be addressed via 40 registers (addresses 0F80H to 0FA7H). The new coefficient word rate must be slower than 0.5fs, e.g. 22 kHz. The equalizer is programmed by dedicated software.
handbook, full pagewidth
clkCORE
audio sample period
start
480 clkCORE cycles
gated clock
MGM128
Fig.8 Derivation of the gated clock from clkCORE.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
8.6 The DSP core
SAA7705H
This IC comprises a DSP core (the actual programmable embedded calculating machine) that is adapted to the required calculation power needed and as such is optimized on area. This DSP core is also known under the name EPICS6, of which EPICS is the generic name of this type of DSP and 6 is the version number. This DSP is mainly a calculator designed for real time processing (at fs = 38 or 44.1 kHz) of the digitized audio data stream. A DSP is especially suited to calculate the sum of products of the data words representing the audio data. See Chapter 13 for document references on EPICS6. 8.7 External control pins and status register
* Instructions to control the equalizer and to program the equalizer coefficient RAM to be able to change the centre frequency, gain and Q-factor of the equalizer sections * Instructions controlling the I2S-bus data flow, such as source selection, IAC control and clock speed. The detailed description of the I2C-bus and the description of the different bits in the memory map is given in Chapter 12. 8.9 I2S-bus inputs and outputs
The DSP core contains a 9-bit status register. These 9 flags contain information which is used by the conditional branch logic of the DSP core. For external use, the flags F0, F1, F2 and F3 are available. Pins DSPIN1 and DSPIN2 control the status of the flags F0 and F1. The two status flags F3 and F4 are controlled by the DSP core and can be read via the pins DSPOUT1 and DSPOUT2. The function of each pin depends on the DSP program. Another important flag is the I-flag. This flag is an input flag and is set the moment new I2S-bus data or another type of digital audio data is available to the DSP core. 8.8 I2C-bus interface (pins SCL and SDA)
For communication with external digital sources, the I2S-bus digital interface bus is used. It is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. For external digital sources the SAA7705H acts as a slave, so the external source is master and supplies the clock. The I2S-bus input is capable of handling Philips I2S-bus and LSB-justified formats of 16, 18 and 20-bit word sizes. The selection of the digital audio format is described in Tables 13 and 28. See Fig.9 for the general waveform formats of the four possible formats. The number of bit clock (BCK) pulses may vary in the application. When the applied word length is shorter than 18 bits (internal resolution), the LSBs will get internally a random value. When the applied word length exceeds 18 bits, the LSBs are skipped. The input circuitry is limited in handling the number of BCK pulses per WS period. The maximum allowed number of bit clocks per WS channel (half of the symmetrical WS period) is 128. The DSP program is synchronized with the external source via the word select signal. On every negative edge of the IISWS the I-flag of the status register is set.
The I2C-bus format is described in "The I2C-bus and how to use it", order no. 9398 393 40011. For the external control of the SAA7705H a fast I2C-bus is implemented. This is a 400 kHz bus which is downward compatible with the standard 100 kHz bus. There are three different types of control instructions: * Instructions to control the DSP program, programming the coefficient RAM and reading the values of parameters (level, multipath etc.)
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1999 Aug 16
WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT DATA MSB B2 MSB B2 INPUT FORMAT I2S-BUS WS LEFT 16 BCK 15 DATA MSB B2
Philips Semiconductors
Car radio Digital Signal Processor (DSP)
>=8
MSB
RIGHT 2 1 16 15 2 1
B15 LSB LSB JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
21
WS LEFT 18 BCK 17 16 15 2 1 RIGHT 18 17 16 15 2 1 DATA MSB B2 B3 B4 B17 LSB LSB JUSTIFIED FORMAT 18 BITS MSB B2 B3 B4 B17 LSB WS LEFT 20 BCK 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB
MGL808
Preliminary specification
SAA7705H
Fig.9 Available serial digital audio data in/output formats.
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
8.10 RDS decoder (pins RDSCLK and RDSDAT)
SAA7705H
The RDS decoder recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting. The (buffered) data is provided as output for further processing by a suitable decoder. The operational functions of the decoder are in accordance with the "European Broadcasting Union (EBU) specification EN 50067". The RDS decoder has three different functions: * Clock and data recovery from the FM multiplex signal * Buffering of 16 bits, if selected * Interfacing with the microcontroller. 8.10.1 CLOCK AND DATA RECOVERY
The second filter reduces the RDS bandwidth around 57 kHz. The quadrature mixer converts the RDS band to the frequency spectrum around 0 Hz and contains the appropriate Q/I signal filters. The final decoder with CORDIC recovers the clock and data signals. These signals are output on pins RDSCLK and RDSDAT. 8.10.2 TIMING OF CLOCK AND DATA SIGNALS
The RDS chain has a separate input. This enables RDS updates during tape play and also the use of a second receiver for monitoring the RDS information of signals from another transmitter (double tuner concept). It can as such be done without interruption of the audio program. The MPX signal from the main tuner of the car radio can be connected to this RDS input via the built-in source selector. The input selection is controlled by bit RDS-CLKIN of the RDSCTR register (see Table 14). The RDS chain contains a third-order Sigma-Delta ADC, followed by two decimation filters. The first filter passes the multiplex band including the signals around 57 kHz and reduces the Sigma-Delta noise.
The timing of the clock and data output is derived from the incoming data signal. Under stable conditions the data will remain valid for 400 s after the clock transition. The timing of the data change is 100 s before a positive clock change. This timing is suited for positive as well as negative triggered interrupts on a microcontroller. The RDS timing is shown in Fig.10. During poor reception it is possible that faults in phase occur, then the duty cycle of the clock and data signals will vary from minimum 0.5 times to a maximum of 1.5 times the standard clock periods. Normally, faults in phase do not occur on a cyclic basis. 8.10.3 BUFFERING OF RDS DATA
The repetition of the RDS data is around the 1187 Hz. This results in an interrupt on the microcontroller for every 842 s. In a second mode, the RDS interface has a double 16-bit buffer.
handbook, full pagewidth
RDSDAT
RDSCLK
ts
Tcy
tHC
tLC
td
MBH175
Fig.10 RDS timing (direct output mode).
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
handbook, full pagewidth
RDSDAT
D0
D1
D2
D13
D14
D15
tLC RDSCLK tw block ready tHC Tcy start reading data
MBH176
Fig.11 Interface signals RDS decoder and microcontroller (buffer mode).
8.10.4
BUFFER INTERFACE
The RDS interface buffers 16 data bits. Every time 16 bits are received, the data line is pulled LOW and the buffer is overwritten. The microcontroller has to monitor the data line in at most every 13.5 ms. This mode is selected by setting the RDS-CLKIN bit of the RDSCTR register (see Table 14) to logic 1. In Fig.11 the interface signals from the RDS decoder and the microcontroller in buffer mode are shown. When the buffer is filled with 16 bits the data line is pulled LOW. The data line will remain LOW until reading of the buffer is started by pulling the clock line LOW. The first bit is clocked out. After 16 clock pulses the reading of the buffer is ready and the data line is set HIGH until the buffer is filled again. The microcontroller stops communication by pulling the line HIGH. The data is written out just after the clock HIGH-to-LOW transition. The data is valid when the clock is HIGH. When a new 16 bits buffer is filled before the other buffer is read, that buffer will be overwritten and the old data is lost. 8.11 DSP reset
A more or less fixed relationship between the DSPRESET and the POM time constant is required. The voltage on the pin POM determines the current flowing in the DACs. When pin POM is at 0 V the DAC currents and output voltages are zero; at VDDA2 voltage the DAC currents are at their nominal (maximum) value. Some time before the QDAC outputs get to their nominal output voltages, the DSP must be in working mode to reset the output register. Therefore the DSP time constant must be less than the POM time constant. For recommended capacitors, see Figs 21 and 22. The reset has the following functions: * The bits of the IAC control register are set to logic 0 * The bits of the SEL register are set to their nominal values * The DSP status registers are reset * The program counter is set to address 0000H * The two output flags in the status register are reset to logic 0 (pins DSPOUT1 and DSPOUT2 are LOW). When the level on pin DSPRESET is HIGH, the DSP program starts to run.
Pin DSPRESET is active LOW and has an internal pull-up resistor. Between this pin and pin VSSD3V a capacitor should be connected to allow a proper switch-on of the supply voltage. The capacitor value is such that the chip is in reset state as long as the power supply is not stabilized.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD3V VDDD5V VDDD3Vx VDDD5Vx IIK IOK PARAMETER supply voltage supply voltage voltage difference between any two VDDD3Vx pins voltage difference between any two VDDD5Vx pins DC input clamping diode current DC output clamping diode current VI < -0.5 V or VI > VDD + 0.5 V output type 4 mA (BD4CR, BT4CR and B4CR); VO < -0.5 V or VO > VDD + 0.5 V output type 4 mA (BD4CR, BT4CR and B4CR); -0.5 < VO < VDD + 0.5 V only valid for the voltages in connection with the 5 V I/Os CONDITIONS MIN. -0.5 -0.5 - - - -
SAA7705H
MAX. +5 +6.5 550 550 10 20 V V
UNIT
mV mV mA mA
IO(sink/source) DC output sink or source current
-
20
mA
IDD ISS Tamb Tstg VESD
DC supply current per pin DC ground supply current per pin ambient temperature storage temperature ESD voltage human body model machine model 100 pF; 1500 100 pF; 2.5 H; 0 CIC specification/test method
- - -40 -65 3000 300 100 - -
750 750 +85 +150 - - - 100 1600
mA mA C C V V mA mW mW
Ilu(prot) P/out Ptot
latch-up protection current power dissipation per output total power dissipation
10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITION VALUE 45 UNIT K/W
thermal resistance from junction to ambient mounted on printed-circuit board
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
11 CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7705H
MAX.
UNIT
Supplies; Tamb = -40 to +85 C; VDDD5V = 4.5 to 5.5 V; VDDD3V = 3 to 3.6 V VDDD3V VDDA VDDA1 VDDD5V IDDD3V IDDD5V IDDA1 IDDA2 IDD(OSC) Ptot digital supply voltage 3.3 V for DSP core analog supply voltage 3.3 V supply voltage analog part ADC supply voltage 5 V for periphery supply current of the 3.3 V digital DSP core supply current of the 5 V digital periphery supply current of the ADCs supply current of the DACs supply current crystal oscillator total power dissipation at start-up at oscillation high activity of the DSP at 27 MHz DSP frequency zero input and output signal VDDD5Vx pins with respect to VSS high activity of the DSP at 27 MHz DSP frequency VDDD3Vx pins with respect to VSS VDDAx pins with respect to VSS 3 3 3 4.5 - - - - - - - 3.3 3.3 3.3 5 80 3 35 4 7 0.6 0.352 3.6 3.6 3.6 5.5 110 5 43 5 15 2 0.535 V V V V mA mA mA mA mA mA W
Digital I/O; Tamb = -40 to +85 C; VDDD5V = 4.5 to 5.5 V; VDDD3V = 3 to 3.6 V VIH HIGH-level input voltage all digital inputs and I/Os; pin types: IBUFD, IBUFU, BD4CR, SCHMITCD LOW-level input voltage all digital inputs and I/Os; pin types: IBUFD, IBUFU, BD4CR, SCHMITCD hysteresis voltage; pin type: SCHMITCD HIGH-level output voltage digital outputs; pin types: B4CR, BD4CR LOW-level output voltage digital outputs; pin types: B4CR, BD4CR IO = -4 mA 0.7VDDD5V - - V
VIL
-
-
0.3VDDD5V
V
Vhys VOH
1
1.3
- -
V V
VDDD5V - 0.4 -
VOL
VDDD5V = 4.5 V; IO = 4 mA
-
-
0.4
V
1999 Aug 16
25
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL VOL(SDA)
PARAMETER LOW-level output voltage I2C-bus data output (SDA); pin type: BD8SCI4 output leakage current 3-state outputs; pin types: BD4CR, BD8SCI4 internal pull-up resistor to VDDD5V; pin type: IBUFU internal pull-down resistor to VSSD5V; pin type: IBUFD input rise time input fall time minimum output rise time digital outputs except I2C-bus data output; pin types: B(D)(T)4CR I2C-bus data output; pin type: BD4SCI4
CONDITIONS IO = 8 mA -
MIN. -
TYP.
MAX. 0.4 V
UNIT
ILO
VO = 0 V or VDD5V
-
-
5
A
Rpu(VDDD)(int)
23
50
80
k
Rpd(VSSD)(int)
23
50
80
k
ti(r) ti(f) to(r)(min)
VDDD5V = 5.5 V VDDD5V = 5.5 V VDDD5V = 5.5 V; VDDD3V = 3.6 V; Tj = -40 C CL = 30 pF
- -
6 6
200 200
ns ns
7.6
-
18.4
ns
CL = 200 pF VDDD5V = 4.5 V; VDDD3V = 3 V; Tj = 125 C CL = 30 pF
tbf
tbf
tbf
ns
to(r)(max)
maximum output rise time digital outputs except I2C-bus data output; pin types: B(D)(T)4CR I2C-bus data output; pin type: BD4SCI4
13.7
-
33.4
ns
CL = 200 pF VDDD5V = 5.5 V; VDDD3V = 3.6 V; Tj = -40 C CL = 30 pF
tbf
tbf
tbf
tbf
to(f)(min)
minimum output fall time digital outputs except I2C-bus data output; pin types: B(D)(T)4CR I2C-bus data output; pin type: BD4SCI4
7
-
17
ns
CL = 200 pF
tbf
tbf
tbf
ns
1999 Aug 16
26
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL to(f)(max)
PARAMETER maximum output fall time digital outputs except I2C-bus data output; pin types: B(D)(T)4CR I2C-bus data output; pin type: BD4SCI4
CONDITIONS VDDD5V = 4.5 V; VDDD3V = 3 V; Tj = 125 C CL = 30 pF
MIN.
TYP.
MAX.
UNIT
12.7
-
30.9
ns
CL = 200 pF
tbf
tbf
tbf
ns
DC characteristics analog inputs; Tamb = 25 C; VDDA1 = 3.3 V VREFAD common-mode reference voltage for SCAD1, 2, 3 and level-ADC output impedance at pin VREFAD positive reference voltage SCAD1, 2, 3 and level-ADC positive reference current SCAD1, 2, 3 and level-ADC negative reference voltage SCAD1, 2, 3 and level-ADC negative reference current SCAD1, 2 3 and level-ADC input offset voltage SCAD1, 2 and 3 with reference to VSSA1 0.47VDDA1 0.5VDDA1 0.53VDDA1 V
Zo(VREFAD) VVDACP
- 3
600 3.3
- 3.6
V
IVDACP
-
-20
-
A
VVDACN1, VVDACN2 IVDACN1, IVDACN2 VIO(SCAD)
-0.3
0
+0.3
V
-
20
-
A
-
140
-
mV
AC characteristics analog inputs; Tamb = 25 C; VDDA1 = 3.3 V Vi(con)(max)(rms) maximum conversion input level at analog input (RMS value) Ri Ri(FMMPX) THDFMMPX input resistance (AM, CD and TAPE inputs) input resistance at pin FMMPX total harmonic distortion FMMPX input signal-to-noise ratio FMMPX input mono THD < 1% 0.6 0.66 - V
1 44 input signal 0.35 V (RMS) - at 1 kHz; - bandwidth = 19 kHz; note 1 input signal at 1 kHz; 80 0 dB reference = 0.35 V (RMS); bandwidth = 19 kHz; note 1
- - -70 0.03 83
- 164 -65 0.056 -
M k dB % dB
S/NFMMPX(m)
1999 Aug 16
27
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL S/NFMMPX(s)
PARAMETER signal-to-noise ratio FMMPX input stereo
CONDITIONS input signal at 1 kHz; 74 0 dB reference = 0.35 V (RMS); bandwidth = 40 kHz; note 1 input signal 0.55 V (RMS) at 1 kHz; input gain = 1 (see Fig.4); bandwidth = 20 kHz input signal at 1 kHz; 0 dB reference = 0.55 V (RMS); bandwidth = 20 kHz input signal 0.55 V (RMS) at 1 kHz; bandwidth = 5 kHz input signal at 1 kHz; 0 dB reference = 0.55 V (RMS); bandwidth = 5 kHz input signal 0.55 V (RMS) at 1 kHz; bandwidth = 20 kHz; input signal at 1 kHz; 0 dB reference = 0.55 V (RMS); bandwidth = 20 kHz pilot signal frequency = 19 kHz unmodulated subcarrier frequency = 38 kHz unmodulated - -
MIN.
TYP. 77 -
MAX.
UNIT dB
THDCD
total harmonic distortion CD inputs
-83 0.007
-78 0.013
dB %
S/NCD
signal-to-noise ratio CD inputs
81
84
-
dB
THDAM
total harmonic distortion AM inputs signal-to-noise ratio AM inputs total harmonic distortion TAPE inputs signal-to-noise ratio TAPE inputs
- - 83
-80 0.01 88
-76 0.016 -
dB % dB
S/NAM
THDTAPE
- - 81
-80 0.01 83
-76 0.016 -
dB % dB
S/NTAPE
19
carrier and harmonic suppression at the output carrier and harmonic suppression at the output
- - - - - - - -
81 98 83 91 83 96 84 94 - - 110 110
- - - - - - - - - - - -
dB dB dB dB dB dB dB dB dB dB dB dB
38
57
carrier and harmonic subcarrier suppression for frequency = 57 kHz 19 kHz, including notch unmodulated carrier and harmonic subcarrier suppression for frequency = 76 kHz 19 kHz, including notch unmodulated intermodulation intermodulation
76
IM10 IM13 57(VF) 67(SCA)
fmod = 10 kHz; fspur = 1 kHz 77 fmod = 13 kHz; fspur = 1 kHz 76 - -
traffic radio (Verkehrs f = 57 kHz Warnfunk) suppression Subsidiary Communication Authority (SCA) suppression f = 67 kHz
1999 Aug 16
28
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL 114 190 Vth(pilot)(rms)
PARAMETER adjacent channel suppression adjacent channel suppression pilot threshold voltage (RMS value) at pin DSPOUT1
CONDITIONS f = 114 kHz f = 190 kHz stereo `on', AD input selection switch position `110' stereo `off', AD input selection switch position `110' - - -
MIN.
TYP. 110 110 35.5 - - -
MAX.
UNIT dB dB mV
-
35.4
-
mV
hys fi(FMMPX) cs fres(FM) GL-R
hysteresis of Vth(pilot)(rms) input frequency of the FMMPX input FM-stereo channel separation audio frequency response FM overall left/right gain unbalance (TAPE, CD, FM and AM inputs) channel separation (TAPE and CD inputs) response frequency (TAPE and CD inputs) crosstalk between inputs fi = 1 kHz fi = 10 kHz fs = 38 kHz; at -3 dB fi = 1 kHz fi = 15 kHz output via ADC input short-circuited; fripple = 1 kHz; Vripple = 100 mV (peak); CVREFAD = 22 F; CVDACP = 10 F output via DAC; ADC input short-circuited; fripple = 1 kHz; Vripple = 100 mV (peak); CVREFAD = 22 F RCDGND = 1 M; resistance of CD player ground cable < 1 k; fi = 1 kHz I2S-bus; -3 dB; AD via bitstream test output fi = 1 kHz fi = 10 kHz at -3 dB via DSP at DAC output
- 0 40 25 17 -
0 - 45 30 - -
- 55 - - - 0.5
dB kHz dB dB kHz dB
cs(TAPE,CD) fres(TAPE,CD) ct
70 65 18 65 50 35
75 70 - - - 45
- - - - - -
dB dB kHz dB dB dB
PSRRMPX/RDS power supply ripple rejection MPX and RDS ADCs
PSRRLAD
power supply ripple rejection level-ADC
29
39
-
dB
CMRRCD
common-mode rejection ratio for CD input mode
60
-
-
dB
AC characteristics RDS input; Tamb = 25 C Vi(con)(max)(rms) maximum conversion THD < 1% input level (RMS value) 0.6 0.66 - V
1999 Aug 16
29
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL Ri(FMRDS) THDFMRDS S/NFMRDS
PARAMETER input resistance FMRDS input total harmonic distortion RDS ADC signal-to-noise ratio RDS ADC
CONDITIONS 44 fc = 57 kHz 6 kHz bandwidth; fc = 57 kHz; 0 dB reference = 0.55 V (RMS); note 1 neighbouring channel at 200 kHz distance -60 54
MIN. -
TYP.
MAX. 164 - -
UNIT k dB dB
-67 -
pilot n(ADC) Vripple(RDS) mux(RDS) fosc
pilot attenuation RDS nearby selectivity RDS RDS ADC noise attenuation ripple voltage RDS pass band multiplex attenuation RDS allowable frequency deviation of the 57 kHz RDS 2.4 kHz bandwidth mono stereo maximum crystal resonance frequency deviation of 100 ppm
50 61 70 - 70 40 -
- - - - - - -
- - - 0.5 - - 6
dB dB dB dB dB dB Hz
Analog level inputs (AML and FML); Tamb = 25 C; VDDA1 = 3.3 V S/NLAD signal-to-noise ratio of level-ADC input resistance full-scale level-ADC input voltage DC offset voltage decimation filter attenuation pass band cut-off frequency sample rate frequency after decimation at -3 dB and DCS clock = 9.728 MHz DCS clock = 9.728 MHz 0 to 29 kHz bandwidth; maximum input level; unweighted 48 54 - dB
Ri Vi(fs)(LAD) VIO fco(PB) fsr
1.5 0 - 20 - -
- - - - 29 38
2.2 VDDA1 60 - - -
M V mV dB -----------------decade kHz kHz
Analog outputs; Tamb = 25 C; VDDA2 = 3.3 V VVREFDA ZVREFDA Vo VO(av) voltage at pin VREFDA impedance at pin VREFDA output voltage of operational amplifiers average DC output voltage with respect to pin VDDA2 with respect to pin VSSA2 maximum I2S-bus signal (RMS); RL > 5 k (AC) RL > 5 k (AC) 0.47VDDA2 - - 0.65 1.5 0.5VDDA2 0.53VDDA2 40 40 0.75 1.65 - - 0.85 1.8 V k k V V
1999 Aug 16
30
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL Ipu(POM) PSRRQDAC
PARAMETER
CONDITIONS 3.3 50 45
MIN. - -
TYP. 5 90 -
MAX.
UNIT A A dB
pull-up current to VDDA2 voltage at pin POM <0.6 V from pin POM voltage at pin POM >0.8 V power supply ripple rejection of QDAC input via I2S-bus; fripple = 1 kHz; Vripple = 100 mV (p-p); CVREFDA = 22 F full-scale output; with respect to the average of the 4 current outputs one output digital silence, three maximum volume output short-circuited to ground f = 1 kHz; Vo = 0.72 V (RMS); RL > 5 k (AC); A-weighted output signal -60 dB at 1 kHz; 0 dB reference = 0.77 V (RMS); A-weighted f = 20 Hz to 17 kHz; reference Vo = 0.77 V (RMS); A-weighted
60
Io(QDAC)(max)
maximum deviation in output level of the QDAC current outputs crosstalk between all outputs in the audio band output short-circuit current DAC resolution total harmonic distortion-plus-noise to signal ratio dynamic range
- - -
- - -
4.47 0.38 -69
% dB dB
ct
Io(sc) RESDAC (THD + N)/S
- - -
- 18 -75
20 - -65
mA bits dBA
DR
92
102
-
dBA
DS
digital silence
-
102
108
dBA
Vno(DS)(rms)
digital silence noise output voltage (RMS value) intermodulation distortion/comparator maximum sample frequency bandwidth DAC load capacitance on DAC voltage outputs load resistance on DAC voltage outputs at -3 dB
-
3
8
V
IM fs(max) B CL RL
f = 60 Hz and 7 kHz; ratio 4 - 48 - - 2
-70 - 0.5fs - -
-55 - - 2.5 -
dB kHz Hz nF k
I2S-bus inputs and outputs; see Fig.12 Tcy tr tf tBCK(H) tBCK(L) bit clock cycle time rise time fall time bit clock HIGH time bit clock LOW time 50 - - 0.35Tcy 0.35Tcy - - - - - - 0.15Tcy 0.15Tcy - - ns ns ns ns ns
1999 Aug 16
31
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
SYMBOL tsu(D) th(D) td(D) tsu(WS) th(WS) fRDSCLK tsu Tcy tHC tLC th tw fi(clk)(ext) Oscillator fxtal fclk(DSP) f Vxtal gm CL Ncy(su) Pxtal Vi(clk)(ext) Note
PARAMETER data set-up time data hold time data delay time word select set-up time word select hold time
CONDITIONS
MIN. 0.2Tcy 0.2Tcy - 0.2Tcy 0.2Tcy - - - - - -
TYP. - -
MAX.
UNIT ns ns ns ns ns
0.15Tcy - - - - - - 640 - 640 - - - 22
RDS interface timing; see Figs 10 and 11 nominal RDS clock frequency clock set-up time cycle time clock HIGH time clock LOW time data output hold time wait time input frequency external RDS clock direct output mode direct output mode buffer mode direct output mode buffer mode direct output mode buffer mode direct output mode buffer mode buffer mode 1187.5 - 842 - - - - - - - - Hz s s s s s s s s s MHz
100 - 2 220 1 220 1 100 1 -
crystal frequency clock frequency DSP core spurious frequency attenuation voltage across the crystal transconductance load capacitance number of cycles in start-up time crystal drive power level external clock input voltage depends on quality of the external crystal at oscillation in slave mode at start-up in operating range
- 27.1656 20 - 10.5 3.6 - - - 3
11.2896 - - 3 19 - 15 1000 0.4 3.3
- - - - 32 38 - - 0.5 5
MHz MHz dB V mS mS pF cycles mW V
1. FMRDS and FMMPX input sensitivity setting `000' (see Table 17).
1999 Aug 16
32
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
handbook, full pagewidth
LEFT
WS RIGHT tBCK(H) tr tf th(WS) td(D) tsu(WS)
BCK tBCK(L) Tcy LSB MSB tsu(D) th(D)
DATA IN
DATA OUT
LSB
MSB
MGM129
Fig.12 Timing of the digital audio data in- and outputs.
1999 Aug 16
33
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
12 I2C-BUS INTERFACE AND PROGRAMMING 12.1 12.1.1 I2C-bus interface CHARACTERISTICS OF THE I2C-BUS 12.1.2 BIT TRANSFER
SAA7705H
The I2C-bus is used for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz clock frequency the recommendations of Philips Semiconductors for this type of bus must be followed e.g. up to loads of 200 pF at the bus a pull-up resistor can be used; loads between 200 to 400 pF need a current source or switched resistor. Data transfer can only be initiated when the bus is not busy.
One data bit is transferred during each clock pulse; see Fig.13. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run on this high frequency all the I/Os connected to this bus must be designed for this high speed according to the Philips specification. 12.1.3 START AND STOP CONDITIONS
Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as a START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a STOP condition (P); see Fig.14.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.13 Bit transfer on the I2C-bus.
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.14 START and STOP condition.
1999 Aug 16
34
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
12.1.4 DATA TRANSFER
SAA7705H
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'; see Fig.15. 12.1.5 ACKNOWLEDGE
The number of data bits transferred between the START and STOP conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. A slave receiver, which
is addressed, must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an `end of data' to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition; see Fig.16.
handbook, full pagewidth
SDA MSB acknowledgement signal from receiver byte complete; interrupt within receiver clock line held low while interrupts are serviced SCL S START CONDITION acknowledgement signal from receiver
1
2
7
8
9 ACK
1
2
3-8
9 ACK
MBH177
P STOP CONDITION
Fig.15 Data transfer on the I2C-bus.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION
MBH178
1
2
8
9
clock pulse for acknowledgement
Fig.16 Acknowledge on the I2C-bus.
1999 Aug 16
35
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
12.2 12.2.1 I2C-bus protocol ADDRESSING 12.2.4 READ CYCLES
SAA7705H
Before any data is transmitted on the I2C-bus, the device that should respond is addressed first. The addressing is always done with the first byte transmitted after the START procedure. 12.2.2 SLAVE ADDRESS
The SAA7705H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The slave address is shown in Table 3. Table 3 MSB 0 0 1 1 1 0 A0 Slave address LSB R/W
The configuration for a read cycle is shown in Fig.18. The read cycle is used to read the data values from XRAM or YRAM. The master starts with a START condition (S), the DSP address `0011100' and a logic 0 (write) for the read/write bit. This is followed by an acknowledge of the SAA7705H. Then the master writes the high memory address (ADDR H) and low memory address (ADDR L) where the reading of the memory content of the SAA7705H must start. The SAA7705H acknowledges these addresses both. The master generates a repeated START and again the SAA7705H address `0011100' but this time followed by a logic 1 (read) of the read/write bit. From this moment on the SAA7705H will send the memory content in groups of 2 (Y-memory) or 3 (X-memory) bytes to the I2C-bus, each time acknowledged by the master. The master stops this cycle by generating a negative acknowledge, then the SAA7705H frees the I2C-bus and the master can generate a STOP condition. The data is transferred from the DSP register to the I2C-bus register at execution of the MPI instruction in the DSP program. Therefore at least once every DSP cycle an MPI instruction should be added.
I2C-bus
The sub-address bit A0 corresponds to the hardware address pin A0 which allows the device to have 2 different addresses. The A0 input is also used in the test mode as a serial input of the test control block. 12.2.3 WRITE CYCLES
The configuration for a write cycle is shown in Fig.17. The write cycle is used to write the bytes to control the DCS block, the PLL for the DSP clock generation, the IAC settings, the AD volume control settings, the analog input selection, the format of the I2S-bus and some other settings. More details can be found in the I2C-bus memory map (see Table 5). The data length is 2 or 3 bytes depending on the accessed memory. If the Y-memory is addressed the data length is 2 bytes, in case of the X-memory the length is 3 bytes. The slave receiver detects the address and adjusts the number of bytes accordingly.
I2C-bus
1999 Aug 16
36
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A
Philips Semiconductors
Car radio Digital Signal Processor (DSP)
S00111000C
K
ADDR H
A C K
ADDR L
A C K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W
MGD568
S = START condition. ACK = acknowledge from DSP (SDA LOW). ADDR H and ADDR L = address DSP register. DATA H, DATA M and DATA L = data of XRAM or registers. DATA H and DATA M = data of YRAM. P = STOP condition.
Fig.17 Master transmitter writes to the DSP registers. 37
A
S00111000C
K
ADDR H
A C K
ADDR L
A A CS00111001C K K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W R/W
MGA808 - 1
Preliminary specification
S = START condition. ACK = acknowledge from DSP (SDA LOW). ADDR H and ADDR L = address DSP register. DATA H, DATA M and DATA L = data of XRAM or registers. DATA H and DATA M = data of YRAM. P = STOP condition.
SAA7705H
Fig.18 Master transmitter reads from the DSP registers.
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Car radio Digital Signal Processor (DSP)
SDA
t BUF
t LOW
tr
tf
t HD;STA
t SP
SCL
t HD;STA P S
t HD;DAT
t HIGH
t SU;DAT
t SU;STA
t SU;STO Sr
MBC611
P
Fig.19 Definition of timing on the I2C-bus.
Table 4
Timing fast I2C-bus (see Fig.19) STANDARD I2C-BUS FAST MODE I2C-BUS UNIT MIN. SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition; after this period, the first clock pulse is generated SCL LOW period SCL HIGH period set-up time for a repeated START condition DATA hold time DATA set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals set-up time for STOP condition capacitive load for each bus line pulse width of spikes to be suppressed by input filter Cb in pF Cb in pF 0 4.7 4.0 4.7 4.0 4.7 0 250 - - 4.0 - - - - - - - - 1000 300 - 400 MAX. 100 0 1.3 0.6 1.3 0.6 0.6 0 100 MIN. - - - - - 0.9 - MAX. 400 kHz s s s s s s s s s s pF ns PARAMETER CONDITIONS
SYMBOL
Preliminary specification
SAA7705H
20 + 0.1Cb 300 20 + 0.1Cb 300 0.6 - 0 - 400 50
not applicable
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
12.3 Memory map specification and register overview
SAA7705H
The SAA7705H memory map contains all defined bits. The map is split up in two different sections: the hardware memory registers and the RAM definitions. In Table 5 the memory map is depicted. Table 6 shows the detailed memory map locations. Table 5 Memory map ADDRESS 9C00H to 9FFFH 9000H to 9BFFH 8000H to 8FFFH 1000H to 7FFFH 0FF9H to 0FFFH 0FF4H to 0FF8H 0FF3H 0FEEH to 0FF2H 0FA8H to 0FEDH 0F80H to 0FA7H 0B30H to 0F7FH 0AFFH to 0B2FH 0AC0H to 0AFEH 0A80H to 0ABFH 0A40H to 0A7FH 0A00H to 0A3FH 0980H to 09FFH 0800H to 097FH 0200H to 07FFH 0180H to 01FFH 0000H to 017FH Table 6 Register overview ADDRESS EPICS6 0FFFH 0FFEH 0FFDH 0FFCH 0FFBH 0FFAH 0FF9H RDS 0FF3H RDSCTR RDS control register (see Table 14) DCSCTR DCSDIV AD LEVELIAC IAC SEL HOST DCS control register (see Table 7) DCS divide register (see Table 8) AD register (see Table 9) IAC level register (see Table 10) IAC register (see Table 11) Input selection register (see Table 12) Host register (see Table 13) NAME DESCRIPTION reserved not used reserved not used DSP core reserved RDS reserved not used equalizer not used reserved not used reserved not used reserved reserved YRAM space YRAM not used reserved XRAM space XRAM 384 x 18 bits 384 x 12 bits 65 x 16 bits 65 x 16 bits 49 x 16 bits 40 x 16 bits 7 x 16 bits 5 x 16 bits 1 x 16 bits 5 x 16 bits 4096 x 28 bits FUNCTION 1024 x 32 bits SIZE
1999 Aug 16
39
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
12.4 Register description DCSCTR register (address 0FFFH) NAME CLK-ISN-ONOFF SIZE (BITS) 1 ISN clock 1: off 0: on PLL-DIV LOOPO-ONOFF 4 1 PLL clock division factor (see Table 15) Loopo 1: on 0: off GAIN-HL 1 variable loop-gain stereo decoder 1: high 0: low LOCKED-PRESET 1 DCS clock 1: locked 0: preset F1-COEF F0-COEF 4 4 coarse division factor F1 (see Table 16) coarse division factor F0 (see Table 16) 0010 (F1 = 11) 0011 (F0 = 11.5) 1 (locked) 1 (high) 1010 (154) 0 (off) DESCRIPTION DEFAULT 1 (off)
SAA7705H
Table 7
BIT POSITION 15
14 to 11 10
9
8
7 to 4 3 to 0
Table 8
DCSDIV register (address 0FFEH) NAME SIZE (BITS) 16 DESCRIPTION Sigma-Delta modulator V (note 1) DEFAULT 28EDH BIT POSITION 15 to 0
DCS-COEF Note
1. DCS-COEF can be calculated by the multiplication V x 215 and then convert this decimal value to hexadecimal.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 9 AD register (address 0FFDH) NAME LDEF TWO-FOUR SIZE (BITS) 3 1 DESCRIPTION always in position 000 equalizer configuration 1: two channels 0: four channels DSPTURBO 1 PLL output frequency 1: double 0: no doubling - VOLFM VOLRDS SELTWOTUN 4 3 3 1 reserved - 0 (no doubling) DEFAULT 000 0 (four channels)
SAA7705H
BIT POSITION 15 to 13 12
11
10 to 7 6, 5 and 4 3, 2 and 1 0
input sensitivity FMMPX input (see Table 17) 110 (200 mV) input sensitivity FMRDS input (see Table 17) 110 (200 mV) select one- or two-tuner operation 1: two tuners 0: one tuner 0 (one tuner)
Table 10 LEVELIAC register (address 0FFCH) NAME LEV-EN-DYN-IAC SIZE (BITS) 1 1: enable 0: disable LEV-DYN-IAC-DEV - LEV-IAC-STRETCH LEV-IAC-FEEDFORWARD LEV-IAC-THRESHOLD 2 5 2 2 4 deviation threshold frequency setting of the dynamic IAC (see Table 18) not used level-IAC stretch time (see Table 19) level-IAC deviation feed-forward factor (see Table 20) level-IAC threshold settings (see Table 21) 00 (50 kHz) - 10 (13 periods) 00 (-2 periods) 0000 (off) 14 and 13 12 to 8 7 and 6 5 and 4 3 to 0 DESCRIPTION FM frequency sweep dependent IAC DEFAULT 0 (disable) BIT POSITION 15
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 11 IAC register (address 0FFBH) NAME IACTRIGGER SIZE (BITS) 1 1: IAC output 0: DSPOUT2 output - AGC 3 1 not used AGC set point 1 1: --------256 1 0: --------128 MPXDELAY SUPPRESSION FEEDFORWARD THRESHOLD 2 3 3 3 IAC delay settings MPX (see Table 22) IAC stretch time suppression (see Table 23) IAC deviation feed-forward factor (see Table 24) IAC threshold sensitivity (see Table 25) 01 (5 periods) 101 (0.00781) 101 (0.031) 1 1 --------- 256 DESCRIPTION input selection for IAC triggering DEFAULT 0 (DSPOUT2)
SAA7705H
BIT POSITION 15
14 to 12 11
10 and 9 5, 4 and 3 2, 1 and 0
011 (2 samples) 8, 7 and 6
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 12 SEL register (address 0FFAH) NAME ADC-BWSWITCH SIZE (BITS) 1 1: 44.1 kHz 0: 38 kHz - INVHOSTWS 1 1 not used word select 1: inverting 0: non-inverting NSDEC 1 select noise detector 1: ratio 1 : 8 0: ratio 1 : 4 ADCSRC - DCOFFSET 1 1 1 compensation switch for Audio-AD reserved DC offset filter 1: off 0: on BYPASSPLL 1 clock oscillator signal handling by PLL 1: PLL by-passed 0: PLL active DEF 1 selection 1: 19 kHz (microphone input and compensation filter) 0: 29 kHz (level filter position) WIDE-NARROW 1 selection 1: audio data 0: audio + RDS info LEVAM-FM 1 select input for level detector 1: AM level (pin AML) 0: FM level (pin FML) - CD-TAPE 1 1 reserved select audio input 1: CD 0: TAPE AM-TAPE 1 select audio input 1: AM 0: TAPE AUX-FM 1 select audio input 1: CD left 0: FM - 1999 Aug 16 1 reserved - 43 0 (FM) 0 (TAPE) - 1 (CD) 0 (FM level) 0 (29 kHz) 0 (PLL active) 0 (Audio-AD, required) - 0 (on) 1 (1 : 8) 0 (non-inverting) DESCRIPTION processing base SCAD1, SCAD2 and LAD DEFAULT 0 (38 kHz)
SAA7705H
BIT POSITION 15
14 13
12
11 10 9
8
7
1 (audio data, required) 6
5
4 3
2
1
0
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 13 HOST register (address 0FF9H) NAME CLOOP-MODE ENHOSTIO SIZE (BITS) 3 1 DESCRIPTION cloop mode (see Table 27) external I2S-bus 1: enable 0: disable HOST-IO-FORMAT AUDIO-FORMAT AUDIO-SOURCE - 2 3 2 5 host input/output data format (see Table 28) 00 (standard I2S-bus, required) audio register data format (see Table 29) audio selection register (see Table 30) reserved 000 (ISN) 01 (ISN) - DEFAULT 110 (WS 50% duty cycle + BCLK/4) 0 (disable)
SAA7705H
BIT POSITION 15 to 13 12
11 and 10 9, 8 and 7 6 and 5 4 to 0
Table 14 RDSCTR register (address 0FF3H) NAME - RDS-CLKIN SIZE (BITS) 7 1 reserved select output for RDS 1: buffered RDS with RDS clock input 0: RDS output - 8 reserved - 7 to 0 DESCRIPTION - 0 (RDS output) DEFAULT BIT POSITION 15 to 9 8
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
12.5 Detailed register description
SAA7705H
Table 15 PLL clock division factor (PLL-DIV bits) PLL-DIV BIT 14 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT 13 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT 12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PLL CLOCK DIVISION FACTOR dsp-turbo = 0 93 99 106 113 121 126 132 137 143 148 154 (default) 159 165 170 176 181 dsp-turbo = 1 (not used) 186 198 106 212 242 252 264 274 286 296 308 318 330 340 352 362
Table 16 Representation of division factors F0 and F1 F0-COEF/F1-COEF BIT 3/7 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BIT 2/6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT 1/5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT 0/4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX-VALUE 8H 9H AH BH CH DH EH FH 0H 1H 2H 3H 4H 5H 6H 7H DIVISION FACTOR F0/F1 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 (default F1) 11.5 (default F0) 12 12.5 13 13.5
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 17 Volume control of the FMMPX and FMRDS input by the AD register. FMMPX/FMRDS INPUTS VOLFM/VOLRDS INPUT VOLTAGE BIT 3/6 0 0 0 0 1 1 1 1 BIT 2/5 0 0 1 1 0 0 1 1 BIT 1/4 0 1 0 1 0 1 0 1 AT 22.5 kHz SWEEP (mV) 65 78 93 111 132 158 188 (default) 225 FOR 0 dB AT DSP (mV) 410 493 587 700 833 1000 1188 (default) 1387
SAA7705H
INPUT IMPEDANCE (k) 137 103 84.8 74 67 62 58.4 (default) 56
Table 18 Dynamic IAC deviation threshold LEV-DYN-IAC-DEV BIT 14 0 0 1 1 BIT 13 0 1 0 1 DEVIATION (kHz) 43 (default) 48.5 58 65
Table 19 IAC-level stretch time LEV-IAC-STRETCH PULSE LENGTH ON SINGLE TRIGGER IN PERIODS OF 304 kHz BIT 7 0 0 1 1 BIT 6 0 1 0 1 9 11 (default) 13 15
Table 20 IAC-level deviation feed-forward factor LEV-IAC-FEEDFORWARD DELAY (DECIMAL VALUE) IN PERIODS OF 304 kHz BIT 5 0 0 1 1 BIT 4 0 1 0 1 -2 (default) -1 0 1
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 21 Level IAC threshold settings LEVEL-IAC-THRESHOLD BIT 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.02 0.025 0.0316 0.04 0.05 0.063 0.08 0.1 0.126 0.16 0.2 0.25 0.316 0.4 0.5 DECIMAL VALUE THRESHOLD
SAA7705H
BINARY VALUE 0.0000010 0.0000011 0.0000100 0.0000101 0.0000110 0.0001000 0.0001010 0.0001101 0.0010000 0.0010100 0.0011010 0.0100000 0.0101000 0.0110100 0.1000000
level-IAC off (default)
Table 22 IAC delay settings MPX MPX-DELAY DELAY (DECIMAL VALUE) IN PERIODS OF 304 kHz BIT 10 1 1 0 0 BIT 9 0 1 0 1 2 3 4 5 (default)
Table 23 IAC stretch time suppression SUPPRESSION BIT 8 1 1 1 1 0 0 0 0 BIT 7 0 0 1 1 0 0 1 1 BIT 6 1 0 1 0 1 0 1 0 STRETCH TIME SUPPRESSION PULSE LENGTH ON SINGLE TRIGGER 0 1 2 3 4 5 6 7 STRETCH (NUMBER OF SAMPLES) not applicable 0 1 2 3 4 5 (default) 6
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 24 IAC deviation feed-forward factor FEEDFORWARD BIT 5 0 0 0 0 1 1 1 1 BIT 4 1 1 0 0 1 1 0 0 BIT 3 1 0 1 0 1 0 1 0 DECIMAL VALUE 0.00146 0.00195 0.00293 0.00391 0.00586 0.00781 0.01172 (default) 0.00000 FACTOR
SAA7705H
BINARY VALUE 0.000000000110 0.000000001000 0.000000001100 0.000000010000 0.000000011000 0.000000100000 0.000000110000 0.000000000000
Table 25 IAC threshold sensitivity DYN-IAC-DEV BIT 2 1 1 1 1 0 0 0 0 BIT 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 1 0 1 0 1 DECIMAL VALUE 0.027 0.031 (default) 0.038 0.047 0.055 0.063 0.074 0.085 THRESHOLD BINARY VALUE 0.000001110000 0.000010000000 0.000010011100 0.000011000000 0.000011100000 0.000100000000 0.000100110000 0.000101100000
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 26 Analog input selection; notes 1 and 2 MODE FMMPX one tuner mode FMMPX two tuner mode AM CD-ANALOG MICROPHONE(4) TAPE Notes AM-TAPE X(3) X(3) 1 X(3) X(3) 0 AUX-FM 0 0 X(3) 1 X(3) X(3) CD-TAPE 1 1 0 1 X(3) 0 SELTWOTUN 0 1 X(3) X(3) X(3) X(3)
SAA7705H
LEVAM-FM 0 0 1 X(3) 1 X(3)
1. It is assumed that the AM level input is used for AM reception and the FM level input for FM reception. It is, however, also possible to have a combined AM and FM level output from the tuner. In that case the FM level input should be used and the LEVAM-FM should remain logic 0. 2. In all the positions it is assumed that pin SELFR is LOW. 3. X = don't care. 4. In the MICROPHONE position it is assumed that the microphone is connected to the AML input. When using a microphone the bandwidth of the level decimation path is limited to 19 kHz. In all other cases the bandwidth is 29 kHz. At the same time the I2C-bus bit DEF of the SEL register must be put in the `voice' = logic 1 position. Table 27 Cloop mode settings CLOOP-MODE OUTPUT BIT 15 Word select (WS) 0 1 Bit clock (BCLK) - - - - 0 0 1 1 0 1 0 1 bypass BCLK divide BCLK by 2 divide BCLK by 4 (default) divide BCLK by 8 - - - - bypass WS WS 50% duty-cycle (default) BIT 14 BIT 13
Table 28 Host input/output data format HOST-IO-FORMAT OUTPUT BIT 11 0 0 1 1 BIT 10 0 1 0 1 standard I2S-bus (default) LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
Table 29 Audio register data format AUDIO-FORMAT
SAA7705H
OUTPUT BIT 9 0 - - - 1 Table 30 Audio selection register AUDIO-SOURCE OUTPUT BIT 6 0 0 1 1 BIT 5 0 1 0 1 Audio-AD ISN L + R and R - L (default) external CD1 external CD2 BIT 8 0 0 1 1 0 BIT 7 0 1 0 1 0 ISN, LSB first (default) LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits standard I2S-bus
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
13 APPLICATION INFORMATION The application diagram shown in Figs 21 and 22 must be considered as one of the examples of a (limited) application of the chip e.g. in this case the I2S-bus inputs of the CD1 and CD2 are not used. For the real application set-up the information of the application report and application support by Philips is necessary on issues such as EMC, kappa reduction of the package, DSP program, etc. 13.1 Software description
SAA7705H
The availability of a programmer's guide does not mean that the normal procedure enables the customer to develop their own DSP software. 13.2 Power supply connection and EMC
The use and description of the software features of the SAA7705H is described in the separate manual: "USER MANUAL SAA7705H, report no. NBA/AN9704, Version 2.1, Author G. Willighagen" Further information about the programming of the EPICS6 DSP core is available in "EPICS6 Programmer's Guide, version 1.3, July 3 1997, Author Ron Schiffelers, CIC development Nijmegen"
The digital part of the chip has in total 7 positive supply line connections and 7 ground connections. To minimise radiation the chip should be put on a double layer Printed-Circuit Board (PCB) with on one side a large ground plane. The ground supply lines should have a short connection to this ground plane. A coil and capacitor network in the positive supply line can be used as high frequency filter.
handbook, full pagewidth
CD (analog) TAPE
CD2 (digital)
AM/FM
CD1 (digital)
SAA7740H
(optional)
AM AM/FM-RF AM/FM-IF FM RDS level DSP
LR RR LF RF POWER AMPLIFIER
TEA6811
TEA6824
SAA7705H
I2C-bus
RDS
MICROCONTROLLER
DISPLAY
MGM120
Fig.20 Application block diagram.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
handbook, full pagewidth
VDDA3V
VDDD5V
R22 R17 100 C47 100 nF VDDD5V1 100 nF
100
C48
VDDD5V2
VDDD5V3
VSSD3V1
VSSD3V2
VSSD3V3
VSSD3V4
VSSD5V1
VSSD5V2 37
74 VDACP C17 R1 FM-LEVEL 27 k C2 CD-L 220 nF 15 k C3 CD-R 220 nF C4 CD-GND 1 F 15 k R7 1 M 47 nF 22 F R5 R6 8.2 k R3 C1 330 pF R2 27 k 10 F AML FML R4 8.2 k CDLB CDLI CDRB CDRI CDGND VREFAD 4 3 73 72 71 70 77 78 INPUT STAGE 1
76
75
2
21
22
36
46
49
50
53
54
23
47
LEVEL-ADC
SIGNAL LEVEL
VSSD5V3 A B C D E 64 OSCOUT 18 pF
MGM132
VDACN2
VDACN1
VDDA1
VSSA1
TP5
SIGNAL QUALITY
C5
C6
R9 100 k AMAFL 67 SCAD1 R11 100 k AMAFR 66 IAC
C7 AM-L 220 nF C9 AM-R 220 nF C11 TAPE-L 220 nF C13 TAPE-R 220 nF
R8 47 k C8 R10 47 k C10 R12 47 k C12 R14 47 k C14 R16 100 pF 100 pF 100 pF 100 pF
R13 SCAD2 100 k TAPEL 69 ANALOG SOURCE SELECTOR
R15 100 k TAPER 68 SCAD3
SAA7705H
C16 C15 150 pF 680 nF
FM 3.3 k
FMMPX
80
FMRDS
79 RDS DECODER OSCILLATOR
SELFR
61
43 RTCB L3 100 H +5 V C47 100 F C48 100 nF L4 BLM21A10 +3.3 V C49 22 F C50 10 nF VDDA3V VDDA5V VDDD5V
44 SHTCB
45 TSCAN
17 TP1
18 TP2
19 TP3
20 TP4
60 RDSDAT
59 RDSCLK
65 VDD(OSC)
63 OSCIN X1 18 pF C21 18 pF C22
R18 220 C18 VDDD3V 100 pF
R19 220 C19 100 pF
C20
L1 BLM21A10
RDS data
RDS clock
VDDA3V
Fig.21 Application diagram (continued in Fig.22).
1999 Aug 16
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
handbook, full pagewidth
VDDD3V
to/ from MICROCONTROLLER
BLM21A10
L2 C26 100 pF R23 220 C27 R24 220 DSPIN2 100 pF C28 100 pF R25 220 DSPOUT1 C29 R26 220 DSPOUT2 100 pF VDDA5V
C49
22 F
VDDD3V1
VDDD3V2
VDDD3V3
VDDD3V4
DSPIN1
R32 1.2 k TR1 11 VDDA2 C30 10 VSSA2 R27 5.6 k 4.7 C33 F R28 C34 15 FLI 2.2 100 nF C38 100 pF C42 front-left 2.2 F 10 nF 22 F C31 100 nF R33 4.7 k
48
51
52
55
38
39
40
41
A 5 EQUALIZER
POM
from MICROCONTROLLER
C32
16 B
FLV
13
FRV C35
R29 2.2 100 nF C39
C43 front-right 2.2 F 10 nF to power amplifier rear-left 2.2 F 10 nF
C
STEREO DECODER
DSP CORE DIGITAL SOURCE SELECTOR
QUAD DIGITAL TO ANALOG CONVERTER (QDAC)
14
FRI
9
RLV C36
R30 2.2 100 nF C40
C44
8
RLI
D 6 RRV C37 R31 2.2 100 nF C41 C45 rear-right 2.2 F 10 nF
E
7 12
RRI
VREFDA C46 22 F
SAA7705H
34 35 30 33 I2C-BUS INTERFACE 31 32 62 VSS(OSC) 29 CD1CL 27 CD1WS 28 CD1DATA 25 CD2DATA 24 CD2WS 26 CD2CL 57 SCL 58 SDA 56 A0 42 DSPRESET IISOUT1 IISOUT2 IISCLK IISWS IISIN1 IISIN2
R20 220 100 pF
R21 220 100 pF 220 nF
MGM133
from MICROCONTROLLER
C23
C24
C25
SCL
SDA
Fig.22 Application diagram (continued from Fig.21).
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
14 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA7705H
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA Lp L detail X A A2 A1 (A 3)
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
15 SOLDERING 15.1 Introduction to soldering surface mount packages
SAA7705H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not
SAA7705H
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7705H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
NOTES
SAA7705H
1999 Aug 16
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
NOTES
SAA7705H
1999 Aug 16
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Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/01/pp60
Date of release: 1999
Aug 16
Document order number:
9397 750 02256

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