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EMC2113
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
PRODUCT FEATURES
General Description
The EMC2113 is an SMBus compliant fan controller. The fan driver can be operated using two methods, each with two modes. The methods include an RPM-based Fan Speed Control Algorithm and a direct PWM drive setting. The modes include manually programming the desired settings or using the internal programmable temperature look-up table to select the desired setting based on measured temperature. The EMC2113 includes a temperature monitor that measures up to three (3) external diodes and the internal diode. The temperature monitors offer 1C accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors. The device includes high and low limits for all temperature channels as well as a hardware set critical temperature limit. This hardware set limit drives a dedicated system shutdown pin. Finally, the device includes an open-drain, active low interrupt pin to flag temperature or fan control errors. Datasheet
Features
Programmable Fan Control circuit
-- 4-wire fan compatible -- Both Low and High frequency PWM
RPM-based fan control algorithm
-- 2% accurate from 500 RPM to 16k RPM -- Automatic Tachometer feedback
Temperature Look-Up Table
-- Controls fan speed or PWM drive setting -- Eight steps that incorporate up to four temperature zones simultaneously (user selectable) -- Supports forced DTS or standard temperature data -- Allows external PWM input (150Hz to 40kHz)
Up to Three External Temperature Channels
-- -- -- -- -- Supports transistor model for 90nm - 45nm Intel CPUs Resistance Error Correction and Beta Compensation 1C accurate (60C to 125C) 0.125C resolution Programmable High and Low limits
Hardware Programmable Thermal Shutdown Temperature
-- Cannot be altered by software -- 65C to 127C Range -- Dedicated system shutdown interrupt pin
Applications
Notebook Computers Projectors Graphics Cards Industrial and Networking Equipment
Internal Temperature Monitor
-- 1C accuracy -- 0.125C resolution
3.3V Supply Voltage Open drain interrupt pin SMBus 2.0 Interface
-- SMBus Alert compatible -- Selectable SMBus Address via pull-up resistor and ADDR_SEL pin -- Block Read and Write
Available in 16-pin 4mm x 4mm QFN Lead-free RoHS Compliant package
SMSC EMC2113
DATASHEET
Revision 1.2 (10-08-09)
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
ORDERING INFORMATION:
ORDERING NUMBER EMC2113-1-AP-TR
PACKAGE 16-pin 4mm x4mm QFN (Lead-free ROHS Compliant)
FEATURES RPM-based Fan Speed Control Algorithm, High Frequency PWM driver, HW Thermal / Critical shutdown
This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.2 (10-08-09)
2
SMSC EMC2113
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table of Contents
Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 2 Delta from EMC2103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 3 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 5 SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 SMBus Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.6 SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.7 SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.6 Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.7 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 18 18 18 18 18 18 19 19 19 20 20 20 21
5.2
Chapter 6 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Critical/Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 SYS_SHDN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 SHDN_SEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 TRIP_SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Programming the Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 DTS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RPM-Based Fan Speed Control Algorithm (FSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Programming the RPM-Based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Stalled Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 Aging Fan or Invalid Drive Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 Power Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.2 Continuous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ALERT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
6.2 6.3 6.4
6.5 6.6 6.7
6.8 6.9 6.10
6.11 6.12
23 23 24 24 26 27 27 29 29 29 30 30 30 31 31 31 32 33 33 34 34 34
SMSC EMC2113
Revision 1.2 (10-08-09)
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
6.13
6.14
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.1 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.2 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.3 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.4 Ideality Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.5 Digital Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.1 Anti-Parallel Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.2 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34 34 35 35 35 35 35 36 36
Chapter 7 Fan Control Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical/Thermal Shutdown Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pushed Temperature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Input Duty Cycle Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRIP_SET Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beta Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.14.1 Tcrit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Driver Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Driver Base Frequency Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Input Duty Cycle High Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Step Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Minimum Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Up Table Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 43 44 45 45 46 46 46 48 49 50 50 51 53 53 54 54 54 55 56 56 57 57 58 58 58 60 62 62 64 64 65 65 66 66 67 68 70 70 71 72 72
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4
SMSC EMC2113
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 8 Typical Operating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Chapter 9 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.1 9.2 EMC2113 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Appendix A Look Up Table Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
A.1 A.2 Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.1 LUT Configuration Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.1 Fan Spin Up Configuration Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.2 LUT Configuration - Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3.1 LUT COnfiguration Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 81 82 82 83 84 84
A.3
SMSC EMC2113
5
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DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table of Figures
Figure 1.1 Figure 3.1 Figure 5.1 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 EMC2113 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 EMC2113-1 Pin Diagram (16-Pin QFN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System Diagram for EMC2113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Diagram of Critical/Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fan Control Look-Up Table Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16-Pin QFN 4mm x 4mm Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 16-Pin QFN 4mm x 4mm PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 16-Pin QFN 4mm x 4mm Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 EMC2113 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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SMSC EMC2113
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
List of Tables
Table 2.1 LUT Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 Pin Description for EMC2113-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.1 ADDR_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.2 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.4 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.5 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.6 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.7 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.8 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.9 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 SHDN_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.2 TRIP_SET Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.3 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.4 Dynamic Averaging Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.1 EMC2113 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.4 Critical/Thermal Shutdown Temperature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.5 Critical/Thermal Shutdown Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.6 Pushed Temperature Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.7 PWM Duty Cycle Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.8 TRIP_SET Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.9 Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.10 Ideality Factor Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.11 Substrate Diode Ideality Factor Look-Up Table (BJT Model) . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.12 Beta Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.13 Beta Compensation Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.14 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.15 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.16 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.17 Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.18 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.19 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.20 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.21 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.22 Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.23 Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.24 Fan Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.25 PWM Driver Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.26 PWM Driver Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.27 PWM_BASEx[1:0] it Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.28 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.29 PWM Duty Cycle High Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.30 Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.31 PWM Divide Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.32 Fan Configuration 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.33 Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.34 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC EMC2113 7
10 11 12 13 14 15 17 19 19 19 19 20 20 20 21 24 25 27 34 37 44 44 45 45 45 46 46 46 47 47 48 48 49 50 50 51 52 52 53 53 54 54 55 56 56 56 57 57 58 58 58 59 59
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DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.35 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.36 Fan Configuration 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.37 Derivative Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.38 Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.39 Gain Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.40 Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.41 Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.42 DRIVE_FAIL_CNT[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.43 Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.44 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.45 Fan Step Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.46 Minimum Fan Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.47 Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.48 Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.49 TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.50 TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.51 Look Up Table Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.52 Look Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.53 Software Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.54 Product Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.55 ADDR_SEL[2:0] Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.56 SHDN_SEL[2:0] Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.57 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.58 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.59 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.1 Look Up Table Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.2 Look Up Table Example #1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.3 Fan Speed Control Table Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.4 Fan Speed Determination for Example #1 (using settings in Table A.3) . . . . . . . . . . . . . . . . . Table A.5 Look Up Table Example #2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.6 Fan Speed Control Table Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.7 Fan Speed Determination for Example #2 (using settings in Table A.6) . . . . . . . . . . . . . . . . . Table A.8 Look Up Table Example #3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.9 Fan Speed Control Table Example #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.10 Fan Speed Determination for Example #2 (using settings in Table A.9) . . . . . . . . . . . . . . . . .
60 60 61 61 62 62 62 62 63 64 64 64 65 65 66 66 67 68 70 70 70 71 71 72 72 80 81 81 82 82 83 84 84 85 85
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SMSC EMC2113
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 1 Block Diagram
SYS_SHDN
SHDN_SEL
TRIP_SET
DP1 DN1 DP2/DN3 DN2/DP3
External Temp Diodes
Thermal Shutdown Logic
Antiparallel Diode
Analog Mux 11 bit ADC
Temp Limit Registers SMBus Slave Interface
GND
VDD
ADDR_SEL SMCLK SMDATA ALERT
Internal Temp Diode Configuration
Temp Registers
PWM
PWM driver
TACH
Lookup Table / RPM Control
Tach
PWM Detect
PWM_IN
Figure 1.1 EMC2113 Block Diagram
SMSC EMC2113
9
Revision 1.2 (10-08-09)
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 2 Delta from EMC2103
The EMC2113 is compatible with the EMC2103-2 with the following changes: Removed two GPIOs - Pins 4 and 5 of the EMC2103-2 were GPIO pins. These have been removed. Added PWM Input functionality - This functionality allows the user to drive a PWM input into the EMC2113. The duty cycle of the PWM represents a temperature value and can be used as an input to the Fan Control Look Up Table. Added ADDR_SEL functionality - This functionality allows the user to choose one of six SMBus address options. Updated Hysteresis within Look Up Table - The Fan Control Look Up Table in the EMC2113 allows the user to program a different hysteresis value to apply to each temperature input channel instead of a single hysteresis value that applies to all temperature input channels. Updated input muxing for the Look Up Table - The Fan Control Look Up Table has more options over which temperature channel is used for fan control. Updated HW set shutdown functionality to include option for Internal diode Added control to disable Ramp Rate control if one or more temperatures exceed the high limit Added SMBus Block Read and Write capability
Table 2.1 LUT Options TEMPERATURE INPUT Temperature Column 1 Temperature Column 2 Temperature Column 3 Temperature Column 4 EMC2113 OPTIONS External Diode 1 -or- Pushed Temperature 1 External Diode 2 External Diode 3 -or- Pushed Temperature 1 Internal Diode -or- Pushed Temperature 2
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SMSC EMC2113
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 3 Pin Layout
13 SHDN_SEL 12 GND 11 PWM 10 TACH 9 SMCLK
PIN FUNCTION
16 DP2 / DN3
15 DN2 / DP3 ALERT 6
DN1 DP1 VDD PWM_IN
1 2 3 4 5 SYS_SHDN 7 SMDATA 8 EMC2113 16-pin QFN
Figure 3.1 EMC2113-1 Pin Diagram (16-Pin QFN)
Table 3.1 Pin Description for EMC2113-1 PIN NUMBER 1 2 3 4 5 6 7 PIN NAME DN1 DP1 VDD PWM_IN ADDR_SEL ALERT SYS_SHDN PIN TYPE AIO AIO Power DI (5V) AIO OD (5V) OD (5V)
ADDR_SEL
Negative (cathode) analog input for External Diode 1 Positive (anode) analog input for External Diode 1 Power Supply PWM input signal from host Address Select Input Active low SMBus slave interrupt - requires external pull-up resistor. Active low Critical/Thermal Shutdown output requires external pull-up resistor
11
SMSC EMC2113
14 TRIP_SET
Revision 1.2 (10-08-09)
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 3.1 Pin Description for EMC2113-1 (continued) PIN NUMBER 8 9 10 PIN NAME SMDATA SMCLK TACH PIN FUNCTION SMBus data input/output - requires external pull-up resistor SMBus clock input - requires external pull-up resistor Tachometer input for the Fan PWM - Open Drain PWM drive output for the Fan (default) 11 PWM PWM - Push Pull PWM drive output for the fan 12 13 14 GND SHDN_SEL TRIP_SET Ground Selects the hardware shutdown channel and operating mode Voltage input to set the Critical/Thermal Shutdown threshold DN2 - Negative (cathode) connection for External Diode 2 15 DN2 / DP3 DP3 - Positive (anode) connection for External Diode 3 DP2 - Positive (anode connection for External Diode 2 16 DP2 / DN3 DN3 - Negative (cathode) connection for External Diode 3 The pin types are described in detail below. All pins labelled with (5V) are 5V tolerant. Note: For all 5V tolerant pins that require a pull-up resistor, the pull-up voltage cannot exceed 3.6V when the device is unpowered. AIO AIO AIO DO Power AIO AIO AIO PIN TYPE DIOD (5V) DI (5V) DI (5V) OD (5V)
Table 3.2 Pin Types PIN TYPE Power DI AIO DO DIO OD DESCRIPTION This pin is used to supply power or ground to the device. Digital Input - this pin is used as a digital input. This pin is 5V tolerant. Analog Input / Output - this pin is used as an I/O for analog signals. Push / Pull Digital Output - this pin is used as a digital output. It can both source and sink current. Digital Input / Output this pin is used as a digital I/O. It can both source and sink current. Open Drain Digital Output - this pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant.
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Chapter 4 Electrical Characteristics
Table 4.1 Absolute Maximum Ratings Voltage on 5V tolerant pins (VPULLUP) Voltage on 5V tolerant pins (|VPULLUP - VDD|) See Note 4.1 Voltage on VDD pin Voltage on any other pin to GND Package Power Dissipation Junction to Ambient (JA) Operating Ambient Temperature Range Storage Temperature Range ESD Rating, All Pins, HBM -0.3 to 5.5 0 to 3.6 -0.3 to 4 -0.3 to VDD + 0.3 0.8W up to TA = 85C 50 -40 to 125 -55 to 150 2000 V V V V W C/W C C V
Note: Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. Note: All voltages are relative to ground. Note: JA numbers are based on a recommended four 12 mil vias connecting the thermal pad to PCB ground. Note 4.1 For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the EMC2113 is unpowered.
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4.1
Electrical Specifications
Table 4.2 Electrical Specifications VDD = 3V to 3.6V, TA = -40C to 125C, all Typical values at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
DC Power Supply Voltage VDD 3 3.3 3.6 V 4 Conversions/second, Fan Driver active at maximum PWM frequency, Dynamic Averaging Enabled 1 Conversion/second, Fan Driver not active, Dynamic Averaging Disabled Time after power up before all channels updated Time before SMBus communications should be sent by host
1.1 Supply Current IDD 0.7 First Conversion Ready SMBus Delay
1.5
mA
1.1
mA
tCONV_T
150
300
ms
tSMB_D
10
15
ms
External Temperature Monitors Temperature Accuracy Temperature Resolution Diode decoupling capacitor Resistance Error Corrected CFILTER RSERIES 0.5 1 0.125 2200 100 Internal Temperature Monitor Temperature Accuracy Temperature Resolution 0.5 TA 1 0.125 RPM-Based Fan Controller Tachometer Range RPM Control Accuracy TACH 480 1 16000 2 RPM % 1 2 C C C 40C < TA < 100C 2700 1 2 C C C pF Ohm Connected across external diode, CPU, GPU, or AMD diode Sum of series resistance in both DP and DN lines 60C < TDIODE < 125C 30C < TA < 100C -40C < TDIODE < 125C
TACH
PWM Fan Driver PWM Resolution PWM Duty Cycle PWM DUTY 0 256 100 Steps %
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Table 4.2 Electrical Specifications (continued) VDD = 3V to 3.6V, TA = -40C to 125C, all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
PWM Input Detection PWM Frequency fPWM_IN 150 40k Hz
TRIP_SET Measurement TRIP_SET Decode Accuracy TRIP_SET Decode Accuracy VTRIP VTRIP 0.5 1 1 2 C C 1% resistor connected to ground 5% resistor connected to ground
Digital I/O pins Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Leakage Current VIH VIL VOH VOL ILEAK VDD 0.4 0.4 5 2.0 0.8 V V V V uA 8 mA current drive 8 mA current sink ALERT and SYS_SHDN pins Device powered or unpowered TA < 85C
4.2
SMBus Electrical Specifications
Table 4.3 SMBus Electrical Specifications VDD= 3V to 3.6V, TA = -40C to 125C Typical values are at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface Input High/Low Current Input Capacitance IIH / IIL CIN 4 5 10 uA pF Device powered or unpowered TA < 85C
SMBus Timing Clock Frequency Spike Suppression Bus free time Start to Stop Setup Time: Start Setup Time: Stop Data Hold Time Data Setup Time
SMSC EMC2113
fSMB tSP tBUF tSU:STA tSU:STP tHD:DAT tSU:DAT
10
400 50
kHz ns us us us
1.3 0.6 0.6 0.6 0.6
15
6 72
us us
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Table 4.3 SMBus Electrical Specifications (continued) VDD= 3V to 3.6V, TA = -40C to 125C Typical values are at TA = 27C unless otherwise noted. CHARACTERISTIC Clock Low Period Clock High Period Clock/Data Fall time Clock/Data Rise time Capacitive Load SYMBOL tLOW tHIGH tFALL tRISE CLOAD MIN 1.3 0.6 300 300 400 TYP MAX UNITS us us ns ns pF Min = 20+0.1CLOAD ns Min = 20+0.1CLOAD ns Total per bus line CONDITIONS
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Chapter 5 SMBus Slave Interface
The EMC2113 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices.
5.1
System Management Bus Interface Protocol
The EMC2113 contains an SMBus slave interface. A detailed timing diagram is shown in Figure 5.1, "SMBus Timing Diagram". Stretching of the SMCLK signal is supported, however the EMC2113 will not stretch the clock signal.
TLOW
THIGH
THD:STA TSU:STO
SMCLK
THD:STA
TRISE
TFALL
THD:DAT
TSU:DAT
TSU:STA
SMDATA
TBUF
P
S
S - Start Condition
S
P - Stop Condition P
Figure 5.1 SMBus Timing Diagram
5.1.1
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic `1' state to a logic `0' state while the SMBus Clock line is in a logic `1' state.
5.1.2
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit is a logic `0', then the host device is writing data to the slave device. If this RD / WR bit is a logic `1', then the host device is reading data from the slave device. The EMC2113 SMBus slave address is determined via the pull-up resistor connected to the ADDR_SEL pin as shown Table 5.1, "ADDR_SEL Pin Decode".
Table 5.1 ADDR_SEL Pin Decode PULL-UP RESISTOR VALUE 4.7k Ohm 5% 6.8k Ohm 5% 10k Ohm 5% 15k Ohm 5% FAN CONTROL ADDRESS 0101_100(r/w) 0101_101(r/w) 0101_110(r/w) 1001_100(r/w)
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Table 5.1 ADDR_SEL Pin Decode (continued) PULL-UP RESISTOR VALUE 22k Ohm 5% 33k Ohm 5% FAN CONTROL ADDRESS 1001_101(r/w) 1001_000(r/w)
5.1.3
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
5.1.4
SMBus ACK and NACK Bits
The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line high after the 8th data bit has been sent.
5.1.5
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic `0' state to a logic `1' state while the SMBus clock line is in a logic `1' state. When the EMC2113 detects an SMBus Stop bit, and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare to receive further communications.
5.1.6
SMBus Time-out
The EMC2113 includes an SMBus time-out feature. Following a 30ms period of inactivity on the SMBus, the device will time-out and reset the SMBus interface. The SMBus timeout defaults to enabled and can be disabled by setting the DIS_TO bit (see Section 7.12, "Configuration 2 Register").
5.1.7
SMBus and I2C Compliance
The major difference between SMBus and I2C devices is highlighted here. For complete compliance information refer to the SMBus 2.0 specification. 1. Minimum frequency for SMBus communications is 10kHz. 2. The slave protocol will reset if the clock is held low longer than 30ms. 3. The slave protocol will reset if both the clock and the data line are high for longer than 150us (idle condition). 4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
5.2
SMBus Protocols
The EMC2113 slave interface is SMBus 2.0 compatible and support Send Byte, Read Byte, Receive Byte, Write Byte, Block Read Byte, Block Write Byte, and the Alert Response Address as valid protocols. These protocols are used as shown below. All of the below protocols use the convention in Table 5.2, "Protocol Format". For the Slave Address fields, the value of YYYY_YYY represents the programmed SMBus address.
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Table 5.2 Protocol Format DATA SENT TO DEVICE # of bits sent DATA SENT TO THE HOST # of bits sent
5.2.1
Write Byte
The Write Byte is used to write one byte of data to the registers as shown below Table 5.3.
Table 5.3 Write Byte Protocol SLAVE ADDRESS YYYY_YYY REGISTER ADDRESS 0 -> 1 REGISTER DATA XXh
START 1 -> 0
WR 0
ACK 0
ACK 0
ACK 0
STOP 0 -> 1
5.2.2
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 5.4.
Table 5.4 Read Byte Protocol SLAVE ADDRESS YYYY_YYY REGISTER ADDRESS XXh SLAVE ADDRESS YYYY_YYY REGISTER DATA XXh
START 1 -> 0
WR 0
ACK 0
ACK 0
START 1 -> 0
RD 1
ACK 0
NACK 1
STOP 0 -> 1
5.2.3
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 5.5.
Table 5.5 Send Byte Protocol SLAVE ADDRESS YYYY_YYY REGISTER ADDRESS XXh
START 1 -> 0
WR 0
ACK 0
ACK 1
STOP 0 -> 1
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5.2.4
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 5.6.
Table 5.6 Receive Byte Protocol SLAVE ADDRESS YYYY_YYY
START 1 -> 0
RD 1
ACK 0
REGISTER DATA XXh
NACK 1
STOP 0 -> 1
5.2.5
Block Write
The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 5.7. It is an extension of the Write Byte Protocol.
Table 5.7 Block Write Protocol SLAVE ADDRESS YYYY_YYY REGISTER ADDRESS XXh REGISTER DATA XXh
START 1 ->0 REGISTER DATA XXh
WR 0 REGISTER DATA XXh
ACK 0
ACK 0 REGISTER DATA XXh
ACK 0
ACK 0
ACK 0
... ...
ACK 0
STOP 0 -> 1
5.2.6
Block Read
The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 5.8. It is an extension of the Read Byte Protocol.
Table 5.8 Block Read Protocol
START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK START SLAVE ADDRESS RD ACK REGISTER DATA
1->0
ACK
YYYY_YYY
REGISTER DATA
0
ACK
0
REGISTER DATA
XXh
ACK
0
REGISTER DATA
1 ->0
ACK
YYYY_YYY
...
1
REGISTER DATA
0
NACK
XXh
STOP
0
XXh
0
XXh
0
XXh
0
...
XXh
1
0 -> 1
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5.2.7
Alert Response Address
The ALERT output can be used as a processor interrupt or as an SMBus Alert when configured to operate as an interrupt. When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 0001_100b. All devices with active interrupts will respond with their slave address as shown in Table 5.9.
Table 5.9 Alert Response Address Protocol ALERT RESPONSE ADDRESS 0001_100
START 1 -> 0
RD 1
ACK 0
DEVICE ADDRESS YYYY_YYY
NACK 1
STOP 0 -> 1
The EMC2113 slave interface will respond to the ARA in the following way if the ALERT pin is asserted. 1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2. Set the MASK bit to clear the ALERT pin.
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Chapter 6 Product Description
The EMC2113 is an SMBus compliant fan controller with up to three (3) external and one (1) internal temperature channels. The fan driver can be operated using two methods, each with two modes. The methods include an RPM-based Fan Speed Control Algorithm and a direct PWM drive setting. The modes include manually programming the desired settings or using the internal programmable temperature look-up table to select the desired setting based on measured temperature. The temperature monitors offer 1C accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors (including support of the BJT or transistor model for a CPU diode). The EMC2113 allows the user to program temperatures generated from external sources to control the fan speed. This functionality also supports DTS data from the CPU. By pushing DTS or standard temperature values into dedicated registers, the external temperature readings can be used in conjunction with the external diode(s) and internal diode to control the fan speed. The EMC2113 also allows the user to input a PWM input signal on the PWM_IN pin that is used as an input to the Fan Speed Control Look Up Table. The EMC2113 includes a hardware programmable temperature limit and dedicated system shutdown output for thermal protection of critical circuitry. Figure 6.1 shows a system diagram of the EMC2113.
VDD VDD ADDR_SEL VDD DP1 HOST DN1 E M C 21 1 3 DP2 / DN3 DN2 / DP3 PW M 1 .5 V F a n D rive C ircu itry SM CLK SM DATA
O ptio na l A n tipa ra llel D iod e
SM Bus In terfa ce
ALERT P W M _ IN
TACH VDD
1 .2k
SYS_SHDN T R IP _S E T GND SHDN _SEL VDD
Figure 6.1 System Diagram for EMC2113
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6.1
Critical/Thermal Shutdown
The EMC2113 provides a hardware Critical/Thermal Shutdown function for systems. Figure 6.2 is a block diagram of this Critical/Thermal Shutdown function. The Critical/Thermal Shutdown function accepts configuration information from the pullup resistor of the SHDN_SEL pin. The analog portion of the Critical/Thermal Shutdown function monitors the hardware determined shutdown channel. This measured temperature is then compared with TRIP_SET point. This TRIP_SET point is set by the system designer with a single external resistor. The SYS_SHDN is asserted when the indicated temperature meets or exceeds the temperature threshold (TTRIP) established by the TRIP_SET input pin for a number of consecutive measurements defined by the fault queue. Each of the software programmed temperature limits can be optionally configured to act as inputs to the Critical/Thermal Shutdown independent of the hardware shutdown operation. When configured to operate this way, the SYS_SHDN pin will be asserted when the temperature meets or exceeds the programmed Tcrit Limit for the enabled channel (see Section 7.10).
Critical Shutdown Logic
S/W Set Sensor Internal Temp S/W Set Sensor External 1 Temp S/W Set Sensor External 2 Temp S/W Set Sensor External 3 Temp
S/W SHUTDOWN Temperature Conversion and Tcrit. Registers Configuration Registers S/W_SHUTDOWN SMBus Config.
External Diode 1 External Diode 2 Internal Diode VREF
PIN Decode H/W SHUTDOWN Temperature Conversion
SHDN_SEL
H/W_SHUTDOWN Voltage Conversion
TRIP_SET
SYS_SHDN
Figure 6.2 Block Diagram of Critical/Thermal Shutdown
6.1.1
SYS_SHDN Pin
The SYS_SHDN pin is an active low dedicated system interrupt. This pin is asserted low when: 1. The programmed temperature channel (see Section 6.1.2) exceeds the hardware set limit (see Section 6.1.3). 2. Any of the measured temperature channels meet or exceed their programmed TCRIT limits and have been linked to the SYS_SHDN pin (see Section 7.10). 3. Any of the measured temperature channels meet or exceed their programmed High limits and have been linked to the SYS_SHDN pin (see Section 7.11).
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When the SYS_SHDN pin is asserted, it will remain asserted until the measured temperatures drop below the respective limits minus the hysteresis. At this point, the pin will be released automatically.
6.1.2
SHDN_SEL Pin
The EMC2113 has a `strappable' input (SHDN_SEL) allowing for configuration of the hardware Critical/Thermal Shutdown input channel. The pull-up resistor used on this pin identifies which configuration setting is used as shown in Table 6.1, "SHDN_SEL Pin Decode".
.
Table 6.1 SHDN_SEL Pin Decode PULL UP RESISTOR MODE / DIODE CHANNEL AMD CPU on External Diode 1 2N3904 on External Diode 1 Intel CPU or 2N3904 on External Diode 1 Internal Diode Intel CPU or 2N3904 on External Diode 2 Intel CPU or 2N3904 on External Diode 1
EXTERNAL DIODE 1 CONFIG Beta Compensation disabled REC disabled Beta and REC controls are locked Beta Compensation disabled REC enabled Beta and REC controls are locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked
EXTERNAL DIODE 2 CONFIG Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are locked Beta Compensation enabled (auto) REC enabled Beta and REC controls are not locked
< 4.7k Ohm
6.8k Ohm
10k Ohm
15k Ohm
22k Ohm
> 33k Ohm
APPLICATION NOTE: The SHDN_SEL pin decode settings with Beta Compensation enabled (auto) will support a diode connected 2N3904 diode normally.
6.1.3
TRIP_SET Pin
The EMC2113's TRIP_SET pin is an analog input to the Critical/Thermal Shutdown block which sets the Thermal Shutdown temperature. The system designer creates a voltage level at the input through a simple resistor connected to GND as shown in Figure 6.2, "Block Diagram of Critical/Thermal Shutdown". The value of this resistor is used to create an input voltage on the TRIP_SET pin which is translated into a temperature ranging from 65C to 127C.
APPLICATION NOTE: Current only flows when the TRIP_SET pin is being monitored. At all other times, the internal reference voltage is removed and the TRIP_SET pin will be pulled down to ground.
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APPLICATION NOTE: The TRIP_SET pin circuitry is designed to use a 1% resistor externally. Using a 1% resistor will result in the Thermal / Critical Shutdown temperature being decoded correctly. If a 5% resistor is used, then the Thermal / Critical Shutdown temperature may be decoded with as much as 1C error.
Table 6.2 TRIP_SET Resistor Setting TTRIP (C) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 RSET (1%) 0.0 28.7 48.7 69.8 90.9 113 137 158 182 210 237 261 294 324. 348 383 412 453 487 523 562 604 649 698 750 787 845 909 953 TTRIP (C) 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 RSET (1%) 1240 1330 1400 1500 1580 1690 1820 1960 2050 2210 2370 2550 2740 2940 3160 3480 3740 4120 4530 4990 5490 6040 6810 7870 9090 10700 12700 15800 20500
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Table 6.2 TRIP_SET Resistor Setting (continued) TTRIP (C) 94 95 96 RSET (1%) 1020 1100 1150 TTRIP (C) 126 127 65 RSET (1%) 29400 49900 Open
6.2
Fan Control Modes of Operation
The EMC2113 has four modes of operation for the fan driver. Each mode uses Ramp Rate control and the Spin Up Routine. 1. PWM Setting Mode - in this mode of operation, the user directly controls the PWM duty cycle setting. Updating the Fan Driver Setting Register (see Section 7.22, "Fan Setting Registers") will instantly update the fan drive. The driver uses the Spin Up Routine and has user definable ramp rate controls. This is the default mode. The PWM Setting Mode is enabled by clearing both the EN_ALGO bit in the Fan Configuration Register (see Section 7.24) and the LUT_LOCK bit in the Look Up Table Configuration Register (see Section 7.34). Whenever the PWM Setting Mode is enabled, the current drive will be changed to what was last written into the Fan Driver Setting Register. The Ramp Rate is controlled by the settings of the Max Step register (see Section 7.28) and Update Period controls (Section 7.24) and must be enabled via the EN_RRC bit (see Section 7.25). 2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a fan speed and the drive setting is automatically updated to achieve this target speed. The algorithm uses the Spin Up Routine and has user definable ramp rate controls. This mode is enabled by clearing the LUT_LOCK bit in the Look Up Table (LUT) Configuration Register and setting the EN_ALGO bit in the Fan Configuration Register. 3. Using the Look Up Table with Fan Drive Settings (PWM Setting w/ LUT Mode) - In this mode of operation, the user programs the Look Up Table with PWM duty cycle settings and corresponding temperature thresholds. The fan drive is set based on the measured temperatures and the corresponding drive settings. The fan driver uses the Spin Up Routine and has user definable ramp rate controls. This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit while the EN_ALGO bit is set to `0'. The RPM / PWM bit in the Look Up Table Configuration Register MUST be set to `1' or the PWM drive settings will be incorrectly set. 4. Using the Look Up Table with Fan Speed Control algorithm (FSC w/ LUT Mode)- In this mode of operation, the user programs the Look Up Table with fan speed target values and corresponding temperature thresholds. The TACH Target Register will be set based on the measured temperatures and the corresponding target settings. The PWM drive settings will be determined automatically based on the RPM-based Fan Speed Control Algorithm. PWM drive settings will be determined automatically based on the RPM-based Fan Speed Control Algorithm This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit while the EN_ALGO bit is set to `1'. The RPM / PWM bit in the Look Up Table Configuration Register MUST be set to `0' or the TACH Target values will be incorrectly set.
APPLICATION NOTE: It is important that the TACH Target settings are in the proper format when using the RPMbased Fan Speed Control Algorithm.
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Table 6.3 Fan Controls Active for Operating Mode DIRECT PWM SETTING MODE Fan Driver Setting (read / write) EDGES[1:0] UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Max Step Valid TACH Count TACH Reading DIRECT PWM SETTING W/ LUT MODE Fan Driver Setting (read only) EDGES[1:0] UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Max Step
FSC MODE Fan Driver Setting (read only) EDGES[1:0] (Fan Configuration) RANGE[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Max Step Fan Minimum Drive Valid TACH Count TACH Target (read / write) TACH Reading -
FSC W/ LUT MODE Fan Driver Setting (read only) EDGES[1:0] RANGE[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Max Step Fan Minimum Drive
Valid TACH Count TACH Reading Look Up Table Drive / Temperature Settings (read only) -
Valid TACH Count TACH Target (read only) TACH Reading Look up Table Drive / Temperature Settings (read only) DRIVE_FAIL_CNT [1:0] (Spin Up Configuration) + Fan Drive Fail Band
-
DRIVE_FAIL_CNT [1:0] (Spin Up Configuration) + Fan Drive Fail Band
6.3
PWM Fan Driver
The EMC2113 supports a high or low frequency PWM driver. The output can be configured as either push-pull or open drain and the frequency ranges from 9.5Hz to 26kHz in four programmable frequency bands. The PWM frequency range is coarsely adjusted via the PWM Base Frequency register (Section 7.19) with a fine tune adjustment performed via the PWM Divider registers (see Section 7.23). General PWM operation is governed by the PWM Configuration register (see Section 7.18).
6.4
Fan Control Look-Up Table
The EMC2113 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to the fan driver. In this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. The Look Up Table supports external data pushed into the device by the Host in either DTS or standard format. Each of the four temperature channels used by the Look Up table is generated from measured temperature sensors on the EMC2113 or from an external source.
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The user programs the look-up table based on the desired operation. If the RPM-based Fan Speed Control Algorithm is to be used (see Section 6.6, "RPM-Based Fan Speed Control Algorithm (FSC)"), then the user must program a fan speed target for each temperature setting of interest. Alternately, if the RPM-based Fan Speed Control Algorithm is not to be used, then the user must program a PWM setting for each temperature setting of interest. If the measured temperature on the External Diode channel meets or exceeds any of the temperature thresholds for any of the channels, the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds are exceeded, the highest fan drive setting will take precedence. Figure 6.3, "Fan Control Look-Up Table Example" shows an example of this behavior using a single channel. When the measured temperature drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to the corresponding lower set point. To turn the fan off, there are 2 methods: The first is to set the Temps1-4 Setting 1 values (+ hysteresis) above the temperatures desired for the fan to turn off. When the temperatures fall below Temps1-4 (out of the LUT) by the hysteresis amount, the fan drive will be set to 0. The second is to set the Drive 1 value to 0% (or 0RPM) as well as the Temp 1-4 values to the temperatures (+ hysteresis) at which the fan should turn off. This method will reduce the effective amount of fan drive settings to 7.
Temp T6 T6 - Hyst T5 T5 - Hyst T4 T4 - Hyst Averaged Temperature
Fan Setting S6
S5
S4
T3 T3 - Hyst Fan Setting
S3 S2
T2 T2 - Hyst T1
Measurement taken
S1
Time
Figure 6.3 Fan Control Look-Up Table Example
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6.4.1
Programming the Look Up Table
When the Look Up Table is used, it must be loaded and configured correctly based on the system requirements. The following steps outline the procedure. 1. Determine whether the Look Up Table will drive a PWM duty cycle or a tachometer target value and set the RPM / PWM bit in the Fan LUT Configuration Register (see Section 7.34, "Look Up Table Configuration Register"). 2. Determine which measurement channels (up to four) are to be used with the Look Up Table and set the TEMP1_CFG, TEMP3_CFG and TEMP4_CFG bits accordingly in the Fan LUT Configuration Register. 3. For each step to be used in the LUT, set the Fan Setting (either PWM or TACH Target as set by the RPM / PWM bit). If a setting is not used, then set it to FFh (if a PWM) or 00h (if a TACH Target). Load the lowest settings first in ascending order (i.e. Fan Setting 1 is the lowest setting greater than "off". Fan Setting 2 is the next highest setting, etc.). See Section 7.35, "Look Up Table Registers". 4. For each step to be used in the LUT, set each of the measurement channel thresholds. These values must be set in the same data format that the data is presented. If DTS is to be used, then the format should be in temperature with a maximum threshold of 100C (64h). If a measurement channel is not used, then set the threshold at FFh. 5. Update the threshold hysteresis to be smaller than the smallest table step. 6. Configure the RPM-based Fan Speed Control Algorithm if it is to be used. See Section 7.24, "Fan Configuration 1 Register" for more details. 7. Set the LUT_LOCK bit to enable the Look Up Table and begin fan control in the Fan LUT Configuration Register.
6.4.2
DTS Support
The EMC2113 supports DTS (Intel's Digital Temperature Sensor) data in the Fan Control Look Up Table. Intel's DTS data is a positive number that represents the processor's relative temperature below a fixed value called TCONTROL which is generally equal to 100C for Intel Mobile processors. For example, a DTS value of 10C means that the actual processor temperature is 10C below TCONTROL or equal to 90C. Either or both of the Pushed Temperature Registers can be written with DTS data and used to control the fan driver. When DTS data is entered, then the USE_DTS_Fx bit must be set in the Fan LUT Configuration register. Once this bit is set, the DTS data entered is automatically subtracted from a value of 100C. This delta value is then used in the Look Up Table as standard temperature data.
APPLICATION NOTE: The device is designed with the assumption that TCONTROL is 100C. As such, all DTS related conversions are done based on this value including Look Up Table comparisons. If TCONTROL is adjusted (i.e. TCONTROL is shifted to 105C), then all of the Look Up Table thresholds should be adjusted by a value equal to TCONTROL - 100C.
6.5
PWM Input
The EMC2113 supports a PWM input that is used as an input to the fan speed control Look Up Table. This is controlled by the PUSH1_CFG bit and either the TEMP1_CFG or TEMP3_CFG bits in the Look Up Table Configuration register (see Section 7.34). When a signal is driven into the PWM_IN pin, then the device will automatically calculate the duty cycle of the input signal (provided that the frequency is within the specified range). This value is stored in the PWM Input Duty Cycle register and may be used as an input to the Look Up Table.
APPLICATION NOTE: The PWM Input duty cycle value is a unit-less value that does not correspond to specific temperature values. When used in the Fan Control LUT, It is compared against unit-less 7bit values that represent PWM duty cycle thresholds to control the desired fan speed.
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This functionality is always active. If the pin does not transition, then it will assume 100% duty cycle or 0% duty cycle based on the pin voltage. The data range required by the Look Up Table is 0 to 127 so 100% duty cycle corresponds to 127 and 0% corresponds to 0. The duty cycle measured on the PWM_IN pin is compared against a user programmed PWM High Limit. If the measured duty cycle meets or exceeds this value, then it may cause the ALERT pin to be asserted (default operation is to mask this event from asserting the ALERT pin).
6.6
RPM-Based Fan Speed Control Algorithm (FSC)
The EMC2113 includes an RPM-based Fan Speed Control Algorithm. This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach and maintain the system's desired fan speed to an accuracy directly proportional to the accuracy of the clock source. The desired tachometer count is set by the user inputting the desired number of 32.768KHz cycles that occur per fan revolution. This is done either manually or by programming the Temperature LookUp Table. The user may change the target count at any time. The user may also set the target count to FFh in order to disable the fan driver for lower current operation. For example, if a desired RPM rate for a 2-pole fan is 3000 RPM then the user would input the hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs. The EMC2113's RPM-based Fan Speed Control Algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT pin. The EMC2113 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal.
6.6.1
Programming the RPM-Based Fan Speed Control Algorithm
The RPM-based Fan Speed Control Algorithm powers-up disabled. The following registers control the algorithm. The EMC2113 fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. Note that steps 1 - 7 are optional and need only be performed if the default settings do not provide the desired fan response. 1. Set the Valid TACH Count Register to maximum number of tach counts to indicate the fan is spinning. 2. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired. 3. Set the Fan Step Register to the desired step size. 4. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation. 5. Set the Update Time and Edges options in the Fan Configuration Register. 6. Set the TACH Target Register to the desired tachometer count. 7. Enable the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit.
6.7
Tachometer Measurement
The tachometer measurement circuitry is used in conjunction with the RPM-based Fan Speed Control Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a diagnostic for host based fan control.
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The EMC2113 monitors the TACH signal in real time. It constantly updates the tachometer measurement by reporting the number of clocks between a user programmed number of edges on the TACH signal (see Table 7.34, "Minimum Edges for Fan Rotation"). Using the Tach Period Measurement method provides fast response times for the RPM-based Fan Speed Control Algorithm and the data is presented as a count value that represents the fan RPM period. When this method is used, all fan target values must be input as a count value for proper operation. APPLICATION NOTE: The Tach Period Measurement method works independently of the drive settings. If the device is put into Direct Setting and the fan drive is set at a level that is lower than the fan can operate (including zero drive), then the tachometer measurement may signal a Stalled Fan condition and assert an interrupt.
6.7.1
Stalled Fan
A Stalled fan is detected if the tach counter exceeds the user-programmable Valid TACH Count setting. The EMC2113 will flag the fan as stalled and trigger an interrupt. If the RPM-based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled. The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the mode of operation. When the Direct Setting Mode or Direct Setting with LUT Mode are enabled, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table 7.44, "Spin Time"). This is to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. In Direct Setting Mode or Direct Setting with LUT Mode, whenever the drive value is changed from 00h, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. In Direct Setting Mode or Direct Setting w/ LUT Mode, and the tachometer measurement is using the Tach Period Measurement method, then whenever the TACH Reading Register value exceeds the Valid TACH Count Register setting, the FAN_STALL status bit will be set. When using the RPM-based Fan Speed Control Algorithm (either FSC Mode or LUT with FSC Mode), the stalled fan condition is checked whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.
6.7.2
Aging Fan or Invalid Drive Detection
The EMC2113 contains circuitry that detects that the programmed fan speed can be reached by the fan. If the target fan speed cannot be reached within a user defined band of tach counts at maximum drive then the DRIVE_FAIL status bit is set and the ALERT pin is asserted. This is useful to detect aging fan conditions (where the fan's natural maximum speed degrades over time) or incorrect fan speed settings.
6.8
Spin Up Routine
The EMC2113 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. The Spin Up Routine is initiated under the following conditions when the Tach Period Measurement method of tach measurement is used: This applies to both the RPMbased Fan Speed Control Algorithm mode, or Direct Setting mode (with or without the Look Up Table - when enabled). 1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid TACH Count (see Section 7.30, "Valid TACH Count Register"). 2. The RPM-based Fan Speed Control Algorithm's measured TACH Reading Register value is greater than the Valid TACH Count setting.
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When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of the total user defined spin up time. For the remaining spin up time, the fan driver output is set to a user defined level (30% through 65% drive). After the Spin Up Routine has finished, the EMC2113 measures the TACH signal. If the measured TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan. Figure 6.4, "Spin Up Routine" shows an example of the Spin Up Routine in response to a programmed fan speed change based on the first condition above.
100% (optional)
30% through 65% Fan Step
New Target Count Algorithm controlled drive Prev Target Count = FFh 1/4 of Spin Up Time
Update Time Spin Up Time
Target Count Changed
Check TACH
Target Count Reached
Figure 6.4 Spin Up Routine
6.9
Ramp Rate Control
The PWM output drive can be configured with automatic ramp rate control. If the RPM-based Fan Speed Control Algorithm is used, then this ramp rate control is automatically used based on the fan control derivative option settings. The user programs a maximum step size for the PWM setting and an update time. The update time varies from 100ms to 1.6s while the PWM maximum step can vary from 1 PWM count to 31 PWM counts. When a new PWM duty cycle value is entered (either directly, as a result of the FSC Algorithm adjusting the output PWM to meet the programmed TACH Target value, or as a result of the ramp rate control circuitry), the delta from the next PWM and the previous PWM is determined. If this delta is greater than the maximum fan step settings, then the PWM is adjusted by the maximum fan step settings. The PWM duty cycle is adjusted (and the delta recalculated) every 100ms to 1.6s as determined by the Update Time until the target PWM setting is reached. See Figure 6.5, "Ramp Rate Control".
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Next Desired Setting Max Step Max Step
Previous Setting
Update Time
Update Time
Setting Changed
Figure 6.5 Ramp Rate Control
6.10
Watchdog Timer
The EMC2113 contains an internal Watchdog Timer for the fan driver. The Watchdog timer monitors the SMBus traffic for signs of activity and works in two different modes based upon device operation. These modes are Power Up Operation and Continuous Operation as described below. For either mode of operation, if four (4) seconds elapse without activity detected by the host, then the watchdog will be triggered and the following will occur: 1. The WATCH status bit will be set which will cause the ALERT pin to be asserted. 2. The fan driver will be set to full scale drive. It will remain at full scale drive until it is disabled.
APPLICATION NOTE: When the Watchdog timer is activated the Fan Speed Control Algorithm is automatically disabled. Disabling the Watchdog will not automatically set the fan drive nor re-activate the Fan Speed Control Algorithm. This must be done manually.
6.10.1
Power Up Operation
The Watchdog Timer only starts immediately after power-up and once it has been triggered or deactivated will not restart although it can be configured to operate in Continuous operation. In the Power Up Operation, the Watchdog Timer is disabled by any of the following actions: 1. Writing the Fan Setting Register will disable the Watchdog Timer. 2. Enabling the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the Watchdog Timer. The fan driver will be set based on the RPM-based Fan Speed Control Algorithm. 3. Changing the Watchdog operating mode by setting the WD_EN bit. Writing any other configuration registers will not disable the Watchdog Timer upon power up.
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6.10.2
Continuous Operation
When configured to operate in Continuous Operation, the Watchdog timer will start immediately. It can be disabled by any access (read or write) to the SMBus register set. Upon completion of SMBus activity, the Watchdog timer is reset and restarted.
6.11
Fault Queue
The EMC2113 contains a programmable fault queue on all fault conditions. The fault queue defines how many consecutive out-of-limit conditions must be reported before the corresponding status bit is set (and the ALERT pin asserted).
6.12
ALERT Pin
The ALERT pin acts as an active low open drain interrupt that flags several conditions. It will be asserted low when: 1. The FSC Algorithm detects a stalled fan. 2. The measured temperature meets or exceeds its programmed high limit or drops below its programmed low limit. 3. A diode fault is detected. 4. The PWM input duty cycle has exceeded its programmed limit. Once asserted, the ALERT pin will remain asserted until the status bits have been cleared or the MASK bit has been set.
6.13
Temperature Monitoring
The EMC2113 can monitor the temperature of up to three (3) externally connected diodes as well as the internal or ambient temperature. Each channel is configured with Resistance Error Correction, BJT Transistor model support, and Averaging enabled or disabled based on user settings and system requirements. All temperature channels offer 1C accuracy and 0.125C resolution.
6.13.1
Dynamic Averaging
The EMC2113 supports dynamic averaging. When enabled, this feature changes the conversion time for all channels based on the selected conversion rate. This essentially increases the averaging factor as shown in Table 6.4, "Dynamic Averaging Behavior". The benefits of Dynamic Averaging are improved noise rejection due to the longer integration time as well as less random variation on the temperature measurement.
Table 6.4 Dynamic Averaging Behavior AVERAGING FACTOR (RELATIVE TO 11-BIT CONVERSI0N) CONVERSION RATE DYNAMIC AVERAGING ENABLED 8x 4x 2x 1x DYNAMIC AVERAGING DISABLED 1x 1x 1x 1x
1 / sec 2 / sec 4 / sec Continuous
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6.13.2
Resistance Error Correction
The EMC2113 includes active Resistance Error Correction to remove the effect of up to 100 ohms of series resistance. Without this automatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. The error induced by parasitic resistance is approximately +0.7C per ohm. Sources of parasitic resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU, and resistance in the printed circuit board traces and package leads. Resistance error correction in the EMC2113 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path.
6.13.3
Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. As well, it is not constant over changes in temperature. The variation in beta causes an error in temperature reading that is proportional to absolute temperature. This correction is done by implementing the BJT or transistor model for temperature measurement. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25C error at 100C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25C error at 100C. The Beta Compensation circuitry in the EMC2113 corrects for this beta variation to eliminate any error which would normally be induced. It automatically detects the appropriate beta setting to use.
6.13.4
Ideality Configuration
The EMC2113 is designed for external diodes with an ideality factor of 1.008. Not all external diodes, processor or discrete, will have this exact value. This variation of the ideality factor introduces error in the temperature measurement which must be corrected for. This correction is typically done using programmable offset registers. Since an ideality factor mismatch introduces an error that is a function of temperature, this correction is only accurate within a small range of temperatures. To provide maximum flexibility to the user, the EMC2113 provides a register for each external diode where the ideality factor of the diode used may be programmed to eliminate errors across all temperatures.
APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most ideality errors.
6.13.5
Digital Averaging
The external diode channels support a 4x digital averaging filter. Every cycle, this filter updates the temperature data based an a running average of the last 4 measured temperature values. The digital averaging reduces temperature flickering and increases temperature measurement stability. The digital averaging can be disabled by setting the DIS_AVG bit in the Configuration 2 Register (see Section 7.25, "Fan Configuration 2 Register").
6.14
Diode Connections
The External Diode 1 channel can support a diode-connected transistor (such as a 2N3904) or a substrate transistor requiring the BJT or transistor model (such as those found in a CPU or GPU) as shown in Figure 6.6, "Diode Connections". The External Diode 2 channel supports any diode connection shown or it can be configured to operate in anti-parallel diode (APD) mode. When configured in APD mode, a third temperature channel is
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available that shares the DP2 and DN2 pins. When in this mode, both the external diode 2 channel and external diode 3 channel thermal diodes must be connected as diodes.
Diode 3
Diode 2
to DP to DN
to DP
to DP
to DP / DN to DN / DP
Local Ground Typical remote Typical remote substrate transistor discrete PNP transistor i.e. CPU substrate PNP i.e. 2N3906
to DN Typical remote discrete NPN transistor i.e. 2N3904
to DN
Anti-parallel diodes using discrete NPN transistors
Figure 6.6 Diode Connections
6.14.1
Anti-Parallel Diodes
The EMC2113 supports connecting two external diodes to the DN2 / DP3 and DP2 / DN3 pins. This second diode is connected in an anti-parallel configuration with respect to the first diode. When the the External Diode 2 channel is measured, the anti-parallel diode will be reverse biased. Likewise, when the External Diode 3 channel is measured, the first diode will be reverse biased. CPU diodes should not be used with anti-parallel diode connections.
6.14.2
Diode Faults
The EMC2113 actively detects an open and short condition on each measurement channel. When a diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is set in the Status Register. When the External Diode 2 channel is configured to operate in APD mode, the circuitry will detect independent open fault conditions; however, a short condition will be shared between the External Diode 2 and External Diode 3 channels.
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Chapter 7 Fan Control Register Set
7.1 Register Map
The following registers are accessible through the SMBus Interface. All register bits marked as `-' will always read `0'. A write to these bits will have no effect.
Table 7.1 EMC2113 Register Set REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Temperature Registers
LOCK
PAGE
00h
R
Internal Temp Reading High Byte Internal Temp Reading Low Byte External Diode 1 Temp Reading High Byte External Diode 1 Temp Reading Low Byte External Diode 2 Temp Reading High Byte External Diode 2 Temp Reading Low Byte External Diode 3 Temp Reading High Byte External Diode 3 Temp Reading Low Byte Critical/Thermal Shutdown Temperature Pushed Temperature 1 Pushed Temperature 2 PWM Input Duty Cycle TRIP_SET Voltage
Stores the integer data of the Internal Diode Stores the fractional data of the Internal Diode Stores the integer data of External Diode 1 Stores the fractional data of External Diode 1 Stores the integer data of External Diode 2 Stores the fractional data of External Diode 2 Stores the integer data of External Diode 3 Stores the fractional data of External Diode 3 Stores the calculated Critical/Thermal Shutdown temperature high limit derived from TRIP_SET pin voltage Stores the integer data for Pushed Temperature 1 to drive the LUT Stores the integer data for Pushed Temperature 2 to drive the LUT Stores the calculated duty cycle on the PWM pin Stores the measured voltage on the TRIP_SET pin
00h
No
Page 44
01h 02h
R R
00h 00h
No No
Page 44 Page 44
03h
R
00h
No
Page 44
04h
R
00h
No
Page 44
05h
R
00h
No
Page 44
06h
R
00h
No
Page 44
07h
R
00h
No
Page 44
0Ah
R
N/A
No
Page 45
0Ch 0Dh 0Fh 10h
R/W R/W R R
00h 00h 00h FFh
No No No No
Page 45 Page 45 Page 46 Page 46
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Table 7.1 EMC2113 Register Set (continued) REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Diode Configuration
LOCK
PAGE
11h 12h
R/W R/W
External Diode 1 Ideality Register External Diode 2 Ideality Register External Diode 3 Ideality Register External Diode 1 Beta Configuration External Diode 2 Beta Configuration External Diode REC Configuration
Stores the Ideality Factor used for External Diode 1 Stores the Ideality factor used for External Diode 2 Stores the Ideality factor used for External Diode 3 Configures the beta compensation settings for External Diode 1 Configures the beta compensation settings for External Diode 2 Configures the Resistance Error Correction functionality for all external diodes Critical Temperature Limit Registers
12h 12h
SWL SWL
Page 46 Page 46 Page 46 Page 48 Page 48 Page 49
13h 14h 15h 17h
R/W R/W R/W R/W
12h 10h 10h 07h
SWL SWL SWL SWL
19h 1Ah 1Bh 1Dh
R/W once R/W once R/W once R/W once
External Diode 1 Tcrit Limit External Diode 2 Tcrit Limit External Diode 3 Tcrit Limit Internal Diode Tcrit Limit
Stores the critical temperature limit for External Diode 1 Stores the critical temperature limit for External Diode 2 Stores the critical temperature limit for External Diode 3 Stores the critical temperature limit for the Internal Diode Configuration and control
64h (100C) 64h (100C) 64h (100C) 64h (100C)
Write Once Write Once Write Once Write Once
Page 50 Page 50 Page 50 Page 50
1Fh 20h 21h 23h 24h 25h 26h 27h 28h
R R/W R/W R R-C R-C R-C R-C R/W
Tcrit Status Configuration Configuration 2 Interrupt Status High Limit Status Low Limit Status Diode Fault Fan Status Interrupt Enable Register
Stores the status bits for all temperature channel tcrit limits Configures the Thermal / Critical Shutdown masking options Controls the conversion rate for monitoring of all channels Stores the status bits for temperature channels Stores the status bits for all temperature channel high limits Stores the status bits for all temperature channel low limits Stores the status bits for all temperature channel diode faults Stores the status bits for the RPMbased Fan Speed Control Algorithm Controls the masking of interrupts on all temperature channels
38
00h 00h 0Eh 00h 00h 00h 00h 00h 00h
No SWL SWL No No No No No No
Page 53 Page 50 Page 51 Page 53 Page 53 Page 53 Page 53 Page 54 Page 54
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Table 7.1 EMC2113 Register Set (continued) REGISTER NAME Fan Interrupt Enable Register PWM Driver Config PWM Driver Base Frequency DEFAULT VALUE 00h 00h 00h
ADDR 29h 2Ah 2Bh
R/W R/W R/W R/W
FUNCTION Controls the masking of interrupts for the Fan Driver Configures the PWM driver Controls the base frequency of the PWM driver Temperature High Limit Registers
LOCK No No No
PAGE Page 55 Page 56 Page 56
30h 31h 32h 34h
R/W R/W R/W R/W
External Diode 1 Temp High Limit External Diode 2 Temp High Limit External Diode 3 Temp High Limit Internal Diode High Limit
High limit for External Diode 1 High limit for External Diode 2 High limit for External Diode 3 High Limit for Internal Diode Temperature Low Limit Registers
55h (+85C) 55h (+85C) 55h (+85C) 55h (85C)
SWL SWL SWL SWL
Page 57 Page 57 Page 57 Page 57
38h 39h 3Ah 3Ch
R/W R/W R/W R/W
External Diode 1 Temp Low Limit External Diode 2 Temp Low Limit External Diode 3 Temp Low Limit Internal Diode Low Limit
Low Limit for External Diode 1 Low Limit for External Diode 2 Low Limit for External Diode 3 Low Limit for Internal Diode PWM Input Duty Cycle Limit
00h (0C) 00h (0C) 00h (0C) 00h (0C)
SWL SWL SWL SWL
Page 57 Page 57 Page 57 Page 57
3Dh
R/W
PWM Input Duty Cycle High Limit
Stores the high limit for the PWM input Duty Cycle Fan Control Registers
7Fh
SWL
Page 57
40h
R/W
Fan Setting
Always displays the most recent fan driver input setting for Fan. If the RPM-based Fan Speed Control Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the frequency for the Fan Sets configuration values for the RPM-based Fan Speed Control Algorithm for the Fan Sets additional configuration values for the Fan driver Holds the gain terms used by the RPM-based Fan Speed Control Algorithm for the Fan
39
00h
No
Page 58
41h 42h
R/W R/W
PWM Divide Fan Configuration 1 Fan Configuration 2 Gain
01h 2Bh
No No
Page 58 Page 58
43h 45h
R/W R/W
28h 2Ah
SWL SWL
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Table 7.1 EMC2113 Register Set (continued) REGISTER NAME Fan Spin Up Configuration Fan Step Fan Minimum Drive Fan Valid TACH Count Fan Drive Fail Band Low Byte Fan Drive Fail Band High Byte TACH Target Low Byte TACH Target High Byte TACH Reading High Byte TACH Reading Low Byte DEFAULT VALUE 19h 10h 66h (40%) F5h
ADDR 46h 47h 48h 49h
R/W R/W R/W R/W R/W
FUNCTION Sets the configuration values for Spin Up Routine of the Fan driver Sets the maximum change per update for the Fan Sets the minimum drive value for the the Fan driver Holds the minimum tachometer reading that indicates the fan is spinning properly Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive
LOCK SWL SWL SWL SWL
PAGE Page 62 Page 64 Page 64 Page 65
4Ah 4Bh 4Ch 4Dh 4Eh 4Fh
R/W R/W R/W R/W R R
00h 00h F8h FFh FFh F8h
SWL SWL No No No No
Page 65
Holds the target tachometer reading low byte for the Fan Holds the target tachometer reading high byte for the Fan Holds the tachometer reading high byte for the Fan Holds the tachometer reading low byte for the Fan Look Up Table (LUT)
Page 66 Page 66 Page 66 Page 66
50h 51h 52h
R/W R/W R/W
LUT Configuration LUT Drive 1 LUT Temp 1 Setting 1 LUT Temp 2 Setting 1 LUT Temp 3 Setting 1
Stores and controls the configuration for the LUT Stores the lowest programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 1 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 1 value Stores the second programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 2 value
40
00h FBh 7Fh (127C) 7Fh (127C) 7Fh (127C)
No LUT Lock LUT Lock LUT Lock LUT Lock
Page 67 Page 68 Page 68
53h
R/W
Page 68
54h
R/W
Page 68
55h
R/W
LUT Temp 4 Setting 1
7Fh (127C)
LUT Lock
Page 68
56h 57h
R/W R/W
LUT Drive 2 LUT Temp 1 Setting 2
E6h 7Fh (127C)
LUT Lock LUT Lock
Page 68 Page 68
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
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Table 7.1 EMC2113 Register Set (continued) REGISTER NAME LUT Temp 2 Setting 2 LUT Temp 3 Setting 2 DEFAULT VALUE 7Fh (127C) 7Fh (127C)
ADDR 58h
R/W R/W
FUNCTION Stores the threshold level for the External Diode 2 channel that is associated with the Drive 2 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 2 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 2 value Stores the third programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 3 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 3 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 3 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 3 value Stores the fourth programmed drive setting for the LUT Stores the threshold level for the External Diode 1channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 4 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 4 value Stores the fifth programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 5 value
LOCK LUT Lock LUT Lock
PAGE Page 68
59h
R/W
Page 68
5Ah
R/W
LUT Temp 4 Setting 2
7Fh (127C)
LUT Lock
Page 68
5Bh 5Ch
R/W R/W
LUT Drive 3 LUT Temp 1 Setting 3 LUT Temp 2 Setting 3 LUT Temp 3 Setting 3
D1h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 68 Page 68
5Dh
R/W
Page 68
5Eh
R/W
Page 68
5Fh
R/W
LUT Temp 4 Setting 3
7Fh (127C)
LUT Lock
Page 68
60h 61h
R/W R/W
LUT Drive 4 LUT Temp 1 Setting 4 LUT Temp 2 Setting 4 LUT Temp 3 Setting 4
BCh 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 68 Page 68
62h
R/W
Page 68
63h
R/W
Page 68
64h
R/W
LUT Temp 4 Setting 4
7Fh (127C)
LUT Lock
Page 68
65h 66h
R/W R/W
LUT Drive 5 LUT Temp 1 Setting 5
A7h 7Fh (127C)
LUT Lock LUT Lock
Page 68 Page 68
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Table 7.1 EMC2113 Register Set (continued) REGISTER NAME LUT Temp 2 Setting 5 LUT Temp 3 Setting 5 DEFAULT VALUE 7Fh (127C) 7Fh (127C)
ADDR 67h
R/W R/W
FUNCTION Stores the threshold level for the External Diode 2 channel that is associated with the Drive 5 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 5 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 5 value Stores the sixth programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 6 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 6 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 6 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 6 value Stores the seventh programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 2 channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 7 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 7 value Stores the highest programmed drive setting for the LUT Stores the threshold level for the External Diode 1 channel that is associated with the Drive 8 value
LOCK LUT Lock LUT Lock
PAGE Page 68
68h
R/W
Page 68
69h
R/W
LUT Temp 4 Setting 5
7Fh (127C)
LUT Lock
Page 68
6Ah 6Bh
R/W R/W
LUT Drive 6 LUT Temp 1 Setting 6 LUT Temp 2 Setting 6 LUT Temp 3 Setting 6
92h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 68 Page 68
6Ch
R/W
Page 68
6Dh
R/W
Page 68
6Eh
R/W
LUT Temp 4 Setting 6
7Fh (127C)
LUT Lock
Page 68
6Fh 70h
R/W R/W
LUT Drive 7 LUT Temp 1 Setting 7 LUT Temp 2 Setting 7 LUT Temp 3 Setting 7
92h 7Fh (127C) 7Fh (127C) 7Fh (127C)
LUT Lock LUT Lock LUT Lock LUT Lock
Page 68 Page 68
71h
R/W
Page 68
72h
R/W
Page 68
73h
R/W
LUT Temp 4 Setting 7
7Fh (127C)
LUT Lock
Page 68
74h 75h
R/W R/W
LUT Drive 8 LUT Temp 1 Setting 8
92h 7Fh (127C)
LUT Lock LUT Lock
Page 68 Page 68
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Table 7.1 EMC2113 Register Set (continued) REGISTER NAME LUT Temp 2 Setting 8 LUT Temp 3 Setting 8 DEFAULT VALUE 7Fh (127C) 7Fh (127C)
ADDR 76h
R/W R/W
FUNCTION Stores the threshold level for the External Diode 2 channel that is associated with the Drive 8 value Stores the threshold level for the External Diode 3 channel (or Pushed Temp 1 temp) that is associated with the Drive 8 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 8 value Stores the hysteresis that is used in the LUT for the Temp 1 Settings Stores the hysteresis that is used in the LUT for the Temp 2 Settings Stores the hysteresis that is used in the LUT for the Temp 3 Settings Stores the hysteresis that is used in the LUT for the Temp 4 Settings Stores and controls the configuration for the LUT Lock Register
LOCK LUT Lock LUT Lock
PAGE Page 68
77h
R/W
Page 68
78h
R/W
LUT Temp 4 Setting 8
7Fh (127C)
LUT Lock
Page 68
79h 7Ah 7Bh 7Ch 7Dh
R/W R/W R/W R/W R/W
LUT Temp 1 Hysteresis LUT Temp 2 Hysteresis LUT Temp 3 Hysteresis LUT Temp 4 Hysteresis LUT Configuration
0Ah (10C) 0Ah (10C) 0Ah (10C) 0Ah (10C) 00h
LUT Lock LUT Lock LUT Lock LUT Lock No
Page 68 Page 68 Page 68 Page 68 Page 67
EFh
R/W
Software Lock
Locks all SWL registers Revision Registers
00h
SWL
Page 70
FCh FDh FEh FFh
R R R R
Product Features Product ID Manufacturer ID Revision
Indicates which pin selected options are enabled Stores the unique Product ID Manufacturer ID Revision
00h 2Eh 5Dh 81h
No No No No
Page 70 Page 71 Page 72 Page 72
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect.
7.1.1
Lock Entries
The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set.
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7.2
Temperature Data Registers
Table 7.2 Temperature Data Registers
ADDR 00h 01h
R/W R R
REGISTER Internal Diode High Byte Internal Diode Low Byte External Diode 1 High Byte External Diode 1 Low Byte External Diode 2 High Byte External Diode 2 Low Byte External Diode 3 High Byte External Diode 3 Low Byte
B7 Sign 0.5 Sign
B6 64 0.25 64
B5 32 0.125 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 00h 00h 00h
02h
R
0.5
0.25
0.125
-
-
-
-
-
00h
03h
R
Sign
64
32
16
8
4
2
1
00h
04h
R
0.5
0.25
0.125
-
-
-
-
-
00h
05h
R
Sign
64
32
16
8
4
2
1
00h
06h
R
0.5
0.25
0.125
-
-
-
-
-
00h
07h
R
The temperature measurement range is from -64C to +127.875C. The data format is a signed two's complement number as shown in Table 7.3, "Temperature Data Format".
Table 7.3 Temperature Data Format HEX (AS READ BY REGISTERS) 80_00h C0_20h C1_00h FF_00h FF_E0h 00_00h 00_20h 01_00h 3F_00h 40_00h
TEMPERATURE (C) Diode Fault -63.875 -63 -1 -0.125 0 0.125 1 63 64
BINARY 1000_0000_000b 1100_0000_001b 1100_0001_000b 1111_1111_000b 1111_1111_111b 0000_0000_000b 0000_0000_001b 0000_0001_000b 0011_1111_000b 0100_0000_000b
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Table 7.3 Temperature Data Format (continued) HEX (AS READ BY REGISTERS) 41_00h 7F_00h 7F_E0h
TEMPERATURE (C) 65 127 127.875
BINARY 0100_0001_000b 0111_1111_000b 0111_1111_111b
7.3
Critical/Thermal Shutdown Temperature Register
Table 7.4 Critical/Thermal Shutdown Temperature Register
ADDR
R/W
REGISTER Critical/Thermal Shutdown Temperature
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT 7Fh (+127C)
0Ah
R
128
64
32
16
8
4
2
1
The Critical/Thermal Shutdown Temperature Register is a read-only register that stores the Voltage Programmable Threshold temperature used in the Thermal / Critical Shutdown circuitry. The contents of the register reflect the calculated temperature determined by the voltage on the TRIP_SET pin (see Section 6.1.2, "SHDN_SEL Pin"). The data format is shown in Table 7.5, "Critical/Thermal Shutdown Data Format".
Table 7.5 Critical/Thermal Shutdown Data Format TEMPERATURE (C) 0 1 63 64 65 127 BINARY 0000_0000b 0000_0001b 0011_1111b 0100_0000b 0100_0001b 0111_1111b HEX 00h 01h 3Fh 40h 41h 7Fh
7.4
Pushed Temperature Registers
Table 7.6 Pushed Temperature Registers
ADDR 0Ch 0Dh
R/W R/W R/W
REGISTER Pushed / Polled Temperature 1 Pushed / Polled Temperature 2
B7 Sign Sign
B6 64 64
B5 32 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 00h 00h
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The Pushed Temperature Registers store user programmed temperature values or temperature values polled from one or more slave devices. This temperature can be used by the look-up table to update the fan control algorithm. Data written in these registers is not compared against any limits and must match the data format shown in Table 7.3, "Temperature Data Format".
7.5
PWM Input Duty Cycle Register
Table 7.7 PWM Duty Cycle Register
ADDR 0Fh
R/W R
REGISTER PWM Input Duty Cycle
B7 -
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 00h
The PWM Input Duty Cycle register stores the calculated duty cycle of the signal on the PWM_IN pin. The value is stored as an 7-bit PWM setting ranging from 0 to 127 and represents the duty cycle as shown in Equation [1]. When used by the Fan Control Look Up Table (LUT), the 7-bit PWM Input Duty Cycle register setting is used as a temperature input and compared against the programmed thresholds.
VALUE PWM Duty Cycle = -------------------- x 100% 128
[1]
7.6
TRIP_SET Voltage Register
Table 7.8 TRIP_SET Voltage Register
ADDR 10h
R/W R
REGISTER TRIP_SET Voltage
B7 750.0
B6 375.0
B5 187.5
B4 93.75
B3 46.88
B2 23.43
B1 11.72
B0 5.86
DEFAULT FFh
The TRIP_SET Voltage Register stores data that is measured on the TRIP_SET Voltage input. Each bit weight represents mV of resolution so that the final voltage can be determined by adding the weighting of the set bits together.
7.7
Ideality Factor Registers
Table 7.9 Ideality Factor Registers
ADDR 11h 12h 13h
R/W R/W R/W R/W
REGISTER External Diode 1 Ideality External Diode 2 Ideality External Diode 3 Ideality
B7 0 0 0
B6 0 0 0
B5 0 0 0
B4 1 1 1
B3 0 0 0
B2 B2 B2 B2
B1 B1 B1 B1
B0 B0 B0 B0
DEFAULT 12h 12h 12h
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These registers store the ideality factors that are applied to the external diodes. Beta Compensation and Resistance Error Correction automatically correct for most diode ideality errors, therefore it is not recommended that these settings be updated without consulting SMSC. For CPU substrate transistors that require the BJT transistor model, the ideality factor behaves slightly differently than for discrete diode-connected transistors. Refer to Table 7.11, "Substrate Diode Ideality Factor Look-Up Table (BJT Model)" when using a CPU substrate transistor. Only the lower three bits can be written. Writing to any other bit will be ignored. The Ideality Factor Registers are software locked.
Table 7.10 Ideality Factor Look-Up Table SETTING 10h 11h 12h 13h 14h 15h 16h 17h FACTOR 1.0053 1.0066 1.0080 1.0093 1.0106 1.0119 1.0133 1.0146
Table 7.11 Substrate Diode Ideality Factor Look-Up Table (BJT Model) SETTING 10h 11h 12h 13h 14h 15h 16h 17h FACTOR 0.9973 0.9986 1.0000 1.0013 1.0026 1.0039 1.0053 1.0066
APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When measuring 45nm Intel CPUs, the Ideality Setting should be 15h.
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7.8
Beta Configuration Register
Table 7.12 Beta Configuration Register
ADDR
R/W
REGISTER External Diode 1 Beta Configuration External Diode 2 Beta Configuration
B7
B6
B5
B4 AUT O1 AUT O2
B3
B2
B1
B0
DEFAULT
14h
R/W
-
-
-
-
BETA1[2:0]
10h
15h
R/W
-
-
-
-
BETA2[2:0]
10h
The Beta Configuration Register controls advanced temperature measurement features of the External Diode channels. If External Diode 1 is selected as the hardware shutdown measurement channel (see Section 6.1, "Critical/Thermal Shutdown") then the External Diode 1 Beta register will be read only. If the internal diode is selected, then this register can be written normally. Likewise, if the External Diode 2 channel is selected then this register can be written normally. Finally, if External Diode 2 is selected as the hardware shutdown measurement channel, then the External Diode 2 Beta Configuration Register will be read only. The External Diode 3 channel beta configuration will always be set at 07h (disabled / diode mode). Writing to a read only register will have no affect. The data will be ignored. Bit 4 - AUTOx - Enables the Automatic Beta detection algorithm for the External Diode X channel. `0' - The Automatic Beta detection algorithm is disabled. The BETAx[2:0] bit settings will be used to control the beta compensation circuitry. `1' (default) - The Automatic Beta detection algorithm is enabled. The circuitry will automatically detect the transistor type and beta values and configure the BETAx[2:0] bits for optimal performance. Bits 2 - 0 - BETAx[2:0] - hold a value that corresponds to a range of betas that the Beta Compensation circuitry can compensate for. These three bits will always show the current beta setting used by the circuitry. If the AUTO bit is set (default), then these bits may be overwritten with every temperature conversion. If the AUTO bit is not set, then the value of these bits is used to drive the beta compensation circuitry. In this case, these bits should be set with a value corresponding to the lowest expected value of beta for the PNP transistor being used as a temperature sensing device. See Table 7.13, "Beta Compensation Look Up Table" for supported beta ranges. A value of 111b indicates that the beta compensation circuitry is disabled. In this condition, the diode channels will function with default current levels and will not automatically adjust for beta variation. This mode is used when measuring a discrete 2N3904 transistor or AMD thermal diode. The Beta Configuration Registers are Software Locked.
Table 7.13 Beta Compensation Look Up Table BETAX[2:0] 2 0 0
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1 0 0
48
0 0 1
MINIMUM BETA < 0.08 < 0.111
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
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Table 7.13 Beta Compensation Look Up Table (continued) BETAX[2:0] 2 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 MINIMUM BETA < 0.176 < 0.29 < 0.48 < 0.9 < 2.33 Disabled
7.9
REC Configuration Register
Table 7.14 REC Configuration Register
ADDR 17h
R/W R/W
REGISTER REC Configuration
B7 -
B6 -
B5 -
B4 -
B3 -
B2 REC3
B1 REC2
B0 REC1
DEFAULT 07h
The REC Configuration Register determines whether Resistance Error Correction is used for each external diode channel. Bit 2 - REC3 - Controls the Resistance Error Correction functionality of External Diode 3 `0' - the REC functionality for External Diode 3 is disabled `1' (default) - the REC functionality for External Diode 3 is enabled. Bit 1 - REC2 - Controls the Resistance Error Correction functionality of External Diode 2. `0' - the REC functionality for External Diode 2 is disabled `1' (default) - the REC functionality for External Diode 2 is enabled. Bit 0 - REC1 - Indicates the Resistance Error Correction functionality of External Diode 1. If External Diode 1 is selected as the hardware shutdown channel then this bit is read only. `0' - the REC functionality for External Diode 1 is disabled `1' (default) - the REC functionality for External Diode 1 is enabled. The REC Configuration Register is software locked.
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7.10
Critical Temperature Limit Registers
Table 7.15 Limit Registers
ADDR 19h 1Ah 1Bh 1Dh
R/W R/W once R/W once R/W once R/W once
REGISTER External Diode 1 Tcrit Limit External Diode 2 Tcrit Limit External Diode 3 Tcrit Limit Internal Diode Tcrit Limit
B7 Sign Sign Sign Sign
B6 64 64 64 64
B5 32 32 32 32
B4 16 16 16 16
B3 8 8 8 8
B2 4 4 4 4
B1 2 2 2 2
B0 1 1 1 1
DEFAULT 64h (+100C) 64h (+100C) 64h (+100C) 64h (+100C)
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown circuitry. Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot be updated again without a power on reset. Second, the respective temperature channel is linked to the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the measured temperature channel meets or exceeds the critical limit, the SYS_SHDN pin will be asserted, the appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will be set.
7.11
Configuration Register
Table 7.16 Configuration Register
ADDR 20h
R/W R/W
REGISTER Configuration
B7 MASK
B6 WD_EN
B5 -
B4 -
B3 SYS3
B2 SYS2
B1 SYS1
B0 APD
DEFAULT 00h
The Configuration Register controls the basic functionality of the EMC2113. The bits are described below. Bit 7 - MASK - Blocks the ALERT pin from being asserted. `0' (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pin will be asserted (unless individually masked via the Mask Register) `1' - The ALERT pin is masked and will not be asserted. Bit 6 - WD_EN - Enables the Watchdog timer to operate in Continuous Mode. `0' (default) - The Watchdog timer does not operate continuously. It will function upon power up and at no other time. `1' - The Watchdog timer operates continuously as described in Section 6.10.2, "Continuous Operation". Bit 3 - SYS3 - Enables the high temperature limit for the External Diode 3 channel to trigger the Critical/Thermal Shutdown circuitry (see Section 6.1, "Critical/Thermal Shutdown"). `0' (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit, the ALERT pin will be asserted normally.
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`1' - the External Diode 3 channel high limit will be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit then the SYS_SHDN pin will be asserted. The SYS_SHDN pin will be released when the temperature drops below the high limit. The ALERT pin will be asserted normally. Bit 2 - SYS2 - Enables the high temperature limit for the External Diode 2 channel to trigger the Critical/Thermal Shutdown circuitry (see Section 6.1). `0' (default) - the External Diode 2 channel high limit will not be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit, the ALERT pin will be asserted normally. `1' - the External Diode 2 channel high limit will be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be asserted normally. Bit 1 - SYS1 - Enables the high temperature limit for the External Diode 1 channel to trigger the Critical/Thermal Shutdown circuitry (see Section 6.1). `0' (default) - The External Diode 1 channel high limit will not be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit, the ALERT pin will be asserted normally. `1' - The External Diode 1 channel high limit will be linked to the SYS_SHDN pin. If the temperature meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be asserted normally. Bit 0 - APD - This bit enables the Anti-parallel diode functionality on the External Diode 3 pins (DP3 and DN3). `0' (default) - The Anti-parallel diode functionality is disabled. The External Diode 2 channel can be configured for any type of diode `1' - The Anti-parallel diode functionality is enabled. Both the External Diode 2 and 3 channels are configured to support a diode or diode connected transistor (such as a 2N3904). APPLICATION NOTE: When the APD diode is enabled, there will be a delay of a full temperature update before any comparisons and functionality associated with the External Diode 3 channel will be implemented. This includes the SYS3 bit operation, limit comparisons, and look up table comparisons. The Configuration Register is software locked.
7.12
Configuration 2 Register
Table 7.17 Configuration 2 Register
ADDR 21h
R/W R/W
REGISTER Config 2
B7 -
B6 DIS_ DYN
B5 DIS_ TO
B4 DIS_ AVG
B3
B2
B1
B0
DEFAULT 0Eh
QUEUE[1:0]
CONV[1:0]
The Configuration 2 Register controls conversion rate of the temperature monitoring as well as the fault queue. Bit 6 - DIS_DYN - Disables the Dynamic Averaging Feature. `0' (default) - The Dynamic Averaging function is enabled. The conversion time for all temperature channels is scaled based on the chosen conversion rate to maximize accuracy and immunity to random temperature measurement variation. `1' - The Dynamic Averaging function is disabled. The conversion time for all temperature channels is fixed regardless of the chosen conversion rate.
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Bit 5 - DIS_TO - Disables the SMBus timeout function. `0' (default) - The SMBus timeout function is enabled. `1' - The SMBus timeout function is disabled allowing the device to be fully I2C compliant. Bit 4 - DIS_AVG - Disables digital averaging of the External Diode channels. `0' (default) - The External Diode channels have digital averaging enabled. The temperature data is the average of the previous four measurements. `1' - The External Diode channels have digital averaging disabled. The temperature data is the last measured data. Bits 3-2 - QUEUE[1:0] - Determines the number of consecutive out of limit conditions that are necessary to trigger an interrupt. Each measurement channel has a separate fault queue associated with the high limit, low limit, and diode fault condition. APPLICATION NOTE: If the fault queue for any channel is currently active (i.e. an out of limit condition has been detected and caused the fault queue to increment) then changing the settings will not take effect until the fault queue is zeroed. This occurs by the ALERT pin asserting or the out of limit condition being removed.
Table 7.18 Fault Queue QUEUE[1:0] 1 0 0 1 1 0 0 1 0 1 NUMBER OF CONSECUTIVE OUT OF LIMIT CONDITIONS 1 (disabled) 2 3 4 (default)
Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the conversion rate and the average current will increase as the conversion rate increases.
Table 7.19 Conversion Rate CONV[1:0] 1 0 0 1 1 0 0 1 0 1 The Configuration 2 Register is software locked. CONVERSION RATE 1 / sec 2 / sec 4 / sec (default) Continuous
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7.13
Interrupt Status Register
Table 7.20 Interrupt Status Register
ADDR
R/W
REGISTER Interrupt Status Register
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
23h
R
PWM
-
TCRIT
-
FAN
HIGH
LOW
FAULT
00h
The Interrupt Status Register reports the operating condition of the EMC2113. If any of the bits are set to a logic `1' (other than TCRIT) then the ALERT pin will be asserted low if the corresponding channel is enabled. Reading from the status register clears the PWM bit. The other bits are cleared automatically when the corresponding register is read. If there are no set status bits, then the ALERT pin will be released. The bits that cause the ALERT pin to be asserted can be masked based on the channel they are associated with unless stated otherwise. Bit 7 - PWM - This bit indicates that the PWM input duty cycle (on the PWM pin) meets or exceeds the high limit. This bit is cleared when the register is read. Bit 5 - TCRIT - This bit is set to `1' if any bit in the Tcrit Status Register is set. This bit is automatically cleared when the Tcrit Status Register is read and the bits are cleared. Bit 3 - FAN - This bit is set to `1' if any bit in the Fan Status Register is set. This bit is automatically cleared when the Fan Status Register is read and the bits are cleared. Bit 2 - HIGH - This bit is set to `1' if any bit in the High Status Register is set. This bit is automatically cleared when the High Status Register is read and the bits are cleared. Bit 1- LOW - This bit is set to `1' if any bit in the Low Status Register is set. This bit is automatically cleared when the Low Status Register is read and the bits are cleared. Bit 0 - FAULT - This bit is set to `1' if any bit in the Diode Fault Register is set. This bit is automatically cleared when the Diode Fault Register is read and the bits are cleared.
7.14
Error Status Registers
Table 7.21 Error Status Register
ADDR 1Fh 24h 25h 26h
R/W R-C R-C R-C R-C
REGISTER Tcrit Status High Status Low Status Diode Fault
B7 HWS -
B6 -
B5 -
B4 -
B3 EXT3_ TCRIT EXT3_ HI EXT3_ LO EXT3_ FLT
B2 EXT2_ TCRIT EXT2_ HI EXT2_ LO EXT2_ FLT
B1 EXT1_ TCRIT EXT1_ HI EXT1_ LO EXT1_ FLT
B0 INT_ TCRIT INT_HI INT_LO -
DEFAULT 00h 00h 00h 00h
The Error Status Registers report the specific error condition for all measurement channels with limits. If any bit is set in the High, Low, or Diode Fault Status register, the corresponding High, Low, or Fault bit is set in the Interrupt Status Register.
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Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status Register that has bits set will clear the register and the corresponding bit in the Interrupt Status Register if the error condition has been removed. If the error condition is persistent, reading the Error Status Registers will have no effect.
7.14.1
Tcrit Status Register
The Tcrit Status Register stores which software enabled temperature channel has caused the SYS_SHDN pin to be asserted. Each of the temperature channels must be associated with the SYS_SHDN pin before they can be set (see Section 7.10, "Critical Temperature Limit Registers"). Once the SYS_SHDN pin is asserted, it will be released when the temperature drops below the threshold level; however, the individual status bit will not be cleared until read. Bit 7 - HWS - This bit is set if the hardware set temperature channel caused the SYS_SHDN pin to be asserted.
7.15
Fan Status Register
Table 7.22 Fan Status Register
ADDR 27h
R/W R-C
REGISTER Fan Status Register
B7 WATCH
B6 -
B5 DRIVE_ FAIL
B4 -
B3 -
B2 -
B1 FAN_ SPIN
B0 FAN_ STALL
DEFAULT 00h
The Fan Status Register contains the status bits associated with each fan driver. Bit 7 - WATCH - This bit is asserted `1' if the Watchdog timer has expired (see Section 6.10, "Watchdog Timer"). Bit 5 - DRIVE_FAIL - Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT pin. `0' - The RPM-based Fan Speed Control Algorithm can drive Fan to the desired target setting. `1' - The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target setting at maximum drive. Bit 1- FAN_SPIN - This bit is asserted `1' if the Spin up Routine for the Fan cannot detect a valid tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT pin. Bit 0 - FAN_STALL - This bit is asserted `1' if the tachometer measurement on the Fan detects a stalled fan. This bit can be masked from asserting the ALERT pin.
7.16
Interrupt Enable Register
Table 7.23 Interrupt Enable Register
ADDR
R/W
REGISTER Interrupt Enable
B7 PWM_ INT_ EN
B6
B5
B4
B3 EXT3_ INT_ EN
B2 EXT2_ INT_ EN
B1 EXT1_ INT_ EN
B0 INT_ INT_ EN
DEFAULT
28h
R/W
-
-
-
00h
The Interrupt Enable Register controls the masking for each temperature channel. When a channel is masked, it will not cause the ALERT pin to be asserted when an error condition is detected.
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Bit 7 - PWM_INT_EN - Allows the PWM input to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted if the PWM input duty cycle meets or exceeds its high limit. `1' - The ALERT pin will be asserted if the PWM input duty cycle meets or exceeds its high limit. Bit 3 - EXT3_INT_EN - Allows the External Diode 3 to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with External Diode 3 channel. `1' - The ALERT pin will be asserted for an error condition associated with External Diode 3 channel. Bit 2 - EXT2_INT_EN - Allows the External Diode 2 to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with External Diode 2 channel. `1' - The ALERT pin will be asserted for an error condition associated with External Diode 2 channel. Bit 1 - EXT1_INT_EN - Allows the External Diode 1 to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with External Diode 1 channel. `1' - The ALERT pin will be asserted for an error condition associated with External Diode 1 channel. Bit 0 - INT_INT_EN - Allows the Internal Diode to assert the ALERT pin. `0' (default) - The ALERT pin will not be asserted for any error condition associated with the Internal Diode. `1' - The ALERT pin will be asserted for an error condition associated with the Internal Diode.
7.17
Fan Interrupt Enable Register
Table 7.24 Fan Interrupt Enable Register
ADDR
R/W
REGISTER Fan Interrupt Enable
B7
B6
B5
B4
B3
B2
B1 SPIN_ INT_EN
B0 STALL_ INT_EN
DEFAULT
29h
R/W
-
-
-
-
-
-
00h
The Fan Interrupt Enable Register controls the masking for errors generated by the Fan Driver. When a channel is masked, it will not cause the ALERT pin to be asserted when an error condition is detected. Bit 1 - SPIN_INT_EN - Allows the FAN_SPIN bit to assert the ALERT pin. `0' (default) - the FAN_SPIN bit will not assert the ALERT pin though it will still update the Status Register normally. `1' - the FAN_SPIN bit will assert the ALERT pin. Bit 0 - STALL_INT_EN - Allows the FAN_STALL bit or DRIVE_FAIL bit to assert the ALERT pin. `0' (default) - the FAN_STALL bit or DRIVE_FAIL bit will not assert the ALERT pin though will still update the Status Register normally. `1' - the FAN_STALL bit will assert the ALERT pin.
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7.18
PWM Driver Configuration Register
Table 7.25 PWM Driver Configuration Register
ADDR 2Ah
R/W R/W
REGISTER PWM Driver Config
B7 -
B6 -
B5 -
B4 PWM_ OT
B3 -
B2 -
B1 -
B0 POLARITY
DEFAULT 00h
The PWM Driver Configuration Register controls the output type and polarity of the PWM fan drive output. Bit 4 - PWM_OT - Determines the output type for the PWM pin. `0' (default) - The PWM pin is configured as an open drain output. `1' - The PWM pin is configured as a push-pull output. Bit 0 - POLARITY - Determines the polarity of the PWM pin. `0' (default) - the Polarity of the PWM output driver is normal. A drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100% duty cycle. `1' - The Polarity of the PWM output driver is inverted. A drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty cycle.
7.19
PWM Driver Base Frequency Register
Table 7.26 PWM Driver Base Frequency Register
ADDR
R/W
REGISTER PWM Driver Base Frequency
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
2Bh
R/W
-
-
-
-
-
-
PWM_BASE[1:0]
00h
The PWM Driver Base Frequency Register controls base frequency of the PWM driver output. Bits 1-0 - PWM_BASE[1:0] - Determines the base frequency of the PWM output driver.
Table 7.27 PWM_BASEx[1:0] it Decode PWM_BASE[1:0] 1 0 0 1 1 0 0 1 0 1 BASE FREQUENCY 26.00kHz (default) 19.531kHz 4,882Hz 2,441Hz
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7.20
Limit Registers
Table 7.28 Limit Registers
ADDR 30h 31h 32h 34h 38h 39h 3Ah 3Ch
R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER External Diode 1 High Limit External Diode 2 High Limit External Diode 3 High Limit Internal Diode High Limit External Diode 1 Low Limit External Diode 2 Low Limit External Diode 3 Low Limit Internal Diode Low Limit
B7 Sign Sign Sign Sign Sign Sign Sign Sign
B6 64 64 64 64 64 64 64 64
B5 32 32 32 32 32 32 32 32
B4 16 16 16 16 16 16 16 16
B3 8 8 8 8 8 8 8 8
B2 4 4 4 4 4 4 4 4
B1 2 2 2 2 2 2 2 2
B0 1 1 1 1 1 1 1 1
DEFAULT 55h (+85C) 55h (+85C) 55h (+85C) 55h (+85C) 00h (0C) 00h (0C) 00h (0C) 00h (0C)
The EMC2113 contains high limits for all temperature channels. If any measurement meets or exceeds the high limit then the appropriate status bit is set and the ALERT pin is asserted (if enabled). Additionally, the EMC2113 contains low limits for all temperature channels. If the temperature channel drops below the low limit, then the appropriate status bit is set and the ALERT pin is asserted (if enabled). All Limit Registers are Software Locked.
7.21
PWM Input Duty Cycle High Limit Register
Table 7.29 PWM Duty Cycle High Limit Register
ADDR
R/W
REGISTER PWM Input Duty Cycle High Limit
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
3Dh
R/W
-
64
32
16
8
4
2
1
7Fh
The PWM Duty Cycle High Limit register stores a high limit on the Duty Cycle input on the PWM pin. The data format for the register is the same as the PWM Input Duty Cycle register (see Section 7.5, "PWM Input Duty Cycle Register") and it is compared at the sampling rate of the PWM Input duty cycle. If the PWM Input Duty Cycle meets or exceeds this limit, then the PWM status bit is set (see Section 7.13, "Interrupt Status Register") and the ALERT pin is asserted. This is treated as a temperature limit by the Fan Control circuitry.
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7.22
Fan Setting Registers
Table 7.30 Fan Driver Setting Register
ADDR 40h
R/W R/W
REGISTER Fan Setting
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 00h
The Fan Setting Register always displays the current setting of the Fan Driver. Reading from the register will report the current fan speed setting of the fan driver regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. While the RPM-based Fan Speed Control Algorithm and/or the Look Up Table are active, then the register is read only. Writing to the register will have no effect and the data will not be stored. If both the RPM-based Fan Control Algorithm and the Look Up Table are disabled, then the register will be set with the previous value that was used. The register is read / write and writing to this register will affect the fan speed. The contents of the register represent the weighting of each bit in determining the final duty cycle. The output drive for a PWM output is given by Equation [2].
VALUE Drive = -------------------- x 100% 255
[2]
7.23
PWM Divide Register
Table 7.31 PWM Divide Register
ADDR 41h
R/W R/W
REGISTER PWM Divide
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 01h
The PWM Divide Register determines the final frequency of the PWM driver. The driver base frequency is divided by the value of the PWM Divide Register to determine the final frequency. The duty cycle settings are not affected by these settings, only the final frequency of the PWM driver. A value of 00h will be decoded as 01h. The final PWM frequency is derived as the base frequency divided by the value of this register as shown in Equation [3]. PWM base freqeuncy f PWM = -------------------------------------------------------------PWM Divide Setting [3]
7.24
Fan Configuration 1 Register
Table 7.32 Fan Configuration 1 Register
ADDR 42h
R/W R/W
REGISTER Fan Configuration 1
B7 EN_ ALGO
B6
B5
B4
B3
B2
B1
B0
DEFAULT 2Bh
RANGE[1:0]
EDGES[1:0]
UPDATE[2:0]
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The Fan Configuration 1 Register controls the general operation of the RPM-based Fan Speed Control Algorithm used on the PWM pin. Bit 7 - EN_ALGO - enables the RPM-based Fan Speed Control Algorithm. Based on the setting of the RPM / PWM bit, this bit is automatically set or cleared when the LUT_LOCK bit is set (see Section 7.34, "Look Up Table Configuration Register"). `0' - (default) the control circuitry is disabled and the fan driver output is determined by the Fan Driver Setting Register. `1' - the control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register. Bits 6- 5 - RANGE[1:0] - Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH Target, and TACH reading) as shown in Table 7.33, "Range Decode".
Table 7.33 Range Decode RANGE[1:0] 1 0 0 1 1 0 0 1 0 1 REPORTED MINIMUM RPM 500 1000 (default) 2000 4000 TACH COUNT MULTIPLIER 1 2 4 8
Bits 4-3 - EDGES[1:0] - determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more accurate tachometer measurement, the minimum number of edges measured may be increased. Increasing the number of edges measured with respect to the number of poles of the fan will cause the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to accommodate this shift. The Effective Tach Multiplier shown in Table 7.34, "Minimum Edges for Fan Rotation" is used as a direct multiplier term that is applied to the Actual RPM to achieve the Reported RPM. It should only be applied if the number of edges measured does not match the number of edges expected based on the number of poles of the fan (which is fixed for any given fan). Contact SMSC for recommended settings when using fans with more or less than 2 poles.
Table 7.34 Minimum Edges for Fan Rotation EDGES[1:0] 1 0 0 1 1 0 0 1 0 1 MINIMUM TACH EDGES 3 5 7 9 NUMBER OF FAN POLES 1 pole 2 poles (default) 3 poles 4 poles EFFECTIVE TACH MULTIPLIER (BASED ON 2 POLE FANS) 0.5 1 1.5 2
Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner
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transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table 7.35.
Table 7.35 Update Time UPDATE[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 UPDATE TIME 100ms 200ms 300ms 400ms (default) 500ms 800ms 1200ms 1600ms
7.25
Fan Configuration 2 Register
Table 7.36 Fan Configuration 2 Register
ADDR 43h
R/W R/W
REGISTER Fan Configuration 2
B7 TEMP_ RR
B6 EN_ RRC
B5 GLITCH_ EN
B4
B3
B2
B1
B0 -
DEFAULT 28h
DER_OPT [1:0]
ERR_RNG:0]
The Fan Configuration 2 Register controls the tachometer measurement and advanced features of the RPM-based Fan Speed Control Algorithm. Bit 7 - TEMP_RR - Overrides max step controls for the FSC algorithm when any temperature exceeds its respective high limit. `0' (default) - All ramp rate control circuitry works at all times for the FSC algorithm or as determined by the EN_RRC bit for manual mode. `1' - If any measured temperature or the PWM Input Duty cycle meets or exceeds its respective high limit, then the Fan Max Step register settings are not used and the FSC algorithm acts as if the Max Step settings were at 3Fh. The device will continue to operate in this way until all temperatures (and the PWM input duty cycle) have dropped below the respective high limit. Bit 6 - EN_RRC - Enables ramp rate control when the fan driver is operated in the Direct Setting mode or the Direct Setting with LUT mode. `0' (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode or Direct Setting with LUT mode, the PWM setting will instantly transition to the next programmed setting. `1' - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode or Direct Setting with LUT mode, the PWM setting will follow the ramp rate controls as determined by the Fan Step and Update Time settings. The maximum PWM step is capped at the Fan Step setting and is updated based on the Update Time as given by Table 7.35.
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Bit 5 - GLITCH_EN - Disables the low pass glitch filter that removes high frequency noise injected on the TACH pin. `0' - The glitch filter is disabled. `1' (default) - The glitch filter is enabled. Bits 4 - 3 - DER_OPT[1:0] - Control some of the advanced options that affect the derivative portion of the RPM-based Fan Speed Control Algorithm as shown in Table 7.37, "Derivative Options".
Table 7.37 Derivative Options DER_OPT[1:0] 1 0 0 0 OPERATION No derivative terms used Basic derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive setting (in addition to proportional and integral terms - default) Step derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive setting and is not capped by the maximum Fan Step Register setting. Both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term.
0
1
1
0
1
1
Bit 2 - 1 - ERR_RNG[1:0] - Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on the error; however, these changes are ignored.
Table 7.38 Error Range Options ERR_RNG[1:0] 1 0 0 1 1 0 0 1 0 1 OPERATION 0 RPM (default) 50 RPM 100 RPM 200 RPM
The Fan Configuration 2 Register is Software Locked.
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7.26
Gain Register
Table 7.39 Gain Register
ADDR 45h
R/W R/W
REGISTER Gain Register
B7 -
B6 -
B5
B4
B3
B2
B1
B0
DEFAULT 2Ah
GAIND[1:0]
GAINI[1:0]
GAINP[1:0]
The Gain Register stores the gain terms used by the proportional and integral portions of the RPMbased Fan Speed Control Algorithm. These terms will affect the FSC closed loop acquisition, overshoot, and settling as would be expected in a classic PID system.
Table 7.40 Gain Decode GAIND OR GAINP OR GAINI [1:0] 1 0 0 1 1 0 0 1 0 1 RESPECTIVE GAIN FACTOR 1x 2x 4x (default) 8x
7.27
Fan Spin Up Configuration Register
Table 7.41 Fan Spin Up Configuration Register
ADDR 46h
R/W R/W
REGISTER Fan Spin Up Configuration
B7
B6
B5 NOK ICK
B4
B3
B2
B1
B0
DEFAULT 19h
DRIVE_FAIL_ CNT [1:0]
SPIN_LVL[2:0]
SPINUP_TIME [1:0]
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine. Bit 7 - 6 - DRIVE_FAIL_CNT[1:0] - Determines how many update cycles are used for the Drive Fail detection function as shown in Table 7.42, "DRIVE_FAIL_CNT[1:0] Bit Decode". This circuitry determines whether the fan can be driven to the desired tach target.
Table 7.42 DRIVE_FAIL_CNT[1:0] Bit Decode DRIVE_FAIL_CNT[1:0] 1 0 0 0 0 1 NUMBER OF UPDATE PERIODS Disabled - the Drive Fail detection circuitry is disabled (default) 16 - the Drive Fail detection circuitry will count for 16 update periods
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Table 7.42 DRIVE_FAIL_CNT[1:0] Bit Decode (continued) DRIVE_FAIL_CNT[1:0] 1 1 1 0 0 1 NUMBER OF UPDATE PERIODS 32 - the Drive Fail detection circuitry will count for 32 update periods 64 - the Drive Fail detection circuitry will count for 64 update periods
Bit 5 - NOKICK - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. `0' (default) - The Spin Up Routine will drive the PWM to 100% for 1/4 of the programmed spin up time before reverting to the programmed spin level. `1' - The Spin Up Routine will not drive the PWM to 100%. It will set the drive at the programmed spin level for the entire duration of the programmed spin up time. Bits 4 - 2 - SPIN_LVL[2:0] - Determines the final drive level that is used by the Spin Up Routine as shown in Table 7.43, "Spin Level".
Table 7.43 Spin Level SPIN_LVL[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 SPIN UP DRIVE LEVEL 30% 35% 40% 45% 50% 55% 60% (default) 65%
Bit 1 -0 - SPINUP_TIME[1:0] - determines the maximum Spin Time that the Spin Up Routine will run for (see Section 6.8, "Spin Up Routine"). If a valid tachometer measurement is not detected before the Spin Time has elapsed, then an interrupt will be generated. When the RPM-based Fan Speed Control Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. The Spin Time is set as shown in Table 7.44.
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Table 7.44 Spin Time SPINUP_TIME[1:0] 1 0 0 1 1 0 0 1 0 1 TOTAL SPIN UP TIME 250 ms 500 ms (default) 1 sec 2 sec
The Fan Spin Up Configuration Register is software locked.
7.28
Fan Step Register
Table 7.45 Fan Step Register
ADDR 47h
R/W R/W
REGISTER Fan Max Step
B7 -
B6 -
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 10h
The Fan Step Register, along with the Update Time, control the ramp rate of the fan driver response. The value of the registers represents the maximum step size each fan driver will take between update times (see Section 7.24, "Fan Configuration 1 Register"). All modes of operation have the options to use the Fan Step Register (and update times) for ramp rate control based on the Fan Configuration 2 Register settings. The Fan Speed Control Algorithm will always use the Fan Step Register settings (but see application note below). The Fan Step Register is software locked.
7.29
Fan Minimum Drive Register
Table 7.46 Minimum Fan Drive Register
ADDR 48h
R/W R/W
REGISTER Fan Minimum Drive
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 66h (40%)
The Fan Minimum Drive Register stores the minimum drive setting for the RPM-based Fan Speed Control Algorithm. This register is not used if the FSC is not active. The RPM-based Fan Speed Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target TACH Target is set at FFh. (See Section 7.32, "TACH Target Register".) During normal operation, if the fan stops for any reason (including low drive), the RPM-based Fan Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. The Fan Minimum Drive Register is software locked.
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7.30
Valid TACH Count Register
Table 7.47 Valid TACH Count Register
ADDR 49h
R/W R/W
REGISTER Valid TACH Count
B7 4096
B6 2048
B5 1024
B4 512
B3 256
B2 128
B1 64
B0 32
DEFAULT F5h
The Valid TACH Count Register store the maximum TACH Reading Register value to indicate that the the fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and decide if the device needs to retry. See Equation [5] for translating the count to an RPM. If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up Routine. APPLICATION NOTE: The automatic invoking of the Spin Up Routine only applies if the Fan Speed Control Algorithm is used. If the FSC is disabled, then the device will only invoke the Spin Up Routine when the PWM setting changes from 00h. If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. The Valid TACH Count Register is software locked.
7.31
Fan Drive Fail Band Registers
Table 7.48 Fan Drive Fail Band Registers
ADDR
R/W
REGISTER Fan Drive Fail Band Low Byte Fan Drive Fail Band High Byte
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Ah
R/W
16
8
4
2
1
-
-
-
00h
4Bh
R/W
4096
2048
1024
512
256
128
64
32
00h
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed is compared against the target fan speed. This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits then the DRIVE_FAIL status bit will be set and an interrupt generated.
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7.32
TACH Target Register
Table 7.49 TACH Target Register
ADDR
R/W
REGISTER Fan TACH Target Low Byte TACH Target
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Ch 4Dh
R/W R/W
16 4096
8 2048
4 1024
2 512
1 256
128
64
32
F8h FFh
The TACH Target Register holds the target tachometer value that is maintained by the RPM-based Fan Speed Control Algorithm. The value in the TACH Target Register will always reflect the current TACH Target value. If the Look Up Table is active and configured to operate in RPM Mode, then this register will be read only. Writing to this register will have no affect and the data will not be stored. If the algorithm is enabled then setting the TACH Target Register to FFh will disable the fan driver (set the PWM duty cycle to 0%). Setting the TACH Target to any other value (from a setting of FFh) will cause the algorithm to invoke the Spin Up Routine after which it will function normally.
7.33
TACH Reading Register
Table 7.50 TACH Reading Register
ADDR 4Eh 4Fh
R/W R R
REGISTER Fan TACH Fan TACH Low Byte
B7 4096 16
B6 2048 8
B5 1024 4
B4 512 2
B3 256 1
B2 128 -
B1 64 -
B0 32 -
DEFAULT FFh F8h
The TACH Reading Register contents describe the current tachometer reading for the fan. By default, the data represents the fan speed as the number of 32kHz clock periods that occur for a single revolution of the fan. Equation [4] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation [5] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768kHz. These equations are solved and tabulated for ease of use in AN17.4 RPM to TACH Counts Conversion.
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where: 1(n - 1) RPM = ------------------- x --------------------------------- x 1,966,080 ( poles ) 1COUNT x ---m poles = number of poles of the fan (typically 2) n = number of edges measured (typically 5) m = the multiplier defined by the RANGE bits [5] COUNT = TACH Reading Register value (in decimal) [4]
3,932,160 x m RPM = ------------------------------------COUNT
7.34
Look Up Table Configuration Register
Table 7.51 Look Up Table Configuration Register
ADDR 50h
R/W R/W
REGISTER LUT Configuration
B7 USE_ DTS_P1
B6 USE_ DTS_P2
B5 LUT LOCK
B4 RPM / PWM
B3 PUSH1_ CFG
B2 TEMP1_ CFG
B1 TEMP3_ CFG
B0 TEMP4_ CFG
DEFAULT 00h
7Dh
The Look Up Table Configuration Register controls the setup information for the temperature to fan drive look up table. APPLICATION NOTE: This register is duplicated at 50h as well as 7Dh for ease of programming using block write mode. Example: Set register 50h to unlock the table and register 7Dh to lock the table. The External Diode 2 channel is always used as the Temperature 2 input to the Fan Control Look Up Table. Bit 7 - USE_DTS_P1 - This bit determines whether the Pushed Temperature 1 Register is using DTS data. `0' (default) - The Pushed Temperature 1 Register is not using DTS data. The contents of the Pushed Temperature 1 registers are standard temperature data. `1' - The Pushed Temperature 1 Register is loaded with DTS data. The contents of this register are automatically subtracted from a fixed value of 100C before being compared to the Look Up Table threshold levels. Bit 6 - USE_DTS_P2 - This bit determines whether the Pushed Temperature 2 Register is using DTS data. `0' (default) - The Pushed Temperature 2 Register is not using DTS data. The contents of this register are standard 2's complement temperature data. `1' - The Pushed Temperature 2 Register is loaded with DTS data. The contents of this register are automatically subtracted from a fixed value of 100C before being compared to the Look Up Table threshold levels. Bit 5 - LUT_LOCK - This bit locks updating the Look Up Table entries and determines whether the look up table is being used. `0' (default) - The Look Up Table entries can be updated normally. The Look Up Table will not be used while the Look Up Table entries are unlocked. During this condition, the PWM output will not change states regardless of temperature or tachometer variation.
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`1' - The Look Up Table entries are locked and cannot be updated. The Look Up Table is fully active and will be used based on the loaded values. The PWM output will be updated depending on the temperature and / or TACH variations. APPLICATION NOTE: When the LUT_LOCK bit is set at a logic `0', the PWM drive setting will be set at whatever value was last used by the RPM-based Fan Speed Control Algorithm or the Look Up Table. Bit 4 - RPM / PWM - This bit selects the data format for the LUT drive settings. `0' (default) - The Look Up Table drive settings are RPM TACH count values for use by the RPMbased Fan Speed Control Algorithm. The Look Up Table drive settings should be loaded highest value to lowest value (to coincide with the inversion between TACH counts and actual RPM). `1' - The Look Up Table drive settings are PWM duty cycle values and are used directly. The drive settings should be loaded lowest value to highest value. Bit 3 - PUSH1_CFG - Determines whether the PWM Input duty cycle is used instead of the Pushed 1 Temperature data when the TEMP1_CFG bit is set. `0' (default) - The Pushed Temperature 1 register can be written via the SMBus and will hold a temperature value. The PWM Input Duty cycle is not used. `1' - If the TEMP1_CFG or TEMP3_CFG bit is set, the PWM Input Duty cycle will be used. The Pushed Temperature 1 register can be written via the SMBus and will hold a temperature value but will not be used. APPLICATION NOTE: If the Pushed Temperature 1 data is configured to hold the PWM input duty cycle and is used in the Look Up Table, then the Look Up Table threshold levels must be programmed in the same format as the PWM input duty cycle - see Section 7.5 and Section 7.35. Bit 2 - TEMP1_CFG - Determine the temperature channel that is used for the Temperature 1 inputs to the Look Up Table. `0' (default) - The External Diode 1 channel is used by the Fan Look Up Table. `1' - Either the data written into the Pushed Temperature 1 Register or the data in the PWM Input Duty Cycle register is used by the Fan Look Up table as determined by the PUSH1_CFG bit. Bit 1 - TEMP3_CFG - Determine the temperature channel that is used for the Temperature 3 inputs to the Look Up Table. `0' (default) - The External Diode 3 channel is used by the Fan Look Up Table (if enabled). `1' - Either the data written into the Pushed Temperature 1 Register or the data in the PWM Input Duty Cycle register is used by the Fan Look Up table as determined by the PUSH1_CFG bit. Bit 0 - TEMP4_CFG - Determine the temperature channel that is used for the Temperature 4 inputs to the Look Up Table. `0' (default) -The Internal diode channel is used by the Fan Look Up Table. `1' - The data written into the Pushed Temperature 2 Register is used by the Fan Look Up Table.
7.35
Look Up Table Registers
Table 7.52 Look Up Table Registers RPM / PWM `0' `1'
ADDR 51h
R/W R/W
REGISTER LUT Drive Setting 1
B7 4096 128
B6 2048 64
B5 1024 32
B4 512 16
B3 256 8
B2 128 4
B1 64 2
B0 32
DEFAULT FBh
1
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Table 7.52 Look Up Table Registers (continued) RPM / PWM X X X X ... `0' `1' X X X X X X X X
ADDR 52h 53h 54h 55h ... 74h
R/W R/W R/W R/W R/W ... R/W
REGISTER LUT Temp 1 Setting 1 LUT Temp 2 Setting 1 LUT Temp 3 Setting 1 LUT Temp 4 Setting 1 ... LUT Drive Setting 8 LUT Temp 1Setting 8 LUT Temp 2 Setting 8 LUT Temp 3 Setting 8 LUT Temp 4 Setting 8 LUT Temp 1 Hysteresis LUT Temp 2 Hysteresis LUT Temp 3 Hysteresis LUT Temp 4 Hysteresis
B7 ... 4096 128 -
B6 64 64 64 64 ... 2048 64 64 64 64 64 -
B5 32 32 32 32 ... 1024 32 32 32 32 32 -
B4 16 16 16 16 ... 512 16 16 16 16 16 16 16 16 16
B3 8 8 8 8 ... 256 8 8 8 8 8 8 8 8 8
B2 4 4 4 4 ... 128 4 4 4 4 4 4 4 4 4
B1 2 2 2 2 ... 64 2 2 2 2 2 2 2 2 2
B0 1 1 1 1 ... 32
DEFAULT 7Fh (127C) 7Fh (127C) 7Fh (127C) 7Fh (127C) ... 92h
1 1 1 1 1 1 1 1 1 7Fh (127C) 7Fh (127C) 7Fh (127C) 7Fh (127C) 0Ah (10C) 0Ah (10C) 0Ah (10C) 0Ah (10C)
75h 76h 77h 78h 79h 7Ah 7Bh 7Ch
R/W R/W R/W R/W R/W R/W R/W R/W
The Look Up Table Registers hold the 40 entries of the Look Up Table that control the drive of the PWM. As the temperature channels are updated, the measured value for each channel is compared against the respective entries in the Look Up Table and the associated drive setting is loaded into an internal shadow register and stored. The bit weighting for temperature inputs represents C and is compared against the measured data. Note that the LUT entry does not include a sign bit. The Look Up Table does not support negative temperature values and the MSBit should not be set for a temperature input. APPLICATION NOTE: When the PWM Input Duty cycle values are used, then the bit weighting represents a unitless threshold that does not corresponded to specific temperature values. It is used to drive the fan speed based on external temperatures known to a separate microcontroller driving the PWM_IN pin. Each temperature channel threshold for a single "column" shares the same hysteresis value; however, each temperature input has a different hysteresis value. When the measured temperature for any of the channels meets or exceeds the programmed threshold, the drive setting associated with that threshold is used. The temperature must drop below the threshold minus the hysteresis value before the drive setting will be set to the previous value.
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If the RPM-based Fan Speed Control Algorithm is used, the TACH Target is updated after every conversion. It is always set to the minimum TACH Target that is stored by the Look Up Table. The PWM duty cycle is updated based on the RPM-based Fan Speed Control Algorithm configuration settings. If the RPM-based Fan Speed Control Algorithm is not used, then the output PWM duty cycle is updated after every conversion. It is set to the maximum duty cycle that is stored by the Look Up Table. If the measured temperature reading on all channels is less than the lowest threshold setting minus the appropriate hysteresis setting, then the Fan driver will be set to 0% duty cycle and the fan will be disabled.
7.36
Software Lock Register
Table 7.53 Software Lock
ADDR EFh
R/W R/W
REGISTER Software Lock
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 -
B0 LOCK
DEFAULT 00h
The Software Lock Register controls the software locking of critical registers. This register is software locked. Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked registers become read only and cannot be updated. `0' (default) - all SWL registers can be updated normally. `1' - all SWL registers cannot be updated and a hard-reset is required to unlock them.
7.37
Product Features Register
Table 7.54 Product Features Register
ADDR FCh
R/W R
REGISTER Product Features
B7 -
B6 -
B5
B4
B3
B2
B1
B0
DEFAULT 00h
ADDR_SEL[2:0]
SHDN_SEL[2:0]
The Product Features Register indicates which pin selected functionality is enabled. Bits 5-3 - ADDR_SEL[2:0] - Indicates the address that is decoded by the ADDR_SEL pin as shown in Table 7.55, "ADDR_SEL[2:0] Encoding".
Table 7.55 ADDR_SEL[2:0] Encoding ADDR_SEL[2:0] 2 0 0 0
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1 0 0 1
70
0 0 1 0
SMBUS ADDRESS 0101_100(r/w) 0101_101(r/w) 0101_110(r/w)
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Table 7.55 ADDR_SEL[2:0] Encoding (continued) ADDR_SEL[2:0] 2 0 1 1 1 1 0 0 0 1 0 1 SMBUS ADDRESS 1001_100(r/w) 1001_101(r/w) 1001_000(r/w)
Bits 2-0 - SHDN_SEL[2:0] - Indicate the functionality enabled by the SHDN_SEL pin as shown in Table 7.56, "SHDN_SEL[2:0] Encoding".
Table 7.56 SHDN_SEL[2:0] Encoding SHDN_SEL[2:0] 2 0 1 0 0 0 DIODE MODE External Diode 1 Simple Mode - Beta compensation disabled, REC disabled recommended for AMD CPU diodes External Diode 1 Diode Mode - Beta compensation disabled, REC enabled External Diode 1 Transistor Mode - Beta compensation enabled, REC enabled - recommended for Intel 45nm and 65mn CPU diodes Internal Diode Transistor Mode - Beta compensation enabled, REC enabled External Diode 2 Transistor Mode - Beta compensation enabled, REC enabled External Diode 1 Transistor Mode - Beta compensation enabled, REC enabled none OTHER FEATURES
0 0
0 1
1 0
none none
0 1 1
1 0 0
1 0 1
none none none
7.38
Product ID Register
Table 7.57 Product ID Register
ADDR FDh
R/W R
REGISTER Product ID Register
B7 0
B6 0
B5 1
B4 0
B3 0
B2 1
B1 0
B0 0
DEFAULT 2Eh
The Product ID Register contains a unique 8-bit word that identifies the product.
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7.39
Manufacturer ID Register
Table 7.58 Manufacturer ID Register
ADDR FEh
R/W R
REGISTER Manufacturer ID
B7 0
B6 1
B5 0
B4 1
B3 1
B2 1
B1 0
B0 1
DEFAULT 5Dh
The Manufacturer ID Register contains an 8-bit word that identifies SMSC.
7.40
Revision Register
Table 7.59 Revision Register
ADDR FFh
R/W R
REGISTER Revision
B7 1
B6 0
B5 0
B4 0
B3 0
B2 0
B1 0
B0 1
DEFAULT 81h
The Revision Register contains an 8-bit word that identifies the die revision.
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Chapter 8 Typical Operating Curves
The following Typical Operating Curves are included: Supply Current vs. Temperature Supply Current vs. Supply Voltage Temperature Error vs. Series Resistance Temperature Error vs. Ambient Temperature Temperature Error vs. Supply Voltage Fan TACH Accuracy vs. Temperature Fan TACH Accuracy vs. Supply Voltage PWM Output Frequency vs. Supply Voltage PWM Output Frequency vs. Temperature FSC Operation Look Up Table operation - PWM / Direct Drive
Supply Current vs. Temperature VDD = 3.3V
1400 1200
Supply Current (uA)
4/ sec w/ dynamic averaging
1400 1200 1000
Supply Current (uA)
Supply Current vs. Supply Voltage TA = 25C
4 / sec w/ Dynamic Averaging
1000 800 600 400 200 0 -50
1/ sec w/o dynamic averaging
800 600 400 200 0 2.95
1 / sec w/o Dynamic Averaging
3.05
3.15
3.25
3.35
3.45
3.55
3.65
0 50 Ambient Temperature (C)
100
150
Supply Voltage (V)
Temperature Measurement Accuracy vs. Series Resistance
1
Temperature Error (C) - REC Enabled
100 90
REC Disabled
Temperature Measurement Error vs. Ambient Temperature
Temperature Error (C) - REC Disabled
0.5 0.4 0.3
Temperature Error (C)
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 40 80 120
Series Resistance (ohm)
REC Enabled
80 70 60 50 40 30 20 10 0 160
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -50 0 50
Ambient Temperature (C)
100
150
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Temperature Measurement Error vs. Supply Voltage
0.5
Tachometer Accuracy (%)
Tachometer Measurement Accuracy vs. Temperature
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
0.4 0.3
Temperature Error (C)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
-0.5 -50
0
50
Ambient Temperature (C)
100
150
Supply voltage (V)
PWM Output Drive Frequency Variation vs. Ambient Temperature
1.4
Base = 26kHz, Divide = 0
Tachometer Measurement Accuracy vs. Supply Voltage
0.5 0.4
Tachometer Accuracy (%)
Normalized Drive Frequency
1.2 1 0.8 0.6 0.4 0.2 0 -50
Base = 2441Hz, Divide = 128 = 19Hz
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.95
0
50
100
150
3.05
Ambient Temperature (C)
3.15 3.25 3.35 Supply Voltage (V)
3.45
3.55
3.65
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1.4 1.2
Normalized Drive Frequency
PWM Output Drive Frequency Variation vs. Supply Voltage
FSC Algorithm PWM Ramping
Update Time = 200ms; Max Step = 16 PWM counts RPM Target from 0 RPM -> 8000 RPM @ time t = 0
Base = 2441Hz, Divide = 128 = 19Hz
1 0.8 0.6 0.4 0.2 0 2.95
Base = 26kHz, Divide = 0
PWM Output
10x Zoom on PWM Output
3.05
3.15
3.25
3.35
3.45
3.55
3.65
Supply Voltage (V)
Spin Up Routine Ends - begins normal operation Update Time ends, PWM duty cycle changed
Update Time ends, PWM duty cycle changed Duty Cycle Measured
FSC Algorithm Spin Up Routine
Spin Time = 1.0s; Spin Level = 55%; Updated Time = 200ms; RPM Target from 0 RPM -> 8000 RPM @ time t = 0
FSC Algorithm Spin Up Routine - NoKick
Spin Time = 1.0s; Spin Level = 50%; UpdateTime = 200ms; RPM Target from 0 RPM -> 8000 RPM @ time t = 0
PWM Output
PWM Output
10x Zoom on PWM Output
10x Zoom on PWM Output
t=0
Duty Cycle Measured = 53.8%
t=0
Duty Cycle Measured = 50%
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Look Up Table Operation
PWM_IN
PWM Drive
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LUT Programmed: PUSH_CFG = `1', TEMP1_CFG = `1'; Temp 1 Threshold 1 = 50%; Temp 2 - 4 Threshold 1 = FFh; Setting 1 = 0% Temp 1 Threshold 2 = 55%; Temp 2 - 4 Threshold 2 = FFh; Setting 2 = 30% Temp 1 Threshold 3 = 65%; Temp 3 - 4 Threshold 3 = FFh; Setting 3 = 70% Temp 1 Threshold 4 = 75%; Temp 3 - 4 Threshold 4 = FFh; Setting 4 = 95% Hysteresis = 5
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Chapter 9 Package Drawing
9.1 EMC2113 Package Information
Figure 9.1 16-Pin QFN 4mm x 4mm Package Dimensions
Figure 9.2 16-Pin QFN 4mm x 4mm PCB Footprint
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Figure 9.3 16-Pin QFN 4mm x 4mm Package Drawing
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
9.2
Package Markings
TOP
0.41 LINE: 1 - SMSC Logo without circled (R) symbol LINE: 2 - Device Number LINE: 3 - Last 7 digits of Lot Number LINE: 4 - Revision and Country Code (RCC) 2113 -1 123456a RCC e3
PIN 1
3x 0.56
PB-FREE/GREEN SYMBOL (Matte Sn) LINES 1 to 3: CENTER HORIZONTAL ALIGNMENT LINE 4: LEFT HORIZONTAL ALIGNMENT
BOTTOM BOTTOM MARKING NOT ALLOWED
Figure 9.4 EMC2113 Package Markings
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Appendix A Look Up Table Operation
The EMC2113 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to the fan driver. In this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. The user programs the look-up table based on the desired operation. If the RPM-based Fan Speed Control Algorithm is to be used (see Section 6.6), then the user must program an RPM target for each temperature setting of interest. Alternately, if the RPM-based Fan Speed Control Algorithm is not to be used, then the user must program a drive setting for each temperature setting of interest. If the measured temperature on the External Diode channel meets or exceeds any of the temperature thresholds for any of the channels, the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds are exceeded, the highest fan drive setting will take precedence. When the measured temperature drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to the corresponding lower set point. The following sections show examples of how the Look Up Table is used and configured. Each Look Up Table Example uses the Fan 1 Look Up Table Registers configured as shown in Table A.1.
Table A.1 Look Up Table Format STEP 1 2 3 4 5 6 7 8 TEMP 1 LUT Temp 1 Setting 1 (52h) LUT Temp 1 Setting 2 (57h) LUT Temp 1 Setting 3 (5Ch) LUT Temp 1 Setting 4 (61h) LUT Temp 1 Setting 5 (66h) LUT Temp 1 Setting 6 (6Bh) LUT Temp 1 Setting 7 (70h) LUT Temp 1 Setting 8 (75h) TEMP 2 LUT Temp 2 Setting 1 (53h) LUT Temp 2 Setting 2 (58h) LUT Temp 2 Setting 3 (5Dh) LUT Temp 2 Setting 4 (62h) LUT Temp 2 Setting 5 (67h) LUT Temp 2 Setting 6 (6Ch) LUT Temp 2 Setting 7 (71h) LUT Temp 2 Setting 8 (76h) TEMP 3 LUT Temp 3 Setting 1 (54h) LUT Temp 3 Setting 2 (59h) LUT Temp 3 Setting 3 (5Eh) LUT Temp 3 Setting 4 (63h) LUT Temp 3 Setting 5 (68h) LUT Temp 3 Setting 6 (6Dh) LUT Temp 3 Setting 7 (72h) LUT Temp 3 Setting 8 (77h) TEMP 4 LUT Temp 4 Setting 1 (55h) LUT Temp 4 Setting 2 (5Ah) LUT Temp 4 Setting 3 (5Fh) LUT Temp 4 Setting 4 (64h) LUT Temp 4 Setting 5 (69h) LUT Temp 4 Setting 6 (6Eh) LUT Temp 4 Setting 7 (73h) LUT Temp 4 Setting 8 (78h) LUT DRIVE LUT Drive Setting 1 (51h) LUT Drive Setting 2 (56h) LUT Drive Setting 3 (5Bh) LUT Drive Setting 4 (60h) LUT Drive Setting 5 (65h) LUT Drive Setting 6 (6Ah) LUT Drive Setting 7 (6Fh) LUT Drive Setting 8 (74h)
A.1
Example #1
This example does not use the RPM-based Fan Speed Control Algorithm. Instead, the Look Up Table is configured to directly set a PWM setting based on the temperature of four of its measured inputs. The configuration is set as shown in Table A.2, "Look Up Table Example #1 Configuration". Once configured, the Look Up Table is loaded as shown in Section Table A.3, "Fan Speed Control Table Example #1". Table A.4 shows three temperature configurations using the settings in Table A.3 and the final PWM output drive setting that the Look Up Table will select.
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Table A.2 Look Up Table Example #1 Configuration ADDR REGISTER LUT Configuration B7 USE_ DTS_F1 0 B6 USE_ DTS_F2 0 B5 LUT_ LOCK 1 B4 RPM / PWM 1 B3 PUSH1_ CFG 0 B2 TEMP1_ CFG 0 B1 TEMP3_ CFG 0 B0 TEMP4_ CFG 0 SETTING
50h
C0h
A.1.1
LUT Configuration Bit Description
Bit 7 - USE_DTS_F1 = `0b' tells the circuitry that the Forced Temperature 1 register data is not in DTS format. Bit 6 - USE_DTS_F2 = `0b' tells the circuitry that the Forced Temperature 2 register data is not in DTS format. Bit 5 - LUT_LOCK = `1b' tells the circuitry that the LUT is programmed and is active. This bit must be set for the LUT to function. Bit 4 - RPM / PWM = `1b' tells the Look Up Table that the FSC algorithm is not used and that the LUT target values will be PWM drive settings instead of TACH Target settings. Bit 3 - PUSH1_CFG = `0b' tells the circuitry that the LUT should referenced the Forced Temperature data instead of the PWM Input Duty Cycle data. This is the default setting. Bit 2 - TEMP1_CFG = `0b' tells the LUT to reference the External Diode 1 data instead of Forced Temperature 1 data. This is the default setting. Bit 1 - TEMP3_CFG = `0b' tells the LUT to reference the External Diode 3 data instead of Forced Temperature 1 data. This is the default setting. Bit 0 - TEMP4_CFG = `0b' tells the LUT to reference the Internal Diode data instead of Forced Temperature 2 data. This is the default setting.
Table A.3 Fan Speed Control Table Example #1 EXTERNAL DIODE 2 TEMPERATURE (GPU) 60oC 70oC 75oC 80oC 85oC 90oC 95oC 100oC
FAN SPEED STEP # 1 2 3 4 5 6 7 8
EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40oC 50oC 60oC 70oC 80oC 90oC 100oC
EXTERNAL DIODE 3 TEMPERATURE (SKIN) 30oC 35oC 40oC 45oC 50oC 55oC 60oC 65oC
INTERNAL DIODE TEMPERATURE (AMBIENT) 40oC 45oC 50oC 55oC 60oC 65oC 70oC 75oC
PWM SETTINGS 0% 30% 40% 50% 60% 70% 80% 100%
Note: The values shown in Table A.3 are example settings. All the cells in the look-up table are programmable via SMBus.
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Table A.4 Fan Speed Determination for Example #1 (using settings in Table A.3)
EXTERNAL DIODE 1 TEMPERATURE (CPU) EXTERNAL DIODE 2 TEMPERATURE (GPU) EXTERNAL DIODE 3 TEMPERATURE (SKIN)
INTERNAL DIODE TEMPERATURE (AMBIENT)
PWM RESULT
Example 1: Example 2: Example 3:
82C
82C 82C
82C
48C
58C 58C
70% (CPU temp requires highest drive) 80% (GPU and Skin require highest drive) 100% (Internal temp requires highest drive)
97C
97C
62C
62C
75C
A.2
Example #2
This example uses the RPM-based Fan Speed Control Algorithm. The Spin Level (used by the Spin Up Routine) should be changed to 40% drive for a total Spin Time of 1 second. For all other RPM configuration settings, the default conditions are used. For control inputs, it uses the External Diode 1 channel normally, the External Diode 2 channel normally, and both Pushed Temperature registers in DTS format. The configuration is set as shown in Table A.5, "Look Up Table Example #2 Configuration" while Table A.6, "Fan Speed Control Table Example #2" shows how the table is loaded. Note that when using DTS data, the USE_DTS_F1 and / or USE_DTS_F2 bits should be set. The Pushed Temperature Registers are loaded with the normal DTS values as received by the processor. When the DTS value is used by the Look Up Table, the value that is stored in the Pushed Temperature Register is subtracted from a fixed temperature of 100C. This resultant value is then compared against the Look Up Table thresholds normally. When programming the Look Up Table, it is necessary to take this translation into account or else incorrect settings may be selected.
Table A.5 Look Up Table Example #2 Configuration ADDR REGISTER Fan Spin Up Configuration B7 B6 B5 NOKICK 0 LUT_ LOCK 1 0 RPM / PWM 0 B4 B3 SPIN_LVL[2:0] 1 PUSH1_ CFG 0 0 TEMP1_ CFG 0 B2 B1 B0 SETTING
46h
DRIVE_FAIL_CNT [1:0] 0 0 USE_ DTS_F2 1
SPINUP_TIME [1:0] 0Ah 1 TEMP3_ CFG 1 0 TEMP4_ CFG 1
50h
LUT Configuration
USE_ DTS_F1 1
E5h
A.2.1
Fan Spin Up Configuration Bit Description
Bits 7-6 - DRIVE_FAIL_CNT[1:0] = `00b' tells the circuitry that the drive fail detection circuitry is not enabled. This is the default setting. Bit 5 - NOKICK = `0b' tells the circuitry that if than Spin Up Routine is invoked, it will drive to 100% duty cycle for 25% of the spin up time. This is the default setting. Bits 4-2 - SPIN_LVL[2:0] = `010b' tells the circuitry that if the Spin Up Routine is invoked, it should run at 40% drive.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Bits 1-0 - SPINUP_TIME[1:0] = `10b' tells the circuitry that if the Spin Up Routine is invoked, it will run at 100% duty cycle for 250ms and at 40% duty cycle for 750ms for a total spin up time of 1s.
A.2.2
LUT Configuration - Bit Description
7 - USE_DTS_F1 = `1b' tells the circuitry that the data in the Pushed Temperature 1 register is in DTS format which means that the value in the register is equal to 100C - CPU Temp. Bit 6 - USE_DTS_F2 = `1b' tells the circuitry that the data in the Pushed Temperature 1 register is in DTS format which means that the value in the register is equal to 100C - CPU temp. Bit 5 - LUT_LOCK = `1b' tells the circuitry that the LUT is programmed and is active. This bit must be set for the LUT to function. Bit 4 - RPM_PWM = `0b' tells the LUT circuitry that the FSC algorithm is active and that the LUT values are TACH Target settings. This is the default setting. Bit 3 - PUSH1_CFG = `0b' tells the circuitry that the LUT should referenced the Forced Temperature data instead of the PWM Input Duty Cycle data. This is the default setting. Bit 2 - TEMP1_CFG = `0b' tells the LUT to reference the External Diode 1 data instead of Forced Temperature 1 data. Bit 1 - TEMP3_CFG = `1'b tells the Look Up Table to reference the Forced Temperature 1 data instead of the External Diode 3 data. Bit 0- TEMP4_CFG = `1b' tells the Look Up Table to reference the Forced Temperature 2 data instead of the Internal Diode data.
Table A.6 Fan Speed Control Table Example #2 EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40oC 50oC 60oC 70oC 80oC 90oC 100oC EXTERNAL DIODE 2 TEMPERATURE (GPU) 65oC 75oC 85oC 90oC 95oC 100oC 105oC 110oC
FAN SPEED STEP # 1 2 3 4 5 6 7 8
PUSHED TEMPERATURE SETTING (DTS1) 50oC 55oC 60oC 65oC 70oC 75oC 80oC 85oC
PUSHED TEMPERATURE SETTING (DTS2) 40oC 45oC 50oC 55oC 60oC 65oC 80oC 100oC
TACH TARGET HIGH BYTE EFh (1028 RPM) A3h (1508 RPM) 7Ah (2014 RPM) 62h (2508 RPM) 52h (2997 RPM) 3Dh (4029 RPM) 31h (5016 RPM) 29h (5994 RPM)
Note: The values shown in Table A.6 are example settings. All the cells in the look-up table are programmable via SMBus.
SMSC EMC2113
83
Revision 1.2 (10-08-09)
DATASHEET
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table A.7 Fan Speed Determination for Example #2 (using settings in Table A.6) EXTERNAL DIODE 1 TEMPERATURE (CPU) EXTERNAL DIODE 2 TEMPERATURE (GPU)
PUSHED TEMPERATURE (DTS1) 35C (translated as 65C)
PUSHED TEMPERATURE (DTS2) 50C (translated as 50C) 20C (translated as 80C)
PWM RESULT 52h (2997 RPM) CPU requires highest target 29h (5994 RPM) DTS1 requires highest target 31h (5016 RPM) DTS2 requires highest target
Example 1:
75C
75C
Example 2:
75C
90C
15C (translated as 85C)
30C (translated as 70C)
Example 3:
75C
97.25C
5C (translated as 95C)
A.3
Example #3
This example uses the RPM-based Fan Speed Control Algorithm with default settings. For control inputs, it uses the External Diode 1 channel normally, the External Diode 2 channel normally, the PWM input instead of External Diode 3, and the Internal Diode. The configuration is set as shown in Table A.8 while Table A.9 shows how the table is loaded.
Table A.8 Look Up Table Example #3 Configuration ADDR REGISTER LUT Configuration B7 USE_ DTS_F1 0 B6 USE_ DTS_F2 0 B5 LUT_ LOCK 1 B4 RPM / PWM 0 B3 PUSH1_ CFG 1 B2 TEMP1_ CFG 0 B1 TEMP3_ CFG 1 B0 TEMP4_ CFG 0 SETTING
90h
2Ah
A.3.1
LUT COnfiguration Bit Description
Bit 7 - USE_DTS_F1 = `0b' tells the circuitry that the Forced Temperature 1 register data is not in DTS format. Bit 6 - USE_DTS_F2 = `0b' tells the circuitry that the Forced Temperature 2 register data is not in DTS format. Bit 5 - LUT_LOCK = `1b' tells the circuitry that the LUT is programmed and is active. This bit must be set for the LUT to function. Bit 4 - RPM_PWM = `0b' tells the LUT circuitry that the FSC algorithm is active and that the LUT values are TACH Target settings. This is the default setting. Bit 3 - PUSH1_CFG = `1b' tells the Look Up Table to reference the PWM Input Duty Cycle instead of the Pushed Temperature 1 register. Bit 2 - TEMP1_CFG = `0b' tells the LUT to reference the External Diode 1 data instead of Forced Temperature 1 data. This is the default setting.
Revision 1.2 (10-08-09)
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Bit 1 - TEMP3_CFG = `1b' tells the Look Up Table to reference Pushed Temperature 1 instead of External Diode 3, except that PUSH1_CFG re-directs the logic to reference the PWM Input Duty Cycle register instead. Bit 0 - TEMP4_CFG = `0b' tells the LUT to reference the Internal Diode data instead of Forced Temperature 2 data. This is the default setting.
Table A.9 Fan Speed Control Table Example #3 EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40oC 50oC 60oC 70oC 80oC 90oC 100oC EXTERNAL DIODE 2 TEMPERATURE (GPU) 65oC 75oC 85oC 90oC 95oC 100oC 105oC 110oC
FAN SPEED STEP # 1 2 3 4 5 6 7 8
PWM DUTY CYCLE 20% Duty Cycle (1Ah) 30% Duty Cycle (26h) 40% Duty Cycle (33h) 50% Duty Cycle (40h) 60% Duty Cycle (4Dh) 70% Duty Cycle (5Ah) 80% Duty Cycle (66h) 90% Duty Cycle (73h)
INTERNAL DIODE 40oC 45oC 50oC 55oC 60oC 65oC 80oC 100oC
TACH TARGET EFh (1028 RPM) A3h (1508 RPM) 7Ah (2014 RPM) 62h (2508 RPM) 52h (2997 RPM) 3Dh (4029 RPM) 31h (5016 RPM) 29h (5994 RPM)
Note: The values shown in Table A.9 are example settings. All the cells in the look-up table are programmable via SMBus.
Table A.10 Fan Speed Determination for Example #2 (using settings in Table A.9) EXTERNAL DIODE 1 TEMPERATURE (CPU) EXTERNAL DIODE 2 TEMPERATURE (GPU)
PWM INPUT DUTY CYCLE
INTERNAL DIODE
PWM RESULT 52h (2997 RPM) CPU requires highest target 31h (5016 RPM) PWM requires highest target 31h (5016 RPM) DTS2 requires highest target
Example 1:
75C
75C
45% Duty Cycle
50C
Example 2:
75C
90C
85% Duty Cycle
70C
Example 3:
75C
97.25C
75% Duty Cycle
95C
SMSC EMC2113
85
Revision 1.2 (10-08-09)
DATASHEET

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