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XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
MARCH 2008 REV. 1.0.0
GENERAL DESCRIPTION
The XR18W753 is a low-power, single-chip RF transceiver designed to operate in license-free European 868 MHz SRD, North American / Australian 915 MHz ISM bands. Digital I/Q modulation, demodulation and direct sequence spread spectrum techniques were employed to provide robust data transmission in signal congested RF environments. The device provides extensive hardware support for packet handling such as frame timing, data buffering, RSSI/ED/LQI for clear channel assessment, and FCS and CRC hardware for error detection. TX output power is programmable from -24 dBm to 0 dBm with 100 Kbps and 250 Kbps O-QPSK data supported. APPLICATIONS
FEATURES
* 2.2 to 3.6 Volt Operation * 868 MHz to 956 MHz * Direct-Sequence-Spread-Spectrum Transceiver * Direct-up-conversion I/Q modulator * Low-IF I/Q digital receiver * Superior blocking/desensitization performance * RSSI / ED / LQI for clear channel assessment * FCS computation and CRC for error detection * Low BOM cost and ease of production * I2C Interface to data buffer and internal registers * Fully integrated loop filter with few external
components needed (crystal, capacitors, antenna and matching networks)
* Industrial/Home automation, monitoring and control * Point of sales and data collection terminals * Entertainment, game, toy, robot, and remote control * Active RFID, asset tracking and keyless entry * Lighting, HVAC energy management * Automatic meter reading * Wireless sensor and telemetry networks
FIGURE 1. RF TRANSCEIVER BLOCK DIAGRAM
* Programmable TX output power in 3 dB steps * Receiver sensitivity of -94 dBm at 100 Kbps * Supports O-QPSK 100 Kbps and 250 Kbps data * Industrial temperature (-40 to +85 oC) * 48-pin QFN package
1Mz 6H XA TL
VE_L_N R GCK E
1Mz 6H CK L
T X DT AA B FE UF R
CO K LC GNRT N E E A IO
V lta e og R g la r e u to
CC R P L M E cae_ ay c _ d re d p k_ _ a y c tx re d p k_ c iv d c re e e p e re d lm _ a y
SL C SA D
D ita ig l Md m oe
R F
M tc in ahg N tw rk eo
DT AA ACS CES C NR LE O T OL R
R X DT AA B FE UF R
Md m oe C n lle o tro r
M d mC n l &S tu o e o tro ta s
IR # Q
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER FIGURE 2. RF SYSTEM ARCHITECTURE
REV. 1.0.0
ADC I/Q DIV IF Filter 1st Stage IF Filter 2nd Stage
7
LNA
DIGITAL MODEM
ADC 7
AGC
RF
LO
SYNTH
Digital Backend
ADC
6
PA
I/Q DIV
ADC
6
DET PA Gain
2
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
FIGURE 3. PIN DIAGRAM
AGND 1 AVDD19 2 AGND 3 AVDD19 4 RFCM1 5 RFIN+ 6 RFIN- 7 RFCM2 8 AVDD19 9 AGND 10 AVDD19 11 AGND 12
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
AVDD19 AVDD19 AVDD19 AVDD_OUT AVDD DVDD DVDD_OUT AGND XTAL1 XTAL2 AVDD19 VREG_CLK_EN
XR18W753
MODEM_RESET CLK_OUTCLK_OUT+ A3 A2 TEST2 TEST1 IRQ# A1 A0 SDA SCL
ORDERING INFORMATION
PART NUMBER XR18W753IL48 PACKAGE 48-Lead QFN OPERATING TEMPERATURE RANGE -40C to +85C DEVICE STATUS Active
R1R1+ AVDD19 AGND VDD_VCO AGND ATI+ ATIATO+ ATODGND TEST0
13 14 15 16 17 18 19 20 21 22 23 24
3
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REV. 1.0.0
PIN DESCRIPTIONS
NAME AGND AVDD19 AGND AVDD19 RFCM1 RFIN+ RFINRFCM2 AVDD19 AGND AVDD AGND R1R1+ AVDD19 AGND VDD_VCO AGND ATI+ ATIATO+ ATODGND TEST0 SCL SDA A0 A1 IRQ# TEST1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TYPE Ground Power I Ground Power I Analog O Analog I/O Analog I/O Analog O Power I Ground Power I Ground Analog I/O Power I Ground Analog O Ground Analog I Analog I Analog O Analog O Ground Digital I Digital OD DigitaI OD Digital I Digital I Digital O Digital I DESCRIPTION Analog ground for IF part of RX and BB part of TX Analog VDD (1.9V 0.1V) for IF part of RX and BB part of TX. Analog ground for RX frontend and PA Analog VDD (1.9V 0.1V) for LNA and PA. Common Mode voltage output for matching network. Voltage output TX: 1.9V RX: 170mV Differential RF signals Common Mode voltage output for matching network. Voltage output TX: 1.9V RX: 170mV Analog VDD (1.9V 0.1V) for LNA and PA. Analog ground for RX frontend and PA Analog VDD (1.9V 0.1V) for LNA and PA. Analog ground for IF part of RX and BB part of TX. External resistor to fix PA power. 470 ohm resistor connected between R1- and R1+ is recommended. Analog VDD (1.9V 0.1V) for synthesizer. Analog ground for synthesizer. VDD of VCO. VDD = 1.9V 0.1V (for decoupling). Analog ground for VCO. Analog Test Input Analog Test Input Analog Test Output Analog Test Output Digital ground Factory Test Mode. For normal operation, this pin should be connected to GND. Open-drain I2C serial clock Open-drain I2C serial data I2C Address bit-0 I2C Address bit-1 Interrupt output (active low, open-drain). Factory Test Mode. For normal operation, this pin should be connected to GND.
4
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 TYPE Digital I Digital I Digital I Digital O Digital O Digital I Digital I Power I Analog I Analog I Ground Power O Power I Power I Power O Power I Power I Power I Ground DESCRIPTION Factory Test Mode. For normal operation, this pin should be connected to GND. I2C Address bit-2 I2C Address bit-3. This address line should be connected to GND. 16 MHz LVDS digital clock outputs. Connect pin 35 to ground for CMOS clock output. Digital modem reset (active high, level sensitive). Voltage Regulator and crystal oscillator enable (active high, level sensitive) VDD (1.9V 0.1V) for crystal oscillator and clock divider. 16MHz crystal input or external clock input. Based on typical PCB stray capacitance, a 27 pF capacitor to GND is recommended. Crystal output, 27 pF capacitor to GND is recommended. If an external clock is used at XTAL1, this input should be left unconnected. Ground for crystal oscillator and buffers. Decoupling pin for digital VDD, 10 nF capacitor to GND recommended. Digital Power Supply, DVDD = 2.2 - 3.6V. DVDD and AVDD should use the same power supply. 100nF capacitor to GND recommended. Analog Power Supply, AVDD = 2.2 - 3.6V. DVDD and AVDD should use the same power supply. 100nF capacitor to GND recommended. 1.9V stabilized analog VDD output. This output should be connected to all AVDD19 pins. 1uF ceramic capacitor to GND recommended. Analog VDD (1.9V 0.1V) for ADC and DAC. Analog VDD (1.9V 0.1V) for ADC. Analog VDD (1.9V 0.1V) for IF strip, TX mixers and both I/Q dividers. The center pad on the backside of the 48-QFN package is metallic and is not electrically connected to anything inside the device. It must be soldered on to the PCB and may be optionally connected to GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
NAME TEST2 A2 A3 CLK_OUT+ CLK_OUTMODEM_RESET VREG_CLK_EN AVDD19 XTAL1 XTAL2 AGND DVDD_OUT DVDD AVDD AVDD_OUT AVDD19 AVDD19 AVDD19 PADDLE
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER 1.0 APPLICATION EXAMPLE An example of how the XR18W753 can be used is shown in the figure below. In this example, the I2C slave address of the XR18W753 is 0x60 (since all address lines are connected to GND). FIGURE 4. APPLICATION DIAGRAM
REV. 1.0.0
VDD C2
GND C5
VDD C3
16 MHz xtal C4 GND GND
Antenna- 50 ohms
L3 C7 C6
L1
L2
C8 GND
AGND AVDD19 AGND AVDD19 RFCM1 RFIN+ RFINRFCM2 AVDD19 AGND AVDD19 AGND
48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 MODEM_RESET CLK_OUTCLK_OUT+ A3 A2 TEST2 TEST1 IRQ# A1 A0 SDA SCL
AVDD19 AVDD19 AVDD19 AVDD_OUT AVDD DVDD DVDD_OUT AGND XTAL1 XTAL2 AVDD19 CLK_ENB
XR18W753
R1R1+ AVDD19 AGND VDD_VCO AGND ATI+ ATIATO+ ATODGND TEST0
13 14 15 16 17 18 19 20 21 22 23 24
GND
R1
C9
Analog Test Bus
GND
C1 GND GND GND
6
Interface to Microcontroller
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
TABLE 1: VALUE OF EXTERNAL COMPONENTS
COMPONENT VALUE1 NOTES
C1 C2 C3 C4 XTAL
1 uF 100 nF 27 pF 27 pF 16 MHz
Ceramic capacitor Ceramic capacitor +/- 5% +/- 5% 16 MHz fundamental mode crystal 18 pF load capacitance +/-20ppm initial tolerance +/-20ppm variation over the temperature range Ceramic capacitor RF matching network capacitor RF matching network capacitor RF matching network capacitor Ceramic capacitor RF matching network inductor RF matching network inductor External resistor to define the PA gain RF matching network inductor
C5 C6 C7 C8 C9 L1 L2 R1 L3
10 nF 2.2 pF 8.2 pF 100 pF 100 pF 4.3 nH 4.3 nH 470 ohms 15 nH
NOTE: 1. Values subject to change.
7
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER 2.0 PRODUCT DESCRIPTION 2.1 Radio Frequency Standards The XR18W753 is designed to operate in licensed-free European 868 MHz SRD, North American / Australian 915 MHz ISM, and 950 - 956 MHz bands. 2.2 Transmitter Block The transmitter block is a direct-up-conversion I/Q modulator consisting of D/A converters, interpolation filters, balanced I/Q mixers and a power amplifier. 2.3 Receiver Block The receiver is a Low-IF digital receiver consisting of a low-noise amplifier (LNA), I/Q mixers, IF filters, variable gain amplifiers, and A/D converters. 2.4 Modem Block The modem block is a Direct-Sequence-Spread-Spectrum (DSSS) O-QPSK digital modem with built-in automatic gain control (AGC), Physical Layer Management Entity (PLME), Frame Check Sum (FCS) computation, and Cyclical Redundancy Check (CRC) hardware. 2.5 Supporting Block The supporting block in the XR18W753 includes voltage/current reference, supply voltage stabilizer, and crystal oscillator. 2.6 Baseband Microcontroller Interface Interface to the XR18W753 can easily be made via the I2C bus as in the XR18W750 baseband microcontroller. All internal registers and data buffers are accessible via this bus. A 16MHz CMOS clock is provided to the microcontroller, eliminating the cost of an extra clock or crystal. 2.6.1 I2C-bus Interface
REV. 1.0.0
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2Cbus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400 kbps. The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the subaddress that contains the address of the register to access. The XR18W751 responds to each write with an acknowledge (SDA driven LOW by XR18W751 for one clock cycle when SCL is HIGH). If the TX FIFO is full, the XR18W751 will respond with a negative acknowledge (SDA driven HIGH by XR18W751 for one clock cycle when SCL is HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I2C-bus master is a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). For complete details, see the I2C-bus specifications. FIGURE 5. I2C START AND STOP CONDITIONS
SDA
SCL
S START condition P STOP condition
8
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER I2C-bus Addressing
2.6.1.1
The RF transceiver acts as an I2C slave. Four LSBs of I2C are mapped to external pins to support multiple chips in one application. There are eight possible slave addresses that can be selected for the XR18W753 using the A3, A2, A1 and A0 address lines. The table below shows the different addresses that can be selected. Note that A3 is always connected to GND.
I2C ADDRESS
A3
A2
A1
A0
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0x60 (0110 000X) 0x62 (0110 001X) 0x64 (0110 010X) 0x66 (0110 011X) 0x68 (0110 100X) 0x6A (0110 101X) 0x6C (0110 110X) 0x6E (0110 111X)
9
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REV. 1.0.0
The Physical Layer Management Entity (PLME) provides layer management service interfaces through which layer management functions may be invoked. The figure below shows the different modes of operation that can be invoked by the PLME. FIGURE 6. MODES OF OPERATION
ed_ready=0
ED
CCA
cca_ready=0
ed_ready=1 plme-ed.request plme-ed.request
cca_ready=1 plme-cca.request
pck_received=0
RX_BUSY
pck_received=1 & one_shot=0
pck_tx_ready=1
RX_ON
plme-set-trx-state.request TX_ON plme-set-trx-state.request RX_ON
TX_ON
pd-data.request
TX_BUSY
pck_tx_ready=0
sync_found=1
sync_found=0 plme-set-trx-state.request TRX_OFF plme-set-trx-state.request RX_ON pck_received=1 & one_shot=1 plme-set-trx-state.request FORCE_TRX_OFF (from every active state) plme-set-trx-state.request TX_ON
PLME
TRX_OFF
pll_on
pll_off
MODEM_RESET
IDLE
POWER MODES
Automatic transitions XR18W753 commands
NOTE: Every XR18W753 command is acknowledged by the `plme_ready' interrupt
The modes of operation can be invoked via the MODEM_REQUEST register and the status can be read from the MODEM_CONF0 and MODEM_CONF1 registers.
10
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
3.0 I2C MEMORY MAP 3.1 REGISTERS OVERVIEW
ADDRESS REGISTER NAME RESET VALUE TYPE COMMENTS
0x00 0x01 0x02 0x03 0x04 0x05 0x06-0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16-0x1F 0x20 0x21 0x22 - 0x26 0x27 0x28 0x29 0x2A-0x2D 0x2E 0x2F - 0x30 0x31-0x4F 0x50 0x51 0x52 0x53 0x54 - 0x7D 0x7E 0x7F
READ_SUBADDDRESS RX_FIFO TX_FIFO FIFO_CONTROL INT_MASKING INT_STATUS Reserved MODEM_REQUEST MODEM_CONF_0 MODEM_CONF_1 ED_AV_TIME MODEM_ED MODEM_LQI Reserved CHANNEL TX_POWER Reserved AGC_ACT_VALUE Reserved SLICER_LEVEL Reserved ED_THRES RSSI_ACT_VALUE_0, 1 Reserved TEST_0 TEST_1 TEST_2 TEST_3 Reserved CHIP_ID REV_ID
0x00 0x00 0x00 0x08 0x00 0x00 0x01 0x00 0x00 0xB1 0x03
R/W R W R/W R/W R R/W R R R/W R R R/W R/W R R R/W R R/W R/W R/W R/W R R For normal operation, initialize to 0xD1 For normal operation, initialize to 0x19 For normal operation, initialize to 0x82 For normal operation, initialize to 0x00 Two's complement number Frequency Offset (2's complement) Frequency channel selection Transmit output power Interrupt masking Interrupt status
Reserved registers are for internal use only. 11
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REV. 1.0.0
3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
TYPE
0x00
READ_SUBADDRESS
b[7:0] To ease reading via I2C, the data of READ_SUBADDRESS is a pointer to the first address in the I2C memory map. If the master wants to read the content of register e.g. 0x2E, the master first need to write 0x2E to READ_SUBADDRESS.
R/W
0x01
RX_FIFO
b[7:0] To retrieve data from the RX Data Buffer, the master must read from this register. All entries of the RX Data Buffer are mapped to this register, offering a FIFO mechanism.
R
0x02
TX_FIFO
b[7:0] To put data into the TX Data Buffer, the master must write to this register. All entries of the TX Data Buffer are mapped to this register, offering a FIFO mechanism.
W
0x03
FIFO_CONTROL
b[2:0] = 001 --> reset RX_FIFO read address b[2:0] = 010 --> reset RX_FIFO write address b[2:0] = 011 --> reset TX_FIFO read address b[2:0] = 100 --> reset TX_FIFO write address b[2:0] = 101 --> reset RX_FIFO read address b[2:0] = 110 --> reset RX_FIFO write address b[2:0] = 001 --> reset RX_FIFO read address b[2:0] = 111 --> reset all RX and TX FIFO addresses b[7:3] not used Via this register, the internal FIFO read and write pointers of the TX Data Buffer and the RX Data Buffer can be set to 0X00. The content of the Data Buffers is unaffected by resetting the pointers.
R/W
0x04
INT_MASKING
b[0] = 0 --> pck_tx_ready interrupt disabled b[0] = 1 --> pck_tx_ready interrupt enabled b[1] = 0 --> pck_received interrupt disabled b[1] = 1 --> pck_received interrupt enabled b[2] = 0 --> cca_ed_ready interrupt disabled b[2] = 1 --> cca_ed_ready interrupt enabled b[3] = 0 --> plme_ready interrupt disabled b[3] = 1 --> plme_ready interrupt enabled b[7:4] not used Via this register, the internal modem interrupts can be enabled or disabled. PLME_ready is enabled at start-up; after reset, a PLME_ready is generated.
R/W
12
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
TYPE
0x05
INT_STATUS
b[0] = 0 --> indicates the pck_tx_ready interrupt occurred b[1] = 0 --> indicates the pck_received interrupt occurred b[2] = 0 --> indicates the cca_ed_ready interrupt occurred b[3] = 0 --> indicates the plme_ready interrupt occurred b[7:4] not used Via this register, the modem interrupt status can be read. Once read, the content of the register will automatically set to 0x00.
R
0x10
MODEM_REQUEST
b[4:0] = 00xxx --> no request (x indicates "don't care") b[4:0] = 01000 --> plme-set-trx-state = FORCE_TRX_OFF b[4:0] = 01010 --> plme-set-trx-state = RX_ON b[4:0] = 01011 --> plme-set-trx-state = TX_ON b[4:0] = 01100 --> pd-data.request (TX-data) b[4:0] = 01101 --> plme-ED.request b[4:0] = 01110 --> plme-CCA.request b[4:0] = 01111 --> not used b[4:0] = 10000 --> PLL off b[4:0] = 10001 --> PLL on b[6:5] = 00 --> not used b[6:5] = 01 --> CCA mode1 b[6:5] = 10 --> CCA mode2 b[6:5] = 11 --> CCA mode3 b[7] = 0 --> after full reception of a packet, the modem is accepting new incoming data (continuous packet reception) b[7] = 0 --> after full reception of a packet, the PLME goes to TRX_OFF state (one shot packet reception) This register is used for: 1. Sending PLME related requests to the modem. 2. Defining CCA mode for clear channel assessment . 3. Defining whether the modem should be sensitive for data after a full reception of a data packet.
R/W
13
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER 3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
REV. 1.0.0
TYPE
0x11
MODEM_CONF_0
b[2:0] = 000 --> plme-set-trx-state = TRX_OFF b[2:0] = 001 --> plme-set-trx-state = SUCCESS b[2:0] = 010 --> plme-set-trx-state = RX_ON b[2:0] = 011 --> plme-set-trx-state = TX_ON b[2:0] = 100 --> plme-set-trx-state = BUSY_RX b[2:0] = 101 --> plme-set-trx-state = BUSY_TX b[2:0] = 110 --> not used b[2:0] = 111 --> not used b[4:3] = 00 --> plme-CCA = TRX_OFF b[4:3] = 01 --> plme-CCA = TX_ON b[4:3] = 10 --> plme-CCA = BUSY b[4:3] = 11 --> plme-CCA = IDLE b[6:5] = 00 --> plme-ED = TRX_OFF b[6:5] = 01 --> plme-ED = TX_ON b[6:5] = 10 --> plme-ED = SUCCESS b[6:5] = 11 --> not used b[7] not used This register is used for reading the confirmation of the PLME of the modem.
R
0x12
MODEM_CONF_1
[1:0] = 00 --> pd-data = TRX_OFF b[1:0] = 01 --> pd-data = RX_ON b[1:0] = 10 --> pd-data = SUCCESS b[1:0] = 11 --> not used b[2] = 0 --> no CRC error in received frame b[2] = 1 --> CRC error in received frame b[7:4] not used This register is used for reading the confirmation of the PLME of the modem and the result of the CRC computation of the received data packet.
R
14
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
TYPE
0x13
ED_AV_TIME
Measurement time for ED Measurement b[3:0] = 0000 --> 8 symbols b[3:0] = 0001 --> 5.0 mSec b[3:0] = 0010 --> 5.5 mSec b[3:0] = 0011 --> 6.0 mSec b[3:0] = 0100 --> 6.5 mSec b[3:0] = 0101 --> 7.0 mSec b[3:0] = 0110 --> 7.5 mSec b[3:0] = 0111 --> 8.0 mSec b[3:0] = 1000 --> 8.5 mSec b[3:0] = 1001 --> 9.0 mSec b[3:0] = 1010 --> 9.5 mSec b[3:0] = 1011 --> 10.0 mSec b[3:0] = 11xx --> 10.0 mSec b[7:4] not used Via this register, the ED measurement time can be defined. In case value 0 is chosen, the measurement time is compliant to the definition of the IEEE802.15.4b standard. In the 902-928 MHz band, the measurement time equals 128us. For the 868 MHz band, this symbol time equals 320us.
R/W
0x14
MODEM_ED
LQI Value, updated as a result of successful ED measurement. The result of the ED measurement is available in this register. The value is normalized and on average will be independent from the ED measurement time (ED_AV_TIME). Note that the value of MODEM_ED also depends on the content of ED_THRESH (0x2E).
R
0x15
MODEM_LQI
LQI Value, updated after complete frame reception. During reception of a data packet, the correlation values of the symbol mapping is accumulated and divided by the number of symbols in the packets. The number is a normalized Link Quality Indication.
R
0x16-0x1F
Reserved
-
-
15
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER 3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
REV. 1.0.0
TYPE
0x20
CHANNEL
b[4:0] = 00000 --> 868.3 MHz b[4:0] = 00001 --> 903 MHz b[4:0] = 00010 --> 904 MHz b[4:0] = 00011 --> 905 MHz b[4:0] = 00100 --> 906MHz b[4:0] = 00101 --> 907MHz b[4:0] = 00110 --> 908 MHz b[4:0] = 00111 --> 909 MHz b[4:0] = 01000 --> 910 MHz b[4:0] = 01001 --> 911 MHz b[4:0] = 01010 --> 912 MHz b[4:0] = 01011 --> 913 MHz b[4:0] = 01100 --> 914 MHz b[4:0] = 01101 --> 915 MHz b[4:0] = 01110 --> 916 MHz b[4:0] = 01111 --> 917 MHz b[4:0] = 10000 --> 918 MHz b[4:0] = 10001 --> 919 MHz b[4:0] = 10010 --> 920 MHz b[4:0] = 10011 --> 921 MHz b[4:0] = 10100 --> 922 MHz b[4:0] = 10101 --> 923 MHz b[4:0] = 10110 --> 924 MHz b[4:0] = 10111 --> 925 MHz b[4:0] = 11000 --> 926 MHz b[4:0] = 11001 --> 927 MHz b[4:0] = 11010 --> 951 MHz b[4:0] = 11011 --> 952 MHz b[4:0] = 11100 --> 953 MHz b[4:0] = 11101 --> 954 MHz b[4:0] = 11110 --> 955 MHz b[7:5] not used Via this register, the channel frequency can be selected.
R/W
16
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
TYPE
0x21
TX_POWER
Transmit output power during normal operation. b[5:0] = 0xxxxx --> TX Power = 0 dBm b[5:0] = 111111 --> TX Power = 0 dBm b[5:0] = 111110--> TX Power = 0 dBm b[5:0] = 111101 --> TX Power = 0dBm b[5:0] = 111100 --> TX Power = -3 dBm b[5:0] = 111011--> TX Power = -3 dBm b[5:0] = 111010 --> TX Power = -3 dBm b[5:0] = 111001 --> TX Power = -6 dBm b[5:0] = 111000--> TX Power = -6 dBm b[5:0] = 110111 --> TX Power = -6 dBm b[5:0] = 110110 --> TX Power = -9 dBm b[5:0] = 110101--> TX Power = -9 dBm b[5:0] = 110110 --> TX Power = -9 dBm b[5:0] = 110011 --> TX Power = -12 dBm b[5:0] = 110010--> TX Power = -12 dBm b[5:0] = 110001 --> TX Power = -12 dBm b[5:0] = 110000 --> TX Power = -15 dBm b[5:0] = 101111--> TX Power = -15 dBm b[5:0] = 101110 --> TX Power = -15 dBm b[5:0] = 101101 --> TX Power = -18 dBm b[5:0] = 101100--> TX Power = -18 dBm b[5:0] = 101011 --> TX Power = -18 dBm b[5:0] = 101010 --> TX Power = -21 dBm b[5:0] = 101001--> TX Power = -21 dBm b[5:0] = 101000 --> TX Power = -21 dBm b[5:0] = 100xxx --> TX Power = -24 dBm b[7:6] not used Note: x indicates don't care
R/W
0x22 - 0x26
Reserved
-
-
17
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER 3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
REV. 1.0.0
TYPE
0x27
AGC_ACT_VALUE
AGC setting instantaneous value b[3:0] = 0000 --> IF-AGC set to 0dB b[3:0] = 0001 --> IF-AGC set to -6dB b[3:0] = 0010 --> IF-AGC set to -12dB b[3:0] = 0011 --> IF-AGC set to -18dB b[3:0] = 0100 --> IF-AGC set to -24dB b[3:0] = 0101 --> IF-AGC set to -30dB b[3:0] = 0110 --> IF-AGC set to -36dB b[3:0] = 0111 --> IF-AGC set to -42dB b[3:0] = 1000 --> IF-AGC set to -48dB b[3:0] = 1001 --> not used b[3:0] = 1010 --> not used b[3:0] = 1011 --> not used b[3:0] = 1100 --> not used b[3:0] = 1101 --> not used b[3:0] = 1110 --> not used b[3:0] = 1111 --> not used b[7:4] not used Frequency offset in a link can be read out via this register. The value is interpreted as an 8-bit two's complement value (-128 to +127). The conversion from this value to frequency is given below. For 902 - 928 MHz application, the frequency offset is:
R
0x28 0x29
Reserved SLICER_LEVEL
R
foffset = 1MHz x SLICER_LEVEL / 128
For 868 MHz application, the frequency offset is:
foffset = 400 kHz x SLICER_LEVEL / 128
0x2A-0x2D 0x2E Reserved ED_THRES Energy detection threshold In IEE802.15.4 specification, it has been defined how the result of the ED measurement given in MODEM_ED (0x15) need to be reported. The value of ED_THRES is used to align the receiver with the IEE802.15.4 ED measurement specification. 0x2F - 0x30 RSSI_ACT_VALUE_0,1 Actual RSSI value_0, 1 The instantaneous level to the digital demodulator can be read via these two registers. The value is interpreted as a two's complement number. Together with the information of AGC_ACT_VALUE (0x27), the instantaneous RF level can be calculated. 0x31-0x4F 0x50 Reserved TEST_0 This register is used for factory test modes. For normal operation, initialize this register to 0xD1. R/W R R/W
18
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
3.2 DETAILED REGISTERS DESCRIPTIONS
ADDRESS
REGISTER NAME DESCRIPTION
TYPE
0x51 0x52 0x53
TEST_1 TEST_2 TEST_3
This register is used for factory test modes. For normal operation, initialize this register to 0x19. This register is used for factory test modes. For normal operation, initialize this register to 0x82. This register is used for factory test modes. For normal operation, initialize this register to 0x00. Chip_ID used to categorize the XR18W753. The CHIP_ID is 0xB1. REV_ID is used to keep track of the hardware version of the XR18W753 chip.
R/W R/W R/W R R
0x54 - 0x7D Reserved 0x7E 0x7F CHIP_ID REV_ID
19
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REV. 1.0.0
ABSOLUTE MAXIMUM RATING
Supply Voltage, AVDD Supply Voltage, DVDD Supply Voltage, AVDD19 Ambient Temperature
+3.6 +3.6 +2.0 +85
V V V
o
C
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: 15%)
Thermal Resistance (48-QFN) theta-ja = 40oC/W, theta-jc = 13oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VDD IS 2.2V TO 3.6V
SYMBOL PARAMETER MIN LIMITS 2.5V TYP LIMITS 3.3V TYP UNIT MAX
S
MAX
MIN
VILCK VIHCK VIL VIH VOL VOH IIL IIH CIN IDD
External Clock Input Low Level External Clock Input High Level Input Low Voltage Input High Voltage Output Low Voltage
-0.3 2.0 -0.3 1.8
0.4 VDD 0.5 5.5
-0.3 2.4 -0.3 2.0
0.6 VDD 0.7 5.5 0.4
V V V V V V V V
0.4 Output High Voltage 1.8 Input Low Leakage Current Input High Leakage Current Input Pin Capacitance Power Supply Current (VREG DISABLED) Power Supply Current (IDLE) Power Supply Current (RX_ON) Power Supply Current (TX_ON) 0.5 1.7 19 22 10 10 5 0.5 1.7 19 22 10 10 5 2.0
uA uA pF mA mA mA mA
20
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS Unless otherwise noted: TA=-40o to +85oC, VDD=2.2 - 3.6V
SYMBOL PARAMETER STANDARD MODE I2C-BUS MIN TYP MAX FAST MODE I2C-BUS MIN TYP MAX UNIT
fSCL TBUF THD;STA TSU;STA THD;DAT TVD;ACK TVD;DAT TSU;DAT TLOW THIGH TF TR TSP TD15
Operating frequency Bus free time between STOP and START START condition hold time START condition setup time Data hold time Data valid acknowledge SCL LOW to data out valid Data setup time Clock LOW period Clock HIGH period Clock/data fall time Clock/data rise time Pulse width of spikes tolerance SCL delay after reset 3 0.5 250 4.7 4.0 4.7 4.0 4.7 0
100 1.3 0.6 0.6 0 0.6 0.6 150 1.3 0.6 300 1000 0.5 3
400
kHz
s s s
ns 0.6 0.6
s
ns ns
s s
300 300
ns ns
s s
FIGURE 7. SCL DELAY AFTER RESET
RESET#
T D15
SCL
21
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REV. 1.0.0
FIGURE 1. I2C-BUS TIMING DIAGRAM
Protocol
START condition (S) T SU;STA
Bit 7 MSB (A7) T LOW T HIGH
Bit 6 (A6)
Bit 0 LSB (R/W)
Acknowledge (A)
STOP condition (P)
1/F SCL
SCL TF T SP
T BUF
TR
SDA
T HD;STA
T SU;DAT
T HD;DAT
T VD;DAT
T VD;ACK
T SU;STO
22
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REFERENCE OSCILLATOR SPECIFICATIONS
PARAMETER MIN TYP MAX UNIT
Center Frequency Frequency Tolerance External Crystal Load Capacitance
16 40 18
MHz ppm pF
OPERATING FREQUENCY
FREQUENCY BAND FREQUENCY UNIT
European SRD North American / Australian ISM 950 MHZ
868.3 903 - 927 951 - 955
MHz MHz MHz
MODULATION
O-QPSK with half-sine wave pulse shaping Equivalent to MSK (FM with m=0.5)
23
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REV. 1.0.0
DATA RATES
FREQUENCY BAND SYMBOL RATE BIT RATE CHIP RATE -3dB BANDWIDTH NOTE
European SRD North American / Australian ISM 950 MHZ
25 Ksps 62.5 Ksps 62.5 Ksps
100 Kbps 250 Kbps 250 Kbps
400 Kcps 1 Mcps 1 Mcps
200 KHz 500 KHz 500 KHz
16-ary symbols 16 chips per symbol 4 bits per symbol 2 symbols per byte
PACKET STRUCTURE
Europe SRD Band
Preamble (all zero-symbols) Start Frame Delimiter (SFD = 0xA7) Frame Length (PHR) Payload Data Frame Check Sum (FCS)
North American / Australian ISM Band
4 1 1 0 - 127 2
Bytes Bytes Bytes Bytes Bytes
Preamble (all zero-symbols) Start Frame Delimiter (SFD = 0xA7) Frame Length (PHR) Payload Data Frame Check Sum (FCS)
950 MHZ Band
10 1 1 0 - 127 2
Bytes Bytes Bytes Bytes Bytes
Preamble (all zero-symbols) Start Frame Delimiter (SFD = 0xA7) Frame Length (PHR) Payload Data Frame Check Sum (FCS)
10 1 1 0 - 127 2
Bytes Bytes Bytes Bytes Bytes
24
XR18W753
REV. 1.0.0
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
TRANSMITTER
PARAMETER MIN TYP MAX UNIT NOTE
TX Output Power
0 -3 -6 -9 -12 -15 -18 -21 -24 3 50 5 -86 -80 -97 -97
dBm
TX Power Control Antenna Impedance Error Vector Magnitude Spurious Emission (wideband) 30MHz - 1GHz 1GHz - 12.75GHz 1.8GHz - 1.9GHz 5.15GHz - 5.3GHz
dB
% dBm/Hz
with external matching network
EN300 328 4.3.4.2
RECEIVER
PARAMETER MIN TYP MAX UNIT NOTE
Sensitivity @100 Kbps Sensitivity 250 Kbps Noise Figure Antenna Impedance Blocking / Desensitization 1MHz 2MHz 5MHz 10MHz Largest signal IP3 RSSI Accuracy
-94 -91 12 50
dBm dBm dB
PER = 1%, Payload = 20 bytes PER = 1%, Payload = 20 bytes
dBm
with external matching network EN 300 220 CW. at -82 dBm sensitivity level
-52 -47 -32 -22 10 -20 6 dBm dBm dB
25
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER
REV. 1.0.0
PACKAGE DIMENSIONS (48 PIN QFN - 7 X 7 X 0.9 mm)
Note: The control dimension is in millimeter. INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX
A A1 A3 D D2 b e L
0.031 0.000 0.006 0.270 0.201 0.007
0.039 0.002 0.010 0.281 0.209 0.012
0.80 0.00 0.15 6.85 5.10 0.18
1.00 0.05 0.25 7.15 5.30 0.30
0.0197 BSC 0.012 0.020
0.50 BSC 0.30 0.50
26
XR18W753
SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER REVISION HISTORY
DATE REVISION DESCRIPTION
REV. 1.0.0
February 2007 September 2007 March 2008
P1.0.0 P1.0.1 1.0.0
Preliminary Datasheet. Updated to new datasheet template. Final Datasheet
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2008 EXAR Corporation Datasheet March 2008. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
27

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