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PRELIMINARY
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ICS854S013
General Description
The ICS854S013 is a low skew, high performance Dual 1-to-3 Differential-to-LVDS Fanout Buffer and HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. The ICS854S013 is characterized to operate from a 3.3V power supply. Guaranteed output and bank skew characteristics make the ICS854S013 ideal for those clock distribution applications demanding well defined performance and repeatability.
Features
* * * * * * * * * * * *
Two differential LVDS output banks Two differential clock input pairs PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Maximum output frequency: >3GHz Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input Output skew: <25ps (typical) Bank skew: <50ps (typical) Propagation delay: TBD Additive phase jitter, RMS: 0.15ps (typical) Full 3.3V power supply 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
ICS
Block Diagram
QA0 nQA0 PCLKA Pulldown nPCLKA Pullup QA1 nQA1 QA2 nQA2 QB0 nQB0 PCLKB Pulldown nPCLKB Pullup QB1 nQB1 QB2 nQB2
Pin Assignment
nQA0 QA0 VDD PCLKA nPCLKA PCLKB nPCLKB VDD nQB0 QB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA1 nQA1 QA2 nQA2 VDD QB2 nQB2 QB1 nQB1 GND
ICS854S013
20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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Table 1. Pin Descriptions
Number 1, 2 3, 8, 16 4 5 6 7 9, 10 11 12, 13 14, 15 17, 18 19, 20 Name nQA0, QA0 VDD PCLKA nPCLKA PCLKB nPCLKB nQB0, QB0 GND nQB1, QB1 nQB2, QB2 nQA2, QA2 nQA1, QA1 Output Power Input Input Input Input Output Power Output Output Output Output Pulldown Pullup Pulldown Pullup Type Description Differential output pair. LVDS interface levels. Power supply pins. Non-inverting differential clock input. Inverting differential clock input. VDD/2 default when left floating. Non-inverting differential clock input. Inverting differential clock input. VDD/2 default when left floating. Differential output pair. LVDS interface levels. Power supply ground. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
Table 3. Clock Input Function Table
Inputs PCLKA, PCLKB 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nPCLKA, nPCLKB 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs QA[0:2], QB[0:2] LOW HIGH LOW HIGH HIGH LOW nQA[0:2], nQB[0:2] HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single-ended to Differential Single-ended to Differential Single-ended to Differential Single-ended to Differential Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting Inverting Inverting
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 87.2C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 135 Maximum 3.465 Units V mA
Table 4B. LVPECL Differential DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Symbol IIH Parameter PCLKA, PCLKB Input High Current nPCLKA, nPCLKB PCLKA, PCLKB IIL Input Low Current nPCLKA, nPCLKB VPP VCMR Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
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Table 4C. LVDS DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 360 50 1.35 50 Maximum Units mV mV V mV
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Parameter fMAX tPD tsk(o) tsk(b) tjit tR / tF odc Symbol Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Bank Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 100MHz, Integration Range: 12kHz - 20MHz 20% to 80% TBD <25 <50 0.15 200 50 ps % Test Conditions Minimum Typical Maximum >3 Units GHz ps ps ps
All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
0 -10 -20 -30 -40 -50 SSB Phase Noise dBc/Hz -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.15ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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Parameter Measurement Information
VDD
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD
Qx
nPCLKA, nPCLKB
V
PP
Cross Points
V
LVDS
nQx
CMR
PCLKA, PCLKB GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
nQXx QXx nQXx QXx
nQx Qx nQy Qy
tsk(b)
tsk(o)
Where X = A or B
Bank Skew
Output Skew
nPCLKA, nPCLKB PCLKA, PCLKB nQAx, nQBx QAx, QBx
nQAx, nQBx QAx, QBx
t PW
t
PERIOD
odc =
tPD
t PW t PERIOD
x 100%
Propagation Delay
Output Duty Cycle/Pulse Width/Period
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Parameter Measurement Information, continued
VDD
80% Clock Outputs
80% VOD
DC Input
out
20% tR tF
20%
LVDS
out
VOS/ VOS
Output Rise/Fall Time
Offset Voltage Setup
VDD

out
DC Input
LVDS
100
VOD/ VOD out
Differential Output Voltage Setup
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Application Information
Recommendations for Unused Input and Output Pins Inputs:
PCLK/nPCLK Inputs
For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN
PCLKx
V_REF
nPCLKx
C1 0.1uF
R2 1K
Figure 1. Single-Ended Signal Driving Differential Input
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LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50 PCLK Zo = 50 nPCLK Zo = 50 R1 100 nPCLK R2 50 3.3V Zo = 50
PCLK
CML
HiPerClockS PCLK/nPCLK
CML Built-In Pullup
HiPerClockS PCLK/nPCLK
Figure 2A. HiPerClockS PCLK/nPCLK Input Driven by an Open Collector CML Driver
Figure 2B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 PCLK Zo = 50 nPCLK R4 125
3.3V 3.3V 3.3V R3 84 Zo = 50 C1 PCLK Zo = 50 C2 nPCLK R4 84
3.3V LVPECL
LVPECL
R1 84 R2 84
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 125
R2 125
HiPerClockS PCLK/nPCLK
Figure 2C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver
Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple
2.5V 3.3V 2.5V R3 120 Zo = 60 PCLK Zo = 60 nPCLK R5 100 C2 R4 120 3.3V Zo = 50 C1
3.3V 3.3V R3 1k R4 1k PCLK
SSTL
R1 120 R2 120
HiPerClockS PCLK/nPCLK
Zo = 50
nPCLK R1 1k R2 1k
LVDS
HiPerClockS PCLK/nPCLK
Figure 2E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver
Figure 2F. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver
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3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 3. Typical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S013. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS854S013 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 135mA = 467.77mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 87.2C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.468W * 87.2C/W = 110.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 87.2C/W 1 82.9C/W 2.5 80.7C/W
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Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 87.2C/W 1 82.9C/W 2.5 80.7C/W
Transistor Count
The transistor count for ICS854S013 is: 363
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8 Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number ICS854S013BG ICS854S013BGT ICS854S013BGLF ICS854S013BGLFT Marking ICS854S013BG ICS854S013BG ICS54S013BL ICS54S013BL Package 20 Lead TSSOP 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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