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PIC16F/LF720/721 Data Sheet
20-Pin Flash Microcontrollers with nanoWatt XLP Technology
2010 Microchip Technology Inc.
DS41430A
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
ISBN: 978-1-60932-482-7
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41430A-page 2
2010 Microchip Technology Inc.
PIC16F/LF720/721
20-Pin Flash Microcontrollers with nanoWatt XLP Technology
Devices Included In This Data Sheet:
* PIC16F720 * PIC16F721 * PIC16LF720 * PIC16LF721
Low-Power Features:
* Standby Current: - 50 nA @ 1.8V, typical * Operating Current: - 100 A @ 500 kHz, 1.8V, typical * Low-Power Watchdog Timer Current: - 500 nA @ 1.8V, typical
High-Performance RISC CPU:
* Only 35 Instructions to Learn: - All single-cycle instructions except branches * Operating Speed: - DC - 16 MHz oscillator/clock input - DC - 250 ns instruction cycle * Up to 4K x 14 Words of Flash Program Memory * Up to 256 bytes of Data Memory (RAM) * Interrupt Capability * 8-Level Deep Hardware Stack * Direct, Indirect and Relative Addressing modes * Processor Self-Write/Read access to Program Memory
Peripheral Features:
* Up to 17 I/O Pins and 1 Input-only Pin: - High-current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups * A/D Converter: - 8-bit resolution - 12 channels - Selectable Voltage reference * Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler * Enhanced Timer1 - 16-bit timer/counter with prescaler - External Gate Input mode with toggle and single shot modes - Interrupt-on-gate completion * Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Capture, Compare, PWM module (CCP) - 16-bit Capture, max resolution 12.5 ns - 16-bit Compare, max resolution 250 ns - 10-bit PWM, max frequency 15 kHz * Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) * Synchronous Serial Port (SSP) - SPI (Master/Slave) - I2CTM (Slave) with Address Mask
Special Microcontroller Features:
* Precision Internal Oscillator: - 16 MHz or 500 kHz operation - Factory calibrated to 1%, typical - Software tunable - Software selectable /1, /2, /4 or /8 divider * Power-Saving Sleep mode * Industrial and Extended Temperature Range * Power-on Reset (POR) * Power-up Timer (PWRT) * Brown-out Reset (BOR) * Multiplexed Master Clear with Pull-up/Input Pin * Programmable Code Protection * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * High-Endurance Flash Cell: - 10,000 write Flash endurance (typical) - Flash retention: > 40 years * Wide Operating Voltage Range: - 1.8V to 5.5V (PIC16F720/721) - 1.8V to 3.6V (PIC16LF720/721)
2010 Microchip Technology Inc.
DS41430A-page 3
PIC16F/LF720/721
Device Program Memory Flash (words) 2048 4096 2048 4096 SRAM (bytes) 128 256 128 256 I/O Timers 8/16-bit 2/1 2/1 2/1 2/1 8-bit A/D (ch) 12 12 12 12 AUSART CCP SSP
PIC16F720 PIC16F721 PIC16LF720 PIC16LF721
18 18 18 18
Yes Yes Yes Yes
1 1 1 1
1 1 1 1
DS41430A-page 4
2010 Microchip Technology Inc.
PIC16F/LF720/721
Pin Diagrams - 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721
PDIP, SOIC, SSOP VDD RA5/T1CKI/CLKIN RA4/AN3/T1G/CLKOUT RA3/MCLR/VPP RC5/CCP1 RC4 RC3/AN7 RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK 1 2 3 PIC16F720/721 PIC16LF720/721 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VSS RA0/AN0/ICSPDAT RA1/AN1/ICSPCLK RA2/AN2/T0CKI/INT RC0/AN4 RC1/AN5 RC2/AN6 RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL
Pin Diagrams - 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721
20-Pin QFN (4x4) RA4/AN3/T1G/CLKOUT
RA5/T1CKI/CLKIN
VDD
20 19 18 17 16 RA3/MCLR/VPP RC5/CCP1 RC4 RC3/AN7 RC6/AN8/SS 1 2 3 4 5 6 7 8 9 10 15 14 PIC16F720/721 13 PIC16LF720/721 12 11 RA1/AN1/ICSPCLK RA2/AN2/T0CKI/INT RC0/AN4 RC1/AN5 RC2/AN6
VSS RB5/AN11/RX/DT
2010 Microchip Technology Inc.
RB4/AN10/SDI/SDA
RC7/AN9/SDO
RB6/SCK/SCL
RB7/TX/CK
RA0/AN0/ICSPDAT
DS41430A-page 5
PIC16F/LF720/721
TABLE 1: 20-PIN ALLOCATION TABLE (PIC16F720/721 AND PIC16LF720/721)
20-Pin DIP/SOIC/ SSOP 20-Pin QFN AUSART Interrupt
Pull-up
Timers
RA0 RA1 RA2 RA3 RA4 RA5 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 VDD Vss
19 18 17 4 3 2 13 12 11 10 16 15 14 7 6 5 8 9 1 20
16 15 14 1 20 19 10 9 8 7 13 12 11 4 3 2 5 6 18 17
AN0 AN1 AN2 -- AN3 -- AN10 AN11 -- -- AN4 AN5 AN6 AN7 -- -- AN8 AN9 -- --
-- -- T0CKI -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP1 -- -- -- --
-- -- -- -- -- -- -- RX/DT -- TX/CK -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- SDI/SDA -- SCK/SCL -- -- -- -- -- -- -- SS SDO -- --
IOC IOC INT/IOC IOC IOC IOC IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- --
Y Y -- Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- -- --
ICSPDAT/ ICDDAT ICSPCLK/ ICDCLK -- MCLR/VPP CLKOUT CLKIN -- -- -- -- -- -- -- -- -- -- -- -- VDD VSS
DS41430A-page 6
2010 Microchip Technology Inc.
Basic
CCP
SSP
A/D
I/O
PIC16F/LF720/721
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................ 13 3.0 Resets ....................................................................................................................................................................................... 27 4.0 Interrupts ................................................................................................................................................................................... 37 5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 45 6.0 I/O Ports .................................................................................................................................................................................... 47 7.0 Oscillator Module....................................................................................................................................................................... 67 8.0 Device Configuration ................................................................................................................................................................. 73 9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 77 10.0 Fixed Voltage Reference........................................................................................................................................................... 87 11.0 Temperature Indicator Module ................................................................................................................................................... 89 12.0 Timer0 Module .......................................................................................................................................................................... 91 13.0 Timer1 Module with Gate Control.............................................................................................................................................. 95 14.0 Timer2 Module ........................................................................................................................................................................ 107 15.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 109 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .......................................................... 119 17.0 SSP Module Overview ............................................................................................................................................................ 139 18.0 Flash Program Memory Self Read/Self Write Control............................................................................................................. 161 19.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 169 20.0 In-Circuit Serial ProgrammingTM (ICSPTM) .............................................................................................................................. 171 21.0 Instruction Set Summary ......................................................................................................................................................... 173 22.0 Development Support.............................................................................................................................................................. 183 23.0 Electrical Specifications........................................................................................................................................................... 187 24.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 213 25.0 Packaging Information............................................................................................................................................................. 225 Appendix A: Data Sheet Revision History......................................................................................................................................... 233 Appendix B: Migrating From Other PIC(R) Devices............................................................................................................................. 233 The Microchip Web Site .................................................................................................................................................................... 241 Customer Change Notification Service ............................................................................................................................................. 241 Customer Support ............................................................................................................................................................................. 241 Reader Response ............................................................................................................................................................................. 242 Product Identification System ............................................................................................................................................................ 243
2010 Microchip Technology Inc.
DS41430A-page 7
PIC16F/LF720/721
TO OUR VALUED CUSTOMERS
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Errata
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DS41430A-page 8
2010 Microchip Technology Inc.
PIC16F/LF720/721
1.0 DEVICE OVERVIEW
The PIC16F/LF720/721 devices are covered by this data sheet. They are available in 20-pin packages. Figure 1-1 shows a block diagram of the PIC16F/LF720/721 devices. Table 1-1 shows the pinout descriptions.
2010 Microchip Technology Inc.
DS41430A-page 9
PIC16F/LF720/721
FIGURE 1-1: 20-PIN DEVICE BLOCK DIAGRAM FOR PIC16F720/721
Configuration 13 Program Counter (PIC16F720 2K x 14 Flash 4K 8K x 14 Program Memory Data Bus 8 PORTA RA0 RA1 RA2 RA3 RA4 RA5
8 Level Stack (13-bit)
(PIC16F720 RAM 128 x 8) File Registers 256 368 x 8 RAM Addr 9 PORTB
Program Bus
14 Instruction Reg Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR Reg FSR reg STATUS Reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control CLKIN CLKOUT Timing Generation Power-on Reset Watchdog Timer Brown-out Reset LDO Regulator 8 W Reg W reg ALU PORTC
RB4 RB5 RB6 RB7
MUX
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
Internal Oscillator Block
PMDATL Self read/ write Flash memory MCLR VDD VSS CCP1 CCP1 EEADDR
TX/CK RX/DT T0CKI T1G T1CKI
ICSPDAT ICSPCLK
SDI/ SCK/ SDO SDA SCL
SS
Timer0
Timer1
Timer2
AUSART
AUSART ICSPTM
Synchronous Serial Port
Analog-To-Digital Converter
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11
DS41430A-page 10
2010 Microchip Technology Inc.
PIC16F/LF720/721
TABLE 1-1:
Name
RA0/AN0/ICSPDAT RA0 AN0 ICSPDAT ICDDAT RA1/AN1/ICSPCLK RA1 AN1 ICSPCLK ICDCLK RA2/AN2/T0CKI/INT RA2 AN2 T0CKI INT RA3/MCLR/VPP RA3 MCLR VPP RA4/AN3/T1G/CLKOUT RA4 AN3 T1G CLKOUT RA5/T1CKI/CLKIN RA5 T1CKI CLKIN RB4/AN10/SDI/SDA RB4 TTL ST ST TTL CMOS -- -- CMOS ST AN ST ST TTL ST HV TTL AN ST -- CMOS -- -- -- CMOS -- -- CMOS -- -- CMOS TTL AN ST ST CMOS -- -- CMOS TTL AN ST ST CMOS -- CMOS CMOS
PINOUT DESCRIPTION
Function
IN OUT
Description
General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. A/D Channel 0 Input. Serial mode Schmitt Trigger. Debug mode Schmitt Trigger. General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. A/D Channel 1 Input. Serial mode Schmitt Trigger. Debug mode Schmitt Trigger. General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. A/D Channel 2 Input. Timer0 Clock Input. External interrupt. General purpose input only. Individually controlled interrupt-onchange. Individually enabled pull-up. Master Clear Reset. Pull-up enabled when configured as MCLR. Programming Voltage. General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. A/D Channel 3 Input. Timer1 Gate Input. FOSC/4 output. General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Timer1 Clock input. External Clock Input (EC mode). General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. A/D Channel 10 Input. SPI Data Input. I2CTM Data. General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. A/D Channel 11 Input. USART asynchronous input. USART synchronous data.
AN10 SDI SDA RB5/AN11/RX/DT RB5
AN ST ST TTL
-- -- OD CMOS
AN11 RX DT Legend:
AN ST ST
-- -- CMOS
AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible input, ST = Schmitt Trigger input with CMOS levels, I2CTM = Schmitt Trigger input with I2C, HV = High Voltage, XTAL = Crystal levels
2010 Microchip Technology Inc.
DS41430A-page 11
PIC16F/LF720/721
TABLE 1-1:
Name
RB6/SCK/SCL
PINOUT DESCRIPTION
Function
RB6 IN TTL OUT CMOS
Description
General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. SPI Clock. I2CTM Clock. General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. USART asynchronous transmit. USART synchronous clock. General purpose I/O. A/D Channel 4 Input. General purpose I/O. A/D Channel 5 Input. General purpose I/O. A/D Channel 6 Input. General purpose I/O. A/D Channel 7 Input. General purpose I/O. General purpose I/O. Capture/Compare/PWM 1. General purpose I/O. A/D Channel 8 Input. Slave Select input. General purpose I/O. A/D Channel 9 Input. SPI Data Output. Positive supply. Ground supply.
SCK SCL RB7/TX/CK RB7
ST ST TTL
CMOS OD CMOS
TX CK RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 RC4 RC5/CCP1 RC6/AN8/SS RC0 AN4 RC1 AN5 RC2 AN6 RC3 AN7 RC4 RC5 CCP1 RC6 AN8 SS RC7/AN9/SDO RC7 AN9 SDO VDD Vss Legend: VDD Vss
-- ST ST AN ST AN ST AN ST AN ST ST ST ST AN ST ST AN -- Power Power
CMOS CMOS CMOS -- CMOS -- CMOS -- CMOS -- CMOS CMOS CMOS CMOS -- -- CMOS -- CMOS -- --
AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible input, ST = Schmitt Trigger input with CMOS levels, I2CTM = Schmitt Trigger input with I2C, HV = High Voltage, XTAL = Crystal levels
DS41430A-page 12
2010 Microchip Technology Inc.
PIC16F/LF720/721
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-2:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F721/LF721
PC<12:0>
The PIC16F720/LF720 has a 13-bit program counter capable of addressing a 2K x 14 program memory space (0000h-07FFh), a 4K x 14 program memory space for the PIC16F721/LF721 (0000h-0FFFh). Accessing a location above the memory boundaries for the PIC16F720/LF720 will cause a wrap-around within the first 2K x 14 program memory space. Accessing a location above the memory boundaries for the PIC16F721/LF721 will cause a wrap-around within the first 4K x 14 program memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h.
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F720/LF720
PC<12:0> On-chip Program Memory
Interrupt Vector Page 0
0004H 0005h 07FFh 0800h
CALL, RETURN RETFIE, RETLW
13
Page 1 0FFFh 1000h Wraps to Page 0 17FFh 1800h Wraps to Page 1 1FFFh
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h
Interrupt Vector On-chip Program Memory Page 0
0004H 0005h 07FFh 0800h
Wraps to Page 0 0FFFh 1000h Wraps to Page 0 17FFh 1800h Wraps to Page 0 1FFFh
2010 Microchip Technology Inc.
DS41430A-page 13
PIC16F/LF720/721
2.2 Data Memory Organization
2.2.1
The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. RP1 0 0 1 1 RP0 0 1 0 1 Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected
GENERAL PURPOSE REGISTER FILE
The register file is organized as 128 x 8 bits in the PIC16F720/LF720, 256 x 8 bits in the PIC16F721/ LF721. Each register is accessed either directly or indirectly through the File Select Register (FSR), (Refer to Section 2.5 "Indirect Addressing, INDF and FSR Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank are mirrored in another bank for code reduction and quicker access.
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (refer to Table 2-1). These registers are static RAM. The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
DS41430A-page 14
2010 Microchip Technology Inc.
PIC16F/LF720/721
FIGURE 2-3: PIC16F720/LF720 SPECIAL FUNCTION REGISTERS
File Address
Indirect addr.(*) 00h
TMR0 PCL STATUS FSR PORTA PORTB PORTC 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG 0Ah 0Bh 0Ch
0Dh
Indirect addr.(*) 80h
OPTION_REG PCL STATUS FSR TRISA TRISB TRISC 81h 82h 83h 84h 85h 86h 87h 88h 89h PCLATH INTCON PIE1 PCON T1GCON OSCCON OSCTUNE PR2 SSPSTAT WPUA IOCA TXSTA SPBRG 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch FVRCON ADCON1 9Dh 9Eh 9Fh A0h General Purpose Register 32 Bytes
Indirect addr.(*) 100h
TMR0 PCL STATUS FSR 101h 102h 103h 104h 105h 106h 107h 108h 109h PCLATH INTCON PMDATL PMADRL PMDATH PMADRH 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h WPUB IOCB 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
Indirect addr.(*) 180h
OPTION_REG PCL STATUS FSR ANSELA ANSELB ANSELC 181h 182h 183h 184h 185h 186h 187h 188h 189h PCLATH INTCON PMCON1 PMCON2 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh
SSPADD/SSPMSK 93h
ADRES
1Eh
ADCON0
1Fh 20h
General Purpose Register 96 Bytes
BFh C0h EFh F0h Accesses 70h - 7Fh 7Fh FFh BANK 1 BANK 2 Accesses 70h - 7Fh 17Fh BANK 3 16Fh 170h Accesses 70h - 7Fh 1FFh 1EFh 1F0h
BANK 0 Legend: *
= Unimplemented data memory locations, read as `0'. = Not a physical register.
2010 Microchip Technology Inc.
DS41430A-page 15
PIC16F/LF720/721
FIGURE 2-4:
Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC
PIC16F721/LF721 SPECIAL FUNCTION REGISTERS
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h PCLATH INTCON PIE1 PCON T1GCON OSCCON OSCTUNE PR2 SSPSTAT WPUA IOCA TXSTA SPBRG 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch FVRCON ADCON1 General Purpose Register 80 Bytes Accesses 70h - 7Fh 7Fh BANK 1 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes Accesses 70h - 7Fh BANK 2 WPUB IOCB PCLATH INTCON PMDATL PMADRL PMDATH PMADRH Indirect addr.(*) TMR0 PCL STATUS FSR 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h PCLATH INTCON PMCON1 PMCON2 Indirect addr.(*) OPTION_REG PCL STATUS FSR ANSELA ANSELB ANSELC 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG
0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh
SSPADD/SSPMSK 93h
ADRES
1Eh
ADCON0
1Fh 20h
General Purpose Register 96 Bytes
EFh F0h FFh
16Fh 170h 17Fh BANK 3 Accesses 70h - 7Fh
1EFh 1F0h 1FFh
BANK 0 Legend: *
= Unimplemented data memory locations, read as `0'. = Not a physical register.
DS41430A-page 16
2010 Microchip Technology Inc.
PIC16F/LF720/721
TABLE 2-1:
Address Bank 0 00h( 2) 01h 02h( 2) 03h( 2) 04h( 2) 05h 06h 07h 08h 09h 0Ah( 1),( 2) 0Bh( 2) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG -- -- -- ADRES ADCON0 -- -- CHS3 -- SPEN -- RX9 WCOL SSPOV -- TOUTPS3 TOUTPS2 TMR1CS1 -- GIE TMR1GIF -- PEIE ADIF -- TMR0IE RCIF -- RB7 RC7 -- RB6 RC6 IRP RP1 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module Register Program Counter (PC) Least Significant Byte RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx RA2 -- RC2 RA1 -- RC1 RA0 -- RC0 --xx xxxx xxxx ---xxxx xxxx -- -- ---0 0000 0000 000x 0000 0000 -- xxxx xxxx xxxx xxxx TMR1ON 0000 -0-0 0000 0000 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx SSPM1 SSPM0 0000 0000 xxxx xxxx xxxx xxxx CCP1M1 OERR CCP1M0 RX9D --00 0000 0000 000x 0000 0000 0000 0000 -- -- -- xxxx xxxx CHS0 GO/ DONE ADON --00 0000 xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu --xx xxxx uuuu ---uuuu uuuu -- -- ---0 0000 0000 000x 0000 0000 -- uuuu uuuu uuuu uuuu uuuu -u-u 0000 0000 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 0000 000x 0000 0000 0000 0000 -- -- -- uuuu uuuu --00 0000
SPECIAL FUNCTION REGISTER SUMMARY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
Indirect Data Memory Address Pointer RA5 RB5 RC5 RA4 RB4 RC4 RA3 -- RC3
Unimplemented Unimplemented Write Buffer for the upper 5 bits of the Program Counter INTE TXIF RABIE SSPIF TMR0IF CCP1IF INTF TMR2IF RABIF TMR1IF
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1CS0 T1CKPS1 T1CKPS0 -- T1SYNC --
Timer2 module Register TOUTPS1 TOUTPS0
Synchronous Serial Port Receive Buffer/Transmit Register SSPEN CKP SSPM3 SSPM2
Capture/Compare/PWM Register Low Byte Capture/Compare/PWM Register High Byte DC1 SREN B1 CREN CCP1M3 ADDEN CCP1M2 FERR
AUSART Transmit Data Register AUSART Receive Data Register Unimplemented Unimplemented Unimplemented ADC Result Register CHS2 CHS1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2.
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TABLE 2-1:
Address Bank 1 80h( 2) 81h 82h( 2) 83h( 2) 84h( 2) 85h(5) 86h 87h 88h 89h 8Ah( 1),( 2) 8Bh( 2) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 93h( 3) 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_ REG PCL STATUS FSR TRISA TRISB TRISC -- -- PCLATH INTCON PIE1 -- PCON T1GCON OSCCON OSCTUNE PR2 SSPADD SSPMSK SSPSTAT WPUA IOCA -- TXSTA SPBRG -- -- -- FVRCON -- ADCON1 -- ADCS2 ADCS1 FVRRDY FVREN TSEN CSRC BRG7 TX9 BRG6 TXEN BRG5 SMP -- -- CKE -- -- D/A WPUA5 IOCA5 -- TMR1GE -- -- -- T1GPOL -- -- -- T1GTM IRCF1 TUN5 -- GIE TMR1GIE -- PEIE ADIE -- TMR0IE RCIE -- TRISB7 TRISC7 -- TRISB6 TRISC6 IRP RP1 Addressing this location uses contents of FSR to address data memory (not a physical register) RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 xxxx xxxx 1111 1111 0000 0000 DC C 0001 1xxx xxxx xxxx TRISA1 -- TRISC1 TRISA0 -- TRISC0 --11 -111 1111 ---1111 1111 -- -- ---0 0000 0000 000x 0000 0000 -- -- T1GGO/ DONE ICSL TUN3 -- T1GVAL ICSS TUN2 POR T1GSS1 -- TUN1 BOR T1GSS0 -- TUN0 ---- --qq 0000 0x00 --10 qq---00 0000 1111 1111 0000 0000 1111 1111 S WPUA3 IOCA3 R/W WPUA2 IOCA2 UA WPUA1 IOCA1 BF WPUA0 IOCA0 0000 0000 --11 1111 --00 0000 -- -- BRG3 BRGH BRG2 TRMT BRG1 TX9D BRG0 0000 -010 0000 0000 -- -- -- -- -- ADFVR1 ADFVR0 q000 --00 -- -- -- -- -- -000 ---xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu --11 -111 1111 ---1111 1111 -- -- ---0 0000 0000 000x 0000 0000 -- ---- --uu uuuu uxuu --10 qq---uu uuuu 1111 1111 0000 0000 1111 1111 0000 0000 --11 1111 --00 0000 -- 0000 -010 0000 0000 -- -- -- q000 --00 -- -000 ----
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
Program Counter (PC) Least Significant Byte RP0 TO PD Z
Indirect Data Memory Address Pointer TRISA5 TRISB5 TRISC5 TRISA4 TRISB4 TRISC4 Note 4 -- TRISC3 TRISA2 -- TRISC2
Unimplemented Unimplemented Write Buffer for the upper 5 bits of the Program Counter INTE TXIE RABIE SSPIE TMR0IF CCP1IE INTF TMR2IE RABIF TMR1IE
Unimplemented -- T1GSPM IRCF0 TUN4
Timer2 module Period Register ADD<7:0> MSK<7:0> P WPUA4 IOCA4
Unimplemented SYNC BRG4
Unimplemented Unimplemented Unimplemented TSRNG Unimplemented ADCS0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2.
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TABLE 2-1:
Address Bank 2 100h( 2) 101h 102h( 2) 103h( 2) 104h( 2) 105h 106h 107h 108h 109h 10Bh( 2) 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR -- -- -- -- -- -- GIE -- PEIE -- TMR0IE IRP RP1 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module Register Program Counter (PC) Least Significant Byte RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx -- -- -- -- -- ---0 0000 0000 000x xxxx xxxx 0000 0000 --xx xxxx ---0 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- 1111 ---0000 ----- -- -- -- -- -- -- -- -- xxxx xxxx uuuu uuuu 0000 0000 000q quuu uuuu uuuu -- -- -- -- -- ---0 0000 0000 000x xxxx xxxx 0000 0000 --xx xxxx ---0 0000 -- -- -- -- -- 1111 ---0000 ----- -- -- -- -- -- -- -- --
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Write Buffer for the upper 5 bits of the Program Counter INTE RABIE TMR0IF INTF RABIF
10Ah( 1),( 2) PCLATH INTCON PMDATL PMADRL PMDATH PMADRH -- -- -- -- -- WPUB IOCB -- -- -- -- -- -- -- -- --
Program Memory Read Data Register Low Byte Program Memory Read Address Register Low Byte -- -- -- -- -- Program Memory Read Data Register High Byte Program Memory Read Address Register High Byte Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented WPUB7 IOCB7 WPUB6 IOCB6 WPUB5 IOCB5 WPUB4 IOCB4 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2.
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TABLE 2-1:
Address Bank 3 180h( 2) 181h 182h( 2) 183h( 2) 184h( 2) 185h 186h 187h 188h 18Bh( 2) 18Ch 18Dh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_ REG PCL STATUS FSR ANSELA ANSELB ANSELC -- -- GIE --(4) -- PEIE CFGS -- TMR0IE LWLO -- -- ANSC7 -- -- ANSC6 IRP RP1 Addressing this location uses contents of FSR to address data memory (not a physical register) RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 xxxx xxxx 1111 1111 0000 0000 DC C 0001 1xxx xxxx xxxx ANSA2 -- ANSC2 ANSA1 -- ANSC1 ANSA0 -- ANSC0 ---1 -111 --11 ---11-- 1111 -- ---0 0000 0000 000x 1000 -000 ---- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu ---1 -111 --11 ---11-- 1111 -- ---0 0000 0000 000x 1000 -000 ---- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
Program Counter (PC) Least Significant Byte RP0 TO PD Z
Indirect Data Memory Address Pointer -- ANSB5 -- ANSA4 ANSB4 -- -- -- ANSC3
Unimplemented Write Buffer for the upper 5 bits of the Program Counter INTE FREE RABIE -- TMR0IF WREN INTF WR RABIF RD
18Ah( 1),( 2) PCLATH INTCON PMCON1 PMCON2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Program Memory Control Register 2 (not a physical register) Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2.
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2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 21.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.
REGISTER 2-1:
R/W-0 IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STATUS: STATUS REGISTER
R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC(1) R/W-x C(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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2.2.2.2 OPTION register
Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION register to `1'. Refer to Section 12.1.3 "Software Programmable Prescaler". The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: * Software programmable prescaler for the Timer0/ WDT * External RA2/INT interrupt * Timer0 * Weak pull-ups on PORTA or PORTB
REGISTER 2-2:
R/W-1 RABPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RABPU: PORTA or PORTB Pull-up Enable bit 1 = PORTA or PORTB pull-ups are disabled 0 = PORTA or PORTB pull-ups are enabled by individual bits in the WPUB register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
bit 6
bit 5
bit 4
bit 3
bit 2-0
000 001 010 011 100 101 110 111
1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
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2.2.2.3 PCON Register
The Power Control (PCON) register contains flag bits (refer to Table 3-4) to differentiate between a: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-3.
REGISTER 2-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR
PCON: POWER CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-q POR R/W-q BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
q = Value depends on condition bit 7-2 bit 1 Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)
bit 0
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2.3 PCL and PCLATH
Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).
2.4
Program Memory Paging
FIGURE 2-5:
PCH 12 PC 5 87
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 8 ALU Result Instruction with PCL as Destination
PCLATH<4:0>
PCLATH PCH 12 11 10 PC 2 PCLATH<4:3> 11 PCL 87 0 GOTO, CALL Opcode<10:0>
All devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is POPed off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
EXAMPLE 2-1:
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
2.3.2
STACK
All devices have an 8-level x 13-bit wide hardware stack (refer to Figures 2-1 and 2-2). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on).
ORG 500h PAGESEL SUB_P1 ;Select page 1 ;(800h-FFFh) CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : ORG 900h ;page 1 (800h-FFFh) SUB1_P1 : : RETURN ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh)
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2.5 Indirect Addressing, INDF and FSR Registers
EXAMPLE 2-2: INDIRECT ADDRESSING
MOVLW020h ;initialize pointer MOVWFFSR ;to RAM BANKISEL020h NEXTCLRFINDF ;clear INDF register INCFFSR ;inc pointer BTFSSFSR,4 ;all done? GOTONEXT ;no clear next CONTINUE ;yes continue
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-6. A simple program to clear RAM location 020h-02Fh using indirect addressing is shown in Example 2-2.
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Indirect Addressing 0 IRP 7 File Select Register0
Direct Addressing RP1 RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
7Fh Bank 0 Note: Bank 1 Bank 2 Bank 3
1FFh
For memory map detail, refer to Figures 2-3 and 2-4.
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NOTES:
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3.0 RESETS
The PIC16F/LF720/721 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 3-5. These bits are used in software to determine the nature of the Reset. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 23.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset (POR) MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR)
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
MCLRE
MCLR/VPP Sleep WDT Module WDT Time-out Reset
POR VDD Brown-out(1) Reset BOREN Power-on Reset
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKIN PWRT WDTOSC 11-bit Ripple Counter Chip_Reset
Enable PWRT Enable OST
Note
1:
Refer to the Configuration Word Register 1 (Register 8-1).
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TABLE 3-1:
POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset or LDO Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep or interrupt wake-up from Sleep Condition
TABLE 3-2:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Condition Program Counter 0000h 0000h 0000h 0000h PC + 1 0000h PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'.
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3.1 MCLR 3.3 Power-up Timer (PWRT)
The PIC16F/LF720/721 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 3-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull-up to VDD. In-Circuit Serial ProgrammingTM is not affected by selecting the internal MCLR option. The Power-up Timer provides a fixed 72 ms (nominal) time out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the WDT oscillator. For more information, see Section 7.3 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). Note: (Section 23.0
FIGURE 3-2:
VDD R1 10 k
RECOMMENDED MCLR CIRCUIT
PIC MCU
(R)
The Power-up Timer is enabled by the PWRTE bit in the Configuration Word.
3.4
Watchdog Timer (WDT)
The WDT has the following features: * Shares an 8-bit prescaler with Timer0 * Time-out period is from 17 ms to 2.2 seconds, nominal * Enabled by a Configuration bit WDT is cleared under certain conditions described in Table 3-3.
MCLR C1 0.1 F
3.4.1
WDT OSCILLATOR
3.2
Power-on Reset (POR)
The WDT derives its time base from 31 kHz internal oscillator.
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See Section 23.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 3.5 "Brown-Out Reset (BOR)"). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
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3.4.2 WDT CONTROL
The WDTE bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. The PSA and PS<2:0> bits of the OPTION register control the WDT period. See Section 12.0 "Timer0 Module" for more information.
FIGURE 3-1:
T1GSS = 11 TMR1GE
WATCHDOG TIMER BLOCK DIAGRAM
WDTE Low-Power WDT OSC
From TMR0 Clock Source
0 Divide by 512 Postscaler 1 8
PS<2:0> TO TMR0 PSA 0 1 WDT Reset To T1G WDTE
TABLE 3-3:
WDTE = 0
WDT STATUS
Conditions WDT Cleared
CLRWDT Command Exit Sleep + System Clock = INTOSC, EXTCLK
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3.5 Brown-Out Reset (BOR)
Brown-out Reset is enabled by programming the BOREN<1:0> bits in the Configuration register. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. Two bits are used to enable the BOR. When BOREN = 11, the BOR is always enabled. When BOREN = 10, the BOR is enabled, but disabled during Sleep. When BOREN = 0X, the BOR is disabled. If VDD falls below VBOR for greater than parameter (TBOR) (see Section 23.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOR for more than parameter (TBOR). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset.
FIGURE 3-3:
VDD
BROWN-OUT SITUATIONS
VBOR
Internal Reset VDD
64 ms(1)
VBOR < 64 ms
Internal Reset
64 ms(1)
VDD
VBOR
Internal Reset
64 ms(1)
Note 1:
64 ms delay only if PWRTE bit is programmed to `0'.
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3.6 Time-out Sequence 3.7 Power Control (PCON) Register
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit = 1 (PWRT disabled), there will be no time-out at all. Figure 3-4, Figure 3-5 and Figure 3-6 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC16F/LF720/721 device operating in parallel. Table 3-5 shows the Reset conditions for some special registers. The Power Control (PCON) register has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out Reset). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 3.5 "Brown-Out Reset (BOR)".
TABLE 3-4:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset PWRTE = 0 TPWRT PWRTE = 1 -- Wake-up from Sleep --
Oscillator Configuration PWRTE = 0 EC, INTOSC TPWRT PWRTE = 1 --
TABLE 3-5:
POR 0 1 u u u u u 0 u u u u
RESET BITS AND THEIR SIGNIFICANCE
BOR TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition
Legend: u = unchanged, x = unknown
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
Internal Reset
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FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
Internal Reset
FIGURE 3-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
Internal Reset
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TABLE 3-6:
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG ADRES ADCON0 OPTION_REG TRISA TRISB TRISC PIE1 Legend: Note 1: 2: 3: 4: 5:
INITIALIZATION CONDITION FOR REGISTERS
Address -- 00h/80h/ 100h/180h 01h/101h 02h/82h/ 102h/182h 03h/83h/ 103h/183h 04h/84h/ 104h/184h 05h 06h 07h 0Ah/8Ah/ 10Ah/18Ah 0Bh/8Bh/ 10Bh/18Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Eh 1Fh 81h/181h 85h 86h 87h 8Ch Power-on Reset/ Brown-out Reset(1) xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xxxx xxxx ---xxxx xxxx ---0 0000 0000 000x 0000 0000 xxxx xxxx xxxx xxxx 0000 -0-0 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx --00 0000 1111 1111 --11 -111 1111 ---1111 1111 0000 0000 MCLR Reset/ WDT Reset uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu --xx xxxx xxxx ---xxxx xxxx ---0 0000 0000 000x 0000 0000 uuuu uuuu uuuu uuuu 0000 -0-0 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 uuuu uuuu --00 0000 1111 1111 --11 -111 1111 ---1111 1111 0000 0000 Wake-up from Sleep through Interrupt/Time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu uuuu ---uuuu uuuu ---u uuuu uuuu uuuu(2) uuuu uuuu(2) uuuu uuuu uuuu uuuu uuuu -u-u uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu --uu -uuu uuuu ---uuuu uuuu uuuu uuuu
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 3-8 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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TABLE 3-6:
Register PCON T1GCON OSCCON OSCTUNE PR2 SSPADD SSPMSK SSPSTAT WPUB WPUA IOCB IOCA TXSTA SPBRG FVRCON ADCON1 PMDATL PMADRL PMDATH PMADRH ANSELA ANSELB ANSELC PMCON1 Legend: Note 1: 2: 3: 4: 5:
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address 8Eh 8Fh 90h 91h 92h 93h 93h 94h 115h 95h 116h 96h 98h 99h 9Dh 9Fh 10Ch 10Dh 10Eh 10Fh 185h 186h 187h 18Ch Power-on Reset/ Brown-out Reset(1) ---- --qq 0000 0x00 --10 qq---00 0000 1111 1111 0000 0000 1111 1111 0000 0000 1111 -----11 1111 0000 -----00 0000 0000 -010 0000 0000 q000 --00 -000 ---xxxx xxxx 0000 0000 --xx xxxx ---0 0000 ---1 -111 --11 ---11-- 1111 1000 -000 MCLR Reset/ WDT Reset ---- --uu(1,5) uuuu uxuu --10 qq---uu uuuu 1111 1111 0000 0000 1111 1111 0000 0000 1111 -----11 1111 0000 -----00 0000 0000 -010 0000 0000 q000 --00 -000 ---xxxx xxxx 0000 0000 --xx xxxx ---0 0000 ---1 -111 --11 ---11-- 1111 1000 -000 Wake-up from Sleep through Interrupt/Time-out ---- --uu uuuu uxuu --uu qq---uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -----uu uuuu uuuu -----uu uuuu uuuu -uuu uuuu uuuu uuuu --uu -uuu ---uuuu uuuu uuuu uuuu --uu uuuu ---u uuuu ---u -uuu --uu ---uu-- uuuu 1000 -000
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 3-8 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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TABLE 3-7: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Program Counter 0000h 0000h 0000h 0000h PC + 1 0000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1xxx uuu1 0uuu
PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
TABLE 3-8:
Name STATUS PCON
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Bit 7 IRP -- Bit 6 RP1 -- Bit 5 RP0 -- Bit 4 TO -- Bit 3 PD -- Bit 2 Z -- Bit 1 DC POR Bit 0 C BOR Value on POR, BOR 0001 1xxx ---- --qq Value on all other Resets(1) 000q quuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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4.0 INTERRUPTS
The PIC16F/LF720/721 device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. The PIC16F/LF720/721 device family has 12 interrupt sources, differentiated by corresponding interrupt enable and flag bits: * * * * * * * * * * * Timer0 Overflow Interrupt External Edge Detect on INT Pin Interrupt PORTA and PORTB Change Interrupt Timer1 Gate Interrupt A/D Conversion Complete Interrupt AUSART Receive Interrupt AUSART Transmit Interrupt SSP Event Interrupt CCP1 Event Interrupt Timer2 Match with PR2 Interrupt Timer1 Overflow Interrupt
A block diagram of the interrupt logic is shown in Figure 4-1.
FIGURE 4-1:
INTERRUPT LOGIC
IOC-RB4 IOCB4 IOC-RB5 IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5
SSPIF SSPIE TXIF TXIE RCIF RCIE TMR2IF TMR2IE TMR1IF TMR1IE ADIF ADIE TMR1GIF TMR1GIE CCP1IF CCP1IE TMR0IF TMR0IE INTF INTE RABIF RABIE PEIE GIE Wake-up (if in Sleep mode)(1) Interrupt to CPU
Note 1:
Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, these peripherals will not wake the part from Sleep. See Section 19.1 "Wake-up from Sleep".
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4.1 Operation
Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 register) The INTCON and PIR1 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual Interrupt Enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * PC is loaded with the interrupt vector 0004h The ISR determines the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its Interrupt Flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.
4.2
Interrupt Latency
Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 instruction cycles. For asynchronous interrupts, the latency is 3 to 4 instruction cycles, depending on when the interrupt occurs. See Figure 4-2 for timing details.
FIGURE 4-2:
Q1 OSC1 CLKOUT (3)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(4)
INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
(1) (5)
(1)
Interrupt Latency (2)
PC
PC + 1 Inst (PC + 1)
PC + 1 --
0004h Inst (0004h)
0005h Inst (0005h) Inst (0004h)
Inst (PC)
Inst (PC - 1)
Inst (PC)
Dummy Cycle
Dummy Cycle
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 23.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
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4.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 19.0 "Power-Down Mode (Sleep)" for more details. following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and PCLATH registers. Note: The microcontroller does not normally require saving the PCLATH register. However, if computed GOTOs are used, the PCLATH register must be saved at the beginning of the ISR and restored when the ISR is complete to ensure correct program flow.
The code shown in Example 4-1 can be used to do the following. * * * * * * * Save the W register Save the STATUS register Save the PCLATH register Execute the ISR program Restore the PCLATH register Restore the STATUS register Restore the W register
4.4
INT Pin
The external interrupt, INT pin, causes an asynchronous, edge-triggered interrupt. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. This interrupt is disabled by clearing the INTE bit of the INTCON register.
4.5
Context Saving
Since most instructions modify the W register, it must be saved immediately upon entering the ISR. The SWAPF instruction is used when saving and restoring the W and STATUS registers because it will not affect any bits in the STATUS register. It is useful to place W_TEMP in shared memory because the ISR cannot predict which bank will be selected when the interrupt occurs. The processor will branch to the interrupt vector by loading the PC with 0004h. The PCLATH register will remain unchanged. This requires the ISR to ensure that the PCLATH register is set properly before using an instruction that causes PCLATH to be loaded into the PC. See Section 2.3 "PCL and PCLATH" for details on PC operation.
When an interrupt occurs, only the return PC value is saved to the stack. If the ISR modifies or uses an instruction that modifies key registers, their values must be saved at the beginning of the ISR and restored when the ISR completes. This prevents instructions
EXAMPLE 4-1:
MOVWFW_TEMP SWAPFSTATUS,W
SAVING W, STATUS AND PCLATH REGISTERS IN RAM
;Copy W to W_TEMP register ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits BANKSELSTATUS_TEMP ;Select regardless of current bank MOVWFSTATUS_TEMP ;Copy status to bank zero STATUS_TEMP register MOVF PCLATH,W ;Copy PCLATH to W register MOVWF PCLATH_TEMP ;Copy W register to PCLATH_TEMP : :(ISR) ;Insert user code here : BANKSELSTATUS_TEMP ;Select regardless of current bank MOVF PCLATH_TEMP,W; MOVWF PCLATH ;Restore PCLATH SWAPFSTATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWFSTATUS ;Move W into STATUS register SWAPFW_TEMP,F ;Swap W_TEMP SWAPFW_TEMP,W ;Swap W_TEMP into W
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4.5.1 INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RA2/INT pin interrupts.
REGISTER 4-1:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 RABIE(1) R/W-0 TMR0IF
(2)
R/W-0 INTF
R/W-x RABIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt RABIE: PORTA or PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTA or PORTB change interrupt 0 = Disables the PORTA or PORTB change interrupt TMR0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur RABIF: PORTA or PORTB Change Interrupt Flag bit 1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTA or PORTB general purpose I/O pins have changed state The appropriate bits in the IOCB register must also be set. TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing TMR0IF bit.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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4.5.2 PIE1 REGISTER
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 4-2.
REGISTER 4-2:
R/W-0 TMR1GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enable the Timer1 gate acquisition complete interrupt 0 = Disable the Timer1 gate acquisition complete interrupt ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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4.5.3 PIR1 REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 4-3.
REGISTER 4-3:
R/W-0 TMR1GIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer1 gate is inactive 0 = Timer1 gate is active ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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TABLE 4-1:
Name INTCON OPTION_REG PIE1 PIR1
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7 GIE RABPU TMR1GIE TMR1GIF Bit 6 PEIE INTEDG ADIE ADIF Bit 5 TMR0IE T0CS RCIE RCIF Bit 4 INTE T0SE TXIE TXIF Bit 3 RABIE PSA SSPIE SSPIF Bit 2 TMR0IF PS2 CCP1IE CCP1IF Bit 1 INTF PS1 Bit 0 RABIF PS0 Value on POR, BOR Value on all other Resets
0000 000x 0000 000x 1111 1111 1111 1111
TMR2IE TMR1IE 0000 0000 0000 0000 TMR2IF TMR1IF 0000 0000 0000 0000
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.
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NOTES:
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5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR
The PIC16F720/721 devices differ from the PIC16LF720/721 devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F720/721 contain an internal LDO, while the PIC16LF720/721 do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die. The LDO voltage regulator allows for the internal digital logic to operate at 3.2V, while I/O's operate at 5.0V (VDD).
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NOTES:
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6.0 I/O PORTS
6.1.1 WEAK PULL-UPS
There are as many as eighteen general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Each of the PORTA pins has an individually configurable internal weak pull-up. Control bits WPUA<5:0> enable or disable each pull-up (see Register 6-5). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the RABPU bit of the OPTION register.
6.1
PORTA and the TRISA Registers
6.1.2
INTERRUPT-ON-CHANGE
PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 6-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 6-1 shows how to initialize PORTA. Reading the PORTA register (Register 6-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISA register (Register 6-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
All of the PORTA pins are individually configurable as an interrupt-on-change pin. Control bits IOCA<5:0> enable or disable the interrupt function for each pin (see Register 6-6). The interrupt-on-change feature is disabled on a Power-on Reset. For enable interrupt-on-change pins, the present value is compared with the old value latched on the last read of PORTA to determine which bits have changed or mismatched the old value. The `mismatch' outputs of the last read are OR'd together to set the PORTA Change Interrupt Flag bit (RABIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: 1. 2. Any read or write of PORTA. This will end the mismatch condition. Clear the flag bit RABIF.
A mismatch condition will continue to set flag bit RABIF. Reading or writing PORTA will end the mismatch condition and allow flag bit RABIF to be cleared. The latch holding the last read value is not affected by a MCLR or Brown-out Reset. After these Resets, the RABIF flag will continue to be set if a mismatch is present. Note: When a pin change occurs at the same time as a read operation on PORTA, the RABIF flag will always be set. If multiple PORTA pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state.
EXAMPLE 6-1:
BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA ANSELA ANSELA TRISA 0Ch TRISA
INITIALIZING PORTA
; ;Init PORTA ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs
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REGISTER 6-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PORTA: PORTA REGISTER
U-0 -- R/W-x RA5 R/W-x RA4 R/W-x RA3(1) R/W-x RA2 R/W-x RA1 R/W-x RA0 bit 0
Unimplemented: Read as `0' RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL PORTA<3> is input only.
Note 1:
REGISTER 6-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
TRISA: PORTA TRI-STATE REGISTER
U-0 -- R/W-1 TRISA5 R/W-1 TRISA4 U-1 --(1) R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TRISA<5:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output TRISA<3> is unimplemented and read as 1.
Note 1:
REGISTER 6-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
WPUA: WEAK PULL-UP PORTA REGISTER
U-0 -- R/W-1 WPUA5 R/W-1 WPUA4 R/W-1 WPUA3(2) R/W-1 WPUA2 R/W-1 WPUA1 R/W-1 WPUA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' WPUA<5:0>: Weak Pull-up PORTA Control bits 1 = Weak pull-up enabled( 1) 0 = Weak pull-up disabled
Note 1: Enabling weak pull-ups also requires that the RABPU bit of the OPTION register be cleared. 2: If MCLREN = 1, WPUA3 is always enabled.
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REGISTER 6-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 -- R/W-0 IOCA5 R/W-0 IOCA4 R/W-0 IOCA3 R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0 bit 0
Unimplemented: Read as `0' IOCA<5:0>: Interrupt-on-Change PORTA Control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled
Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set.
6.1.3
ANSELA REGISTER
The ANSELA register (Register 6-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.
REGISTER 6-5:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
ANSELA: PORTA ANALOG SELECT REGISTER
U-0 -- U-0 -- R/W-1 ANSA4 U-0 -- R/W-1 ANSA2 R/W-1 ANSA1 R/W-1 ANSA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ANSA: Analog Select between Analog or Digital Function on Pin RA<4> 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer is disabled. Unimplemented: Read as `0' ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer is disabled. Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external control of the voltage on the pin.
bit 3 bit 2-0
Note 1:
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6.1.4 PIN DESCRIPTIONS AND DIAGRAMS 6.1.4.3 RA2/AN2/T0CKI/INT
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the A/D Converter (ADC), refer to the appropriate section in this data sheet. Figure 6-3 shows the diagram for this pin. This pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the ADC external interrupt clock input for Timer0
6.1.4.1
RA0/AN0/ICSPDAT
Figure 6-1 shows the diagram for this pin. This pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the ADC * ICSP programming data (separate controls from TRISA) * ICD Debugging data (separate controls from TRISA)
The Timer0 clock input function works independently of any TRIS register setting. Effectively, if TRISA2 = 0, the PORTA2 register bit will output to the pad and Clock Timer0 at the same time.
6.1.4.4
RA3/MCLR/VPP
Figure 6-4 shows the diagram for this pin. This pin is configurable to function as one of the following: * a general purpose I/O * Master Clear Reset with weak pull-up
6.1.4.2
RA1/AN1/ICSPCLK 6.1.4.5 RA4/AN3/T1G/CLKOUT
Figure 6-5 shows the diagram for this pin. This pin is configurable to function as one of the following: * * * * a general purpose I/O analog input for the ADC Timer1 gate input clock output
Figure 6-2 shows the diagram for this pin. This pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the ADC * ICSP programming clock (separate controls from TRISA) * ICD Debugging clock (separate controls from TRISA)
6.1.4.6
RA5/T1CKI/CLKIN
Figure 6-6 shows the diagram for this pin. This pin is configurable to function as one of the following: * a general purpose I/O * Timer1 Clock input * clock input
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PIC16F/LF720/721
FIGURE 6-1: BLOCK DIAGRAM OF RA0
ICSPTM mode DEBUG Data Bus D WR WPUA RD WPUA Q
Analog(1) Input mode VDD Weak RABPU
CK Q
PORT_ICDDAT 1 0 D Q
1 0
VDD
WR PORTA
CK Q
I/O Pin
0
VSS
1
D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA
Q
TRIS_ICDDAT
CK Q
Analog(1) Input mode
Q
CK Q Q D EN Q D EN Q3
Interrupt-on-Change
RD PORTA ICSPDAT
To A/D Converter
Note
1:
ANSEL determines Analog Input mode.
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FIGURE 6-2: BLOCK DIAGRAM OF RA1
Data Bus
D
Q
Analog(1) Input mode VDD Weak RABPU
ICSPTM mode DEBUG
WR WPUA
CK Q
RD WPUA
D WR PORTA
Q
PORT_ICDCLK 1 0
1 0
VDD
CK Q
I/O Pin
D WR TRISA
Q
0
CK Q
1
VSS
RD TRISA
Analog(1) Input mode
RD PORTA D WR IOCA Q Q D EN RD IOCA Q Interrupt-on-Change EN D Q3
TRIS_ICDCLK
CK Q
RD PORTA To A/D Converter ICSPCLK
Note
1:
ANSEL determines Analog Input mode.
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FIGURE 6-3: BLOCK DIAGRAM OF RA2
Data Bus WR WPUA RD WPUA D CK Q Q RABPU Analog(1) Input mode VDD Weak To Voltage Regulator (for PIC16F720/721 only)
D WR PORTA CK
Q Q
VDD
I/O Pin D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA CK Q Q Q EN Q D EN Q3 D CK Q Q Analog(1) Input mode VSS
Interrupt-onChange
RD PORTA
To Timer0 To INT To A/D Converter
Note
1:
ANSEL determines Analog Input mode.
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FIGURE 6-4: BLOCK DIAGRAM OF RA3
VDD MCLRE Weak Data Bus Data Bus Reset VSS MCLRE VSS RD WPUA RABPU MCLRE WR WPUA D CK Q Q
FIGURE 6-5:
BLOCK DIAGRAM OF RA4
Analog(2) Input mode
CLK modes VDD Weak
Input Pin
RD TRISA RD PORTA D WR IOCA RD IOCA CK Q
Q Q
D EN Q3 WR PORTA D CK Q Q
CLKOUT Enable FOSC/4 1 0 CLKOUT Enable
VDD
I/O Pin
Q
D EN
Interrupt-onChange
VSS D Q Q WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA CK Q Q Q EN Q D EN Q3 D CK INTOSC/ RC/EC(1) CLKOUT Enable Analog Input mode
RD PORTA
Interrupt-onChange
RD PORTA To T1G To A/D Converter Note 1: 2: With CLKOUT option. ANSEL determines Analog Input mode.
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FIGURE 6-6: BLOCK DIAGRAM OF RA5
INTOSC mode Data Bus WR WPUA RD WPUA D CK Q Q RABPU VDD Weak
D WR PORTA CK
Q Q
VDD
I/O Pin D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA Q D EN Interrupt-onChange RD PORTA To TMR1 or CLKIN CK Q Q Q EN Q3 D CK Q Q INTOSC mode VSS
TABLE 6-1:
Name ADCON0 ANSELA OPTION_REG PORTA TRISA Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- RABPU -- -- Bit 6 -- -- INTEDG -- -- Bit 5 CHS3 -- T0CS RA5 TRISA5 Bit 4 CHS2 ANSA4 T0SE RA4 TRISA4 Bit 3 CHS1 -- PSA RA3 -- Bit 2 CHS0 ANSA2 PS2 RA2 TRISA2 Bit 1 GO/DONE ANSA1 PS1 RA1 TRISA1 Bit 0 ADON ANSA0 PS0 RA0 TRISA0 Value on POR, BOR --00 0000 ---1 -111 1111 1111 --xx xxxx --11 -111 Value on all other Resets --00 0000 ---1 -111 1111 1111 --xx xxxx --11 -111
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
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6.2 PORTB and TRISB Registers
6.2.1 ANSELB REGISTER
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 6-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-2 shows how to initialize PORTB. Reading the PORTB register (Register 6-6) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISB register (Register 6-7) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Example 6-2 shows how to initialize PORTB. The ANSELB register (Register 6-10) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no affect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.
6.2.2
WEAK PULL-UPS
Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:4> enable or disable each pull-up (see Register 6-8). Each weak pullup is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the RABPU bit of the OPTION register.
6.2.3
INTERRUPT-ON-CHANGE
EXAMPLE 6-2:
BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTB
PORTB ; PORTB ;Init PORTB ANSELB ANSELB ;Make RB<7:4> digital TRISB ; B'11110000';Set RB<7:4> as inputs TRISB ;
All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:4> enable or disable the interrupt function for each pin. Refer to Register 6-9. The interrupt-on-change feature is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the present value is compared with the old value latched on the last read of PORTB to determine which bits have changed or mismatched the old value. The `mismatch' outputs of the last read are OR'd together to set the PORTB Change Interrupt Flag bit (RABIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear the flag bit RABIF.
Note:
The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
A mismatch condition will continue to set flag bit RABIF. Reading or writing PORTB will end the mismatch condition and allow flag bit RABIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RABIF flag will continue to be set if a mismatch is present. Note: When a pin change occurs at the same time as a read operation on PORTB, the RABIF flag will always be set. If multiple PORTB pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state.
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REGISTER 6-6:
R/W-x RB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PORTB: PORTB REGISTER
R/W-x RB6 R/W-x RB5 R/W-x RB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
RB<7:4>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL Unimplemented: Read as `0'
bit 3-0
REGISTER 6-7:
R/W-1 TRISB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4
TRISB: PORTB TRI-STATE REGISTER
R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISB<7:4>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output Unimplemented: Read as `0'
bit 3-0
REGISTER 6-8:
R/W-1 WPUB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4
WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
WPUB<7:4>: Weak Pull-up PORTB Control bits 1 = Weak pull-up enabled (1,2) 0 = Weak pull-up disabled Unimplemented: Read as `0' Global RABPU bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output.
bit 3-0 Note 1: 2:
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REGISTER 6-9:
R/W-0 IOCB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 IOCB6 R/W-0 IOCB5 R/W-0 IOCB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IOCB<7:4>: Interrupt-on-Change PORTB Control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled Unimplemented: Read as `0'
bit 3-0
Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set.
REGISTER 6-10:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4
ANSELB: PORTB ANALOG SELECT REGISTER
U-0 -- R/W-1 ANSB5 R/W-1 ANSB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ANSB<5:4>: Analog Select between Analog or Digital Function on Pins RB<5:4>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Unimplemented: Read as `0' Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user, in order to allow external control of the voltage on the pin.
bit 3-0 Note 1:
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6.2.4 PIN DESCRIPTIONS AND DIAGRAMS FIGURE 6-7:
Data Bus WR WPUB RD WPUB D Q
Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the SSP, I2CTM or interrupts, refer to the appropriate section in this data sheet.
BLOCK DIAGRAM OF RB4
Analog(1) Input mode VDD Weak RABPU
CK Q
6.2.4.1
RB4/AN10/SDI/SDA
Figure 6-7 shows the diagram for this pin. The RB4 pin is configurable to function as one of the following: * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * Analog input for the A/D * Synchronous Serial Port Input (SPI) * I2C data I/O
D WR PORTB
Q
SSPEN SSP 1 0
1 0
VDD
CK Q
I/O Pin
D WR TRISB RD TRISB RD PORTB D WR IOCB RD IOCB CK
Q Q
6.2.4.2
RB5/AN11/RX/DT
From 0 1 SSP VSS
1 0
Figure 6-8 shows the diagram for this pin. The RB5 pin is configurable to function as one of the following: * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * Analog input for the A/D * USART asynchronous receive * USART synchronous receive
Analog(1) Input mode
Q Q D EN Q D ST EN Q3
CK Q
6.2.4.3
RB6/SCK/SCL
Figure 6-9 shows the diagram for this pin. The RB6 pin is configurable to function as one of the following: * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * Synchronous Serial Port clock for both SPI and I2C
Interrupt-onChange RD PORTB To SSP To A/D Converter
6.2.4.4
RB7/TX/CK
Note 1:
Figure 6-10 shows the diagram for this pin. The RB7 pin is configurable to function as one of the following: * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * USART asynchronous transmit * USART synchronous clock
ANSEL determines Analog Input mode.
2010 Microchip Technology Inc.
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FIGURE 6-8:
Data Bus WR WPUB RD WPUB
BLOCK DIAGRAM OF RB5
Analog(1) Input mode VDD Weak RABPU SYNC SPEN
FIGURE 6-9:
Data Bus WR WPUB RD WPUB D Q
BLOCK DIAGRAM OF RB6
VDD Weak RABPU
D
Q
CK Q
CK Q
D D WR PORTB Q AUSART DT 0 1
1 0
Q
SSPEN SSP Clock 0 1
1 0 From SSP 0 1
VDD
VDD
WR PORTB
CK Q
CK Q
I/O Pin
D WR TRISB RD TRISB RD PORTB D WR IOCB RD IOCB
Q
From AUSART 0 1 0 1 Analog(1) Input mode VSS
I/O Pin WR TRISB RD TRISB RD PORTB
D CK
Q Q
1 0
VSS
CK Q
D Q Q D EN Q D ST EN Interrupt-onChange Q3 WR IOCB RD IOCB
Q Q D EN Q D ST EN Q3
CK Q
CK Q
Interrupt-onChange RD PORTB To AUSART RX/DT To A/D Converter To SSP
RD PORTB
Note
1:
ANSEL determines Analog Input mode.
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PIC16F/LF720/721
FIGURE 6-10:
Data Bus WR WPUB RD WPUB D Q
BLOCK DIAGRAM OF RB7
VDD Weak RABPU SPEN TXEN SYNC AUSART CK 0 1 AUSART TX 1 0 1 0 0 1
CK Q
D WR PORTB
Q
VDD
CK Q
D WR TRISB RD TRISB RD PORTB D WR IOCB RD IOCB
Q `1' 1 0
1 0
I/O Pin
CK Q
VSS
Q Q D EN Q D EN Q3
CK Q
Interrupt-onChange RD PORTB
TABLE 6-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR --00 0000 --11 ---0000 000x 0000 ---1111 1111 xxxx ---0000 0x00 1111 ---1111 ---0000 000x 0000 0000 0000 0000 Value on all other Resets --00 0000 --11 ---0000 000x 0000 ---1111 1111 uuuu ---uuuu uxuu 1111 ---1111 ---0000 000x 0000 0000 0000 0000
ADCON0 ANSELB INTCON IOCB OPTION_REG PORTB T1GCON TRISB WPUB RCSTA TXREG RCREG Legend:
--
-- GIE IOCB7 RABPU RB7 TMR1GE TRISB7 WPUB7 SPEN
--
-- PEIE IOCB6 INTEDG RB6 T1GPOL TRISB6 WPUB6 RX9
CHS3 ANSB5 TMR0IE IOCB5 T0CS RB5 T1GTM TRISB5 WPUB5 SREN
CHS2 ANSB4 INTE IOCB4 T0SE RB4 T1GSPM TRISB4 WPUB4 CREN
CHS1 -- RABIE -- PSA -- T1GGO/ DONE -- -- ADDEN
CHS0 -- TMR0IF -- PS2 -- T1GVAL -- -- FERR
GO/DONE -- INTF -- PS1 -- T1GSS1 -- -- OERR
ADON -- RABIF -- PS0 -- T1GSS0 -- -- RX9D
AUSART Transmit Data Register AUSART Receive Data Register
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB.
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6.3 PORTC and TRISC Registers
PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 6-12). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-3 shows how to initialize PORTC. Reading the PORTC register (Register 6-11) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISC register (Register 6-12) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'.
EXAMPLE 6-3:
BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTC
; ;Init PORTC ; ;Set RC<3:2> as inputs ;and set RC<7:4,1:0> ;as outputs
PORTC PORTC TRISC B`00001100' TRISC
6.3.1
ANSELC REGISTER
The ANSELC register (Register 6-13) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.
REGISTER 6-11:
R/W-x RC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PORTC: PORTC REGISTER
R/W-x RC6 R/W-x RC5 R/W-x RC4 R/W-x RC3 R/W-x RC2 R/W-x RC1 R/W-x RC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL
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REGISTER 6-12:
R/W-1 TRISC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
TRISC6
TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output
REGISTER 6-13:
R/W-1 ANSC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6
ANSELC: ANALOG SELECT REGISTER FOR PORTC
U-0 -- U-0 -- R/W-1 ANSC3 R/W-1 ANSC2 R/W-1 ANSC1 R/W-1 ANSC0 bit 0
R/W-1 ANSC6
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ANSC<7:6>: Analog Select between Analog or Digital Function on Pins RB<7:6>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Unimplemented: Read as `0' ANSC<3:0>: Analog Select between Analog or Digital Function on Pins RC<3:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 5-4 bit 3-0
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external control of the voltage on the pin.
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6.3.2 RC0/AN4 FIGURE 6-11:
Data Bus
Figure 6-11 shows the diagram for this pin. The RC0 pin is configurable to function as one of the following: * general purpose I/O * analog input for the A/D
BLOCK DIAGRAM OF RC0 AND RC1
D WR PORTC CK
Q Q
VDD
6.3.3
RC1/AN5
Figure 6-11 shows the diagram for this pin. The RC1 pin is configurable to function as one of the following: * general purpose I/O * analog input for the A/D
WR TRISC RD TRISC RD PORTC
I/O Pin D CK Q Q Analog Input mode(1) VSS
6.3.4
RC2/AN6
Figure 6-12 shows the diagram for this pin. The RC2 pin is configurable to function as one of the following: * general purpose I/O * analog input for the A/D
To A/D Converter
6.3.5
RC3/AN7
Note 1: ANSEL determines Analog Input mode.
Figure 6-12 shows the diagram for this pin. The RC3 pin is configurable to function as one of the following: * general purpose I/O * analog input for the A/D
FIGURE 6-12: 6.3.6 RC4
Data Bus
BLOCK DIAGRAM OF RC2 AND RC3
Figure 6-13 shows the diagram for this pin. The RC4 pin functions as one of the following: * general purpose I/O
D WR PORTC CK
Q Q
VDD
6.3.7
RC5/CCP1
Figure 6-14 shows the diagram for this pin. The RC5 pin is configurable to function as one of the following: * general purpose I/O * Capture, Compare or PWM (1 output)
I/O Pin D WR TRISC RD TRISC RD PORTC CK Q Q Analog Input mode(1) VSS
6.3.8
RC6/AN8/SS
Figure 6-15 shows the diagram for this pin. The RC6 pin is configurable to function as one of the following: * general purpose I/O * analog input for the A/D * SS input to SSP
To A/D Converter
6.3.9
RC7/AN9/SDO
Note 1: ANSEL determines Analog Input mode.
Figure 6-16 shows the diagram for this pin. The RC7 pin is configurable to function as one of the following: * general purpose I/O * analog input for the A/D * SDO output of SSP
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FIGURE 6-13: BLOCK DIAGRAM OF RC4
VDD
FIGURE 6-15:
Data Bus
BLOCK DIAGRAM OF RC6
D Data Bus D WR PORTC Q VSS WR TRISC RD TRISC RD PORTC I/O Pin WR PORTC CK
Q Q
VDD
CK Q
I/O Pin D CK Q Q Analog Input mode(1) VSS
D WR TRISC RD TRISC RD PORTC
Q
CK Q
To SS Input To A/D Converter
Note
1:
ANSEL determines Analog Input mode.
FIGURE 6-14:
Data bus
BLOCK DIAGRAM OF RC5
CCP1OUT Enable
FIGURE 6-16:
VDD
BLOCK DIAGRAM OF RC7
PORT/SDO Select
D WR PORTC CK
Q Q CCP1OUT 1 0
Data Bus
1 0
SDO I/O Pin D VSS WR PORTC CK Q Q
1 0
1 0
D WR TRISC RD TRISC RD PORTC To CCP1 input CK
Q Q
VDD
I/O Pin D WR TRISC RD TRISC RD PORTC To A/D Converter CK Q Q Analog Input mode(1) VSS
Note
1:
ANSEL determines Analog Input mode.
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TABLE 6-3:
Name TRISC PORTC ANSELC ADCON0 SSPCON CCP1CON Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 TRISC7 RC7 ANSC7 -- WCOL -- Bit 6 TRISC6 RC6 ANSC6 -- SSPOV -- Bit 5 TRISC5 RC5 -- CHS3 SSPEN DC1 Bit 4 TRISC4 RC4 -- CHS2 CKP B1 Bit 3 TRISC3 RC3 ANSC3 CHS1 SSPM3 CCP1M3 Bit 2 TRISC2 RC2 ANSC2 CHS0 SSPM2 CCP1M2 Bit 1 TRISC1 RC1 ANSC1 GO/DONE SSPM1 CCP1M1 Bit 0 TRISC0 RC0 ANSC0 ADON SSPM0 CCP1M0 Value on POR, BOR 1111 1111 xxxx xxxx 11-- 1111 --00 0000 0000 0000 --00 0000 Value on all other Resets 1111 1111 uuuu uuuu 11-- 1111 --00 0000 0000 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC.
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7.0
7.1
OSCILLATOR MODULE
Overview
Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation. 1. 2. 3. 4. EC - CLKOUT function on RA4/CLKOUT pin, CLKIN on RA5/CLKIN. EC - I/O function on RA4/CLKOUT pin, CLKIN on RA5/CLKIN. INTOSC - CLKOUT function on RA4/CLKOUT pin, I/O function on RA5/CLKIN INTOSCIO - I/O function on RA4/CLKOUT pin, I/O function on RA5/CLKIN
The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 7-1 illustrates a block diagram of the oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system can be configured to use an internal calibrated high-frequency oscillator as clock source, with a choice of selectable speeds via software.
FIGURE 7-1:
SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word 1)
CLKIN
EC MUX
Internal Oscillator MFINTOSC 500 kHz 0 MUX
IRCF<1:0> (OSCCON Register) INTOSC 16 MHz/500 kHz
System Clock (CPU and Peripherals)
11
32x PLL
1 Postscaler HFINTOSC
8 MHz/250 kHz
10 MUX 01 00
4 MHz/125 kHz
2 MHz/62.5 kHz
PLLEN (Configuration Word 1)
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7.2 Clock Source Modes
7.3.2 FREQUENCY SELECT BITS (IRCF)
Clock source modes can be classified as external or internal. * Internal clock source (INTOSC) is contained within the oscillator module and derived from a 500 kHz high precision oscillator. The oscillator module has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. * The external clock mode (EC) relies on an external signal for the clock source. The system clock can be selected between external or internal clock sources via the FOSC bits of the Configuration Word 1. The output of the 500 kHz MFINTOSC and 16 MHz HFINTOSC, with Phase Locked Loop enabled, connect to a postscaler and multiplexer (see Figure 7-1). The Internal Oscillator Frequency Select bits (IRCF) of the OSCCON register select the frequency output of the internal oscillator. Depending upon the PLLEN bit, one of four frequencies of two frequency sets can be selected via software: If PLLEN = 1, HFINTOSC frequency selection is as follows: * * * * 16 MHz 8 MHz (default after Reset) 4 MHz 2 MHz
7.3
Internal Clock Modes
The oscillator module has eight output frequencies derived from a 500 kHz high precision oscillator. The IRCF bits of the OSCCON register select the postscaler applied to the clock source dividing the frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the Configuration Word 1 locks the internal clock source to 16 MHz before the postscaler is selected by the IRCF bits. The PLLEN bit must be set or cleared at the time of programming; therefore, only the upper or low four clock source frequencies are selectable in software. Internal clock sources are contained internally within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase Locked Loop that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 500 kHz (MFINTOSC). Both can be user-adjusted via software using the OSCTUNE register (Register 7-2).
If PLLEN = 0, MFINTOSC frequency selection is as follows: * * * * 500 kHz 250 kHz (default after Reset) 125 kHz 62.5 kHz Note: Following any Reset, the IRCF<1:0> bits of the OSCCON register are set to `10' and the frequency selection is set to 8 MHz or 250 kHz. The user can modify the IRCF bits to select a different frequency.
There is no start-up delay before a new frequency selected in the IRCF bits takes effect. This is because the old and new frequencies are derived from INTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the Table 23-2 in Section 23.0 "Electrical Specifications".
7.3.1
INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the CONFIG1 register. See Section 8.0 "Device Configuration" for more information. In INTOSC mode, CLKIN is available for general purpose I/O. CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, CLKIN and CLKOUT are available for general purpose I/O.
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7.4 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 7-1) displays the status and allows frequency selection of the internal oscillator (INTOSC) system clock. The OSCCON register contains the following bits: * Frequency selection bits (IRCF) * Status Locked bits (ICSL) * Status Stable bits (ICSS)
REGISTER 7-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR
OSCCON: OSCILLATOR CONTROL REGISTER
U-0 -- R/W-1 IRCF1 R/W-0 IRCF0 R-q ICSL R-q ICSS U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
q = Value depends on condition bit 7-6 bit 5-4 Unimplemented: Read as `0' IRCF<1:0>: Internal Oscillator Frequency Select bits
When PLLEN = 1 (16 MHz HFINTOSC) 11 = 16 MHz 10 = 8 MHz (POR value) 01 = 4 MHz 00 = 2 MHz When PLLEN = 0 (500 kHz MFINTOSC) 11 = 500 kHz 10 = 250 kHz (POR value) 01 = 125 kHz 00 = 62.5 kHz
bit 3
ICSL: Internal Clock Oscillator Status Locked bit (2% Stable) 1 = 16 MHz/500 kHz internal oscillator is in lock 0 = 16 MHz/500 kHz internal oscillator has not yet locked ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable) 1 = 16 MHz/500 kHz internal oscillator has stabilized to its maximum accuracy 0 = 16 MHz/500 kHz internal oscillator has not yet reached its maximum accuracy Unimplemented: Read as `0'
bit 2
bit 1-0
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7.5 Oscillator Tuning
The INTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 7-2). The default value of the OSCTUNE register is `0'. The value is a 6-bit two's complement number. When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
REGISTER 7-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TUN<5:0>: Frequency Tuning bits 01 1111 = Maximum frequency 01 1110 = * * * 00 0001 = 00 0000 = Oscillator module is running at the factory-calibrated frequency. 11 1111 = * * * 10 0000 = Minimum frequency
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7.6
7.6.1
External Clock Modes
EC MODE
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the CLKOUT input and the CLKIN is available for general purpose I/O. Figure 7-2 shows the pin connections for EC mode.
FIGURE 7-2:
EXTERNAL CLOCK (EC) MODE OPERATION
Clock from Ext. System
CLKIN PIC(R) MCU I/O CLKOUT
TABLE 7-1:
Name CONFIG1(1) OSCCON OSCTUNE Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 -- -- -- Bit 6 CP -- -- Bit 5 MCLRE IRCF1 TUN5 Bit 4 PWRTE IRCF0 TUN4 Bit 3 WDTEN ICSL TUN3 Bit 2 -- ICSS TUN2 Bit 1 FOSC1 -- TUN1 Bit 0 FOSC0 -- TUN0 Value on POR, BOR -- --10 qq---00 0000 Value on all other Resets(1) -- --10 qq---uu uuuu
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. See Configuration Word 1 (Register 8-1) for operation of all bits.
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NOTES:
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8.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Word 1 and Configuration Word 2 registers, code protection and device ID.
8.1
Configuration Words
There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h. These registers are only accessible during programming.
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REGISTER 8-1: CONFIGURATION WORD 1
R/P-1 -- bit 15 U-1 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 13 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/P-1 CP R/P-1 MCLRE R/P-1 PWRTE R/P-1 WDTEN U-1 -- R/P-1 FOSC1 R/P-1 FOSC0 bit 0 -- DEBUG
(1)
R/P-1 PLLEN
U-1 --
U-1 --
R/P-1 BOREN1
R/P-1 BOREN0 bit 8
DEBUG(1): Debugger Mode bit 0 = Background debugger is enabled 1 = Background debugger is disabled PLLEN: INTOSC PLL Enable bit 0 = INTOSC frequency is 500 kHz 1 = INTOSC frequency is 16 MHz (32x) Unimplemented: Read as `1' BOREN<1:0>: Brown-out Reset Enable bits (2) 0x = Brown-out Reset disabled 10 = Brown-out Reset enabled during operation and disabled in Sleep 11 = Brown-out Reset enabled Unimplemented: Read as `1' CP: Flash Program Memory Code Protection bit PIC16F720/721 0 = 0000h to 07FFh/0FFFh code protection on 1 = Code protection off MCLRE: RA3/MCLR/VPP Pin Function Select bit 1 = RA3/MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = RA3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled PWRTE: Power-up Timer Enable bit 0 = PWRT enabled 1 = PWRT disabled WDTEN: Watchdog Timer Enable bit 0 = WDT disabled 1 = WDT enabled Unimplemented: Read as `1' FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator: CLKOUT function on RA4/CLKOUT pin, CLKIN on RA5/CLKIN 10 = EC oscillator: I/O function on RA4/CLKOUT pin, CLKIN on RA5/CLKIN 01 = INTOSC oscillator: CLKOUT function on RA4/CLKOUT pin, I/O function on RA5/CLKIN 00 = INTOSCIO oscillator: I/O function on RA4/CLKOUT pin, I/O function on RA5/CLKIN
bit 12
bit 11-10 bit 9-8
bit 7 bit 6
bit 5
bit 4
bit 3
bit 2 bit 1-0
Note 1: The Configuration bit is managed automatically by the device development tools. The user should not attempt to manually write this bit location. However, the user should ensure that this location has been programmed to a `1' and the device checksum is correct for proper operation of production software. 2: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
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REGISTER 8-2: CONFIGURATION WORD 2
U-1 -- bit 15 U-1 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 13-5 bit 4 bit 3-2 bit 1-0 P = Programmable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-1 -- U-1 -- Reserved -- U-1 -- U-1 -- R/P-1 WRT1 -- -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 8 R/P-1 WRT0 bit 0
Unimplemented: Read as `1' Reserved: Maintain as `1' Unimplemented: Read as `1' WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory: PIC16F722/LF722: 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control 4 kW Flash memory: PIC16F723/LF723: 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control
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8.2 Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSPTM for verification purposes. Note: The entire Flash program memory will be erased when the code protection is turned off. See the "PIC16F72X/PIC16LF72X Memory Programming Specification" (DS41332) for more information.
8.3
User ID
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB(R) IDE. See the "PIC16F72X/PIC16LF72X Memory Programming Specification" (DS41332) for more information.
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9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 8-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES). Figure 9-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep.
FIGURE 9-1:
ADC BLOCK DIAGRAM
AVDD
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Temperature Indicator FVREF
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 GO/DONE 1010 1011 1110 1111 ADON VSS
ADC 8 ADRES
CHS<3:0>
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9.1 ADC Configuration
When configuring and using the ADC the following functions must be considered: * * * * Port configuration Channel selection ADC conversion clock source Interrupt control When changing channels, a delay is required before starting the next conversion. Refer to Section 9.2 "ADC Operation" for more information.
9.1.3
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
9.1.1
PORT CONFIGURATION
When converting analog signals, the I/O pin selected as the input channel should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 6.0 "I/O Ports" for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
9.1.2
CHANNEL SELECTION
The time to complete one bit conversion is defined as TAD. One full 8-bit conversion requires 10 TAD periods as shown in Figure 9-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 23.0 "Electrical Specifications" for more information. Table 9-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
There are 14 channel selections available: - AN<11:0> pins - Temperature Indicator - FVR (Fixed Voltage Reference) Output Refer to Section 11.0 "Temperature Indicator Module" and Section 10.0 "Fixed Voltage Reference" for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit.
TABLE 9-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
Device Frequency (FOSC)
ADC Clock Period (TAD) ADC Clock Source FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC Legend: Note 1: 2: 3: 4: 5: ADCS<2:0> 000 100 001 101 010 110 x11 16 MHz 125 ns(2) 250 ns(2) 0.5 s(2) 1.0 s 2.0 s 4.0 s 1.0-6.0 s
(1,4)
8 MHz 250 ns(2) 500 ns(2) 1.0 s 2.0 s 4.0 s 8 s(5) 1.0-6.0 s
(1,4)
4 MHz 500 ns(2) 1.0 s 2.0 s 4.0 s 8 s(5)
(1,4)
1 MHz 2.0 s 4.0 s 8 s(5) 16.0 s(5) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4)
16.0 s(5) 1.0-6.0 s
Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. Recommended values for VDD 2.0V and temperature -40C to 85C. The 16.0 s setting should be avoided for temperature > 85C.
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FIGURE 9-2:
TCY to TAD TAD0
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TAD1 TAD2 b7 Conversion Starts Holding Capacitor is disconnected from Analog Input (typically 100 ns) TAD3 b6
TAD4
TAD5 b4
TAD6 b3
TAD7
TAD8
TAD9
b5
b2
b1
b0
Set GO/DONE bit
ADRES register is loaded, GO/DONE bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input
9.1.4
INTERRUPTS
9.2
9.2.1
ADC Operation
STARTING A CONVERSION
The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 9.1.4 "Interrupts" for more information.
To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 "A/D Conversion Procedure".
9.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRES register with new conversion result
9.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRES register will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.
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9.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 4. 5. 6. Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled).
7. 8.
Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 9.3 "A/D Acquisition Requirements".
9.2.5
SPECIAL EVENT TRIGGER
The Special Event Trigger of the CCP module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. Refer to Section 15.0 "Capture/Compare/PWM (CCP) Module" for more information.
EXAMPLE 9-1:
A/D CONVERSION
9.2.6
A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1)
2.
;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'01110000' ;ADC Frc clock, ;VDD reference MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSELA ; BSF ANSELA,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001';AN0, On MOVWF ADCON0 ; CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRES ; MOVF ADRES,W ;Read result MOVWF RESULT ;store in GPR space
3.
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9.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 9-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-2
ADCON0: A/D CONTROL REGISTER 0
U-0 -- R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CHS<3:0>: Analog Channel Select bits 0000 = AN0 0001 = AN1 0010 = AN2 0011 = AN3 0100 = AN4 0101 = AN5 0110 = AN6 0111 = AN7 1000 = AN8 1001 = AN9 1010 = AN10 1011 = AN11 1110 = Temperature Indicator(1) 1111 = Fixed Voltage Reference (FVREF)(2) GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current See Section 11.0 "Temperature Indicator Module" for more information. See Section 10.0 "Fixed Voltage Reference" for more information.
bit 1
bit 0
Note 1: 2:
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REGISTER 9-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON1: A/D CONTROL REGISTER 1
R/W-0
ADCS2
R/W-0
ADCS1
R/W-0
ADCS0
U-0 --
U-0 --
U-0 --
U-0 -- bit 0
Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) Unimplemented: Read as `0'
bit 3-0
REGISTER 9-3:
R/W-x ADRES7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
ADRES: ADC RESULT REGISTER
R/W-x ADRES6 R/W-x ADRES5 R/W-x ADRES4 R/W-x ADRES3 R/W-x ADRES2 R/W-x ADRES1 R/W-x ADRES0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES<7:0>: ADC Result Register bits 8-bit conversion result.
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9.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 9-3. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (256 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. It is noted that if the device is operated at or below 2.0V VDD with the FRC clock selected for the ADC and if the analog input changes by more than 1 or 2 LSBs from the previous conversion, then the use of at least 16 s TACQ time is recommended.
EQUATION 9-1: Assumptions:
ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + Temperature - 25C 0.05s/C Note: TCOFF is zero for temperatures below 25 degrees C. The value for TC can be approximated with the following equations:
1 VAPPLIED 1 - -------------------------- = VCHOLD n+1 2 -1
--------- RC VAPPLIED 1 - e = VCHOLD - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
-------- RC 1 VAPPLIED 1 - e = VAPPLIED 1 - -------------------------- ;combining [1] and [2] n+1 2 -1
Note: Where n = number of bits of the ADC. Solving for TC:
TC = - CHOLD RIC + RSS + RS ln(1/511) = - 20pF 1k + 7k + 10k ln(0.001957) = 2.25 s
Therefore: TACQ = 2s + 2.25s + 50C- 25C 0.05s/C = 5.5s
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Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
FIGURE 9-3:
ANALOG INPUT MODEL
VDD Rs VA ANx CPIN 5 pF VT 0.6V RIC 1k I LEAKAGE(1) Sampling Switch SS Rss
VT 0.6V
CHOLD = 20 pF VSS
6V Legend: CHOLD CPIN = Sample/Hold Capacitance = Input Capacitance VDD 4V 2V
I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance RSS = Resistance of Sampling Switch SS VT = Sampling Switch = Threshold Voltage
5
10
15
20
Sampling Switch, Typical (k)
Note 1: Refer to Section 23.0 "Electrical Specifications".
FIGURE 9-4:
ADC TRANSFER FUNCTION
Full-Scale Range
FFh FEh FDh ADC Output Code FCh FBh Full-Scale Transition 1 LSB ideal
04h 03h 02h 01h 00h 1 LSB ideal VSS Zero-Scale Transition VREF
Analog Input Voltage
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TABLE 9-2:
Name
SUMMARY OF ASSOCIATED ADC REGISTERS
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR --00 0000 -000 -----11 -111 --11 ---11-- 1111 xxxx xxxx -- TMR0IF CCP1IE CCP1IF TRISA2 -- TRISC2 ADFVR1 INTF TMR2IE TMR2IF TRISA1 -- TRISC1 ADFVR0 RABIF TMR1IE TMR1IF TRISA0 -- TRISC0 q000 --00 0000 000x 0000 0000 0000 0000 --11 -111 1111 ---1111 1111 Value on all other Resets --00 0000 -000 -----11 -111 --11 ---11-- 1111 uuuu uuuu q000 --00 0000 000x 0000 0000 0000 0000 --11 -111 1111 ---1111 1111
ADCON0 ADCON1 ANSELA ANSELB ANSELC ADRES FVRCON INTCON PIE1 PIR1 TRISA TRISB TRISC Legend:
-- -- -- -- ANSC7
-- ADCS2 -- -- ANSC6
CHS3 ADCS1 ANSA5 ANSB5 --
CHS2 ADCS0 ANSA4 ANSB4 --
CHS1 -- -- -- ANSC3
CHS0 -- ANSA2 -- ANSC2
GO/DONE -- ANSA1 -- ANSC1
ADON -- ANSA0 -- ANSC0
ADC Result Register FVRRDY GIE TMR1GIE TMR1GIF -- TRISB7 TRISC7 FVREN PEIE ADIE ADIF -- TRISB6 TRISC6 TSEN TMR0IE RCIE RCIF TRISA5 TRISB5 TRISC5 TSRNG INTE TXIE TXIF TRISA4 TRISB4 TRISC4 -- RABIE SSPIE SSPIF -- -- TRISC3
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for ADC module.
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10.0 FIXED VOLTAGE REFERENCE
This device contains an internal voltage regulator. To provide a reference for the regulator, a band gap reference is provided. This band gap is also user accessible via an A/D converter channel. User level band gap functions are controlled by the FVRCON register, which is shown in Register 10-1.
REGISTER 10-1:
R-q FVRRDY bit 7 Legend: R = Readable bit -n = Value at POR
FVRCON: FIXED VOLTAGE REFERENCE REGISTER
R/W-0 R/W-0 TSEN R/W-0 TSRNG U-0 -- U-0 -- R/W-0 ADFVR1 R/W-0 ADFVR0 bit 0
FVREN
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
q = Value depends on condition bit 7 FVRRDY(1): Fixed Voltage Reference Ready Flag bit 0 = Fixed Voltage Reference output is not active or stable 1 = Fixed Voltage Reference output is ready for use FVREN(2): Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled TSEN: Temperature Indicator Enable bit(3) 0 = Temperature indicator is disabled 1 = Temperature indicator is enabled TSRNG: Temperature Indicator Range Selection bit(3) 0 = VOUT = VDD - 4VT (High Range) 1 = VOUT = VDD - 2VT (Low Range) Unimplemented: Read as `0' ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bits 00 = A/D Converter Fixed Voltage Reference Peripheral output is off 01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) FVRRDY is always `1' for the PIC16F720/721 devices. Fixed Voltage Reference output cannot exceed VDD. See Section 11.0 "Temperature Indicator Module" for additional information.
bit 6
bit 5
bit 4
bit 3-2 bit 1-0
Note 1: 2: 3:
TABLE 10-1:
Name FVRCON Legend:
SUMMARY OF ASSOCIATED FIXED VOLTAGE REFERENCE REGISTERS
Bit 6 FVREN Bit 5 TSEN Bit 4 TSRNG Bit 3 -- Bit 2 -- Bit 1 ADFVR1 Bit 0 Value on POR, BOR Value on all other Resets q000 --00
Bit 7 FVRRDY
ADFVR0 q000 --00
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for ADC module.
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11.0 TEMPERATURE INDICATOR MODULE
FIGURE 11-1: TEMPERATURE CIRCUIT DIAGRAM
This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS01333) for more details regarding the calibration process.
VDD TSEN
TSRNG
VOUT
ADC MUX
ADC
n CHS bits (ADCON0 register)
11.1
Circuit Operation 11.2 Minimum Operating VDD vs. Minimum Sensing Temperature
Figure 11-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 11-1 describes the output characteristics of the temperature indicator.
When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 11-1 shows the recommended minimum VDD vs. range setting.
EQUATION 11-1:
VOUT RANGES
High Range: VOUT = VDD - 4VT Low Range: VOUT = VDD - 2VT
TABLE 11-1:
The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 10.0 "Fixed Voltage Reference" for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.
RECOMMENDED VDD VS. RANGE
Min. VDD, TSRNG = 0 1.8V
Min. VDD, TSRNG = 1 3.6V
11.3
Temperature Output
The output of the circuit is measured using the internal Analog-to-Digital converter. Channel 14 is reserved for the temperature circuit output. Refer to Section 9.0 "Analog-to-Digital Converter (ADC) Module" for detailed information.
Note:
Every time the ADC MUX is changed to the temperature indicator output selection (CHS bit in the ADCCON0 register), wait 500 usec for the sampling capacitor to fully charge before sampling the temperature indicator output.
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12.0 TIMER0 MODULE
12.1.1 8-BIT TIMER MODE
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the T0CS bit of the OPTION register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
Figure 12-1 is a block diagram of the Timer0 module.
12.1
Timer0 Operation
12.1.2
8-BIT COUNTER MODE
The Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 8-Bit Counter mode using the T0CKI pin is selected by setting the T0CS bit in the OPTION register to `1'. The rising or falling transition of the incrementing edge for either input source is determined by the T0SE bit in the OPTION register.
FIGURE 12-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 T0CKI 1 0 0 T0SE T1GSS = 11 TMR1GE PSA WDTE 8 T0CS 1 8-bit Prescaler PSA 1 SYNC 2 TCY TMR0 Set Flag bit T0IF on Overflow Overflow to Timer1 8
Low-Power WDT OSC Divide by 512
PS<2:0>
1 WDT Time-out 0
PSA
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12.1.3 SOFTWARE PROGRAMMABLE PRESCALER 12.1.4 TIMER0 INTERRUPT
A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a `0'. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. Note: When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
12.1.5
8-BIT COUNTER MODE SYNCHRONIZATION
When in 8-Bit Counter Mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 23.0 "Electrical Specifications".
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REGISTER 12-1:
R/W-1 RABPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
INTEDG
RABPU: PORTA or PORTB Pull-up Enable bit 1 = PORTA or PORTB pull-ups are disabled 0 = PORTA or PORTB pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 12-1:
Name INTCON OPTION_REG TMR0 TRISA Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 GIE RABPU Bit 6 PEIE INTEDG Bit 5 TMR0IE T0CS Bit 4 INTE T0SE Bit 3 RABIE PSA Bit 2 TMR0IF PS2 Bit 1 INTF PS1 Bit 0 RABIF PS0 Value on POR, BOR 0000 000x 1111 1111 xxxx xxxx TRISA2 TRISA1 TRISA0 --11 -111 Value on all other Resets 0000 000x 1111 1111 uuuu uuuu --11 -111
Timer0 module Register -- -- TRISA5 TRISA4 --
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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13.0 TIMER1 MODULE WITH GATE CONTROL
* * * * Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt
The Timer1 module is a 16-bit timer/counter with the following features: * * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Synchronous or asynchronous operation Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Special Event Trigger (with CCP) * Selectable Gate Source Polarity
Figure 13-1 is a block diagram of the Timer1 module.
FIGURE 13-1:
T1GSS<1:0> T1G From Timer0 Overflow From Timer2 Match PR2 From WDT Overflow
TIMER1 BLOCK DIAGRAM
00 01 10
D Q Q
T1GSPM T1G_IN 0 Single Pulse Acq. Control T1GGO/DONE 1 0 T1GVAL
Q1 D EN Q
Data Bus
RD T1GCON
1
11
CK R
Interrupt det TMR1GE TMR1ON
Set TMR1GIF
T1GPOL TMR1ON T1GTM TMR1(2) TMR1H Set flag bit TMR1IF on Overflow T1CKI Reserved FOSC/4 Internal Clock FOSC Internal Clock TMR1L
Q
EN
T1CLK
D
0
Synchronized clock input
1 TMR1CS<1:0>
(1)
T1SYNC 10 11 2 T1CKPS<1:0> 00 FOSC/2 Internal Clock Sleep input Synchronize(3) det
Prescaler 1, 2, 4, 8
01
Note 1: ST buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.
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13.1 Timer1 Operation 13.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 13-1 displays the Timer1 enable selections. The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. Table 13-2 displays the clock source selections.
13.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler.
13.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: *Timer1 enabled after POR Reset *Write to TMR1H or TMR1L *Timer1 is disabled *Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low.
TABLE 13-1:
TIMER1 ENABLE SELECTIONS
TMR1GE 0 1 0 1 Timer1 Operation Off Off Always On Count Enabled
TMR1ON 0 0 1 1
TABLE 13-2:
0 0 1 1
CLOCK SOURCE SELECTIONS
TMR1CS0 1 0 0 1 System Clock (FOSC) Instruction Clock (FOSC/4) External Clocking on T1CKI Pin Reserved Clock Source
TMR1CS1
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13.3 Timer1 Prescaler 13.5 Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. Timer1 gate can also be driven by multiple selectable sources.
13.4
Timer1 Operation in Asynchronous Counter Mode
13.5.1
TIMER1 GATE COUNT ENABLE
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 13.4.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.
The Timer1 gate is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 gate is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate (T1G) input is active, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 gate input is inactive, no incrementing will occur and Timer1 will hold the current count. See Figure 13-3 for timing details.
TABLE 13-3:
T1CLK
TIMER1 GATE ENABLE SELECTIONS
T1G 0 1 0 1 Timer1 Operation Counts Holds Count Holds Count Counts 0 0 1 1
T1GPOL
13.4.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
13.5.2
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.
TIMER1 GATE SOURCE SELECTION
The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register.
TABLE 13-4:
T1GSS 00 01 10 11
TIMER1 GATE SOURCES
Timer1 Gate Source
Timer1 Gate Pin Overflow of Timer0 (TMR0 increments from FFh to 00h) Timer2 match PR2 (TMR2 increments to match PR2) Count Enabled by WDT Overflow (Watchdog Time-out interval expired)
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13.5.2.1 T1G Pin Gate Operation 13.5.2.4 Watchdog Overflow Gate Operation
The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. The Watchdog Timer oscillator, prescaler and counter will be automatically turned on when TMR1GE = 1 and T1GSS selects the WDT as a gate source for Timer1 (T1GSS = 11). TMR1ON does not factor into the oscillator, prescaler and counter enable. See Table 13-5. The PSA and PS bits of the OPTION register still control what time-out interval is selected. Changing the prescaler during operation may result in a spurious capture. Enabling the Watchdog Timer oscillator does not automatically enable a Watchdog Reset or Wake-up from Sleep upon counter overflow. Note: When using the WDT as a gate source for Timer1, operations that clear the Watchdog Timer (CLRWDT, SLEEP instructions) will affect the time interval being measured. This includes waking from Sleep. All other interrupts that might wake the device from Sleep should be disabled to prevent them from disturbing the measurement period.
13.5.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry.
13.5.2.3
Timer2 Match Gate Operation
The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry.
As the gate signal coming from the WDT counter will generate different pulse widths depending on if the WDT is enabled, when the CLRWDT instruction is executed, and so on, Toggle mode must be used. A specific sequence is required to put the device into the correct state to capture the next WDT counter interval.
TABLE 13-5:
WDTE 1 1 0 0
WDT/TIMER1 GATE INTERACTION
TMR1GE = 1 and T1GSS = 11
N Y Y N
WDT Oscillator Enable Y Y Y N
WDT Reset Y Y N N
Wake-up Y Y N N
WDT Available for T1G Source N Y Y N
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13.5.3 TIMER1 GATE TOGGLE MODE 13.5.5 TIMER1 GATE VALUE STATUS
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 13-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared).
13.5.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared).
13.5.4
TIMER1 GATE SINGLE-PULSE MODE
When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/DONE bit. See Figure 13-5 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 13-6 for timing details.
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13.6 Timer1 Interrupt 13.8 CCP Capture/Compare Time Base
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The CCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 15.0 "Capture/ Compare/PWM (CCP) Module".
The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
13.9
CCP Special Event Trigger
13.7
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, the clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured * TMR1GE bit of the T1GCON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).
When the CCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized to the FOSC/4 to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 9.2.5 "Special Event Trigger".
FIGURE 13-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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FIGURE 13-3: TIMER1 GATE COUNT ENABLE MODE
TMR1GE
T1GPOL T1G_IN
T1CKI
T1GVAL
TIMER1
N
N+1
N+2
N+3
N+4
FIGURE 13-4:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
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FIGURE 13-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE T1GPOL T1GSPM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL
T1CKI
T1GVAL
TIMER1
N
N+1
N+2 Cleared by software
TMR1GIF
Cleared by software
Set by hardware on falling edge of T1GVAL
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FIGURE 13-6:
TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1CKI
T1GVAL
TIMER1
N
N+1
N+2
N+3
N+4 Cleared by software
TMR1GIF
Cleared by software
Set by hardware on falling edge of T1GVAL
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13.10 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 13-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 13-1:
R/W-0 TMR1CS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6
T1CON: TIMER1 CONTROL REGISTER
R/W-0 R/W-0 T1CKPS1 R/W-0 T1CKPS0 U-0 -- R/W-0 T1SYNC U-0 -- R/W-0 TMR1ON bit 0
TMR1CS0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Reserved 10 = Timer1 clock source is pin or oscillator. External clock from T1CKI pin (on the rising edge) 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value Unimplemented: Read as `0' T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 5-4
bit 3 bit 2
bit 1 bit 0
Unimplemented: Read as `0' TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop
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13.11 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in Register 13-2, is used to control Timer1 gate.
REGISTER 13-2:
R/W-0 TMR1GE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0 R/W-0 T1GTM R/W-0 T1GSPM R/W-0 T1GGO/ DONE R-x T1GVAL R/W-0 T1GSS1 R/W-0 T1GSS0 bit 0
T1GPOL
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) T1GTM: Timer1 Gate Toggle mode bit 1 = Timer1 Gate Toggle mode is enabled. 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. T1GSPM: Timer1 Gate Single Pulse mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 overflow output 10 = TMR2 match PR2 output 11 = Watchdog Timer scaler overflow Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
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TABLE 13-6:
Name ANSELB CCP1CON INTCON PIE1 PIR1 PORTB TMR1H TMR1L TRISB TRISC T1CON T1GCON Legend: TRISB7 TRISC7 Bit 7 -- -- GIE TMR1GIE TMR1GIF RB7
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 6 -- -- PEIE ADIE ADIF RB6 Bit 5 ANSB5 DC1 TMR0IE RCIE RCIF RB5 Bit 4 ANSB4 B1 INTE TXIE TXIF RB4 Bit 3 -- CCP1M3 RABIE SSPIE SSPIF -- Bit 2 -- CCP1M2 TMR0IF CCP1IE CCP1IF -- Bit 1 -- CCP1M1 INTF TMR2IE TMR2IF -- Bit 0 -- CCP1M0 RABIF TMR1IE TMR1IF -- Value on POR, BOR --11 -----00 0000 0000 000x 0000 0000 0000 0000 xxxx ---xxxx xxxx xxxx xxxx -- TRISC0 TMR1ON T1GSS0 1111 ---1111 1111 0000 -0-0 0000 0x00 Value on all other Resets --11 -----00 0000 0000 000x 0000 0000 0000 0000 uuuu ---uuuu uuuu uuuu uuuu 1111 ---1111 1111 uuuu -u-u uuuu uxuu
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TRISB6 TRISC6 TRISB5 TRISC5 T1CKPS1 T1GTM TRISB4 TRISC4 T1CKPS0 T1GSPM -- TRISC3 -- T1GGO/ DONE -- TRISC2 T1SYNC T1GVAL -- TRISC1 -- T1GSS1
TMR1CS1 TMR1CS0 TMR1GE T1GPOL
x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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14.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following features: * * * * * 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a `1'. Timer2 is turned off by clearing the TMR2ON bit to a `0'. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: * A write to TMR2 occurs. * A write to T2CON occurs. * Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written.
See Figure 14-1 for a block diagram of Timer2.
14.1
Timer2 Operation
The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: * TMR2 is reset to 00h on the next increment cycle. * The Timer2 postscaler is incremented. The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register.
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS<1:0>
TMR2
Reset
Comparator EQ PR2
Postscaler 1:1 to 1:16 4 TOUTPS<3:0>
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REGISTER 14-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T2CON: TIMER2 CONTROL REGISTER
R/W-0 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0
TOUTPS3
Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2
bit 1-0
TABLE 14-1:
Name INTCON PIE1 PIR1 PR2 TMR2 T2CON Legend: -- Bit 7 GIE TMR1GIE TMR1GIF
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 6 PEIE ADIE ADIF Bit 5 TMR0IE RCIE RCIF Bit 4 INTE TXIE TXIF Bit 3 RABIE SSPIE SSPIF Bit 2 TMR0IF CCP1IE CCP1IF Bit 1 INTF TMR2IE TMR2IF Bit 0 RABIF TMR1IE TMR1IF Value on POR, BOR 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 TMR2ON T2CKPS1 T2CKPS0 -000 0000 Value on all other Resets 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 -000 0000
Timer2 module Period Register Timer2 module Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used for Timer2 module.
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15.0 CAPTURE/COMPARE/PWM (CCP) MODULE
TABLE 15-1: CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. The timer resources used by the module are shown in Table 15-1. Additional information on CCP modules is available in the Application Note AN594, "Using the CCP Modules" (DS00594).
CCP Mode Capture Compare PWM
REGISTER 15-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4
CCP1CON: CCP1 CONTROL REGISTER
U-0 -- R/W-0 DC1 R/W-0 B1 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' DC1:B1: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M<3:0>: CCP mode Select bits 0000 = Capture/Compare/PWM off (resets CCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit of the PIRx register is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit of the PIR1 register is set) 1001 = Compare mode, clear output on match (CCP1IF bit of the PIR1 register is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set of the PIRx register, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit of the PIR1register is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP1 pin is unaffected.) 11xx = PWM mode.
bit 3-0
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15.1 Capture Mode
15.1.3 SOFTWARE INTERRUPT
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode
15.1.4
CCP PRESCALER
When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (refer to Figure 15-1).
There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (refer to Example 15-1).
15.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit.
EXAMPLE 15-1:
BANKSEL CCP1CON CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
Note:
If the CCP1 pin is configured as an output, a write to the port can cause a capture condition.
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1 register)
MOVWF
;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value
Prescaler 1, 4, 16 CCP1
15.1.5
CCPR1L
CAPTURE DURING SLEEP
CCPR1H and Edge Detect Capture Enable TMR1H
Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. If Timer1 is clocked by FOSC/4, then Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. If Timer1 is clocked by an external clock source, then Capture mode will operate as defined in Section 15.1 "Capture Mode".
TMR1L
CCP1CON<3:0> System Clock (FOSC)
15.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode or when Timer1 is clocked at FOSC, the capture operation may not work. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCP1 pin, Timer1 must be clocked from the Instruction Clock (FOSC/4) or from an external clock source.
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TABLE 15-2:
Name ANSELB CCP1CON CCPR1L CCPR1H INTCON PIE1 PIR1 T1CON T1GCON TMR1L TMR1H TRISB TRISC Legend: TRISB7 TRISC7 GIE TMR1GIE TMR1GIF TMR1CS1 TMR1GE PEIE ADIE ADIF TMR1CS0 T1GPOL
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Bit 7 -- -- Bit 6 -- -- Bit 5 ANSB5 DC1 Bit 4 ANSB4 B1 Bit 3 -- CCP1M3 Bit 2 -- CCP1M2 Bit 1 -- CCP1M1 Bit 0 -- CCP1M0 Value on POR, BOR --11 -----00 0000 xxxx xxxx xxxx xxxx INTF TMR2IE TMR2IF -- T1GSS1 RABIF TMR1IE TMR1IF TMR1ON T1GSS0 0000 000x 0000 0000 0000 0000 0000 -0-0 0000 0x00 xxxx xxxx xxxx xxxx -- TRISC0 1111 ---1111 1111 Value on all other Resets --11 -----00 0000 uuuu uuuu uuuu uuuu 0000 000x 0000 0000 0000 0000 uuuu -u-u uuuu uxuu uuuu uuuu uuuu uuuu 1111 ---1111 1111
Capture/Compare/PWM Register Low Byte Capture/Compare/PWM Register High Byte TMR0IE RCIE RCIF T1CKPS1 T1GTM INTE TXIE TXIF T1CKPS0 T1GSPM RABIE SSPIE SSPIF -- T1GGO/ DONE TMR0IF CCP1IE CCP1IF T1SYNC T1GVAL
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISB6 TRISC6 TRISB5 TRISC5 TRISB4 TRISC4 -- TRISC3 -- TRISC2 -- TRISC1
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the capture.
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15.2 Compare Mode
15.2.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: * * * * * Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. For the Compare operation of the TMR1 register to the CCPR1 register to occur, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.
The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt.
15.2.3
SOFTWARE INTERRUPT MODE
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0> Mode Select Set CCP1IF Interrupt Flag (PIR1) 4 CCPR1H CCPR1L
When Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1IF bit in the PIR1 register is set and the CCP1 module does not assert control of the CCP1 pin (refer to the CCP1CON register).
15.2.4
SPECIAL EVENT TRIGGER
CCP1 Q S R TRIS Output Enable
When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode (refer to the CCP1CON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.
Output Logic
Match
Comparator TMR1H TMR1L
Special Event Trigger Special Event Trigger will: * Clear TMR1H and TMR1L registers. * NOT set interrupt flag bit TMR1IF of the PIR1 register. * Set the GO/DONE bit to start the ADC conversion.
15.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch.
15.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep.
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TABLE 15-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR --00 0000 --11 -----00 0000 xxxx xxxx xxxx xxxx INTF TMR2IE TMR2IF -- T1GSS1 RABIF TMR1IE TMR1IF TMR1ON T1GSS0 0000 000x 0000 0000 0000 0000 0000 -0-0 0000 0x00 xxxx xxxx xxxx xxxx -- TRISC0 1111 ---1111 1111 Value on all other Resets --00 0000 --11 -----00 0000 uuuu uuuu uuuu uuuu 0000 000x 0000 0000 0000 0000 uuuu -u-u uuuu uxuu uuuu uuuu uuuu uuuu 1111 ---1111 1111
ADCON0 ANSELB CCP1CON CCPR1L CCPR1H INTCON PIE1 PIR1 T1CON T1GCON TMR1L TMR1H TRISB TRISC Legend:
-- -- --
-- -- --
CHS3 ANSB5 DC1
CHS2 ANSB4 B1
CHS1 -- CCP1M3
CHS0 -- CCP1M2
GO/DONE -- CCP1M1
ADON -- CCP1M0
Capture/Compare/PWM Register Low Byte Capture/Compare/PWM Register High Byte GIE TMR1GIE TMR1GIF TMR1CS1 TMR1GE PEIE ADIE ADIF TMR1CS0 T1GPOL TMR0IE RCIE RCIF T1CKPS1 T1GTM INTE TXIE TXIF T1CKPS0 T1GSPM RABIE SSPIE SSPIF -- T1GGO/ DONE TMR0IF CCP1IE CCP1IF T1SYNC T1GVAL
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISB7 TRISC7 TRISB6 TRISC6 TRISB5 TRISC5 TRISB4 TRISC4 -- TRISC3 -- TRISC2 -- TRISC1
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the compare.
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15.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: * * * * PR2 T2CON CCPR1L CCP1CON The PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle).
FIGURE 15-4:
Period Pulse Width
CCP PWM OUTPUT
TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4>
In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. Figure 15-3 shows a simplified block diagram of PWM operation. Figure 15-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, refer to Section 15.3.8 "Setup for PWM Operation".
TMR2 = 0
15.3.1
CCPX PIN CONFIGURATION
In PWM mode, the CCP1 pin is multiplexed with the PORT data latch. The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin.
FIGURE 15-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H(2) (Slave) CCP1 Comparator R S TRIS Comparator Clear Timer2, toggle CCP1 pin and latch duty cycle Q
TMR2
(1)
PR2
Note
1:
2:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register.
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15.3.2 PWM PERIOD 15.3.3 PWM DUTY CYCLE
The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 15-1. The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1 and B1 bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1 and B1 bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1 and B1 bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 15-2 is used to calculate the PWM pulse width. Equation 15-3 is used to calculate the PWM duty cycle ratio.
EQUATION 15-1:
PWM PERIOD
PWM Period = PR2 + 1 4 TOSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPR1L into CCPR1H. Note: The Timer2 postscaler (refer to Section 14.1 "Timer2 Operation") is not used in the determination of the PWM frequency.
EQUATION 15-2:
PULSE WIDTH
Pulse Width = CCPR1L:CCP1CON<5:4> TOSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC
EQUATION 15-3:
DUTY CYCLE RATIO
CCPR1L:CCP1CON<5:4> Duty Cycle Ratio = ---------------------------------------------------------------------4 PR2 + 1 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (refer to Figure 15-3).
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15.3.4 PWM RESOLUTION EQUATION 15-4: PWM RESOLUTION
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 15-4. Note: log 4 PR2 + 1 Resolution = ----------------------------------------- bits log 2
If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.
TABLE 15-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 15-5:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
1.22 kHz 16 0x65 8 4.90 kHz 4 0x65 8 19.61 kHz 1 0x65 8 76.92 kHz 1 0x19 6 153.85 kHz 1 0x0C 5 200.0 kHz 1 0x09 5
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
15.3.5
OPERATION IN SLEEP MODE
15.3.8
SETUP FOR PWM OPERATION
In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state.
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Disable the PWM pin (CCP1) output driver(s) by setting the associated TRIS bit(s). Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. Load the CCPR1L register and the DCxBx bits of the CCP1CON register, with the PWM duty cycle value. Configure and start Timer2: Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: Wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. Enable the PWM pin (CCP1) output driver(s) by clearing the associated TRIS bit(s). In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored.
15.3.6
CHANGES IN SYSTEM CLOCK FREQUENCY
The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 7.0 "Oscillator Module" for additional details.
4.
5. *
15.3.7
EFFECTS OF RESET
* * 6. * *
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
Note:
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TABLE 15-6:
Name ANSELB CCP1CON CCPR1L CCPR1H PR2 T2CON TMR2 TRISB TRISC Legend: TRISB7 TRISC7 TRISB6 TRISC6 TRISB5 TRISC5 -- TOUTPS3
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Bit 7 -- -- Bit 6 -- -- Bit 5 ANSB5 DC1 Bit 4 ANSB4 B1 Bit 3 -- CCP1M3 Bit 2 -- CCP1M2 Bit 1 -- CCP1M1 Bit 0 -- CCP1M0 Value on POR, BOR --11 -----00 0000 xxxx xxxx xxxx xxxx 1111 1111 TMR2ON T2CKPS1 T2CKPS0 -000 0000 0000 0000 -- TRISC2 -- TRISC1 -- TRISC0 1111 ---1111 1111 Value on all other Resets --11 -----00 0000 uuuu uuuu uuuu uuuu 1111 1111 -000 0000 0000 0000 1111 ---1111 1111
Capture/Compare/PWM Register Low Byte Capture/Compare/PWM Register High Byte Timer2 module Period Register TOUTPS2 TOUTPS1 TOUTPS0
Timer2 module Register TRISB4 TRISC4 -- TRISC3
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM.
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NOTES:
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16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART)
The AUSART module includes the following capabilities: * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Sleep operation
The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The AUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device.
Block diagrams of the AUSART transmitter and receiver are shown in Figure 16-1 and Figure 16-2.
FIGURE 16-1:
AUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIE Interrupt TXREG Register 8 MSb (8) LSb TX/CK Pin Buffer and Control TXIF
***
Transmit Shift Register (TSR)
0
TXEN Baud Rate Generator TRMT FOSC /n n +1 Multiplier SYNC SPBRG BRGH x4 1 x x16 x64 0 1 0 0 TX9D TX9 SPEN
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FIGURE 16-2: AUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR
RX/DT Pin Buffer and Control Baud Rate Generator FOSC Data Recovery
MSb Stop (8) 7
RSR Register
LSb 0 START
***
RX9
1
/n
+1
Multiplier SYNC
x4 1 x
x16 x64 0 1 0 0
n
SPBRG
BRGH
FERR
RX9D
RCREG Register 8 Data Bus RCIF RCIE
FIFO
Interrupt
The operation of the AUSART module is controlled through two registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) These registers are detailed in Register 16-1 and Register 16-2, respectively.
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16.1 AUSART Asynchronous Mode
Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the AUSART receiver is enabled. The RX/DT pin data can be read via a normal PORT read but PORT latch data output is precluded. 2: The TXIF transmitter interrupt flag is set when the TXEN enable bit is set. The AUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(baud rate). An on-chip dedicated 8-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. Refer to Table 16-5 for examples of baud rate configurations. The AUSART transmits and receives the LSb first. The AUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit.
16.1.1.2
Transmitting Data
16.1.1
AUSART ASYNCHRONOUS TRANSMITTER
A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG.
16.1.1.3
Transmit Interrupt Flag
The AUSART transmitter block diagram is shown in Figure 16-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register.
16.1.1.1
Enabling the Transmitter
The AUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other AUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the AUSART. Clearing the SYNC bit of the TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the TX/CK I/O pin as an output.
The TXIF interrupt flag bit of the PIR1 register is set whenever the AUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG.
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16.1.1.4 TSR Status 16.1.1.6
1.
Asynchronous Transmission Setup:
The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: The TSR register is not mapped in data memory, so it is not available to the user.
2. 3.
16.1.1.5
Transmitting 9-Bit Characters
4.
The AUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the AUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. Refer to Section 16.1.2.7 "Address Detection" for more information on the Address mode.
5.
6. 7.
Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (Refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission.
FIGURE 16-3:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
1 TCY
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 16-4:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1 Word 2
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
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TABLE 16-1:
Name INTCON PIE1 PIR1 RCSTA SPBRG TRISC TXREG TXSTA Legend: CSRC TX9
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 6 PEIE ADIE ADIF RX9 BRG6 TRISC6 Bit 5 TMR0IE RCIE RCIF SREN BRG5 TRISC5 TXEN Bit 4 INTE TXIE TXIF CREN BRG4 TRISC4 SYNC Bit 3 RABIE SSPIE SSPIF ADDEN BRG3 TRISC3 -- Bit 2 TMR0IF CCP1IE CCP1IF FERR BRG2 TRISC2 BRGH Bit 1 INTF TMR2IE TMR2IF OERR BRG1 TRISC1 TRMT Bit 0 RABIF TMR1IE TMR1IF RX9D BRG0 TRISC0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 000x 0000 0000 1111 1111 0000 0000 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 0000 0000 000x 0000 0000 1111 1111 0000 0000 0000 -010
Bit 7 GIE TMR1GIE TMR1GIF SPEN BRG7 TRISC7
AUSART Transmit Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for asynchronous transmission.
16.1.2
AUSART ASYNCHRONOUS RECEIVER
16.1.2.1
Enabling the Receiver
The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 16-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the AUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register.
The AUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other AUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the AUSART. Clearing the SYNC bit of the TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the RX/DT I/O pin as an input.
Note:
When the SPEN bit is set, the TX/CK I/O pin is automatically configured as an output, regardless of the state of the corresponding TRIS bit and whether or not the AUSART transmitter is enabled. The PORT latch is disconnected from the output driver so it is not possible to use the TX/CK pin as a general purpose output.
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16.1.2.2 Receiving Data 16.1.2.4 Receive Framing Error
The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. Refer to Section 16.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the AUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. Refer to Section 16.1.2.5 "Receive Overrun Error" for more information on overrun errors. Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the AUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit.
16.1.2.5
Receive Overrun Error
16.1.2.3
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set whenever the AUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE, Peripheral Interrupt Enable bit of the INTCON register * GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit of the PIR1 register will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by setting the AUSART by clearing the SPEN bit of the RCSTA register.
16.1.2.6
Receiving 9-bit Characters
The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the AUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
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16.1.2.7 Address Detection 16.1.2.9 9-bit Address Detection Mode Setup
A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit of the PIR1 register. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 4. Enable 9-bit reception by setting the RX9 bit. 5. Enable address detection by setting the ADDEN bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit of the PIR1 register will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit of the PIE1 register was also set. 8. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.
16.1.2.8
1.
Asynchronous Reception Setup:
2.
3.
4. 5. 6.
7.
8.
9.
Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Enable reception by setting the CREN bit. The RCIF interrupt flag bit of the PIR1 register will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE bit of the PIE1 register was also set. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
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FIGURE 16-5:
RX/DT pin Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
TABLE 16-2:
Name INTCON PIE1 PIR1 RCREG RCSTA SPBRG TRISC TXSTA Legend:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 6 PEIE ADIE ADIF RX9 BRG6 TRISC6 TX9 Bit 5 TMR0IE RCIE RCIF SREN BRG5 TRISC5 TXEN Bit 4 INTE TXIE TXIF CREN BRG4 TRISC4 SYNC Bit 3 RABIE SSPIE SSPIF ADDEN BRG3 TRISC3 -- Bit 2 TMR0IF CCP1IE CCP1IF FERR BRG2 TRISC2 BRGH Bit 1 INTF TMR2IE TMR2IF OERR BRG1 TRISC1 TRMT Bit 0 RABIF TMR1IE TMR1IF RX9D BRG0 TRISC0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 1111 1111 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 1111 1111 0000 -010
Bit 7 GIE TMR1GIE TMR1GIF SPEN BRG7 TRISC7 CSRC
AUSART Receive Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for asynchronous reception.
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REGISTER 16-1:
R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 TX9 R/W-0 TXEN(1) R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: AUSART mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as `0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Synchronous mode.
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
Note 1:
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REGISTER 16-2:
R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit(1) 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care Synchronous mode: Must be set to `0' FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure TRISx = 1.
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16.2 AUSART Baud Rate Generator (BRG)
EXAMPLE 16-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, and Asynchronous mode with SYNC = 0 and BRGH = 0 (as seen in Table 16-5): FOSC Desired Baud Rate = -------------------------------------64 SPBRG + 1 Solving for SPBRG: FOSC SPBRG = -------------------------------------------------------- - 1 64 Desired Baud Rate 16000000 = ----------------------- - 1 64 9600 = 25.042 = 25 16000000 Actual Baud Rate = -------------------------64 25 + 1 = 9615 Actual Baud Rate - Desired Baud Rate % Error = ------------------------------------------------------------------------------------------------- 100 Desired Baud Rate 9615 - 9600 = ----------------------------- 100 = 0.16% 9600
The Baud Rate Generator (BRG) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation. The SPBRG register determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by the BRGH bit of the TXSTA register. In Synchronous mode, the BRGH bit is ignored. Table 16-3 contains the formulas for determining the baud rate. Example 16-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 16-5. It may be advantageous to use the high baud rate (BRGH = 1), to reduce the baud rate error. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.
TABLE 16-3:
SYNC 0 0 1 Legend:
BAUD RATE FORMULAS
AUSART Mode BRGH 0 1 x Asynchronous Asynchronous Synchronous FOSC/[64 (n+1)] FOSC/[16 (n+1)] FOSC/[4 (n+1)] Baud Rate Formula
Configuration Bits
x = Don't care, n = value of SPBRG register
TABLE 16-4:
Name RCSTA SPBRG TXSTA Legend:
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 6 RX9 BRG6 TX9 Bit 5 SREN BRG5 TXEN Bit 4 CREN BRG4 SYNC Bit 3 ADDEN BRG3 -- Bit 2 FERR BRG2 BRGH Bit 1 OERR BRG1 TRMT Bit 0 RX9D BRG0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 -010
Bit 7 SPEN BRG7 CSRC
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for the Baud Rate Generator.
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TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate -- 1221 2404 9470 10417 19.53k -- -- % Error -- 1.73 0.16 -1.36 0.00 1.73 -- -- SPBRG value (decimal) -- 255 129 32 29 15 -- -- FOSC = 18.432 MHz Actual Rate -- 1200 2400 9600 10286 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -1.26 0.00 0.00 -- SPBRG value (decimal) -- 239 119 29 27 14 7 -- FOSC = 16.0000 MHz Actual Rate -- 1201 2403 9615 10416 19.23k -- -- % Error -- 0.08 0.16 0.16 -0.01 0.16 -- -- SPBRG value (decimal) -- 207 103 25 23 12 -- -- FOSC = 11.0592 MHz Actual Rate -- 1200 2400 9600 10165 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -2.42 0.00 0.00 -- SPBRG value (decimal) -- 143 71 17 16 8 2 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- -- FOSC = 4.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- FOSC = 3.6864 MHz Actual Rate 300 1200 2400 9600 -- 19.20k 57.60k -- % Error 0.00 0.00 0.00 0.00 -- 0.00 0.00 -- SPBRG value (decimal) 191 47 23 5 -- 2 0 -- FOSC = 1.000 MHz Actual Rate 300 1202 -- -- -- -- -- -- % Error 0.16 0.16 -- -- -- -- -- -- SPBRG value (decimal) 51 12 -- -- -- -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 56.82k 113.64k % Error -- -- -- 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) -- -- -- 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate -- -- -- 9600 10378 19.20k 57.60k 115.2k % Error -- -- -- 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 119 110 59 19 9 FOSC = 16.0000 MHz Actual Rate -- -- -- 9615 10417 19.23k 58.8k -- % Error -- -- -- 0.16 0.00 0.16 2.12 -- SPBRG value (decimal) -- -- -- 103 95 51 16 -- FOSC = 11.0592 MHz Actual Rate -- -- -- 9600 10473 19.20k 57.60k 115.2k % Error -- -- -- 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 71 65 35 11 5
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate -- -- 2404 9615 10417 19231 55556 -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 8 -- FOSC = 4.000 MHz Actual Rate -- 1202 2404 9615 10417 19.23k -- -- % Error -- 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) -- 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate -- 1200 2400 9600 10473 19.2k 57.60k 115.2k % Error -- 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- 191 95 23 21 11 3 1 FOSC = 1.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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16.3 AUSART Synchronous Mode
16.3.1.2 Synchronous Master Transmission
Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The AUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the AUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user.
16.3.1
SYNCHRONOUS MASTER MODE
16.3.1.3
1.
The following bits are used to configure the AUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1
Synchronous Master Transmission Setup:
2. 3. 4. 5. 6.
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the AUSART.
7. 8.
16.3.1.1
Master Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the AUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.
Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register.
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FIGURE 16-6:
RX/DT pin TX/CK pin Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit
SYNCHRONOUS TRANSMISSION
bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7
Write Word 1
Write Word 2
TXEN bit Note:
`1' Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
`1'
FIGURE 16-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 16-6:
Name INTCON PIE1 PIR1 RCSTA SPBRG TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 6 PEIE ADIE ADIF RX9 BRG6 TRISC6 TX9 Bit 5 TMR0IE RCIE RCIF SREN BRG5 TRISC5 TXEN Bit 4 INTE TXIE TXIF CREN BRG4 TRISC4 SYNC Bit 3 RABIE SSPIE SSPIF ADDEN BRG3 TRISC3 -- Bit 2 TMR0IF CCP1IE CCP1IF FERR BRG2 TRISC2 BRGH Bit 1 INTF TMR2IE TMR2IF OERR BRG1 TRISC1 TRMT Bit 0 RABIF TMR1IE TMR1IF RX9D BRG0 TRISC0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 000x 0000 0000 1111 1111 0000 0000 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 0000 0000 000x 0000 0000 1111 1111 0000 0000 0000 -010
Bit 7 GIE TMR1GIE TMR1GIF SPEN BRG7 TRISC7 CSRC
AUSART Transmit Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous master transmission.
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16.3.1.4 Synchronous Master Reception 16.3.1.7 Receiving 9-bit Characters
Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit of the PIR1 register is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are un-read characters in the receive FIFO. The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the AUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. Address detection in Synchronous modes is not supported, therefore the ADDEN bit of the RCSTA register must be cleared.
16.3.1.8
1.
Synchronous Master Reception Setup
16.3.1.5
Slave Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/ CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits.
16.3.1.6
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register.
Initialize the SPBRG register for the appropriate baud rate. Set or clear the BRGH bit, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set bit RX9. 6. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF of the PIR1 register will be set when reception of a character is complete. An interrupt will be generated if the RCIE interrupt enable bit of the PIE1 register was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit, which resets the AUSART.
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FIGURE 16-8:
RX/DT pin
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RCREG `0'
Note:
Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 16-7:
Name INTCON PIE1 PIR1 RCREG RCSTA TRISC TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 6 PEIE ADIE ADIF RX9 TRISC6 TX9 Bit 5 TMR0IE RCIE RCIF SREN TRISC5 TXEN Bit 4 INTE TXIE TXIF CREN TRISC4 SYNC Bit 3 RABIE SSPIE SSPIF ADDEN TRISC3 -- Bit 2 TMR0IF CCP1IE CCP1IF FERR TRISC2 BRGH Bit 1 INTF TMR2IE TMR2IF OERR TRISC1 TRMT Bit 0 RABIF TMR1IE TMR1IF RX9D TRISC0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 1111 1111 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 1111 1111 0000 -010
Bit 7 GIE TMR1GIE TMR1GIF SPEN TRISC7 CSRC
AUSART Receive Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous master reception.
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16.3.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the AUSART for synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the AUSART.
5.
16.3.2.2
1. 2. 3.
Synchronous Slave Transmission Setup
16.3.2.1
AUSART Synchronous Slave Transmit
The operation of the Synchronous Master and Slave modes are identical (refer to Section 16.3.1.2 "Synchronous Master Transmission"), except in the case of the Sleep mode.
4. 5. 6. 7. 8.
Set the SYNC and SPEN bits and clear the CSRC bit. Clear the CREN and SREN bits. If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the TXIE bit. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register.
TABLE 16-8:
Name INTCON PIE1 PIR1 RCSTA TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 6 PEIE ADIE ADIF RX9 TRISC6 TX9 Bit 5 TMR0IE RCIE RCIF SREN TRISC5 TXEN Bit 4 INTE TXIE TXIF CREN TRISC4 SYNC Bit 3 RABIE SSPIE SSPIF ADDEN TRISC3 -- Bit 2 TMR0IF CCP1IE CCP1IF FERR TRISC2 BRGH Bit 1 INTF TMR2IE TMR2IF OERR TRISC1 TRMT Bit 0 RABIF TMR1IE TMR1IF RX9D TRISC0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 000x 1111 1111 0000 0000 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 0000 0000 000x 1111 1111 0000 0000 0000 -010
Bit 7 GIE TMR1GIE TMR1GIF SPEN TRISC7 CSRC
AUSART Transmit Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous slave transmission.
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16.3.2.3 AUSART Synchronous Slave Reception 16.3.2.4
1. 2.
Synchronous Slave Reception Setup
The operation of the Synchronous Master and Slave modes is identical (Section 16.3.1.4 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE interrupt enable bit of the PIE1 register is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector.
3. 4. 5. 6.
7.
8. 9.
Set the SYNC and SPEN bits and clear the CSRC bit. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. Set the CREN bit to enable reception. The RCIF bit of the PIR1 register will be set when reception is complete. An interrupt will be generated if the RCIE bit of the PIE1 register was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register.
TABLE 16-9:
Name INTCON PIE1 PIR1 RCREG RCSTA TRISC TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Bit 6 PEIE ADIE ADIF RX9 TRISC6 TX9 Bit 5 TMR0IE RCIE RCIF SREN TRISC5 TXEN Bit 4 INTE TXIE TXIF CREN TRISC4 SYNC Bit 3 RABIE SSPIE SSPIF ADDEN TRISC3 -- Bit 2 TMR0IF CCP1IE CCP1IF FERR TRISC2 BRGH Bit 1 INTF TMR2IE TMR2IF OERR TRISC1 TRMT Bit 0 RABIF TMR1IE TMR1IF RX9D TRISC0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 1111 1111 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 1111 1111 0000 -010
Bit 7 GIE TMR1GIE TMR1GIF SPEN TRISC7 CSRC
AUSART Receive Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous slave reception.
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16.4 AUSART Operation During Sleep
16.4.2
The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers.
SYNCHRONOUS TRANSMIT DURING SLEEP
To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for synchronous slave transmission (refer to Section 16.3.2.2 "Synchronous Slave Transmission Setup"). * The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. Upon entering Sleep mode, the device will be ready to accept clocks on the TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE, Global Interrupt Enable bit is also set then the Interrupt Service Routine at address 0004h will be called.
16.4.1
SYNCHRONOUS RECEIVE DURING SLEEP
To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for synchronous slave reception (refer to Section 16.3.2.4 "Synchronous Slave Reception Setup"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the PEIE bit of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE, Global Interrupt Enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 0004h will be called.
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17.0 SSP MODULE OVERVIEW
The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripherals or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) A typical SPI connection between microcontroller devices is shown in Figure 17-1. Addressing of more than one slave device is accomplished via multiple hardware slave select lines. External hardware and additional I/O pins must be used to support multiple slave select addressing. This prevents extra overhead in software for communication. For SPI communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS)
17.1
SPI Mode
The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. The SSP module can be operated in one of two SPI modes: * Master mode * Slave mode SPI is a full-duplex protocol, with all communication being bidirectional and initiated by a master device. All clocking is provided by the master device and all bits are transmitted, MSb first. Care must be taken to ensure that all devices on the SPI bus are setup to allow all controllers to send and receive data at the same time.
FIGURE 17-1:
TYPICAL SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx SDO Serial Input Buffer (SSPBUF) SDI
SPI Slave SSPM<3:0> = 010x
Serial Input Buffer (SSPBUF)
Shift Register (SSPSR) MSb LSb
SDI
SDO MSb
Shift Register (SSPSR) LSb
SCK General I/O Processor 1
Serial Clock Slave Select (optional)
SCK SS Processor 2
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FIGURE 17-2: SPI MODE BLOCK DIAGRAM
Internal Data Bus Read SSPBUF Reg Write
SSPSR Reg SDI bit 0 Shift Clock bit 7
SDO
RA5/SS
SS Control Enable
RA0/SS
SSSEL
2 Clock Select Edge Select 2 Edge Select SCK TRISx 4 SSPM<3:0> Prescaler 4, 16, 64 TMR2 Output FOSC
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17.1.1 MASTER MODE 17.1.1.3 Master Mode Setup
In Master mode, data transfer can be initiated at any time because the master controls the SCK line. Master mode determines when the slave (Figure 17-1, Processor 2) transmits data via control of the SCK line. In Master mode, the data is transmitted/received as soon as the SSPBUF register is loaded with a byte value. If the master is only going to receive, SDO output could be disabled (programmed and used as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. When initializing SPI Master mode operation, several options need to be specified. This is accomplished by programming the appropriate control bits in the SSPCON and SSPSTAT registers. These control bits allow the following to be specified: * * * * * SCK as clock output Idle state of SCK (CKP bit) Data input sample phase (SMP bit) Output data on rising/falling edge of SCK (CKE bit) Clock bit rate
17.1.1.1
Master Mode Operation
The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR register shifts the data in and out of the device, MSb first. The SSPBUF register holds the data that is written out of the master until the received data is ready. Once the eight bits of data have been received, the byte is moved to the SSPBUF register. The Buffer Full Status bit, BF of the SSPSTAT register, and the SSP Interrupt Flag bit, SSPIF of the PIR1 register, are then set. Any write to the SSPBUF register during transmission/ reception of data will be ignored and the Write Collision Detect bit, WCOL of the SSPCON register, will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data is written to the SSPBUF. The BF bit of the SSPSTAT register is set when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. The SSP interrupt may be used to determine when the transmission/reception is complete and the SSPBUF must be read and/or written. If interrupts are not used, then software polling can be done to ensure that a write collision does not occur. Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. Note: The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register.
In Master mode, the SPI clock rate (bit rate) is user selectable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 TCY) FOSC/64 (or 16 TCY) (Timer2 output)/2
This allows a maximum data rate of 5 Mbps (at FOSC = 16 MHz). Figure 17-3 shows the waveforms for Master mode. The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The sample time of the input data is shown based on the state of the SMP bit and can occur at the middle or end of the data output time. The time when the SSPBUF is loaded with the received data is shown.
17.1.1.4
Sleep in Master Mode
17.1.1.2
Enabling Master I/O
To enable the serial port, the SSPEN bit of the SSPCON register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON register and then set the SSPEN bit. If a Master mode of operation is selected in the SSPM bits of the SSPCON register, the SDI, SDO and SCK pins will be assigned as serial port pins. For these pins to function as serial port pins, they must have their corresponding data direction bits set or cleared in the associated TRIS register as follows: * SDI configured as input * SDO configured as output * SCK configured as output
In Master mode, all module clocks are halted and the transmission/reception will remain in their current state, paused, until the device wakes from Sleep. After the device wakes up from Sleep, the module will continue to transmit/receive data.
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FIGURE 17-3:
Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0
SPI MASTER MODE WAVEFORM
4 Clock Modes
bit 7
bit 0
bit 7
bit 0
EXAMPLE 17-1:
LOOP BANKSEL BTFSS GOTO BANKSEL MOVF MOVWF MOVF MOVWF
LOADING THE SSPBUF (SSPSR) REGISTER
SSPSTAT SSPSTAT, BF LOOP SSPBUF SSPBUF, W RXDATA TXDATA, W SSPBUF ; ;Has data been received(transmit complete)? ;No ; ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit
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17.1.2 SLAVE MODE 17.1.2.2 Enabling Slave I/O
For any SPI device acting as a slave, the data is transmitted and received as external clock pulses appear on SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. To enable the serial port, the SSPEN bit of the SSPCON register must be set. If a Slave mode of operation is selected in the SSPM bits of the SSPCON register, the SDI, SDO and SCK pins will be assigned as serial port pins. For these pins to function as serial port pins, they must have their corresponding data direction bits set or cleared in the associated TRIS register as follows: * SDI configured as input * SDO configured as output * SCK configured as input Optionally, a fourth pin, Slave Select (SS) may be used in Slave mode. Slave Select may be configured to operate on the RC6/SS pin via the SSSEL bit in the APFCON register. Upon selection of a Slave Select pin, the appropriate bits must be set in the ANSELA and TRISA registers. Slave Select must be set as an input by setting the corresponding bit in TRISA, and digital I/O must be enabled on the SS pin by clearing the corresponding bit of the ANSELA register.
17.1.2.1
Slave Mode Operation
The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. The slave has no control as to when data will be clocked in or out of the device. All data that is to be transmitted, to a master or another slave, must be loaded into the SSPBUF register before the first clock pulse is received. Once eight bits of data have been received: * Received byte is moved to the SSPBUF register * BF bit of the SSPSTAT register is set * SSPIF bit of the PIR1 register is set Any write to the SSPBUF register during transmission/ reception of data will be ignored and the Write Collision Detect bit, WCOL of the SSPCON register, will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. The user's firmware must read SSPBUF, clearing the BF flag, or the SSPOV bit of the SSPCON register will be set with the reception of the next byte and communication will be disabled. A SPI module transmits and receives at the same time, occasionally causing dummy data to be transmitted/ received. It is up to the user to determine which data is to be used and what can be discarded.
17.1.2.3
Slave Mode Setup
When initializing the SSP module to SPI Slave mode, compatibility must be ensured with the master device. This is done by programming the appropriate control bits of the SSPCON and SSPSTAT registers. These control bits allow the following to be specified: * * * * SCK as clock input Idle state of SCK (CKP bit) Data input sample phase (SMP bit) Output data on rising/falling edge of SCK (CKE bit)
Figure 17-4 and Figure 17-5 show example waveforms of Slave mode operation.
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FIGURE 17-4:
SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
bit 7
bit 0
FIGURE 17-5:
SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 0
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17.1.2.4 Slave Select Operation
The SS pin allows Synchronous Slave mode operation. The SPI must be in Slave mode with SS pin control enabled (SSPM<3:0> = 0100). The associated TRIS bit for the SS pin must be set, making SS an input. In Slave Select mode, when: * SS = 0, The device operates as specified in Section 17.1.2 "Slave Mode". * SS = 1, The SPI module is held in Reset and the SDO pin will be tri-stated. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPM<3:0> = 0100), the SPI module will reset if the SS pin is driven high. 2: If the SPI is used in Slave mode with CKE set, the SS pin control must be enabled. When the SPI module resets, the bit counter is cleared to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. Figure 17-6 shows the timing waveform for such a synchronization event. Note: SSPSR must be reinitialized by writing to the SSPBUF register before the data can be clocked out of the slave again.
17.1.2.5
Sleep in Slave Mode
While in Sleep mode, the slave can transmit/receive data. The SPI Transmit/Receive Shift register operates asynchronously to the device on the externally supplied clock source. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the SSP Interrupt Flag bit will be set and, if enabled, will wake the device from Sleep.
FIGURE 17-6:
SS
SLAVE SELECT SYNCHRONIZATION WAVEFORM
SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0)
Write to SSPBUF
SSPSR must be reinitialized by writing to the SSPBUF register before the data can be clocked out of the slave again.
SDO
bit 7
bit 6
bit 7
bit 0
SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
bit 0 bit 7 bit 7
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REGISTER 17-1:
R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)
R/W-0 R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
SSPOV
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins(1) 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level SSPM<3:0>: Synchronous Serial Port mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. When enabled, these pins must be properly configured as input or output.
bit 6
bit 5
bit 4
bit 3-0
Note 1:
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REGISTER 17-2:
R/W-0 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE)
R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data stable on rising edge of SCK 0 = Data stable on falling edge of SCK SPI mode, CKP = 1: 1 = Data stable on falling edge of SCK 0 = Data stable on rising edge of SCK D/A: Data/Address bit Used in I2C mode only. P: Stop bit Used in I2C mode only. S: Start bit Used in I2C mode only. R/W: Read/Write Information bit Used in I2C mode only. UA: Update Address bit Used in I2C mode only. BF: Buffer Full Status bit 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty
bit 6
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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TABLE 17-1:
Name ANSELC INTCON PIE1 PIR1 PR2 SSPBUF SSPCON SSPSTAT TRISB TRISC T2CON Legend: WCOL SMP TRISB7 TRISC7 -- Bit 7 ANSC7 GIE TMR1GIE TMR1GIF
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 6 ANSC6 PEIE ADIE ADIF Bit 5 -- TMR0IE RCIE RCIF Bit 4 -- INTE TXIE TXIF Bit 3 ANSC3 RABIE SSPIE SSPIF Bit 2 ANSC2 TMR0IF CCP1IE CCP1IF Bit 1 ANSC1 INTF TMR2IE TMR2IF Bit 0 ANSC0 RABIF TMR1IE TMR1IF Value on POR, BOR 11-- 1111 0000 000x 0000 0000 0000 0000 1111 1111 xxxx xxxx SSPM0 BF -- TRISC0 T2CKPS0 0000 0000 0000 0000 1111 ---1111 1111 -000 0000 Value on all other Resets 11-- 1111 0000 000x 0000 0000 0000 0000 1111 1111 uuuu uuuu 0000 0000 0000 0000 1111 ---1111 1111 -000 0000
Timer2 module Period Register Synchronous Serial Port Receive Buffer/Transmit Register SSPOV CKE TRISB6 TRISC6 TOUTPS3 SSPEN D/A TRISB5 TRISC5 TOUTPS2 CKP P TRISB4 TRISC4 TOUTPS1 SSPM3 S -- TRISC3 TOUTPS0 SSPM2 R/W -- TRISC2 TMR2ON SSPM1 UA -- TRISC1 T2CKPS1
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode.
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17.2 I2C Mode
FIGURE 17-8:
The SSP module, in I2C mode, implements all slave functions except general call support. It provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the I2C Standard mode specifications: * * * I2C Slave mode (7-bit address) I2C Slave mode (10-bit address) Start and Stop bit interrupts enabled to support firmware Master mode * Address masking Two pins are used for data transfer; the SCL pin (clock line) and the SDA pin (data line). The user must configure the two pin's data direction bits as inputs in the appropriate TRIS register. Upon enabling I2C mode, the I2C slew rate limiters in the I/O pads are controlled by the SMP bit of SSPSTAT register. The SSP module functions are enabled by setting the SSPEN bit of SSPCON register. Data is sampled on the rising edge and shifted out on the falling edge of the clock. This ensures that the SDA signal is valid during the SCL high time. The SCL clock input must have minimum high and low times for proper operation. Refer to Section 23.0 "Electrical Specifications".
Master SDA SCL
TYPICAL I2CTM CONNECTIONS
VDD VDD
Slave 1 SDA SCL Slave 2 SDA SCL (optional)
The SSP module has six registers for I2C operation. They are: SSP Control (SSPCON) register SSP Status (SSPSTAT) register Serial Receive/Transmit Buffer (SSPBUF) register SSP Shift Register (SSPSR), not directly accessible * SSP Address (SSPADD) register * SSP Address Mask (SSPMSK) register * * * *
FIGURE 17-7:
I2CTM MODE BLOCK DIAGRAM
Internal Data Bus Read SSPBUF Reg Shift Clock SSPSR Reg Write
17.2.1
HARDWARE SETUP
SCL
Selection of I2C mode, with the SSPEN bit of the SSPCON register set, forces the SCL and SDA pins to be open drain, provided these pins are programmed as inputs by setting the appropriate TRISC bits. The SSP module will override the input state with the output data, when required, such as for Acknowledge and slavetransmitter sequences. Note: Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module.
SDA
MSb
LSb SSPMSK Reg Match Detect SSPADD Reg Start and Stop bit Detect Addr Match
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17.2.2 START AND STOP CONDITIONS
During times of no data transfer (Idle time), both the clock line (SCL) and the data line (SDA) are pulled high through external pull-up resistors. The Start and Stop conditions determine the start and stop of data transmission. The Start condition is defined as a high-to-low transition of the SDA line while SCL is high. The Stop condition is defined as a low-to-high transition of the SDA line while SCL is high. Figure 17-9 shows the Start and Stop conditions. A master device generates these conditions for starting and terminating data transfer. Due to the definition of the Start and Stop conditions, when data is being transmitted, the SDA line can only change state when the SCL line is low.
FIGURE 17-9:
START AND STOP CONDITIONS
SDA
SCL S Change of Start Condition Data Allowed Change of Data Allowed Stop Condition P
17.2.3
ACKNOWLEDGE
After the valid reception of an address or data byte, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to generate this ACK pulse. They include any or all of the following: * The Buffer Full bit, BF of the SSPSTAT register, was set before the transfer was received. * The SSP Overflow bit, SSPOV of the SSPCON register, was set before the transfer was received. * The SSP module is being operated in Firmware Master mode.
In such a case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF of the PIR1 register is set. Table 17-2 shows the results of when a data transfer byte is received, given the status of bits BF and SSPOV. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software.
TABLE 17-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
SSPSR SSPBUF Yes No No No Generate ACK Pulse Yes No No No Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 0 Note 1: SSPOV 0 0 1 1
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
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17.2.4 ADDRESSING 17.2.4.2 10-bit Addressing
Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock line (SCL). In 10-bit Address mode, two address bytes need to be received by the slave (Figure 17-11). The five Most Significant bits (MSbs) of the first address byte specify if it is a 10-bit address. The R/W bit of the SSPSTAT register must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows for reception: 1. 2. 3. 4. 5. Load SSPADD register with high byte of address. Receive first (high) byte of address (bits SSPIF, BF and UA of the SSPSTAT register are set). Read the SSPBUF register (clears bit BF). Clear the SSPIF flag bit. Update the SSPADD register with second (low) byte of address (clears UA bit and releases the SCL line). Receive low byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the high byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF). Clear flag bit SSPIF.
17.2.4.1
7-bit Addressing
In 7-bit Addressing mode (Figure 17-10), the value of register SSPSR<7:1> is compared to the value of register SSPADD<7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: * The SSPSR register value is loaded into the SSPBUF register. * The BF bit is set. * An ACK pulse is generated. * SSP Interrupt Flag bit, SSPIF of the PIR1 register, is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse.
6. 7.
8. 9.
If data is requested by the master, once the slave has been addressed: 1. 2. 3. 4. 5. Receive repeated Start condition. Receive repeat of high byte address with R/W = 1, indicating a read. BF bit is set and the CKP bit is cleared, stopping SCL and indicating a read request. SSPBUF is written, setting BF, with the data to send to the master device. CKP is set in software, releasing the SCL line.
17.2.4.3
Address Masking
The Address Masking register (SSPMSK) is only accessible while the SSPM bits of the SSPCON register are set to `1001'. In this register, the user can select which bits of a received address the hardware will compare when determining an address match. Any bit that is set to a zero in the SSPMSK register, the corresponding bit in the received address byte and SSPADD register are ignored when determining an address match. By default, the register is set to all ones, requiring a complete match of a 7-bit address or the lower eight bits of a 10-bit address.
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17.2.5 RECEPTION
When the R/W bit of the received address byte is clear, the master will write data to the slave. If an address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received. An SSP interrupt is generated for each data transfer byte. The BF, R/W and D/A bits of the SSPSTAT register are used to determine the status of the last received byte.
FIGURE 17-10:
I2CTM WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W = 0 ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 8 9 1 2 3 4 5 6 7 8 9 ACK Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P
Receiving Address SDA A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7
SCL SSPIF
S
Cleared in software
Bus Master sends Stop condition
BF
SSPBUF register is read
SSPOV Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
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FIGURE 17-11:
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte ACK A7 A0 D7 D6 A6 A3 A2 A1 D3 D5 D4 A5 A4 D5 D4 D2 D1 D0 D7 D6 ACK Receive Data Byte D3 D2 A9 R/W ACK A8 0
2010 Microchip Technology Inc.
Clock is held low until update of SSPADD has taken place Clock is held low until update of SSPADD has taken place ACK D1 D0 6 4 1 5 6 7 1 2 3 4 5 6 7 8 7 1 2 3 2 8 9 8 9 9 3 4 5 6 7 8 9 P Bus master sends Stop condition Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address
SDA
1
1
1
1
0
SCL
S
1
2
3
4
5
SSPIF
Cleared in software
BF
SSPBUF is written with contents of SSPSR
SSPOV
UA
I2CTM SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
UA is set indicating that the SSPADD needs to be updated
CKP
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17.2.6 TRANSMISSION
When the R/W bit of the received address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set and the slave will respond to the master by reading out data. After the address match, an ACK pulse is generated by the slave hardware and the SCL pin is held low (clock is automatically stretched) until the slave is ready to respond. See Section 17.2.7 "Clock Stretching". The data the slave will transmit must be loaded into the SSPBUF register, which sets the BF bit. The SCL line is released by setting the CKP bit of the SSPCON register. An SSP interrupt is generated for each transferred data byte. The SSPIF flag bit of the PIR1 register initiates an SSP interrupt, and must be cleared by software before the next byte is transmitted. The BF bit of the SSPSTAT register is cleared on the falling edge of the 8th received clock pulse. The SSPIF flag bit is set on the falling edge of the ninth clock pulse. Following the 8th falling clock edge, control of the SDA line is released back to the master so that the master can acknowledge or not acknowledge the response. If the master sends a not acknowledge, the slave's transmission is complete and the slave must monitor for the next Start condition. If the master acknowledges, control of the bus is returned to the slave to transmit another byte of data. Just as with the previous byte, the clock is stretched by the slave, data must be loaded into the SSPBUF and CKP must be set to release the clock line (SCL).
FIGURE 17-12:
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF BF
Dummy read of SSPBUF to clear BF flag
Cleared in software
SSPBUF is written in software
From SSP Interrupt Service Routine
CKP Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)
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FIGURE 17-13:
Bus Master sends Stop condition Clock is held low until CKP is set to `1' Receive First Byte of Address R/W = 1 ACK ACK 1 1 1 1 0 A9 A8 Transmitting Data Byte D7 D6 D5 D4 D3 D2 D1 D0 ACK
2010 Microchip Technology Inc.
Clock is held low until update of SSPADD has taken place R/W = 0 Receive Second Byte of Address ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPADD has taken place Bus Master sends Restarts condition 4 Sr 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF Dummy read of SSPBUF to clear BF flag Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address. UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address. CKP is set in software, initiates transmission CKP is automatically cleared in hardware holding SCL low
Receive First Byte of Address
SDA
1
1
1
SCL
S
1
2
3
SSPIF
BF
SSPBUF is written with contents of SSPSR
UA
UA is set indicating that the SSPADD needs to be updated
I2C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)
CKP
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17.2.7 CLOCK STRETCHING
2
During any SCL low phase, any device on the I C bus may hold the SCL line low and delay, or pause, the transmission of data. This "stretching" of a transmission allows devices to slow down communication on the bus. The SCL line must be constantly sampled by the master to ensure that all devices on the bus have released SCL for more data. Stretching usually occurs after an ACK bit of a transmission, delaying the first bit of the next byte. The SSP module hardware automatically stretches for two conditions: * After a 10-bit address byte is received (update SSPADD register) * Anytime the CKP bit of the SSPCON register is cleared by hardware The module will hold SCL low until the CKP bit is set. This allows the user slave software to update SSPBUF with data that may not be readily available. In 10-bit addressing modes, the SSPADD register must be updated after receiving the first and second address bytes. The SSP module will hold the SCL line low until the SSPADD has a byte written to it. The UA bit of the SSPSTAT register will be set, along with SSPIF, indicating an address update is needed.
Refer to Application Note AN554, "Software Implementation of I2CTM Bus Master" (DS00554) for more information.
17.2.9
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allow the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit of the SSPSTAT register is set or when the bus is Idle, and both the S and P bits are clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the Stop condition occurs. In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRIS bits). There are two stages where this arbitration of the bus can be lost. They are the Address Transfer and Data Transfer stages. When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. Refer to Application Note AN578, "Use of the SSP Module in the I2CTM Multi-Master Environment" (DS00578) for more information.
17.2.8
FIRMWARE MASTER MODE
Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits of the SSPSTAT register are cleared from a Reset or when the SSP module is disabled (SSPEN cleared). The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit is set or the bus is Idle and both the S and P bits are clear. In Firmware Master mode, the SCL and SDA lines are manipulated by setting/clearing the corresponding TRIS bit(s). The output level is always low, irrespective of the value(s) in the corresponding PORT register bit(s). When transmitting a `1', the TRIS bit must be set (input) and a `0', the TRIS bit must be clear (output). The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): * Start condition * Stop condition * Data transfer byte transmitted/received Firmware Master mode of operation can be done with either the Slave mode Idle (SSPM<3:0> = 1011), or with either of the Slave modes in which interrupts are enabled. When both master and slave functionality is enabled, the software needs to differentiate the source(s) of the interrupt.
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17.2.10 CLOCK SYNCHRONIZATION 17.2.11 SLEEP OPERATION
When the CKP bit is cleared, the SCL output is held low once it is sampled low. Therefore, the CKP bit will not stretch the SCL line until an external I2C master device has already asserted the SCL line low. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (Figure 17-14). While in Sleep mode, the I2C module can receive addresses of data, and when an address match or complete byte transfer occurs, wake the processor from Sleep (if SSP interrupt is enabled).
FIGURE 17-14:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device asserts clock Master device deasserts clock
WR SSPCON
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REGISTER 17-3:
R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE)
R/W-0 R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
SSPOV
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit 1 = Release control of SCL 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) SSPM<3:0>: Synchronous Serial Port mode Select bits 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = Reserved 1001 = Load SSPMSK register at SSPADD SFR Address(1) 1010 = Reserved 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
bit 6
bit 5
bit 4
bit 3-0
Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register. 2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.
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REGISTER 17-4:
R/W-0 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE)
R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
SMP: SPI Data Input Sample Phase bit 1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard mode (100 kHz and 1 MHz). 0 = Slew Rate Control (limiting) enabled. Operating in I2C Fast mode (400 kHz). CKE: SPI Clock Edge Select bit This bit must be maintained clear. Used in SPI mode only. D/A: DATA/ADDRESS bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last S: Start bit This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last R/W: READ/WRITE bit Information This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit: 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty
bit 6 bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 17-5:
R/W-1 MSK7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPMSK: SSP MASK REGISTER
R/W-1 MSK6 R/W-1 MSK5 R/W-1 MSK4 R/W-1 MSK3 R/W-1 MSK2 R/W-1 MSK1 R/W-1 MSK0 bit 0
MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match MSK<0>: Mask bit for I2C Slave Mode, 10-bit Address I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111): 1 = The received address bit `0' is compared to SSPADD<0> to detect I2C address match 0 = The received address bit `0' is not used to detect I2C address match All other SSP modes: this bit has no effect.
bit 0
REGISTER 17-6:
R/W-0 ADD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
SSPADD: SSP I2C ADDRESS REGISTER
R/W-0 ADD6 R/W-0 ADD5 R/W-0 ADD4 R/W-0 ADD3 R/W-0 ADD2 R/W-0 ADD1 R/W-0 ADD0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADD<7:0>: Address bits Received address
TABLE 17-3:
Name INTCON PIR1 PIE1 SSPBUF SSPADD SSPCON SSPMSK(2) SSPSTAT TRISB Legend: Note 1: 2:
REGISTERS ASSOCIATED WITH I2C OPERATION
Bit 7 GIE Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RABIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RABIF TMR1IF TMR1IE Value on POR, BOR 0000 000x 0000 0000 0000 0000 xxxx xxxx 0000 0000 SSPM2 R/W
--
Value on all other Resets 0000 000x 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 1111 1111 0000 0000 1111 ----
TMR1GIF TMR1GIE
Synchronous Serial Port Receive Buffer/Transmit Register ADD<7:0> WCOL SMP(1) TRISB7 SSPOV CKE(1) TRISB6 SSPEN D/A TRISB5 CKP P TRISB4 SSPM3 S
--
SSPM1 UA
--
SSPM0 BF
--
0000 0000 1111 1111 0000 0000 1111 ----
MSK<7:0>
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by SSP module in I2C mode. Maintain these bits clear in I2C mode. Accessible only when SSPM<3:0> = 1001.
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18.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL
18.1 Program Memory Read Operation
To read a program memory location, the user must write two bytes of the address to the PMADRH and PMADRL registers, then set control bit RD (PMCON1<0>). Once the read control bit is set, the Program Memory Read (PMR) controller uses the two instruction cycles to read the data. This causes the two instructions immediately following the `BSF PMCON1, RD' instruction to be ignored. The data is available in the third cycle, following the set of the RD bit, in the PMDATH and PMDATL registers. PMDATL and PMDATH registers will hold this value until another read is executed. See Example 18-1 and Figure 18-1 for more information.
The Flash Program Memory is readable and writable during normal operation of the device. This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are six SFRs used to read/write this memory: * * * * * * PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH
Note:
When interfacing the program memory block, the PMDATL and PMDATH registers form a two byte word which holds the 14-bit program data for reading, and the PMADRL and PMADRH registers form a two byte word which holds the 13-bit address of the program Flash location being accessed. These devices have 2K to 4K words of program memory with an address range from 0000h to 0FFFh. Devices without a full map of memory will shadow accesses to unused blocks back to the implemented memory.
Interrupts must be disabled during the time from setting PMCON1<0> (RD) to the third instruction thereafter.
EXAMPLE 18-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL BANKSEL BCF BSF NOP NOP BSF BANKSEL MOVF MOVWF MOVF MOVWF PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH PMCON1 INTCON,GIE PMCON1,RD ; Select Bank 2 ; ; Store LSB of address ; ; Store MSB of address ; ; ; ; ; ; ; ; ; ; ; Select Bank 3 Disable interrupts Initiate read Ignored (Figure 18-1) Ignored (Figure 18-1) Restore interrupts Select Bank 2 Get LSB of word Store in user location Get MSB of word Store in user location
INTCON,GIE PMDATL PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI
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FIGURE 18-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION - NORMAL MODE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Flash ADDR
PC
PC + 1
PMADRH, PMADRL
PC+3
PC + 4
PC + 5
Flash DATA
INSTR (PC)
INSTR (PC + 1)
PMDATH, PMDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR (PC - 1) Executed here
BSF PMCON1, RD Executed here
Forced NOP Executed here
Forced NOP Executed here
INSTR (PC + 3) Executed here
INSTR (PC + 4) Executed here
RD bit
PMDATH PMDATL Register
Force NOP Stop PC
18.2
Code Protection
18.4
PMCON1 and PMCON2 Registers
When the device is code-protected, the CPU may continue to read and write the Flash program memory. Depending on the settings of the Flash program memory enable (WRT<1:0>) bits, the device may or may not be able to write certain blocks of the program memory. However, reads of the program memory are allowed. When the Flash program memory Code Protection (CP) bit in the Configuration Word register is enabled, the program memory is code-protected, and the device programmer (ICSPTM) cannot access data or program memory.
PMCON1 is the control register for the data program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, but only set in software. They are cleared in hardware at the completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation. Setting the control bit WR initiates a write operation. For program memory writes, WR initiates a write cycle if FREE = 0 and an erase cycle if FREE = 1. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. PMCON2 is not a physical register. Reading PMCON2 will read all `0's. The PMCON2 register is used exclusively in the Flash memory write sequence.
Note:
Code-protect does not affect the CPU from performing a read operation on the program memory. For more information, refer to Section 8.2 "Code Protection".
18.3
PMADRH and PMADRL Registers
The PMADRH:PMADRL register pair can address up to a maximum of 4K words of program Flash. The Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register.
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18.5 Writing to Flash Program Memory
A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory. Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of the Configuration Word Register 2. Flash program memory must be written in 32-word rows. See Figure 18-2 for more details. A row consists of 32 words with sequential addresses, with a lower boundary defined by an address, where PMADR<4:0>= 00000. All row writes to program memory are done as 32-word erase and one to 32-word write operations. The write operation is edge-aligned. Crossing boundaries is not recommended, as the operation will only affect the new boundary, wrapping the data values at the same time. Once the write control bit is set, the Program Memory (PM) controller will immediately write the data. Program execution is stalled while the write is in progress. To erase a program memory row, the address of the row to erase must be loaded into the PMADRH:PMADRL register pair. A row consists of 32 words so, when selecting a row, PMADR<4:0> are ignored. After the Address has been set up, then the following sequence of events must be executed: 1. 2. 3. Set the WREN and FREE control bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set the WR control bit of the PMCON1 register. When the LWLO bit is `1', the write sequence will only load the buffer register and will not actually initiate the write to program Flash: 1. 2. 3. Set the WREN and LWLO bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the write operation.
Note:
Self-write execution to Flash memory cannot be done while running in low power PFM and Voltage Regulator modes. Therefore, executing a self-write will put the PFM and voltage regulator into High Power mode for the duration of the sequence.
To transfer data from the buffer registers to the program memory, the last word to be written should be written to the PMDATH:PMDATL register pair. Then, the following sequence of events must be executed: 1. 2. 3. 4. Clear the LWLO bit of the PMCON1 Register. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set control bit WR of the PMCON1 register to begin the write operation. Two NOP must follow the setting of the WR bit.
This is necessary to provide time for the address and to be provided to the program Flash memory to be put in the write latches.
To write program data, it must first be loaded into the buffer latches (see Figure 18-2). This is accomplished by first writing the destination address to PMADRL and PMADRH and then writing the data to PMDATA and PMDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. 2. 3. Set the WREN control bit of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set the WR control bit of the PMCON1 register.
Note:
An ICD break that occurs during the 55h AAh - Set WR bit sequence will interrupt the timing of the sequence and prevent the unlock sequence from occurring. In this case, no write will be initiated, as there was no operation to complete.
No automatic erase occurs upon the initiation of the write; if the program Flash needs to be erased before writing, the row (32 words) must be previously erased. After the "BSF PMCON1, WR" instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. These two instructions will also be forced in hardware to NOP, but if an ICD break occurs at this point, the forcing to NOP will be lost.
All 32 buffer register locations should be written to with correct data. If less than 32 words are being written to in the block of 32 words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the PMDATL and PMDATH registers. Then, the sequence of events to transfer data to the buffer registers must be executed.
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Since data is being written to buffer registers, the writing of the first 31 words of the block appears to occur immediately. The processor will halt internal operations for the typical 4ms, only during the cycle in which the erase takes place (i.e., the last word of the 32-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the 32word write cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction.
FIGURE 18-2:
BLOCK OF 32 WRITES TO FLASH PROGRAM MEMORY
7 5 PMDATH 07 PMDATL 0
6
8
14
PMADRL<4:0> = 00000 PMADRL<4:0> = 00001
14
PMADRL<4:0> = 00010
14
PMADRL<4:0> = 11111
14
Buffer Register
Buffer Register
Buffer Register
Buffer Register
Program Memory
An example of the complete 32-word write sequence is shown in Example 18-2. The initial address is loaded into the PMADRH:PMADRL register pair; the 32 words of data are loaded using indirect addressing.
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EXAMPLE 18-2:
; ; ; ; ;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following: 1. A valid starting address (the least significant bits = `00000')is loaded in ADDRH:ADDRL 2. The 64 bytes of data are loaded, starting at the address in DATADDR 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f BANKSEL MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF PMADRH ADDRH,W PMADRH ADDRL,W PMADRL DATAADDRL,W FSR0L DATAADDRH,W FSR0H INDF0++ PMDATL INDF0++ PMDATH PMCON1,WREN PMCON1,LWLO 55h PMCON2 AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank 3 Load initial address
Load initial data address Load initial data address
LOOP
MOVIW MOVWF MOVIW MOVWF BSF BSF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP
Load first data byte into lower Load second data byte into upper Enable writes Only Load Write Latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction
Required Sequence
MOVF XORLW ANDLW BTFSC GOTO INCF GOTO START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF
PMADR,W 0x1F 0x1F STATUS,Z START_WRITE PMADR,F LOOP
; Check if lower five bits of address are `11111' ; Check if we're on the last of 8 addresses ; ; Exit if last of 32 words, ; ; Still loading latches Increment address ; Write next latches
PMCON1,LWLO 55h PMCON2 AAh PMCON2 PMCON1,WR
; No more Latches only; Actually start write ; ; ; ; ; ; ; ; ; ; Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction Disable writes
Required Sequence
PMCON1,WREN
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18.6 Protection Against Spurious Write 18.7 Operation During Code-Protect
There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents program memory writes. The write initiates sequence and the WREN bit helps prevent an accidental write during brown-out, power glitch or software malfunction. When the device is code-protected, the CPU is able to read and write unscrambled data to the program memory.
18.8
Operation During Write-Protect
When the program memory is write-protected, the CPU can read and execute from the program memory. The portions of program memory that are write-protected can be modified by the CPU using the PMCON registers, but the protected program memory cannot be modified using ICSP mode.
REGISTER 18-1:
U-1 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
R/W-0/0 LWLO R/W/HC-0/0 FREE U-0 -- R/W-0/0 WREN R/S/HC-0/0 WR R/S/HC-0/0 RD bit 0 S = Setable bit, cleared in hardware W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CFGS
R/W-0/0
Unimplemented: Read as `1' CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, user ID and device ID registers 0 = Accesses Flash program LWLO: Load Write Latches Only bit 1= The next WR command does not initiate a write to the PFM; only the program memory latches are updated. 0= The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write to the PFM of all the data stored in the program memory latches. FREE: Program Flash Erase Enable bit 1= Perform an program Flash erase operation on the next WR command (cleared by hardware after completion of erase). 0= Perform a program Flash write operation on the next WR command. Unimplemented: Read as `0' WREN: Program/Erase Enable bit 1 = Allows program/erase cycles. 0 = Inhibits programming/erasing of Program Flash and Data EEPROM. WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive. RD: Read Control bit 1 = Initiates an program memory read (The RD is cleared in hardware; the RD bit can only be set (not cleared) in software). 0 = Does not initiate a program memory read
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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REGISTER 18-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PMDATH: PROGRAM MEMORY DATA HIGH REGISTER
U-0 -- R/W-x PMD13 R/W-x PMD12 R/W-x PMD11 R/W-x PMD10 R/W-x PMD9 R/W-x PMD8 bit 0
Unimplemented: Read as `0' PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a program memory read command.
REGISTER 18-3:
R/W-x PMD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PMDATL: PROGRAM MEMORY DATA LOW REGISTER
R/W-x PMD6 R/W-x PMD5 R/W-x PMD4 R/W-x PMD3 R/W-x PMD2 R/W-x PMD1 R/W-x PMD0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a program memory read command.
REGISTER 18-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0
PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER
U-0 -- U-0 -- R/W-x PMA12 R/W-x PMA11 R/W-x PMA10 R/W-x PMA9 R/W-x PMA8 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PMA<12:8>: Program Memory Read Address bits
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REGISTER 18-5:
R/W-x PMA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER
R/W-x PMA6 R/W-x PMA5 R/W-x PMA4 R/W-x PMA3 R/W-x PMA2 R/W-x PMA1 R/W-x PMA0 bit 0
PMA<7:0>: Program Memory Read Address bits
TABLE 18-1:
Name PMCON1 PMCON2 PMADRH PMADRL PMDATH PMDATL Legend: -- --
SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ
Bit 6 CFGS -- -- Bit 5 LWLO -- Bit 4 FREE Bit 3 -- Bit 2 WREN Bit 1 WR Bit 0 RD Value on POR, BOR 1000 -000 ---- ------0 0000 0000 0000 --xx xxxx xxxx xxxx Value on all other Resets 1000 -000 ---- ------0 0000 0000 0000 --xx xxxx xxxx xxxx
Bit 7 --
Program Memory Control Register 2 (not a physical register) Program Memory Read Address Register High Byte Program Memory Read Data Register High Byte Program Memory Read Data Register Low Byte Program Memory Read Address Register Low Byte
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the program memory read.
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19.0 POWER-DOWN MODE (SLEEP)
19.1 Wake-up from Sleep
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RA2/INT pin, PORTB change or a peripheral interrupt.
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level when external MCLR is enabled. Note: A Reset generated by a WDT time-out does not drive MCLR pin low.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of a device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. USART Receive Interrupt (Synchronous Slave mode only) A/D conversion (when A/D clock source is RC) Interrupt-on-change External interrupt from INT pin Capture event on CCP1 SSP interrupt in SPI or I2C Slave mode
Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
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19.2 Wake-up Using Interrupts
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
FIGURE 19-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Oscillator CLKOUT(3) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Processor in Sleep
Interrupt Latency (2)
PC Inst(PC) = Sleep Inst(PC - 1)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
Note
1: 2: 3:
TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC mode. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in EC Oscillator mode, but shown here for timing reference.
TABLE 19-1:
Name IOCB INTCON PIE1 PIR1 Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Bit 7 Bit 6 IOCB6 PEIE ADIE ADIF Bit 5 IOCB5 TMR0IE RCIE RCIF Bit 4 IOCB4 INTE TXIE TXIF Bit 3 -- RABIE SSPIE SSPIF Bit 2 -- TMR0IF CCP1IE CCP1IF Bit 1 -- INTF TMR2IE TMR2IF Bit 0 -- RABIF TMR1IE TMR1IF Value on POR, BOR 0000 ---0000 000x 0000 0000 0000 0000 Value on all other Resets 0000 ---0000 000x 0000 0000 0000 0000
IOCB7 GIE TMR1GIE TMR1GIF
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used in Power-Down mode.
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20.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM)
The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP from 0V to VPP. In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ISCPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC16F72x/PIC16LF72x Programming Specification" (DS41332). Note: The MPLAB(R) ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16F/LF720/721. When using this programmer, an external circuit, such as the AC164112 MPLAB ICD 2 VPP voltage limiter, is required to keep the VPP voltage within the device specifications.
ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS
FIGURE 20-1:
TYPICAL CONNECTION FOR ICSPTM PROGRAMMING
External Programming Signals
VDD
Device to be Programmed
VDD 10k VPP GND Data Clock
VDD MCLR/VPP VSS ICSPDAT ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
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NOTES:
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21.0 INSTRUCTION SET SUMMARY
TABLE 21-1:
Field
f W b k x
The PIC16F/LF720/721 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 21-1, while the various opcode fields are summarized in Table 21-1. Table 21-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
d
PC TO C DC Z PD
FIGURE 21-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations
0
21.1
Read-Modify-Write Operations
General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 8 7 k (literal) 0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTB instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended consequence of clearing the condition that set the RABIF flag.
k = 11-bit immediate value
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TABLE 21-2:
Mnemonic, Operands
PIC16F/LF720/721 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C, DC, Z Z Z Z Z Z Z Z Z
1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, b f, b f, b f, b k k k - k k k - k - - k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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21.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d 0,1 (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b' in register `f' is `0' the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d 0,1 (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. k
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0
MOVWF Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVW F OPTION MOVWF f 0 f 127
Words: Cycles: Example:
Before Instruction OPTION = W = After Instruction OPTION = W =
0xFF 0x4F 0x4F 0x4F
After Instruction W= value in FSR register Z=1
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A
NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None No operation. 1 1
NOP
MOVLW k
NOP
0 k 255
Words: Cycles: Example:
After Instruction W=
0x5A
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RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table
;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
RETFIE
Words: Cycles: Example:
Words: Cycles: Example:
After Interrupt PC = GIE =
TABLE TOS 1
Before Instruction W = 0x07 After Instruction W = value of k8
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
SLEEP Syntax: Operands: Operation:
Enter Sleep mode [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
RLF
f,d
Status Affected: Description:
Words: Cycles: Example:
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Before Instruction
After Instruction
REG1 W C
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBLW Syntax: Operands: Operation: Description:
Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. C=0 C=1 DC = 0 DC = 1 Wk Wk W<3:0> k<3:0> W<3:0> k<3:0>
Status Affected: C, DC, Z
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SUBWF Syntax: Operands: Operation: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. C=0 C=1 DC = 0 DC = 1 Wf Wf W<3:0> f<3:0> W<3:0> f<3:0> XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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NOTES:
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1.0 DEVELOPMENT SUPPORT
1.1
The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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1.2 MPLAB C Compilers for Various Device Families 1.5 MPLINK Object Linker/ MPLIB Object Librarian
The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
1.3
HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.
1.6
MPLAB Assembler, Linker and Librarian for Various Device Families
1.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
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1.7 MPLAB SIM Software Simulator 1.9
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.
1.10
1.8
MPLAB REAL ICE In-Circuit Emulator System
PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
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1.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 1.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
1.12
MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.
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23.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS, PIC16F720/721 ........................................................................ -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF720/721 ...................................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by all ports, -40C TA +85C for industrial............................................................ 200 mA Maximum current sunk by all ports, -40C TA +125C for extended ........................................................... 90 mA Maximum current sourced by all ports, 40C TA +85C for industrial....................................................... 140 mA Maximum current sourced by all ports, -40C TA +125C for extended ...................................................... 65 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
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23.1 DC Characteristics: PIC16F/LF720/721-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage PIC16LF720/721 D001 D002* D002* VPOR* VPORR* VDR RAM Data Retention PIC16F720/721 Voltage(1) 1.5 1.7 -- -- -- -5.5 -5.5 -5.5 -6 -6 -6 D004* * SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 -- -- 1.6 0.8 1.5 -- -- -- -- -- -- -- -- -- -- -- -- 5.5 5.5 5.5 6 6 6 -- V V V V V % % % % % % V/ms Device in Sleep mode Device in Sleep mode VFVR = 1.024V, VDD 2.5V VFVR = 2.048V, VDD 2.5V VFVR = 4.096V, VDD 4.75V; -40 TA85C VFVR = 1.024V, VDD 2.5V VFVR = 2.048V, VDD 2.5V VFVR = 4.096V, VDD 4.75V; -40 TA125C See Section 3.2 "Power-on Reset (POR)" for details. Device in Sleep mode Device in Sleep mode PIC16F720/721 Power-on Reset Release Voltage Power-on Reset Rearm Voltage PIC16LF720/721 PIC16F720/721 D003 VFVR Fixed Voltage Reference Voltage, Initial Accuracy PIC16LF720/721 1.8 1.8 -- -- 3.6 5.5 V V FOSC 16 MHz: HFINTOSC, EC FOSC 16 MHz: HFINTOSC, EC Min. Typ Max. Units Conditions
PIC16LF720/721
PIC16F720/721 Param. No. D001 Sym. VDD
These parameters are characterized but not tested. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
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FIGURE 23-1:
VDD VPOR VPORR
POR AND POR REARM WITH SLOW RISING VDD
VSS NPOR
POR REARM VSS TPOR(3)
TVLOW(2) Note 1: 2: 3:
When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.
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23.2 DC Characteristics: PIC16F/LF720/721-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Conditions Min. Typ Max. Units VDD Note
PIC16LF720/721
PIC16F720/721
Param No.
Device Characteristics Supply Current (IDD)(1, 2)
D013 D013
-- -- -- -- -- Supply Current (IDD)
(1, 2)
125 230 150 225 250
180 270 205 320 410
A A A A A A A A A A A A A A A A A A A A mA mA mA mA mA
1.8 3.0 1.8 3.0 5.0
FOSC = 1 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode
D014 D014
-- -- -- -- --
290 460 300 450 500 100 120 115 135 150 650 1000 625 1000 1100 1.0 1.5 1 1.5 1.7
330 500 430 655 730 130 150 195 200 220 800 1200 850 1200 1500 1.2 1.85 1.2 1.7 2.1
1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0
FOSC = 4 MHz EC Oscillator mode FOSC = 4 MHz EC Oscillator mode
D015 D015
-- -- -- -- --
FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode
D016 D016
-- -- -- -- --
FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode
D017 D017
-- -- -- -- --
FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode
Note 1: 2:
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail (except for INTOSC mode); all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
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PIC16F/LF720/721
23.3 DC Characteristics: PIC16F/LF720/721-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. (IPD)(2) -- -- D020 -- -- -- D021 D021 -- -- -- -- -- D021A D021A -- -- -- -- -- D022 D022 -- -- -- -- -- Power-down Base Current (IPD) D027 D027
(2)
PIC16LF720/721
PIC16F720/721
Param No.
Device Characteristics Power-down Base Current
Typ
Max. +85C
Max. +125C
Conditions Units VDD A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Note
D020
0.02 0.08 17 20 22 0.5 0.8 18 21 23 8.5 8.5 35 42 72 -- 7.5 -- 36 70 0.06 0.08 16 21 25 250 250 280 280 280
1 2 35 40 50 6 7 35 40 55 23 26 50 72 120 -- 12 -- 59 100 0.7 1.0 36 24 54 400 400 430 430 430
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0
WDT, BOR, FVR, and all Peripherals Inactive WDT, BOR, FVR, and all Peripherals Inactive
LPWDT Current (Note 1) LPWDT Current (Note 1)
FVR current (Note 1. Note 3) FVR current (Note 1, Note 3)
BOR Current (Note 1, Note 3) BOR Current (Note 1, Note 3)
-- -- -- -- --
A/D Current (Note 1, Note 4), no conversion in progress A/D Current (Note 1, Note 4), no conversion in progress
D027A D027A
-- -- -- -- --
A/D Current (Note 1, Note 4), conversion in progress A/D Current (Note 1, Note 4), conversion in progress
Note 1:
2: 3: 4:
Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. A/D oscillator source is FRC.
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PIC16F/LF720/721
23.4 DC Characteristics: PIC16F/LF720/721-I/E
DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
Sym. VIL
Characteristic Input Low Voltage I/O PORT: with TTL buffer with Schmitt Trigger buffer with I2CTM levels MCLR, OSC1 (RC mode) OSC1 (HS mode)
D030 D030A D031 D032 D033A VIH D040 D040A D041 D042 D043A D043B IIL D060
-- -- -- -- -- --
-- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.3 VDD 0.2 VDD 0.3 VDD -- -- -- -- -- -- -- -- 125 1000 200 1500 200 300
V V V V V V
4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V
Input High Voltage I/O ports: with TTL buffer 2.0 0.25 VDD + 0.8 with Schmitt Trigger buffer with I2CTM levels MCLR OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current(1) I/O ports -- 5 5 nA nA nA nA VSS VPIN VDD, Pin at highimpedance, 85C 125C VSS VPIN VDD, 85C 125C VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V 0.8 VDD 0.7 VDD 0.8 VDD 0.7 VDD 0.9 VDD -- -- -- -- -- -- -- V V V V V V V 4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V
D061 IPUR D070* VOL D080
MCLR(2) MCLR(3) PORTB Weak Pull-up Current
-- -- 25 25
50 300 100 140
A
Output Low Voltage(3) I/O ports -- -- 0.6 V
VOH D090
Output High Voltage(3) I/O ports VDD - 0.7 -- -- V
CIO D101A* EP D130 D131
Capacitive Loading Specs on Output Pins All I/O pins Program Flash Memory Cell Endurance VDD for Read 1k VMIN 10k -- -- -- E/W V Temperature during programming: 10C TA 40C -- -- 50 pF
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Including OSC2 in CLKOUT mode.
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PIC16F/LF720/721
23.4 DC Characteristics: PIC16F/LF720/721-I/E (Continued)
DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. 8.0 2 2 -- -- -- 40 -- Typ -- -- -- -- Max. 9.0 5.5 3.6 5.0 5.0 2.8 -- Units V V V mA mA ms Year Conditions Temperature during programming: 10C TA 40C PIC16F720/21 PIC16LF720/21 Temperature during programming: 10C TA 40C Temperature during programming: 10C TA 40C Temperature during programming: 10C TA 40C Provided no other specifications are violated
Sym.
Characteristic Voltage on MCLR/VPP during Erase/Program
D132
VPEW
VDD for Write or Row Erase
IPPPGM* Current on MCLR/VPP during Erase/Write IDDPGM* Current on VDD during Erase/ Write D133 D134* TPEW TRETD Erase/Write cycle time Characteristic Retention
Legend: TBD = To Be Determined * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Including OSC2 in CLKOUT mode.
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PIC16F/LF720/721
23.5 Thermal Considerations
Standard Operating Conditions (unless otherwise stated) Operating temperature-40C TA +125C Param No. TH01 Sym. JA Characteristic Thermal Resistance Junction to Ambient Typ. 62.4 85.2 108.1 40 28.1 24.2 32.2 2.5 150 -- -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C W W W Conditions 20-pin PDIP package 20-pin SOIC package 20-pin SSOP package 20-pin QFN 4x4mm package 20-pin PDIP package 20-pin SOIC package 20-pin SSOP package 20-pin QFN 4x4mm package
TH02
JC
Thermal Resistance Junction to Case
PD = PINTERNAL + PI/O PINTERNAL = IDD x VDD(1) PI/O = (IOL * VOL) + (IOH * (VDD VOH)) TH07 PDER Derated Power -- W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature
TH03 TH04 TH05 TH06
TJMAX PD PINTERNAL PI/O
Maximum Junction Temperature Power Dissipation Internal Power Dissipation I/O Power Dissipation
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PIC16F/LF720/721
23.6 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 23-2:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output
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PIC16F/LF720/721
23.7 AC Characteristics: PIC16F720/721-I/E
CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 23-3:
OSC1/CLKIN OS02 OS04 OS03 OS04
OSC2/CLKOUT (CLKOUT Mode)
FIGURE 23-4:
5.5
PIC16F720/721 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V)
3.6 2.5 2.3 2.0 1.8 0 4 10 Frequency (MHz) 16
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
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PIC16F/LF720/721
FIGURE 23-5: PIC16LF720/721 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V)
3.6 2.5 2.3 2.0 1.8 0 4 10 Frequency (MHz) 16
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 23-6:
125
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
+ 5% 85 Temperature (C) 3% 60 2% 25
0 -20 + 5% -40 1.8 2.0 2.5 3.0 3.3(2) 3.5 4.0 VDD (V) Note 1: This chart covers both regulator enabled and regulator disabled states. 2: Regulator Nominal voltage. 4.5 5.0 5.5
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PIC16F/LF720/721
TABLE 23-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 OS02 OS03 * Sym. FOSC TOSC TCY Characteristic External CLKIN Frequency(1) External CLKIN Period
(1)
Min. DC 63 250
Typ -- -- TCY
Max. 16 DC
Units MHz ns ns
Conditions EC Oscillator mode EC Oscillator mode TCY = 4/FOSC
Instruction Cycle Time(1)
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to CLKIN pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
TABLE 23-2:
OSCILLATOR PARAMETERS(1)
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS08 Sym HFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2, 3) Freq Tolerance 2% 3% 5% OS08 MFOSC Internal Calibrated MFINTOSC Frequency(2, 3) 2% 3% 5% OS10* TIOSC ST HFINTOSC 16 MHz and 500 kHz Oscillator Wake-up from Sleep Start-up Time * -- Min -- -- -- -- -- -- -- Typ 16.0 16.0 16.0 500 500 500 5 Max Units -- -- -- -- -- -- 8 Conditions
MHz 0C TA +85C, VDD 2.5V MHz +60C TA +85C, VDD 2.5V MHz -40C TA +125C, VDD 2.5V kHz kHz kHz s 0C TA +85C, VDD 2.5V +60C TA +85C, VDD 2.5V -40C TA +125C, VDD 2.5V
These parameters are characterized but not tested. Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at `min' values with an external clock applied to the OSC1 pin. When an external clock input is used, the `max' cycle time limit is `DC' (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: The frequency tolerance of the internal oscillator is 2% from 0-60C and 3% from 60-85C (see Figure 23-6).
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PIC16F/LF720/721
FIGURE 23-7:
Cycle
CLKOUT AND I/O TIMING
Write Q4 Fetch Q1 Read Q2 Execute Q3
FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12
TABLE 23-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. Characteristic FOSC to CLKOUT (1)
(1)
Min. -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 TCY
Typ -- -- -- -- 50 -- -- 15 40 28 15 -- --
Max. 70 72 20 -- 70* -- -- 32 72 55 30 -- --
Units ns ns ns ns ns ns ns ns ns ns ns
Conditions VDD = 3.3-5.0V VDD = 3.3-5.0V
OS11* TOSH2CKL
OS12* TOSH2CKH FOSC to CLKOUT OS13* TCKL2IOV OS14* TIOV2CKH OS15* TOSH2IOV OS16* TOSH2IOI OS17* TIOV2OSH OS18* TIOR OS19* TIOF OS20* TINP OS21* TRBP * Note 1: 2:
CLKOUT to Port out Port input valid before
valid(1) CLKOUT(1)
FOSC (Q1 cycle) to Port out valid FOSC (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to FOSC(Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2) INT pin input high or low time PORTB interrupt-on-change new input level time
VDD = 3.3-5.0V VDD = 3.3-5.0V
VDD = 2.0V VDD = 3.3-5.0V VDD = 2.0V VDD = 3.3-5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Includes OSC2 in CLKOUT mode.
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PIC16F/LF720/721
FIGURE 23-8:
VDD VBOR VBOR + VHYST
BROWN-OUT RESET TIMING AND CHARACTERISTICS
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
TBORREJ 37
Reset (due to BOR)
33(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to `0'. 2ms delay if PWRTE = 0 and VREGEN = 1.
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PIC16F/LF720/721
TABLE 23-4: RESET, WATCHDOG TIME, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30* 31 33* 34* 35 36* 37* * Sym. TMCL TWDT TPWRT TIOZ VBOR VHYST Characteristic MCLR Pulse Width (low) Standard Watchdog Timer Time-out Period (No Prescaler)(2) Power-up Timer Period, PWRTE = 0 I/O high-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis Min. 2 5 10 10 40 -- 1.80 0 1 Typ -- -- 18 18 65 -- 1.9 25 3 Max. Units -- -- 27 33 140 2.0 2.1 50 5 10 s s ms ms ms s V mV s VDD VBOR, -40C to +85C VDD VBOR Conditions VDD = 5V, -40C to +85C VDD = 5V(1) VDD = 3.3V-5V, -40C to +85C VDD = 3.3V-5V(1)
TBORDC Brown-out Reset DC Response Time
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Voltages above 3.6V require that the regulator be enabled. 2: Design Target. If unable to meet this target, the maximum can be increased, but the minimum cannot be changed.
FIGURE 23-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 41
42
T1CKI 45 47 46 49
TMR0 or TMR1
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PIC16F/LF720/721
TABLE 23-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* TT0P T0CKI Period Min. 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 2 TOSC Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Time
Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
T1CKI Synchronous, No Low Time Prescaler Synchronous, with Prescaler Asynchronous
47*
TT1P
T1CKI Input Period
Synchronous
Asynchronous 49* * TCKEZ Delay from External Clock Edge to TMR1 Timer Increment
-- --
-- 7 TOSC
ns -- Timers in Sync mode
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 23-10:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP (Capture mode)
CC01 CC03 Note: Refer to Figure 23-2 for load conditions.
CC02
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PIC16F/LF720/721
TABLE 23-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param Sym. No. CC01* TccL CC02* TccH CC03* TccP * Characteristic CCP Input Low Time CCP Input High Time CCP Input Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5TCY + 20 20 0.5TCY + 20 20 3TCY + 40 N Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 23-7:
PIC16F720/721 A/D CONVERTER (ADC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. AD01 AD02 AD03 AD04 AD07 AD07 AD08 * NR EIL EDL Characteristic Resolution Integral Error Differential Error Min. -- -- -- -- -- VSS -- Typ -- -- -- -- -- -- -- Max. 8 1.0 1 2.0 1.5 VREF 50 Units bit LSb LSb LSb LSb V VDD = 3.0V No missing codes VDD = 3.0V VDD = 3.0V VDD = 3.0V Can go higher if external 0.01F capacitor is present on input pin. Conditions
EOFF Offset Error EGN VAIN ZAIN Gain Error Full-Scale Range Recommended Impedance of Analog Voltage Source
k
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16F/LF720/721
TABLE 23-8: PIC16F720/721 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym. Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Acquisition Time Min. 1.0 4.0 1.0 -- Typ -- -- 2.0 10.5 2 Max. 9.0 16.0 6.0 -- -- Units S S S TAD S Set GO/DONE bit to new data in A/D Result register VDD = 3.0V, EC or INTOSC Clock mode(3) VDD 2.0V(2) VDD 2.0V(2) (ADRC mode) Conditions
AD130* TAD
AD132* TACQ *
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. 2: Setting of 16.0 s TAD not recommended for temperature > 85C. 3: If ADRC mode is selected for use with VDD 2.0V, longer acquisition times will be required (see Section 9.3 "A/D Acquisition Requirements" )
FIGURE 23-11:
PIC16F720/721 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY AD131 AD130
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132
(TOSC/2(1))
7
6 OLD_DATA
5
4
3
2
1
0 NEW_DATA 1 TCY DONE
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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PIC16F/LF720/721
FIGURE 23-12: PIC16F720/721 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 7 6 5 4 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY(1)) 1 TCY AD131 AD130
OLD_DATA
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
FIGURE 23-13:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK US121 DT US120 Note: Refer to Figure 23-2 for load conditions. US122 US121
TABLE 23-9:
USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V * These parameters are characterized but not tested. Min. -- -- -- -- -- -- Max. 80 100 45 50 45 50 Units ns ns ns ns ns ns Conditions
US120* TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid US121* TCKRF US122* TDTRF Clock out rise time and fall time (Master mode) Data-out rise time and fall time
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PIC16F/LF720/721
FIGURE 23-14:
CK US125 DT US126 Note: Refer to Figure 23-2 for load conditions.
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 23-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. Max. Units Conditions
US125* TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126* TCKL2DTL Data-hold after CK (DT hold time) * These parameters are characterized but not tested.
10 15
-- --
ns ns
FIGURE 23-15:
SS
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SP70 SCK (CKP = 0) SP71 SP72 SP78 SCK (CKP = 1) SP79 SP80 SDO MSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In SP74 SP73 Note 1: Refer to Figure 23-2 for load conditions. bit 6 - - - -1 LSb In LSb SP78 SP79
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PIC16F/LF720/721
FIGURE 23-16:
SS SP81 SCK (CKP = 0) SP71 SP73 SCK (CKP = 1) SP80 SP78 bit 6 - - - - - -1 SP75, SP76 SDI MSb In SP74 bit 6 - - - -1 LSb In LSb SP72 SP79
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SDO
MSb
Note 1:
Refer to Figure 23-2 for load conditions.
FIGURE 23-17:
SS
SPI SLAVE MODE TIMING (CKE = 0)
SP70 SCK (CKP = 0) SP71 SP72 SP78 SCK (CKP = 1) SP79 SP80 SDO MSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In SP74 SP73 Note 1: Refer to Figure 23-2 for load conditions. bit 6 - - - -1 LSb In LSb SP77 SP78 SP79 SP83
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PIC16F/LF720/721
FIGURE 23-18: SPI SLAVE MODE TIMING (CKE = 1)
SP82 SP70 SCK (CKP = 0) SP71 SCK (CKP = 1) SP80 SP72 SP83
SS
SDO
MSb
bit 6 - - - - - -1 SP75, SP76
LSb SP77
SDI
MSb In SP74
bit 6 - - - -1
LSb In
Note 1:
Refer to Figure 23-2 for load conditions.
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PIC16F/LF720/721
TABLE 23-11: SPI MODE REQUIREMENTS
Param No. Symbol Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output high-impedance SCK output rise time (Master mode) 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V SP76* TDOF SP77* TSSH2DOZ SP78* TSCR SP79* TSCF SP80* TSCH2DOV, TSCL2DOV SP81* TDOV2SCH, TDOV2SCL SP82* TSSL2DOV SP83* TSCH2SSH, TSCL2SSH Min. TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- Tcy -- 1.5TCY + 40 Typ Max. Units Conditions -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SP70* TSSL2SCH, TSSL2SCL SP71* TSCH SP72* TSCL SP73* TDIV2SCH, TDIV2SCL SP74* TSCH2DIL, TSCL2DIL SP75* TDOR
SCK output fall time (Master mode) SDO data output valid after SCK edge
SDO data output setup to SCK edge SDO data output valid after SS edge SS after SCK edge
* These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 23-19:
I2CTM BUS START/STOP BITS TIMING
SCL SP91 SP90 SDA SP92 SP93
Start Condition Note 1: Refer to Figure 23-2 for load conditions.
Stop Condition
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TABLE 23-12: I2CTM BUS START/STOP BITS REQUIREMENTS
Param No. SP90* SP91* SP92* SP93 * Symbol TSU:STA THD:STA TSU:STO Characteristic Start condition Setup time Start condition Hold time Stop condition Setup time THD:STO Stop condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min. 4700 600 4000 600 4700 600 4000 600 Typ -- -- -- -- -- -- -- -- Max. Units -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated
These parameters are characterized but not tested.
FIGURE 23-20:
I2CTM BUS DATA TIMING
SP103 SP100 SP101 SP102
SCL SP90 SP91 SDA In SP109 SDA Out SP109 SP106 SP107 SP92 SP110
Note 1:
Refer to Figure 23-2 for load conditions.
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TABLE 23-13: I2CTM BUS DATA REQUIREMENTS
Param. No. 100* Symbol THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 101* TLOW Clock low time 100 kHz mode 400 kHz mode SSP Module 102* TR SDA and SCL rise time SDA and SCL fall time Start condition setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min. 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1CB -- 20 + 0.1CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max. -- -- -- -- -- -- 1000 300 250 250 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10-400 pF Only relevant for Repeated Start condition After this period the first clock pulse is generated CB is specified to be from 10-400 pF s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
103*
TF
90* 91* 106* 107* 92* 109* 110*
TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
Start condition hold 100 kHz mode time 400 kHz mode Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
CB * Note 1: 2:
Bus capacitive loading
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
2010 Microchip Technology Inc.
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PIC16F/LF720/721
NOTES:
DS41430A-page 212
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PIC16F/LF720/721
24.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
PIC16F720/721 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE FIGURE 24-1:
210 200 190 180 170 IDD (A) 160 150 1.8V 140 130 120 110 62.5 kHz 125 kHz FOSC 250 kHz 500 kHz 3.6V 2.5V Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
5V
FIGURE 24-2:
170
PIC16LF720/721 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE
160
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
3.6V
150
3V 2.5V
IDD (A)
140
130 1.8V 120
110
100 62.5 KHz 125 KHz FOSC 250 KHz 500 KHz
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PIC16F/LF720/721
FIGURE 24-3:
2,000 1,800 1,600 1,400 1,200 IDD (A) 1,000 800 600 400 200 0 2 MHz 4 MHz FOSC 8 MHz 16 MHz 1.8V 2.5V Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) 5V 3.6V
PIC16F720/721 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE
FIGURE 24-4:
2,250
PIC16LF720/721 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE
2,000
s Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
3.6V
1,750 3V 1,500 2.5V IDD (A) 1,250 1.8V
1,000
750
500
250
0 2 MHz 4 MHz FOSC 8 MHz 16 MHz
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PIC16F/LF720/721
FIGURE 24-5:
160 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
150
5V 3.6V
140
IDD (A)
130 2.5V 120 1.8V 110
100
90
80 62.5 kHz 125 kHz FOSC 250 kHz 500 kHz
FIGURE 24-6:
140
PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
130
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
3.6V
3V 120 2.5V 110 IDD (A)
100
1.8V
90
80
70 62.5 kHz 125 kHz FOSC 250 kHz 500 kHz
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PIC16F/LF720/721
FIGURE 24-7:
2,000 1,800 1,600 1,400 2.5V 1,200 IDD (A) 1,000 1.8V 800 600 400 200 0 2 MHz 4 MHz FOSC 8 MHz 16 MHz Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
5V 3.6V
FIGURE 24-8:
2,000 1,800 1,600 1,400
PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) 3.6V
3V
2.5V IDD (A) 1,200 1,000 1.8V 800 600 400 200 0 2 MHz 4 MHz VDD (V) 8 MHz 16 MHz
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PIC16F/LF720/721
FIGURE 24-9:
7 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
PIC16LF720/721 MAXIMUM BASE IPD vs. VDD
6
125C
5
IPD (A)
4
3
85C
2
1
0 1.8V 2V 2.5V VDD (V) 3V 3.6V
FIGURE 24-10:
250
PIC16LF720/721 TYPICAL BASE IPD vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) 200 25C
150 IPD (nA) 100 50
0 1.8V 2V 2.5V VDD (V) 3V 3.6V
FIGURE 24-11:
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FIGURE 24-12:
18 16 14 12 10 IPD (A) 8 6 4 2 0 1.8V 2V 3V VDD (V) 3.6V 5V 5.5V Typ. 25C Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. 85C
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
FIGURE 24-13:
3.5
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
3.0
Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C)
2.5
VIH Max. -40C
2.0 VIN (V)
1.5 VIH Min. 125C 1.0
0.5
0.0 1.8 3.6 VDD (V) 5.5
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PIC16F/LF720/721
FIGURE 24-14:
3.0 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) VIL Max. -40C
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
2.5
2.0
VIN (V)
1.5
1.0 VIL Min. 125C
0.5
0.0 1.8 3.6 VDD (V) 5.5
FIGURE 24-15:
5.6
VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V
5.5
Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C)
5.4
VOH (V)
5.3
Max. -40
5.2
Typ. 25
5.1
Min. 125
5 -0.2 -1.0 -1.8 -2.6 IOH (mA) -3.4 -4.2 -5.0
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PIC16F/LF720/721
FIGURE 24-16:
3.8 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C)
VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V
3.6
3.4 Max. -40 VOH (V)
3.2 Typ. 25
3
Min. 125 2.8
2.6 -0.2 -1.0 -1.8 -2.6 IOH (mA) -3.4 -4.2 -5.0
FIGURE 24-17:
2 1.8 1.6
VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V
Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C)
Max. -40 1.4 1.2 VOH (V) 1 0.8 0.6 Min. 125 0.4 0.2 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 IOH (mA) Typ. 25
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FIGURE 24-18:
0.5 0.45 0.4 0.35 Max. 125 0.3 0.25 0.2 Typ. 25 0.15 0.1 Min. -40 0.05 0 5.0 6.0 7.0 IOL (mA) 8.0 9.0 10.0 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C)
VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V
FIGURE 24-19:
0.9
VOL (V)
VOL vs. IOL OVER TEMPERATURE, VDD = 3.6
0.8
Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C)
0.7
0.6 Max. 125 0.5 VOL (V)
0.4 Typ. 25 0.3
0.2 Min. -40 0.1
0 4.0 5.0 6.0 7.0 IOL (mA) 8.0 9.0 10.0
2010 Microchip Technology Inc.
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PIC16F/LF720/721
FIGURE 24-20:
1.2 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C)
VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V
1
0.8 Max. 125 VOL (V) 0.6
0.4
0.2 Min. -40
0 0.0 0.4 0.8 1.2 1.6 IOL (mA) 2.0 2.4 2.8
FIGURE 24-21:
105
PIC16F720/721 PWRT PERIOD
95
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. -40C
85 TIME (ms)
75 Typ. 25C
65 Min. 125C 55
45 1.8V 2V 2.2V 2.4V 3V VDD 3.6V 4V 4.5V 5V 5.5V
DS41430A-page 222
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PIC16F/LF720/721
FIGURE 24-22:
24.00 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. -40C 20.00
PIC16F720/721 WDT TIME-OUT PERIOD
22.00
18.00 TIME (ms) Typ. 25C 16.00
14.00 Min. 125C 12.00
10.00 1.8V 2V 2.2V 2.4V 3V VDD 3.6V 4V 4.5V 5V
FIGURE 24-23:
6.0
PIC16F720/721 A/D INTERNAL RC OSCILLATOR PERIOD
5.0
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
4.0 Period (s)
3.0
Max.
2.0
Min.
1.0
0.0 1.8V 3.6V VDD(V) 5.5V
2010 Microchip Technology Inc.
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PIC16F/LF720/721
FIGURE 24-24: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V
1.5
1
Percent Change (%)
0.5
0
-0.5
-1
-1.5 1.8 2.5 3 Voltage 3.6 4.2 5.5
FIGURE 24-25:
TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25C
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -40 0 45 Temperature (C) 85 125
Percent Change (%)
DS41430A-page 224
2010 Microchip Technology Inc.
PIC16F/LF720/721
25.0
25.1
PACKAGING INFORMATION
Package Marking Information
20-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F721 -I/P e3 0810017
20-Lead QFN 4x4
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F721 -I/ML e3 0810017
20-Lead SOIC
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F720 -I/SO e3 0810017
20-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example PIC16F720 -I/SS e3 0810017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2010 Microchip Technology Inc.
DS41430A-page 225
PIC16F/LF720/721
25.2 Package Details
The following sections give the technical details of the packages.
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PIC16F/LF720/721
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PIC16F/LF720/721
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DS41430A-page 228
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PIC16F/LF720/721
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2010 Microchip Technology Inc.
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PIC16F/LF720/721
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS41430A-page 230
2010 Microchip Technology Inc.
PIC16F/LF720/721
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2010 Microchip Technology Inc.
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PIC16F/LF720/721
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS41430A-page 232
2010 Microchip Technology Inc.
PIC16F/LF720/721
APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: MIGRATING FROM OTHER PIC(R) DEVICES
Revision A (September 2010)
Original release of this document.
This shows a comparison of features in the migration from another PIC(R) device, the PIC16F722, to the PIC16F720 device.
B.1
PIC16F722 to PIC16F720
FEATURE COMPARISON
PIC16F722 20 MHz 2K 128 8-bit 2/1 8 Y RB<7:4> RB<7:0> 0 Y N N 500 kHz 16 MHz N PIC16F720 20 MHz 2K 128 8-bit 2/1 8 Y RB<7:4> RB<7:4> 0 Y N N 500 kHz 16 MHz N Feature
TABLE B-1:
Max. Operating Speed Max. Program Memory (Words) Max. SRAM (Bytes) A/D Resolution Timers (8/16-bit) Oscillator Modes Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator AUSART Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching
Note:
This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
Note:
The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the oscillator mode may be required.
2010 Microchip Technology Inc.
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PIC16F/LF720/721
NOTES:
DS41430A-page 234
2010 Microchip Technology Inc.
PIC16F/LF720/721
INDEX
A
A/D Specifications.................................................... 203, 204 Absolute Maximum Ratings .............................................. 187 AC Characteristics Industrial and Extended ............................................ 196 Load Conditions ........................................................ 195 ADC .................................................................................... 77 Acquisition Requirements ........................................... 83 Associated registers.................................................... 85 Block Diagram............................................................. 77 Calculating Acquisition Time....................................... 83 Channel Selection....................................................... 78 Configuration............................................................... 78 Configuring Interrupt ................................................... 80 Conversion Clock........................................................ 78 Conversion Procedure ................................................ 80 Internal Sampling Switch (RSS) Impedance................ 83 Interrupts..................................................................... 79 Operation .................................................................... 79 Operation During Sleep .............................................. 80 Port Configuration ....................................................... 78 Source Impedance...................................................... 83 Special Event Trigger.................................................. 80 ADCON0 Register......................................................... 17, 81 ADCON1 Register......................................................... 18, 82 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)............................... 119 ADRES Register ................................................................. 82 ADRESH Register............................................................... 17 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................... 49 ANSELB Register ............................................................... 58 Assembler MPASM Assembler................................................... 184 AUSART ........................................................................... 119 Associated Registers Baud Rate Generator........................................ 129 Asynchronous Mode ................................................. 121 Associated Registers Receive..................................................... 126 Transmit.................................................... 123 Baud Rate Generator (BRG) ............................ 129 Receiver............................................................ 123 Setting up 9-bit Mode with Address Detect....... 125 Transmitter........................................................ 121 Baud Rate Generator (BRG) Baud Rate Error, Calculating ............................ 129 Baud Rates, Asynchronous Modes .................. 130 Formulas ........................................................... 129 High Baud Rate Select (BRGH Bit) .................. 129 Synchronous Master Mode ............................... 132, 136 Associated Registers Receive..................................................... 135 Transmit.................................................... 133 Reception.......................................................... 134 Transmission .................................................... 132 Synchronous Slave Mode Associated Registers Receive..................................................... 137 Transmit.................................................... 136 Reception.......................................................... 137 Transmission .................................................... 136
B
BF bit ........................................................................ 147, 159 Block Diagrams (CCP) Capture Mode Operation ............................... 110 ADC ............................................................................ 77 ADC Transfer Function............................................... 84 Analog Input Model..................................................... 84 AUSART Receive ..................................................... 120 AUSART Transmit .................................................... 119 CCP PWM ................................................................ 114 Clock Source .............................................................. 67 Compare................................................................... 112 Interrupt Logic............................................................. 37 MCLR Circuit .............................................................. 29 On-Chip Reset Circuit................................................. 27 RA0 Pins..................................................................... 51 RA1 Pins..................................................................... 52 RA2 Pin ...................................................................... 53 RA4 Pin ...................................................................... 54 RA5 Pin ................................................................ 54, 55 RB0 Pin ...................................................................... 59 RB3 Pin ...................................................................... 60 RC0 Pin ...................................................................... 64 RC5 Pin ...................................................................... 65 RC6 Pin ...................................................................... 65 RC7 Pin ...................................................................... 65 SPI Mode.................................................................. 140 SSP (I2C Mode)........................................................ 149 Timer1 ................................................ 95, 101, 102, 103 Timer2 ...................................................................... 107 TMR0/WDT Prescaler ................................................ 91 Brown-out Reset (BOR)...................................................... 31 Specifications ........................................................... 201 Timing and Characteristics ....................................... 200
C
C Compilers MPLAB C18.............................................................. 184 Capture Module. See Capture/Compare/PWM (CCP) Capture/Compare/PWM (CCP) ........................................ 109 Associated registers w/ Capture............................... 111 Associated registers w/ Compare............................. 113 Associated registers w/ PWM................................... 117 Capture Mode........................................................... 110 CCPx Pin Configuration............................................ 110 Compare Mode......................................................... 112 CCPx Pin Configuration.................................... 112 Software Interrupt Mode ........................... 110, 112 Special Event Trigger ....................................... 112 Timer1 Mode Selection............................. 110, 112 Prescaler .................................................................. 110 PWM Mode............................................................... 114 Duty Cycle ........................................................ 115 Effects of Reset ................................................ 116 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 116 Example PWM Frequencies and Resolutions, 8 MHz .................................. 116 Operation in Sleep Mode.................................. 116 Setup for Operation .......................................... 116 System Clock Frequency Changes .................. 116 PWM Period ............................................................. 115 Setup for PWM Operation ........................................ 116
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Timer Resources....................................................... 109 CCP. See Capture/Compare/PWM (CCP) CCP1CON Register ............................................................ 17 CCPR1H Register ............................................................... 17 CCPR1L Register................................................................ 17 CCPxCON Register .......................................................... 109 CKE bit ...................................................................... 147, 159 CKP bit ...................................................................... 146, 158 Clock Sources External Modes ........................................................... 71 EC ....................................................................... 71 Code Examples A/D Conversion ........................................................... 80 Call of a Subroutine in Page 1 from Page 0................ 24 Changing Between Capture Prescalers .................... 110 Indirect Addressing ..................................................... 25 Initializing PORTA ....................................................... 47 Initializing PORTB ....................................................... 56 Initializing PORTC....................................................... 62 Loading the SSPBUF (SSPSR) Register .................. 142 Saving W, STATUS and PCLATH Registers in RAM . 39 Writing to Flash Program Memory ............................ 165 Comparators C2OUT as T1 Gate ..................................................... 97 Compare Module. See Capture/Compare/PWM (CCP) Customer Change Notification Service ............................. 241 Customer Notification Service........................................... 241 Customer Support ............................................................. 241 Instruction Format............................................................. 173 Instruction Set................................................................... 173 ADDLW..................................................................... 175 ADDWF..................................................................... 175 ANDLW..................................................................... 175 ANDWF..................................................................... 175 MOVF ....................................................................... 178 BCF .......................................................................... 175 BSF........................................................................... 175 BTFSC ...................................................................... 175 BTFSS ...................................................................... 176 CALL......................................................................... 176 CLRF ........................................................................ 176 CLRW ....................................................................... 176 CLRWDT .................................................................. 176 COMF ....................................................................... 176 DECF ........................................................................ 176 DECFSZ ................................................................... 177 GOTO ....................................................................... 177 INCF ......................................................................... 177 INCFSZ..................................................................... 177 IORLW ...................................................................... 177 IORWF...................................................................... 177 MOVLW .................................................................... 178 MOVWF .................................................................... 178 NOP .......................................................................... 178 RETFIE ..................................................................... 179 RETLW ..................................................................... 179 RETURN................................................................... 179 RLF ........................................................................... 180 RRF .......................................................................... 180 SLEEP ...................................................................... 180 SUBLW ..................................................................... 180 SUBWF..................................................................... 181 SWAPF ..................................................................... 181 XORLW .................................................................... 181 XORWF .................................................................... 181 Summary Table ........................................................ 174 INTCON Register................................................................ 40 Internal Oscillator Block INTOSC Specifications ........................................... 198, 199 Internal Sampling Switch (RSS) Impedance........................ 83 Internet Address ............................................................... 241 Interrupts............................................................................. 37 ADC ............................................................................ 80 Associated registers w/ Interrupts............................... 43 Interrupt-on-Change ................................................... 56 TMR1 ........................................................................ 100 INTOSC Specifications ............................................. 198, 199 IOCB Register..................................................................... 58
D
D/A bit ............................................................................... 159 Data Memory....................................................................... 14 Data/Address bit (D/A) ...................................................... 159 DC and AC Characteristics ............................................... 213 DC Characteristics Extended and Industrial ............................................ 192 Industrial and Extended ............................................ 188 Development Support ....................................................... 183 Device Configuration........................................................... 73 Code Protection .......................................................... 76 Configuration Word ..................................................... 73 User ID ........................................................................ 76 Device Overview ................................................................... 9
E
EECON1 Register ............................................................... 20 Effects of Reset PWM mode ............................................................... 116 Electrical Specifications .................................................... 187 Errata .................................................................................... 7
F
Firmware Instructions........................................................ 173 Fixed Voltage Reference. See FVR FSR Register................................................................. 17, 18 FVR ..................................................................................... 87 FVRCON Register............................................................... 87
L
Load Conditions................................................................ 195
M
M....................................................................................... 202 MCLR.................................................................................. 29 Internal........................................................................ 29 Memory Organization ......................................................... 13 Data ............................................................................ 14 Program ...................................................................... 13 Microchip Internet Web Site.............................................. 241 Migrating from other PIC Microcontroller Devices ............ 233 MPLAB ASM30 Assembler, Linker, Librarian ................... 184 MPLAB Integrated Development Environment Software.. 183
G
General Purpose Register File............................................ 14
I
I2C Mode Associated Registers ................................................ 160 INDF Register ............................................................... 17, 18 Indirect Addressing, INDF and FSR Registers.................... 25
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MPLAB PM3 Device Programmer .................................... 186 MPLAB REAL ICE In-Circuit Emulator System................. 185 MPLINK Object Linker/MPLIB Object Librarian ................ 184 PORTC Register......................................................... 17 RC0 ............................................................................ 64 RC2 ............................................................................ 64 RC3 ............................................................................ 64 RC4 ............................................................................ 64 RC5 ............................................................................ 64 RC6 ............................................................................ 64 RC7 ............................................................................ 64 Specifications ........................................................... 199 PORTC Register................................................................. 62 Power-Down Mode (Sleep)............................................... 169 Associated Registers................................................ 170 Power-on Reset .................................................................. 29 Power-up Timer (PWRT) .................................................... 29 Specifications ........................................................... 201 PR2 Register .............................................................. 18, 148 Precision Internal Oscillator Parameters .......................... 199 Prescaler Shared WDT/Timer0................................................... 92 Product Identification System ........................................... 243 Program Memory ................................................................ 13 Map and Stack (PIC16F720/LF720) ........................... 13 Map and Stack (PIC16F721/LF721) ........................... 13 Paging ........................................................................ 24 Program Memory Read (PMR) ......................................... 161 Associated Registers................................................ 168 Programming, Device Instructions.................................... 173
O
OPCODE Field Descriptions ............................................. 173 OPTION Register ................................................................ 22 OPTION_REG Register ...................................................... 93 OSCCON Register .............................................................. 69 Oscillator Associated registers............................................ 71, 106 Oscillator Module EC ............................................................................... 67 Oscillator Tuning ......................................................... 70 Oscillator Parameters ....................................................... 198 Oscillator Specifications .................................................... 198 OSCTUNE Register ............................................................ 70
P
P (Stop) bit ........................................................................ 159 Packaging ......................................................................... 225 Marking ..................................................................... 225 PDIP Details.............................................................. 226 Paging, Program Memory ................................................... 24 PCL and PCLATH ............................................................... 24 Computed GOTO........................................................ 24 Stack ........................................................................... 24 PCL Register................................................................. 17, 18 PCLATH Register ......................................................... 17, 18 PCON Register ....................................................... 18, 23, 32 PIE1 Register ................................................................ 18, 41 PIR1 Register................................................................ 17, 42 PMADRH Register ............................................................ 167 PMADRL Register............................................................. 168 PMCON1 Register .................................................... 166, 168 PMDATH Register ............................................................ 167 PMDATL Register ............................................................. 167 PORTA................................................................................ 47 ANSELA Register ....................................................... 49 Associated Registers .................................................. 55 Pin Descriptions and Diagrams................................... 50 PORTA Register ......................................................... 17 RA0 ............................................................................. 50 RA1 ............................................................................. 50 RA2 ............................................................................. 50 RA3 ............................................................................. 50 RA4 ............................................................................. 50 RA5 ............................................................................. 50 RA6 ............................................................................. 50 Specifications............................................................ 199 PORTA Register ................................................................. 48 PORTB Additional Pin Functions ANSELB Register ............................................... 56 Weak Pull-up ...................................................... 56 Associated Registers .................................................. 61 Interrupt-on-Change.................................................... 56 Pin Descriptions and Diagrams................................... 59 PORTB Register ......................................................... 17 RB0 ............................................................................. 59 RB4 ............................................................................. 59 RB5 ............................................................................. 59 RB6 ............................................................................. 59 RB7 ............................................................................. 59 PORTB Register ................................................................. 57 PORTC
R
R/W bit .............................................................................. 159 RCREG............................................................................. 125 RCSTA Register ................................................... 17, 61, 128 Reader Response............................................................. 242 Read-Modify-Write Operations ......................................... 173 Receive Overflow Indicator bit (SSPOV) .................. 146, 158 Registers ADCON0 (ADC Control 0) .......................................... 81 ADCON1 (ADC Control 1) .......................................... 82 ADRES (ADC Result) ................................................. 82 ANSELA (PORTA Analog Select) .............................. 49 ANSELB (PORTB Analog Select) .............................. 58 CCPxCON (CCP Operation) .................................... 109 FVRCON (Fixed Voltage Reference Register) ........... 87 INTCON (Interrupt Control) ........................................ 40 IOCB (Interrupt-on-Change PORTB).......................... 58 OPTION_REG (OPTION)........................................... 22 OPTION_REG (Option) .............................................. 93 OSCCON (Oscillator Control)..................................... 69 OSCTUNE (Oscillator Tuning).................................... 70 PCON (Power Control Register)................................. 23 PCON (Power Control) ............................................... 32 PIE1 (Peripheral Interrupt Enable 1) .......................... 41 PIR1 (Peripheral Interrupt Register 1) ........................ 42 PMADRH (Program Memory Address High) ............ 167 PMADRL (Program Memory Address Low).............. 168 PMCON1 (Program Memory Control 1) ................... 166 PMDATH (Program Memory Data High) .................. 167 PMDATL (Program Memory Data Low).................... 167 PORTA ....................................................................... 48 PORTB ....................................................................... 57 PORTC ....................................................................... 62 RCSTA (Receive Status and Control) ...................... 128 Reset Values .............................................................. 34 Reset Values (Special Registers)............................... 36 SSPCON (Sync Serial Port Control) Register .. 146, 158 SSPSTAT (Sync Serial Port Status) Register .. 147, 159
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STATUS ...................................................................... 21 T1CON (Timer1 Control)........................................... 104 T1GCON (Timer1 Gate Control) ............................... 105 T2CON ...................................................................... 108 TRISA (Tri-State PORTA) ........................................... 48 TRISB (Tri-State PORTB) ........................................... 57 TRISC (Tri-State PORTC) .......................................... 63 TXSTA (Transmit Status and Control) ...................... 127 WPUB (Weak Pull-up PORTB) ................................... 57 Reset................................................................................... 27 Resets Associated Registers .................................................. 36 Revision History ................................................................ 233 Timer1................................................................................. 95 Associated registers ................................................. 106 Asynchronous Counter Mode ..................................... 97 Reading and Writing ........................................... 97 Interrupt .................................................................... 100 Modes of Operation .................................................... 96 Module On/Off (TMR1ON Bit)................................... 105 Operation During Sleep ............................................ 100 Prescaler .................................................................... 97 Specifications ........................................................... 202 Timer1 Gate Selecting Source ................................................ 97 TMR1H Register ......................................................... 95 TMR1L Register.......................................................... 95 Timer2 Associated registers ................................................. 108 Timers Timer1 T1CON ............................................................. 104 T1GCON........................................................... 105 Timer2 T2CON ............................................................. 108 Timing Diagrams A/D Conversion......................................................... 204 A/D Conversion (Sleep Mode) .................................. 205 Asynchronous Reception.......................................... 126 Asynchronous Transmission..................................... 122 Asynchronous Transmission (Back-to-Back)............ 122 Brown-out Reset (BOR)............................................ 200 Brown-out Reset Situations ........................................ 31 CLKOUT and I/O ...................................................... 199 Clock Synchronization .............................................. 157 Clock Timing ............................................................. 196 I2C Bus Data............................................................. 210 I2C Bus Start/Stop Bits ............................................. 209 I2C Reception (7-bit Address)................................... 152 I2C Slave Mode with SEN = 0 (Reception, 10-bit Address) ................................................. 153 I2C Transmission (7-bit Address).............................. 154 INT Pin Interrupt ......................................................... 38 Slave Select Synchronization ................................... 145 SPI Master Mode ...................................................... 142 SPI Master Mode (CKE = 1, SMP = 1) ..................... 207 SPI Mode (Slave Mode with CKE = 0)...................... 144 SPI Mode (Slave Mode with CKE = 1)...................... 144 SPI Slave Mode (CKE = 0) ....................................... 207 SPI Slave Mode (CKE = 1) ....................................... 208 Synchronous Reception (Master Mode, SREN) ....... 135 Synchronous Transmission ...................................... 133 Synchronous Transmission (Through TXEN) ........... 133 Time-out Sequence Case 1 ................................................................ 32 Case 2 ................................................................ 33 Case 3 ................................................................ 33 Timer0 and Timer1 External Clock ........................... 201 Timer1 Incrementing Edge ....................................... 100 USART Synchronous Receive (Master/Slave) ......... 206 USART Synchronous Transmission (Master/Slave). 205 Wake-up from Interrupt............................................. 170 Timing Parameter Symbology .......................................... 195 Timing Requirements I2C Bus Data............................................................. 211 I2C Bus Start/Stop Bits ............................................. 210 SPI Mode .................................................................. 209 TMR0 Register.................................................................... 17
S
S (Start) bit ........................................................................ 159 SMP bit...................................................................... 147, 159 Software Simulator (MPLAB SIM)..................................... 185 SPBRG.............................................................................. 129 SPBRG Register ................................................................. 18 Special Event Trigger.......................................................... 80 Special Function Registers ................................................. 14 SPI Mode .......................................................................... 145 Associated Registers ................................................ 148 Typical Master/Slave Connection ............................. 139 SSP ................................................................................... 139 I2C Mode ................................................................... 149 Acknowledge..................................................... 150 Addressing ........................................................ 151 Clock Stretching................................................ 156 Clock Synchronization ...................................... 157 Firmware Master Mode ..................................... 156 Hardware Setup ................................................ 149 Multi-Master Mode ............................................ 156 Reception.......................................................... 152 Sleep Operation ................................................ 157 Start/Stop Conditions ........................................ 150 Transmission..................................................... 154 Master Mode ............................................................. 141 SPI Mode .................................................................. 139 Slave Mode ....................................................... 143 Typical SPI Master/Slave Connection....................... 139 SSPADD Register ............................................................... 18 SSPBUF Register ............................................................... 17 SSPCON Register............................................... 17, 146, 158 SSPEN bit ................................................................. 146, 158 SSPM bits ................................................................. 146, 158 SSPOV bit ................................................................. 146, 158 SSPSTAT Register ............................................. 18, 147, 159 STATUS Register................................................................ 21 Synchronous Serial Port Enable bit (SSPEN)........... 146, 158 Synchronous Serial Port Mode Select bits (SSPM) .. 146, 158
T
T1CON Register.......................................................... 17, 104 TMR1ON Bit.............................................................. 105 T1GCON Register............................................................. 105 T2CON Register.................................................. 17, 108, 148 Temperature Indicator Module ............................................ 89 Thermal Considerations .................................................... 194 Time-out Sequence............................................................. 32 Timer0 ................................................................................. 91 Associated Registers .................................................. 93 Interrupt....................................................................... 93 Operation .............................................................. 91, 96 Specifications ............................................................ 202
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TMR1H Register ................................................................. 17 TMR1L Register .................................................................. 17 TMR2 Register .................................................................... 17 TMRO Register ................................................................... 19 TRISA ................................................................................. 47 TRISA Register ............................................................. 18, 48 TRISB ................................................................................. 56 TRISB Register ............................................................. 18, 57 TRISC ................................................................................. 62 TRISC Register ............................................................. 18, 63 TXREG.............................................................................. 121 TXREG Register ........................................................... 17, 61 TXSTA Register .......................................................... 18, 127 BRGH Bit .................................................................. 129
U
UA ..................................................................................... 159 Update Address bit, UA .................................................... 159 USART Synchronous Master Mode Requirements, Synchronous Receive .............. 206 Requirements, Synchronous Transmission ...... 205 Timing Diagram, Synchronous Receive ........... 206 Timing Diagram, Synchronous Transmission ... 205
W
Wake-up Using Interrupts ................................................. 170 Watchdog Timer (WDT) ...................................................... 29 Clock Source............................................................... 29 Modes ......................................................................... 30 Period.......................................................................... 29 Specifications............................................................ 201 WCOL bit .................................................................. 146, 158 WPUB Register ................................................................... 57 Write Collision Detect bit (WCOL)............................. 146, 158 WWW Address.................................................................. 241 WWW, On-Line Support ....................................................... 7
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NOTES:
DS41430A-page 240
2010 Microchip Technology Inc.
PIC16F/LF720/721
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
2010 Microchip Technology Inc.
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PIC16F/LF720/721
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41430A FAX: (______) _________ - _________
Device: PIC16F/LF720/721 Questions: 1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41430A-page 242
2010 Microchip Technology Inc.
PIC16F/LF720/721
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC16F720(1), PIC16LF720(1), PIC16F721(1), PIC16LF721(1) PIC16F720-E/P 301 = Extended Temp., PDIP package, QTP pattern #301 PIC16F721-I/SO = Industrial Temp., SOIC package
Temperature Range:
I E MV
= = =
-40C to +85C -40C to +125C Micro Lead Frame (UQFN)
Package:
ML P SO SS
= = = =
Micro Lead Frame (QFN) Plastic DIP SOIC SSOP Note 1: T = In tape and reel.
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
2010 Microchip Technology Inc.
DS41430A-page 243
Worldwide Sales and Service
AMERICAS
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ASIA/PACIFIC
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ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
08/04/10
DS41430A-page 244
2010 Microchip Technology Inc.

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