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SSTUG32868
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
Rev. 01 -- 23 April 2007 Product data sheet
1. General description
The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs. The SSTUG32868 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). It further offers added features over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUG32868 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. Finally, the SSTUG32868 is optimized for the fastest propagation delay in the SSTU family of registers. The SSTUG32868 is packaged in a 176-ball, 8 x 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 6 mm x 15 mm of board space) allows for adequate signal routing and escape using conventional card technology.
2. Features
I 28-bit data register supporting DDR2 I Fully compliant to JEDEC standard for SSTUB32868 I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 x SSTUA32864 or 2 x SSTUA32866) I Parity checking function across 22 input data bits I Parity out signal I Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed I Meets or exceeds SSTUB32868 JEDEC standard speed performance I Supports up to 450 MHz clock frequency of operation I Permanently configured for high output drive I Optimized pinout for high-density DDR2 module design I Chip-selects minimize power consumption by gating data outputs from changing state
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
I I I I
Two additional chip select inputs allow optional flexible enabling and disabling Supports Stub Series Terminated Logic SSTL_18 data inputs Differential clock (CK and CK) inputs Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) switching levels on the control and RESET inputs I Single 1.8 V supply operation (1.7 V to 2.0 V) I Available in 176-ball 6 mm x 15 mm, 0.65 mm ball pitch TFBGA package
3. Applications
I 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs I DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality
4. Ordering information
Table 1. Ordering information Solder process Package Name SSTUG32868ET/G SSTUG32868ET/S Description Version Type number
Pb-free (SnAgCu solder ball TFBGA176 plastic thin fine-pitch ball grid array package; SOT932-1 compound) 176 balls; body 6 x 15 x 0.7 mm Pb-free (SnAgCu solder ball TFBGA176 plastic thin fine-pitch ball grid array package; SOT932-1 compound) 176 balls; body 6 x 15 x 0.7 mm
4.1 Ordering options
Table 2. Ordering options Temperature range Tamb = 0 C to +70 C Tamb = 0 C to +85 C Type number SSTUG32868ET/G SSTUG32868ET/S
SSTUG32868_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 23 April 2007
2 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
5. Functional diagram
RESET
SSTUG32868
CK CK VREF DCKE0, DCKE1
2 2 2
D CLK R Q
2
QCKE0A, QCKE1A QCKE0B, QCKE1B
2
DODT0, DODT1
2
2
D CLK R Q
2
2
QODT0A, QODT1A QODT0B, QODT1B
2
DCS0
D CLK R Q
QCS0A QCS0B
CSGEN
DCS1
D CLK R Q
QCS1A QCS1B
DCS2
DCS3
one of 22 channels D1 D CE CLK R Q Q1B Q1A
to 21 other channels(1)
002aac915
(1) Register A configuration (C = 0): D2 to D5, D7, D9 to D12, D17 to D28 Register B configuration (C = 1): D2 to D12, D17 to D20, D22, D24 to D28
Fig 1. Logic diagram of SSTUG32868 (positive logic)
SSTUG32868_1
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Product data sheet
Rev. 01 -- 23 April 2007
3 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
RESET CK CK
Dn(1) VREF
22
22
D CLK R CE
22
22
QnA(2) QnB(3)
Q
22 22
PAR_IN
D CLK R CE Q
PARITY GENERATOR AND ERROR CHECK
QERR
DCS0
D CLK R Q
QCS0A QCS0B
CSGEN
DCS1
D CLK R Q
QCS1A QCS1B
DCS2
DCS3
002aac497
(1) Register A configuration (C = 0): D1 to D5, D7, D9 to D12, D17 to D28 Register B configuration (C = 1): D1 to D12, D17 to D20, D22, D24 to D28 (2) Register A configuration (C = 0): Q1A to Q5A, Q7A, Q9A to Q12A, Q17A to Q28A Register B configuration (C = 1): Q1A to Q12A, Q17A to Q20A, Q22A, Q24A to Q28A (3) Register A configuration (C = 0): Q1B to Q5B, Q7B, Q9B to Q12B, Q17B to Q28B Register B configuration (C = 1): Q1B to Q12B, Q17B to Q20B, Q22B, Q24B to Q28B
Fig 2. Parity logic diagram (positive logic)
SSTUG32868_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 23 April 2007
4 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUG32868ET/G
ball A1 SSTUG32868ET/S index area 2 4 6 8 1357 B D F H K M P T V A C E G J L N R U W
Y AA AB
002aac916
Transparent top view
Fig 3. Pin configuration for TFBGA176
SSTUG32868_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 23 April 2007
5 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
1 A B C D E F G H J K L M N P R T U V W Y AA AB D2 D4 D6 (DCKE1) D8 (DCKE0) D9 D10 D11 D12 DCS1 (D13) DCS0 (D14) CK CK D15 (DODT0) D16 (DODT1) D17 D18 D19 D20 D21 D23 D25 D27
2 D1 D3 D5 D7 Q6A (QCKE1A) Q8A (QCKE0A) Q10A Q12A QCS1A (Q13A) QCS0A (Q14A) CSGEN RESET Q15A (QODT0A) Q16A (QODT1A) Q17A Q19A Q21A Q23A D22 D24 D26 D28
3 C VDD GND VDD GND VDD GND VDD GND DCS2 PAR_IN QERR GND DCS3 GND VDD GND VDD GND VDD GND SELDR
4 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD
5 VREF VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VREF
6 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD
7 Q1A Q2A Q3A Q4A Q5A Q7A Q9A Q11A Q10B Q12B Q14B (QCS0B) Q15B (QODT0B) Q17B Q19B Q18A Q20A Q22A Q24A Q25A Q26A Q27A Q28A
8 Q1B Q2B Q3B Q4B Q5B Q6B (QCKE1B) Q7B Q8B (QCKE0B) Q9B Q11B Q13B (QCS1B) Q16B (QODT1B) Q18B Q20B Q21B Q22B Q23B Q24B Q25B Q26B Q27B Q28B
002aac917
176-ball, 8 x 22 grid; top view.
Fig 4. Ball mapping (1 : 2 Register A; C = 0)
SSTUG32868_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 23 April 2007
6 of 29
NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
1 A B C D E F G H J K L M N P R T U V W Y AA AB D2 D4 D6 D8 D9 D10 D11 D12 D13 (DODT1) D14 (DODT0) CK CK D15 (DCS0) D16 (DCS1) D17 D18 D19 D20 D21 (DCKE0) D23 (DCKE1) D25 D27
2 D1 D3 D5 D7 Q6A Q8A Q10A Q12A Q13A (QODT1A) Q14A (QODT0A) CSGEN RESET Q15A (QCS0A) Q16A (QCS1A) Q17A Q19A Q21A (QCKE0A) Q23A (QCKE1A) D22 D24 D26 D28
3 C VDD GND VDD GND VDD GND VDD GND DCS2 PAR_IN QERR GND DCS3 GND VDD GND VDD GND VDD GND SELDR
4 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD
5 VREF VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VREF
6 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD
7 Q1A Q2A Q3A Q4A Q5A Q7A Q9A Q11A Q10B Q12B Q14B (QODT0B) Q15B (QCS0B) Q17B Q19B Q18A Q20A Q22A Q24A Q25A Q26A Q27A Q28A
8 Q1B Q2B Q3B Q4B Q5B Q6B Q7B Q8B Q9B Q11B Q13B (QODT1B) Q16B (QCS1B) Q18B Q20B Q21B (QCKE0B) Q22B Q23B (QCKE1B) Q24B Q25B Q26B Q27B Q28B
002aac918
176-ball, 8 x 22 grid; top view.
Fig 5. Ball mapping (1 : 2 Register B; C = 1)
SSTUG32868_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 23 April 2007
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NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
6.2 Pin description
Table 3. Symbol Pin description Pin 1 : 2 Register A (C = 0) Ungated inputs DCKE0 DCKE1 DODT0 DODT1 D1 C1 N1 P1 W1 Y1 K1 J1 SSTL_18 SSTL_18 The outputs of this register will not be suspended by the DCS0 and DCS1 control. The outputs of this register will not be suspended by the DCS0 and DCS1 control. Data inputs, clocked in on the crossing of the rising edge of CK and the falling edge of CK. 1 : 2 Register B (C = 1) Type Description
Chip Select gated inputs D1 to D28 A2, A1, B2, B1, C2, C1, D2, D1, E1, F1, G1, H1, N1, P1, R1, T1, U1, V1, W1, W2, Y1, Y2, AA1, AA2, AB1, AB2 K1 J1 K3 P3 SSTL_18 A2, A1, B2, B1, C2, C1, D2, D1, E1, F1, G1, H1, J1, K1, N1, P1, R1, T1, U1, V1, W1, W2, Y1, Y2, AA1, AA2, AB1, AB2 N1 P1 K3 P3 SSTL_18
Chip Select inputs DCS0 DCS1 DCS2 DCS3 Chip select inputs. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs (CSGEN = HIGH) only when at least one chip select input is LOW. If CSGEN, DCS0 and DCS1 inputs are HIGH, D1 to D28[1] inputs will be disabled. Configuration control inputs; Register A or Register B Data outputs[2] that are suspended by the DCS0 and DCS1 control.
Configuration control inputs C A3 A3 LVCMOS input
Re-driven outputs Q1A to Q28A A7, B7, C7, D7, E7, E2, F7, F2, G7, G2, H7, H2, N2, P2, R2, R7, T2, T7, U2, U7, V2, V7, W7, Y7, AA7, AB7 A8, B8, C8, D8, E8, F8, G8, H8, J8, J7, K8, K7, L8, L7, M7, M8, N7, N8, P7, P8, R8, T8, V8, U8, W8, Y8, AA8, AB8 K2 L7 J2 L8 A7, B7, C7, D7, E7, E2, F7, 1.8 V CMOS F2, G7, G2, H7, H2, J2, K2, N2, P2, R2, R7, T2, T7, outputs U2, U7, V2, V7, W7, Y7, AA7, AB7 A8, B8, C8, D8, E8, F8, G8, H8, J8, J7, K8, K7, L8, L7, M7, M8, N7, N8, P7, P8, R8, T8, U8, V8, W8, Y8, AA8, AB8 N2 M7 P2 M8 1.8 V CMOS outputs Data outputs that will not be suspended by the DCS0 and DCS1 control.
Q1B to Q28B
QCS0A QCS0B QCS1A QCS1B
SSTUG32868_1
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Product data sheet
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SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
Table 3. Symbol
Pin description ...continued Pin 1 : 2 Register A (C = 0) 1 : 2 Register B (C = 1) U2 R8 V2 U8 K2 L7 J2 L8 M3 open-drain output Output error bit; generated on clock cycle after the corresponding data output. Parity input. Arrives one clock cycle after the corresponding data input. Chip select gate enable. When HIGH, the D1 to D28[1] inputs will be latched only when at least one chip select input is LOW during the rising edge of the clock. When LOW, the D1 to D28[1] inputs will be latched and re-driven on every rising edge of the clock. Positive master clock input. Negative master clock input. 1.8 V CMOS outputs Data outputs that will not be suspended by the DCS0 and DCS1 control. 1.8 V CMOS outputs Data outputs that will not be suspended by the DCS0 and DCS1 control. Type Description
QCKE0A F2 QCKE0B H8 QCKE1A E2 QCKE1B F8 QODT0A N2 QODT0B M7 QODT1A P2 QODT1B M8 Output error QERR M3
Parity input PAR_IN L3 L3 SSTL_18
Program inputs CSGEN L2 L2 LVCMOS input
Clock inputs CK CK L1 M1 L1 M1 differential input differential input LVCMOS input 0.9 V nominal
Miscellaneous inputs RESET M2 M2 Asynchronous reset input. Resets registers and disables VREF data and clock differential-input receivers. Input reference voltage. Power supply voltage.
VREF VDD
A5, AB5 B3, B4, B5, B6, D3, D4, D5, D6, F3, F4, F5, F6, H3, H4, H5, H6, K4, K5, K6, M4, M5, M6, P4, P5, P6, T3, T4, T5, T6, V3, V4, V5, V6, Y3, Y4, Y5, Y6, AB4, AB6
A5, AB5
1.8 V B3, B4, B5, B6, D3, D4, D5, D6, F3, F4, F5, F6, H3, nominal H4, H5, H6, K4, K5, K6, M4, M5, M6, P4, P5, P6, T3, T4, T5, T6, V3, V4, V5, V6, Y3, Y4, Y5, Y6, AB4, AB6
SSTUG32868_1
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Product data sheet
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SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
Table 3. Symbol GND
Pin description ...continued Pin 1 : 2 Register A (C = 0) A4, A6, C3, C4, C5, C6, E3, E4, E5, E6, G3, G4, G5, G6, J3, J4, J5, J6, L4, L5, L6, N3, N4, N5, N6, R3, R4, R5, R6, U3, U4, U5, U6, W3, W4, W5, W6, AA3, AA4, AA5, AA6 AB3 1 : 2 Register B (C = 1) ground A4, A6, C3, C4, C5, C6, input E3, E4, E5, E6, G3, G4, G5, G6, J3, J4, J5, J6, L4, L5, L6, N3, N4, N5, N6, R3, R4, R5, R6, U3, U4, U5, U6, W3, W4, W5, W6, AA3, AA4, AA5, AA6 AB3 LVCMOS input with weak pull-up Ground. Type Description
SELDR
Selects output drive strength: `HIGH' for normal drive; `LOW' for high drive. This pin will default HIGH if left open-circuit (built-in weak pull-up resistor).
[1] [2]
Data inputs = D1 to D5, D7, D9 to D12, D17 to D28 when C = 0. Data inputs = D1 to D12, D17 to D20, D22, D24 to D28 when C = 1. Data outputs = Q1x to Q5x, Q7x, Q9x to Q12x, Q17x to Q28x when C = 0. Data outputs = Q1x to Q12x, Q17x to Q20x, Q22x, Q24x to Q28x when C = 1.
7. Functional description
7.1 Function table
Table 4. RESET H H H H H H H H H H H H H H H L Function table (each flip-flop) Inputs DCS0[2] L L L L L L H H H H H H H H H X or floating DCS1[2] L L L H H H L L L H H H H H H X or floating CSGEN X X X X X X X X X L L L H H H X or floating CK L or H L or H L or H L or H L or H X or floating CK L or H L or H L or H L or H L or H X or floating Dn, DODTn, DCKEn L H X L H X L H X L H X L H X X or floating Qn L H Q0 L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs[1] QCS0x QCS1x L L Q0 L L Q0 H H Q0 H H Q0 H H Q0 L L L Q0 H H Q0 L L Q0 H H Q0 H H Q0 L QODTn, QCKEn L H Q0 L H Q0 L H Q0 L H Q0 L H Q0 L
[1] [2]
Q0 is the previous state of the associated output. DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
(c) NXP B.V. 2007. All rights reserved.
SSTUG32868_1
Product data sheet
Rev. 01 -- 23 April 2007
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SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
Table 5. RESET H H H H H H H H H H L
[1] [2] [3] [4] [5]
Parity and standby function table Inputs DCS0[1] L L L L X X X X H X X or floating DCS1[1] X X X X L L L L H X X or floating CK L or H X or floating CK L or H X or floating of inputs = H (D1 to D28) even odd even odd even odd even odd X X X PAR_IN[2] L L H H L L H H X X X or floating Output QERR[3][4] H L L H H L L H QERR0[5] QERR0 H
DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function. PAR_IN arrives one clock cycle after the data to which it applies. This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. QERR0 is the previous state of output QERR. If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus two clock cycles or until RESET is driven LOW.
7.2 Functional information
The SSTUG32868 is a 28-bit 1 : 2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always must be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable
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Product data sheet
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SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUG32868 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The SSTUG32868 includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. The corresponding QERR output signal for the data inputs is generated two clock cycles after the data, to which the QERR signal applies, is registered. The SSTUG32868 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D inputs (D1 to D5, D7, D9 to D12, D17 to D28 when C = 0; or D1 to D12, D17 to D20, D22, D24 to D28 when C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D inputs must be tied to a known logic state. If an error occurs and the QERR output is driven LOW, it stays latched LOW for a minimum of two clock cycles or until RESET is driven LOW. If two or more consecutive parity errors occur, the QERR output is driven LOW and latched LOW for a clock duration equal to the parity error duration or until RESET is driven LOW. If a parity error occurs on the clock cycle before the device enters the Low-Power Mode (LPM) and the QERR output is driven LOW, then it stays latched LOW for the LPM duration plus two clock cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0, DCS1, DCS2 and DCS3) are not included in the parity check computation. The C input controls the pinout configuration from Register A configuration (when LOW) to Register B configuration (when HIGH). The C input should not be switched during normal operation. It should be hard-wired to a valid LOW or HIGH level to configure the register in the desired mode. The device also supports low-power active operation by monitoring both system chip select (DCS0, DCS1, DCS2 and DCS3) and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0 and DCS1 inputs are HIGH. If CSGEN or the DCSn inputs are LOW, the Qn outputs will function normally. Also, if all DCSn inputs are HIGH, the device will gate the QERR output from changing states. If any of the DCSn are LOW, the QERR output will function normally. The RESET input has priority over the DCSn control, and when driven LOW will force the Qn outputs LOW and the QERR output HIGH. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground (GND), in which case the set-up time requirement for DCSn would be the same as for the other D data inputs. To control the Low-power mode with DCSn only, the CSGEN input should be pulled up to VDD through a pull-up resistor. The two VREF pins (A5 and AB5) are connected together internally by approximately 150 . However, it is necessary to connect only one of the two VREF pins to the external Vref power supply. An unused VREF pin should be terminated with a Vref coupling capacitor. The SSTUG32868 is available in a TFGBA176 package.
SSTUG32868_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 23 April 2007
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NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
7.3 Register timing
RESET
CSGEN
DCSn
m CK
m+1
m+2
m+3
m+4
CK tACT
tsu
th
Dn, DODTn, DCKEn(1) tPDM, tPDMSS CK to Q Qn, QODTn, QCKEn tsu PAR_IN(1) tPHL CK to QERR QERR(2) data to QERR latency tPHL, tPLH CK to QERR th
HIGH, LOW, or Don't care
HIGH or LOW
002aab899
(1) After RESET is switched from LOW to HIGH, all data and PAR_IN input signals must be set and held LOW for a minimum time of tACT(max) to avoid false error. (2) If the data is clocked on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be produced on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse.
Fig 6. Timing diagram during start-up (RESET switches from LOW to HIGH)
SSTUG32868_1
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Product data sheet
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SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
RESET
CSGEN
DCSn
m CK
m+1
m+2
m+3
m+4
CK tsu th
Dn, DODTn, DCKEn tPDM, tPDMSS CK to Q Qn, QODTn, QCKEn tsu th
PAR_IN tPHL, tPLH CK to QERR QERR(1) data to QERR latency output signal is dependent on the prior unknown event
unknown input event
HIGH or LOW
002aab900
(1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be generated on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. If an error occurs and the QERR output is driven LOW, it stays LOW for a minimum of two clock cycles or until RESET is driven LOW.
Fig 7. Timing diagram during normal operation (RESET = HIGH)
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1.8 V DDR2-1G configurable registered buffer with parity
RESET
tINACT
CSGEN(1)
DCSn(1)
CK(1)
CK(1)
Dn, DODTn, DCKEn(1) tPHL RESET to Q Qn, QODTn, QCKEn
PAR_IN(1) tPLH RESET to QERR QERR
HIGH, LOW, or Don't care
HIGH or LOW
002aac511
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at valid logic levels (not floating) for a minimum time of tINACT(max).
Fig 8. Timing diagram during shutdown (RESET switches from HIGH to LOW)
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8. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO IIK IOK IO IDDC Tstg Vesd Parameter supply voltage input voltage output voltage input clamping current output clamping current output current continuous current through each VDD or GND pin storage temperature electrostatic discharge voltage Human Body Model (HBM); 1.5 k; 100 pF Machine Model (MM); 0 ; 200 pF receiver driver VI < 0 V or VI > VDD VO < 0 V or VO > VDD continuous; 0 V < VO < VDD
[1][2] [1][2]
Conditions
Min -0.5 -0.5 -0.5 -65 2 200
Max +2.5 +2.5 VDD + 0.5 50 50 50 100 +150 -
Unit V V V mA mA mA mA C kV V
[1] [2]
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 2.5 V maximum.
9. Recommended operating conditions
Table 7. Symbol VDD Vref VT VI VIH(AC) VIL(AC) VIH(DC) VIL(DC) VIH VIL VICR VID IOH IOL Tamb Recommended operating conditions Parameter supply voltage reference voltage termination voltage input voltage AC HIGH-level input voltage AC LOW-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage Dn and PAR_IN inputs Dn and PAR_IN inputs Dn and PAR_IN inputs RESET, CSGEN RESET, CSGEN
[1] [1] [1] [1] [2] [2]
Conditions
Min 1.7 0.49 x VDD 0 0.65 x VDD 0.675 600 -
Typ 0.50 x VDD -
Max 2.0 0.51 x VDD VDD 0.35 x VDD 1.125 -8 8 +70 +85
Unit V V V V V V V V mV mA mA C C
Vref - 0.040 Vref Vref + 0.250 Vref + 0.125 -
Vref + 0.040 V
Vref - 0.250 V Vref - 0.125 V
DC HIGH-level input voltage Dn and PAR_IN inputs
common mode input voltage CK, CK range differential input voltage HIGH-level output current LOW-level output current ambient temperature operating in free air SSTUG32868ET/G SSTUG32868ET/S CK, CK
0 0
[1] [2]
The differential inputs must not be floating, unless RESET is LOW. The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation.
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1.8 V DDR2-1G configurable registered buffer with parity
10. Characteristics
Table 8. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol VOH VOL II IDD Parameter HIGH-level output voltage LOW-level output voltage input current supply current Conditions IOH = -6 mA; VDD = 1.7 V IOL = 6 mA; VDD = 1.7 V all inputs; VI = VDD or GND; VDD = 1.9 V static standby; RESET = GND; VDD = 1.9 V; IO = 0 mA static operating; RESET = VDD; VDD = 1.9 V; IO = 0 mA; VI = VIH(AC) or VIL(AC) IDDD dynamic operating current per MHz clock only; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V per each data input (1 : 1 mode); RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V per each data input (1 : 2 mode); RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V Ci input capacitance Dn, CSGEN, PAR_IN inputs; VI = Vref 250 mV; VDD = 1.8 V DCSn; VICR = 0.9 V; VID = 600 mV; VDD = 1.8 V CK and CK; VICR = 0.9 V; VID = 600 mV; VDD = 1.8 V RESET; VI = VDD or GND; VDD = 1.8 V Zo output impedance instantaneous steady-state
[1] Instantaneous is defined as within < 2 ns following the output data transition edge.
[1]
Min 1.2 -
Typ -
Max 0.5 5 2 80
Unit V V A mA mA
-
16
-
A
-
19
-
A
-
19
-
A
2.5 2.5 2 3 -
7 53
4 4 3 5 -
pF pF pF pF
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1.8 V DDR2-1G configurable registered buffer with parity
Table 9. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol fclk tW tACT tINACT tsu Parameter clock frequency pulse duration differential inputs active time differential inputs inactive time set-up time DCSn before CK, CK DODTn, DCKEn and Dn before CK, CK PAR_IN before CK, CK th hold time DCSn, DODTn, DCKEn and Dn after CK, CK PAR_IN after CK, CK
[1] [2] [3] This parameter is not necessarily production tested. VREF must be held at a valid input voltage level, and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken HIGH. VREF, data and clock inputs must be held at valid voltage levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Conditions CK, CK HIGH or LOW
[1][2]
Min 1 0.6 0.5 0.5 0.4 0.4
Typ -
Max 450 10 15 -
Unit MHz ns ns ns ns ns ns ns ns
[1][3]
Table 10. Switching characteristics Over recommended operating conditions, unless otherwise noted. Symbol fclk(max) tPDM tPLH tPHL tPDMSS Parameter maximum clock frequency peak propagation delay LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay simultaneous switching peak propagation delay Conditions input single bit switching; from CK and CK to Qn from CK and CK to QERR from RESET to QERR from CK and CK to QERR from RESET to Qn from CK and CK to Qn
[1] [1]
Min 450 1.0 1.2 1 -
Typ -
Max 1.4 3 3 2.4 3 1.5
Unit MHz ns ns ns ns ns ns
[1]
Includes 350 ps of test-load transmission line delay.
Table 11. Output edge rates Over recommended operating conditions, unless otherwise noted. Symbol dV/dt_r dV/dt_f dV/dt_ Parameter rising edge slew rate falling edge slew rate Conditions from 20 % to 80 % from 80 % to 20 % Min 1 1 Typ Max 4 4 1 Unit V/ns V/ns V/ns
absolute difference between dV/dt_r (from 20 % to 80 %) or and dV/dt_f (from 80 % to 20 %)
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11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement.
VDD DUT
50
CK inputs
CK CK test point
RL = 100
delay = 350 ps Zo = 50
RL = 1000
OUT
CL = 30 pF(1) RL = 1000
test point
002aab902
(1) CL includes probe and jig capacitance.
Fig 9. Load circuit, data output measurements
LVCMOS RESET 0.5VDD tINACT IDD(1) 0.5VDD
VDD 0V tACT 90 % 10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 10. Voltage and current waveforms; inputs active and inactive times
tW VIH input VICR VICR VID VIL
002aaa373
VID = 600 mV. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; pulse duration
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1.8 V DDR2-1G configurable registered buffer with parity
CK VICR CK tsu input Vref th VIH Vref VIL
002aaa374
VID
VID = 600 mV. Vref = 0.5VDD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; set-up and hold times
CK VICR CK tPLH tPHL VOH output VT VOL 002aaa375 VICR Vi(p-p)
tPLH and tPHL are the same as tPD.
Fig 13. Voltage waveforms; propagation delay times (clock to output)
LVCMOS VIH RESET 0.5VDD VIL tPHL VOH output VT VOL 002aaa376
tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 14. Voltage waveforms; propagation delay times (reset to output)
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1.8 V DDR2-1G configurable registered buffer with parity
11.2 Data output slew rate measurement
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 50
OUT
CL = 10 pF(1)
test point
002aaa377
(1) CL includes probe and jig capacitance.
Fig 15. Load circuit, HIGH-to-LOW slew measurement
output 80 % dv_f 20 % dt_f
002aaa378
VOH
VOL
Fig 16. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
CL = 10 pF(1)
test point
RL = 50
002aaa379
(1) CL includes probe and jig capacitance.
Fig 17. Load circuit, LOW-to-HIGH slew measurement
dt_r VOH 80 % dv_r 20 % output
002aaa380
VOL
Fig 18. Voltage waveforms, LOW-to-HIGH slew rate measurement
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1.8 V DDR2-1G configurable registered buffer with parity
11.3 Error output load circuit and voltage measurement
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 1 k
OUT
CL = 10 pF(1)
test point
002aaa500
(1) CL includes probe and jig capacitance.
Fig 19. Load circuit, error output measurements
LVCMOS RESET 0.5VDD
VDD
0V tPLH VOH output waveform 2 0.15 V
002aab903
0V
Fig 20. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input
timing inputs
VICR tPHL
VICR
Vi(p-p)
VDD output waveform 1 0.5VDD
002aab904
VOL
Fig 21. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs
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Product data sheet
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1.8 V DDR2-1G configurable registered buffer with parity
timing inputs
VICR tPLH
VICR
Vi(p-p)
VOH output waveform 2 0.15 V
002aab907
0V
Fig 22. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs
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1.8 V DDR2-1G configurable registered buffer with parity
12. Package outline
TFBGA176: plastic thin fine-pitch ball grid array package; 176 balls; body 6 x 15 x 0.7 mm SOT932-1
D
B
A
ball A1 index area
E
A
A2
A1 detail X
e1 1/2 e e b
AB AA Y W V U T R P N M L K J H G F E D C B A
C v w
M M
CAB C
y1 C
y
e
e2 1/2 e
ball A1 index area
1
2
3
4
5
6
7
8
X 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.15 A1 0.35 0.25 A2 0.80 0.65 b 0.45 0.35 D 6.1 5.9 E 15.1 14.9 e 0.65 e1 4.55 e2 13.65 v 0.15 w 0.08 y 0.1 y1 0.1 10 mm
OUTLINE VERSION SOT932-1
REFERENCES IEC --JEDEC MO-246 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 06-01-11 06-01-16
Fig 23. Package outline SOT932-1 (TFBGA176)
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1.8 V DDR2-1G configurable registered buffer with parity
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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1.8 V DDR2-1G configurable registered buffer with parity
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24.
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Product data sheet
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1.8 V DDR2-1G configurable registered buffer with parity
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 14. Acronym CMOS DDR2 DIMM DRAM LVCMOS PRR RDIMM SSTL Abbreviations Description Complementary Metal Oxide Semiconductor Double Data Rate 2 Dual In-line Memory Module Dynamic Random Access Memory Low Voltage Complementary Metal Oxide Semiconductor Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic
15. Revision history
Table 15. Revision history Release date 20070423 Data sheet status Product data sheet Change notice Supersedes Document ID SSTUG32868_1
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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18. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 8 9 10 11 11.1 11.2 11.3 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 10 Function table . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional information . . . . . . . . . . . . . . . . . . 11 Register timing . . . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended operating conditions. . . . . . . 16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 19 Parameter measurement information for data output load circuit . . . . . . . . . . . . . . . . . . . . . . 19 Data output slew rate measurement . . . . . . . . 21 Error output load circuit and voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction to soldering . . . . . . . . . . . . . . . . . 25 Wave and reflow soldering . . . . . . . . . . . . . . . 25 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information. . . . . . . . . . . . . . . . . . . . . 28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
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