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(Advance Version
IP178A 8-Port 10/100 Ethernet Integrated Switch
Feature
Three-in-one 8 port 10/100 Ethernet switch - Built in an 8 port Ethernet switch engine - Built in 8 10/100M transceivers - Built in SSRAM Support flow control - Support IEEE802.3x for full duplex mode operation - Support backpressure for half duplex mode operation Built in up to 1K MAC address An 8 port switching fabric - Support two-level hashing algorithm to improve address collision - Support address aging - Store and forward mode - Broadcast storm protection - Full line speed capability of 148800 (14880) packets/sec for 100M (10M) - Support 1536 byte data transfer for VLAN traffic - Support one MII port - Support port base VLAN - Support CoS DSP approach transceivers - Auto negotiation - Fully digital adaptive equalizer and timing recovery module - Base line Wander correction - 10BaseT, 100BaseT, and 100BaseFX(port6, port7 only) operation - Automatic MDI/MDI-X configuration LED status of Link, Receive, Full duplex, and Speed LED with power on diagnostic function Set operation parameters via pins or EEPROM
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
interface Utilize single clock source (25Mhz) Utilize single power supply (2.5v) 0.25um technology Packaged in 208 pin PQFP
General Description
IP178A is an 8 port 10/100 Ethernet integrated switch. It consists of an 8-port switch controller and eight Fast Ethernet transceivers. Each of the transceivers complies with the IEEE802.3, IEEE802.3u, and IEEE802.3x specifications. The transceivers in IP178A are designed in DSP approach with advance 0.25um technology; this results in high noise immunity and robust performance. Two ports of IP178A can be configured as 100BaseFX.
The IP178A operates in store and forward mode. It stores the incoming packet to the internal SSRAM and learns the SA (source address) automatically if the packet is error free. The SA is stored to the internal address table. IP178A forwards a packet according to DA and address table. When the segments of destination ports are free, it reads the packet from the internal SSRAM and forwards it to the appropriate ports according to the address table. The incoming packets with errors are dropped. IP178A supports IEEE802.3x, optional backpressure, Auto MDI/MDI-X, CoS, port base VLAN, one MII port and various LED functions, etc. These functions can be configured to fit the different requirements by feeding operation parameters via EEPROM interface or pull up/down resistors on specified pins.
1
(Advance Version)
IP178A
The major differences in application circuit between IP178 and IP178A
No more external bias and series resistors
RXIP RXIM 95.3 R 95.3 R AVCC 49.9 R 49.9 R 10k RD + RD RXIP RXIM RD + RD AVCC 49.9 R 49.9 R CT
IP178
IP178A
transformer 10k 0.1u 0.1u
MDI-MDIX transformer
GND
GND
GND
No more A/D bypass capacitors & add a pull up resistor to turn on auto MDI_MDIX
472p VRTP VRBM pin134=NC VRTM VRBP 472p VCC R NC NC pin134= MDI_MDIX_EN NC NC
IP178
IP178A
Transmit circuit is the same as receive circuit for MDI-MDIX function.
GND AVCC 0.1u
49.9 R TXOP TXOM
49.9 R
49.9 R
49.9 R
AVCC TCT TD + TD TXOP TXOM
AVCC CT TD + TD MDI-MDIX transformer
IP178
transformer
IP178A
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
2
(Advance Version)
IP178A
Block Diagram
Address Table RxMAC 10/100BaseTX PHYceiver with Auto-negotiation MDI/MDIX Rx Buffer Mgnt Hashing Unit
(x8)
(x8)
TxMAC Tx Buffer Mgnt
Memory I/F Unit Empty Buffer Mgnt
SSRAM
VLAN Cos Logic
Queue Mgnt
(x8) Fiber Port MII port EEPROM Interface LED Controller
System Block Diagram
MII
OSC
IP178A
OSC
IP178A
EEPROM
OSC
IP178A
UP
4
Xfm
Xfm
4
Xfm
4
Xfm
4
Xfm
MII
4
Xfm
3
OSC
IP178A
OSC
IP178A
RISC
4
Xfm
3
Xfm
FIBER MAU
Xfm
4
Xfm
3
Preliminary, Specification subject to change without notice 3
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
PIN Assignments
BP_KIND[1] / MRXD0
BP_KIND[0] / MRXD1
VCC EESK / MII_CLK
EEDI / MRXD3
UPDATE_R4_EN
BK_EN/ MRXD2
X_EN / MCOL
BF_STM_EN
TXVCC01
RXGND0
TXGND0
VCC_IO
MTXEN
TXOM0
TXOP0
RXIM0
RXIP0
NC
NC
182
181
180
179
178
177
176
175
174
173
172
MTXD3
GND
GND
GND
EEDO
171
170
169
168
167
166
165
164
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
163
162
161
160
159
158
157
UTP_DET#
TWOPART
RXGND1
TXGND1
RXVCC1
RXVCC0
DROP16
GND_IO
MRXDV
TXOM1
MTXD2
MTXD1
MTXD0
TXOP1
RXIP1
RXIM1
NC
NC
NC
NC
EECS
GND
VCC
VCC
VCC
NC
NC
RXVCC2 NC NC RXIP2 RXIM2 NC NC RXGND2 TXGND2 TXOP2 TXOM2 TXVCC23 TXOM3 TXOP3 TXGND3 RXGND3 NC NC RXIM3 RXIP3 NC NC RXVCC3 BGVCC BGRES BGGND PLLGND PLLVCC RXVCC4 NC NC RXIP4 RXIM4 NC NC RXGND4 TXGND4 TXOP4 TXOM4 TXVCC45 TXOM5 TXOP5 TXGND5 RXGND5 NC NC RXIM5 RXIP5 NC NC RXVCC5 FXSD6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 100 101 102 103 104 57 53 54 55 56 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
P6_7_HIGH (LINK_LED0) COS_EN (LINK_LED1) MII_P0_FULL MII_P0_SPEED VCC_SRAM OP0[1] (LINK_LED2) OP0[0] (LINK_LED3) FORCE_MODE NC NC GND_SRAM NC NC NC NC MODBCK (LINK_LED4) VCC_IO SAVEPW_A_EN ALLPASS (LINK_LED5 ) NC MII_P0_FLOW_CTL MII_P0_EXT_EN MDI_MDIX_EN (LINK_LED6) HASH_MODE[1] (LINK_LED7) GND_IO HASH_MODE[0] (FDX_LED0) OP1[0] (FDX_LED1) OP1[1] (FDX_LED2) FEF_EN MII_P0_SNI AGETIME[1] AGETIME[0] NC VCC_IO NC NC NC NC GND_IO LED_SEL[0] LED_SEL[1] VLAN_ON (FDX_LED3) PHASE0 (FDX_LED4) PHASE1 (FDX_LED5) PHASE2 (FDX_LED6) PHASE3 (FDX_LED7) VCC_SRAM LINK_A (SPEED_LED0) LINK_B/ DIRECT_LED (SPEED_LED1) RX_A (SPEED_LED2) RX_B (SPEED_LED3) FDX_A (SPEED_LED4)
IP178A
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
OSCVCC GND
GND
NC
NC
NC
RESETB
GND
GND
TXOM7
GND
GND_SRAM
TXOP7
TXGND7
RXGND7
RXVCC7
GND
GND
VCC
VCC
VCC
VCC
NC
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
4
SPEED_B (SPEED_LED7)
SPEED_A (SPEED_LED6)
FDX_B (SPEED_LED5)
NC
NC
NC
NC
OSCGND
VCC
TXVCC67
RXVCC6
FXSD7
RXIM7
RXIM6
RXIP6
RXIP7
VCC
NC
NC
NC
NC
TXGND6
RXGND6
OSCI
TXOM6
TXOP6
NC
NC
X2
(Advance Version)
IP178A
PIN Description
Type I IPL IPH O I/O Description Input pin Input pin with internal pull low Input pin with internal pull high Output pin Input and Output pin Type I I Description Band gap resister It is connected to GND through a 6.19k (1%) resistor in application circuit. 100Base-FX signal detect Fiber signal detect of port 6 and 7 when the ports are configured to be fiber ports. Fiber signal detect is active if the voltage of FXSD is higher than 1.2v. If TP mode is selected, the pins must be connected to ground. TP receive
Pin no. Label MLT3 signals 25 BGRES 52, 76 FXSD6 FXSD7
189, 190, RXIP0~7 205, 204, 4, RXIM0~7 5, 20, 19, 32, 33, 48, 47, 56, 57, 72, 71 195, 196, 199, 198, 10,11, 14, 13, 38, 39, 42, 41, 62, 63, 66, 65 TXOP0~7 TXOM0~7
I
O
TP transmit
Preliminary, Specification subject to change without notice 5
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
PIN Description (continued)
Pin no. 174 175 Label EEDO EEDI Type IPL IPL/O Description Data input of EEPROM Data output of EEPROM It is input during reset period. After reset, it is an output signal EEDI to read EEPROM. After reading EEPROM, this pin becomes an output signal MRXD3, if external MII port is enabled (MII_P0_EXT_EN=1); otherwise, it is an input signal. Chip select of EEPROM It is input during reset period. After reset, it is an output signal EECS to read EEPROM. After reading EEPROM, this pin becomes an input signal. Clock input of EEPROM It is input during reset period. After reset, it is an output signal EESK to read EEPROM. After reading EEPRM, this pin becomes an output signal MII_CLK, if external MII port is enabled (MII_P0_EXT_EN=1); otherwise, it is an input signal. 25Mhz system clock. A 25Mhz clock from oscillator is fed to this pin. The X2 pin should be left open in this application. Crystal pin A 25Mhz crystal can be connected to OSCI and X2. Reset It is low active. It must be hold for more than 1ms. It is Schmitt trigger input.
176
EECS
IPL/O
177
EESK
IPL/O
Misc. 78
OSCI
I
79 89
X2 RESETB
O I
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
6
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Direct mode LED. 133, 134, LINK_LED[7:0] 138, 141, 150, 151, 155, 156 102, 103, 104, 105, 106, 107, 108, 109 111, 112, 113, 114, 115, 129, 130, 131 116, 117 SPEED_LED[7:0] Type O Description LINK_LED of port 7~0 If pin 108 DIRECT_LED is pulled up, LINK_LED[7:0] are link LED of port 7~0. The detail functions are illustrated in the following table.
O
SPEED_LED of port 7~0 If pin 108 DIRECT_LED is pulled up, SPEED_LED[7:0] are speed LED of port 7~0. The detail functions are illustrated in the following table.
FDX_LED[7:0]
O
FDX_LED of port 7~0 If pin 108 DIRECT_LED is pulled up, FDX_LED[7:0] are full duplex LED of port 7~0. The detail functions are illustrated in the following table.
LED_SEL[1:0]
IPH LED function selection The pins are latched at the end of reset to select LED functions. The detail functions are illustrated in the following table. A table for direct mode LED LED_SEL[1:0] LinK_LED[7:0] SPEED_LED[7:0] FDX_LED[7:0] 00 Off: link fail Off: link fail Off: half duplex On: 10M link ok On: 100M link ok On: full duplex Flash: Tx/Rx Flash: Tx/Rx 01 Off: link fail Off: 10M Off: half duplex On: link ok On: 100M On: full duplex Flash: Rx Flash: collision 10 Off: link fail Off: link fail Off: half duplex On: 10M link ok On: 100M link ok On: full duplex Flash: Tx/Rx Flash: Tx/Rx Flash: collision 11 (default) Off: link fail Off: 10M Off: half duplex On: link ok On: 100M On: full duplex Flash: Tx/Rx Flash: collision
Preliminary, Specification subject to change without notice 7
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Direct mode LED. 108 DIRECT_LED Type IPL Description Direct mode LED It is latched at the end of reset to select LED mode. It will be lathed as high, if it is connected to VCC through a resistor. It will be latched as low, if it is left open. 1: LED direct mode. IP178A provides 24 LED pins to drives 24 LED directly. The 24 LED are LINK_LED[7:0], SPEED_LED[7:0], and FDX_LED[7:0]. 0: LED scan mode (default) IP178A provides 12 LED pins to drives 32 LED in scan mode. The 32 LED are Link LED[7:0], Speed LED[7:0], Full duplex LED[7:0], and Rx LED[7:0]. It is compatible to the previous version of IP178.
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
8
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Scan mode LED. 102 SPEED_B 103 104 105 106 107 108 109 111, 112, 113, 114 SPEED_A FDX_B FDX_A RX_B RX_A LINK_B LINK_A PHASE[3:0] Type O O IPL/O IPL/O IPL/O IPL/O IPL/O IPL/O IPL/O Description It is a control signal of speed LED for port 4~7 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. It is a control signal of speed LED for port 0~3 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. It is a control signal of full duplex LED for port 4~7 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. It is a control signal of full duplex LED for port 0~3 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. It is a control signal of rx LED for port 4~7 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. It is a control signal of rx LED for port 0~3 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. It is a control signal of link LED for port 4~7 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. It is a control signal of link LED for port 0~3 after reset if LED scan mode is selected. The detail functions are illustrated in the following table. These pins are phase control signals after reset if LED scan mode is selected.
A table for scan mode LED LED_SEL[1:0] Link LED 00 Off: link fail On: 10M link ok Flash: Tx/ Rx 01 Off: link fail On: link ok Flash: Rx 10 Off: link fail On: 10M link ok Flash: Tx/Rx 11 (default) Off: link fail On: link ok Flash: Tx/Rx
Rx LED Off: no collision Flash: collision Off: idle Flash: Tx/ Rx Off: no collision Flash: collision Off: no collision Flash: collision
Full duplex LED Off: half duplex On: full duplex Off: half duplex On: full duplex Flash: collision Off: half duplex On: full duplex Flash: collision Off: half duplex On: full duplex Flash: collision
Speed LED Off: link fail On: 100M link ok Flash: Tx/ Rx Off: 10M On: 100M Off: link fail On: 100M link ok Flash: Tx/Rx Off: 10M On: 100M
Preliminary, Specification subject to change without notice 9
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label MII ports 177 MII_CLK Type Description
159
MRXDV
175
MRXD3
170
MRXD2
169
MRXD1
IPL/O MII_CLK It is an output signal MII_CLK, if external MII port is enabled (MII_P0_EXT_EN=1). Both MRXD and MTXD are synchronous to this clock. This pin is shared with EESK. Please reference pin description of EESK for more detail information MII_CLK is CLK in SNI mode. IPL/O MRXDV It is an output signal MRXDV, if external MII port is enabled (MII_P0_EXT_EN=1). MRXDV is CRS in SNI mode. IPL/O MRXD3 It is an output signal MRXD3, if external MII port is enabled (MII_P0_EXT_EN=1). This pin is shared with EEDI. Please reference pin description of EEDI for more detail information IPH/ MRXD2 O It is an output signal MRXD2, if external MII port is enabled (MII_P0_EXT_EN=1). This pin is shared with BK_EN. Please reference pin description of BK_EN for more detail information IPL/O MRXD1 It is an output signal MRXD1 if external MII port is enabled (MII_P0_EXT_EN=1).
168
MRXD0
IPL/O MRXD0 It is an output signal MRXD0 if external MII port is enabled (MII_P0_EXT_EN=1). MRXD0 is RXD in SNI mode. IPH/ MCOL O It is an output signal MCOL if external MII port is enabled (MII_P0_EXT_EN=1). This pin is shared with X_EN. Please reference pin description of X_EN for more detail information IPL MTXEN MTXEN is TXEN in SNI mode. IPL MTXD[3:0] MTXD0 is TXD in SNI mode.
167
MCOL
173
MTXEN
172, 166, MTXD3[3:0] 164, 158
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
10
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Type Description Basic operation parameter setting of switch 170 BK_EN IPH/O Backpressure enable 1: enable (default), 0: disable This pin is input to set backpressure during reset. It becomes an output signal MRXD2 after reset, if external MII port is enabled. 168, 169 BP_KIND[1:0] IPL/O Backpressure type selection 00: carrier base backpressure (default) 01: (reserved) 10: (reserved) These two pins are input during reset. It becomes output signals MRXD0 and MRXD1 after reset, if external MII port is enabled. IP178A supports carrier base backpressure only. IPH/O IEEE 802.3x flow control enable 1: enable (default), 0:disable This pin is an input to set flow control during reset. It becomes an output signal MCOL after reset, if external MII port is enabled. IPL Broadcast storm enable 1: enable, 0: disable (default) IP178A drops the incoming packet if the number of broadcast packet in queue is over the threshold. Drop the transmitting packet after 16 consecutive collisions 1: drop, 0: not drop (default)
167
X_EN
163
BF_STM_EN
162
DROP16
IPL
161
TWOPART
141
MODBCK
Turn on twopartD (Twopart) 1: enable (fixed), 0: disable IP178A examine the carrier for 64 bits only during its back off period if this function is enabled. It makes IP178A have higher priority in a collision event. IP178A uses the default value. User can't change the setting. IPH/O Aggressive back off enable (MODBCK) IP178A uses modified (aggressive) back off algorithm if this function is enabled. The maximum back off period is limited to 8-slot time. It makes IP178A have higher priority in a collision event. 1: aggressive mode enable (default), 0: standard back off It is link LED of port 4 after reset if LED direct mode is selected. IPL/O It is for testing only. This pin should be left open to turn off the function for normal operation. It is link LED of port 5 after reset if LED direct mode is selected.
IPH
138
ALLPASS
Preliminary, Specification subject to change without notice 11
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Type Description Basic operation parameter setting of switch 133, 131 HASH_MODE[1:0] IPL Hashing algorithm selection for 1st layer and 2nd layer 00: direct and CRC (default) 01: direct and CRC 10: CRC and CRC 11: reserved The pins are input signals during reset and are latched at the end of reset to select hashing algorithm. HASH_MODE[0] is full duplex LED of port 0 after reset if LED direct mode is selected. HASH_MODE[1] is link LED of port 7 after reset if LED direct mode is selected. 126, 125 AGETIME[1:0] IPH, Aging time selection of address table IPL An address tag in hashing table will be removed if this function is turned on and its aging timer expires.
AGETIME[1] 0 0 1 1
AGETIME[0] 0 1 0 1
Aging time no aging 120s 240s (default) 480s
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
12
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Type Description Advance operation parameter setting of switch 156 P6_7_HIGH IPL/O Port6 port7 are set to be high priority port Packets received from port6 or port7 are handled as high priority packets if the function is enabled. 1: enable, 0: disabled (default) It is an input signal during reset and its value is latched at the end of reset to set high priority port. It is link LED of port 0 after reset if LED direct mode is selected. IPL/O Class of service enable Packets with high priority tag are handled as high priority packets if the function is enabled. 1: enable, 0: disabled (default) It is an input signal during reset and its value is latched at the end of reset to set CoS. It is link LED of port 1 after reset if LED direct mode is selected. IPL/O VLAN enable Enable a specified configuration of port base VLAN. It is an input signal during reset and its value is latched at the end of reset to set VLAN. It is full duplex LED of port 3 after reset if LED direct mode is selected. 0: disabled (default), 1: enable IP178A are separated into 7 VLANs if this function is enabled. The VLAN group is as follows, VLAN 1: port0, port 7 VLAN 2: port 1, port 7 VLAN 3: port 2, port 7 VLAN 4: port 3, port 7 VLAN 5: port 4, port 7 VLAN 6: port 5, port 7 VLAN 7: port 6, port 7 The configuration can be updated by programming EEPROM register. Please refer to EEPROM register 07h~0Ah for detail information.
155
COS_EN
115
VLAN_ON
Preliminary, Specification subject to change without notice 13
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Type PHY operation parameter setting 134 MDI_MDIX_EN IPL/O MDI/MDI-X enable MDI/MDI-X auto cross over 1: enable, 0:disable (default) Description
160
UPDATE_R4_EN
IPH
It is an input signal during reset and its value is latched at the end of reset to set auto MDI/MDIX function. It is link LED of port 6 after reset if LED direct mode is selected. It is internally pulled low. Change capability enable Force to be link at half duplex, if each node doesn't support IEEE802.3x. This will prevent the packet loss due to no flow control in full duplex mode. 1: enable (default), 0: disable It is internally pulled high. It is connected to GND through a resistor to turn off the function in IP178A application circuit. Savepw_a_en, Power saving mode for fast link pulse 1: enable (default), 0:disable It is internally pulled high. The default value must be adopted normal operation.
139
SAVEPW_A_EN
IPH
157
UTP_DET#
I
UTP detect enable Power saving mode for unplugged port. 1: disable, FLP is sent out every 12~16ms. 0: enable FLP is sent out every 1.2 sec if cable is unplugged and the function is enabled. If a FLP is received, IP178A resumes to send out FLP every 12~16ms. This function is disabled in spite of the setting on this pin and it can be enable by EEPROM only. Far end fault detect function of Fiber port 1: enable (default), 0: disable
128
FEF_EN
IPH
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
14
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Type Description PHY operation parameter setting 149, FORCE_MODE IPL Transceiver operation mode selection 129, 130, OP1[1:0] These pins are internally pulled low. 151, 150 OP0[1:0] Summary OP1 [1:0] 00 10 11 x x x OP0 [1:0] x x x 00 10 11 FORCE_MODE 0 0 0 0 0 0 Description Port1, 3, 5, 7 nway with all capability (default) Port7 FX full duplex, port1, 3, 5 nway with all capability Port7 FX half duplex, port1, 3, 5 nway with all capability Port0, 2, 4, 6 nway with all capability (default) Port6 FX full duplex, port0, 2, 4 nway with all capability Port6 FX half duplex, port0, 2, 4 nway with all capability
Preliminary, Specification subject to change without notice 15
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
PIN Description (continued)
Pin no. Label Type External MII port operation parameter setting 135 MII_P0_EXT_EN IPL External MII port enable 1: enable, 0: disable (default) 154 MII_P0_FULL IPH Description
Duplex setting of external MII port 1: full (default), 0: half It is valid only if MII_P0_EXT_EN is set to logic high. Speed setting of external MII port 1: 10M (default), 0: 100M It is valid only if MII_P0_EXT_EN is set to logic high. Flow control setting of external MII port 1: on, 0: off (default) It is valid only if MII_P0_EXT_EN is set to logic high. External Mac interface selection 1: SNI interface 0: MII interface (default) It is valid only if MII_P0_EXT_EN is set to logic high. If the SNI interface is enabled, port0 of switch core is forced to 10Mbps.
153
MII_P0_SPEED
IPH
136
MII_P0_FLOW_CTL
IPL
127
MII_P0_SNI
IPL
Power BGVCC BGGND PLLGND PLLVCC OSCGND OSCVCC GND VCC GND_SRAM VCC_SRAM GND_IO VCC_IO RXVCC0~7 RXGND0~7 TXGND0~7 TXVCC01 TXVCC23 TXVCC45 TXVCC67 NC
I I I I I I I I I I I I I I I I
Power of band gap circuit Power of band gap circuit Power of PLL circuit Power of PLL circuit Power of oscillator Power of oscillator Power of internal logic Power of internal logic Power of internal SRAM Power of internal SRAM Power for LED and EEPROM Power for LED and EEPROM Power of analog receive block Power of analog receive block Power of analog transmit buffer Power of analog transmit buffer
No connection. They should be left open for normal operation.
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
16
(Advance Version)
IP178A
Functional Description
Basic Operation IP178A consists of eight switching ports. Full/half duplex and speed of each port depends on the result of auto negotiation of its corresponding transceiver. It is not necessary to use an external memory to buffer packets. Each port of IP178A has its own receive buffer management, transmit buffer management, transmit queue management, transmit MAC and receive MAC. All ports share a hashing unit, a memory interface unit, an empty buffer management, and an address table. An incoming packet is stored to the internal memory if the packet is error free. A packet is error free if its crc field is correct and its length is between 64 and 1536 byte. At the same time, IP178A examines the address field of the packet. By the way, switch learns the locations of every station (source address) and records them on the address table. IP178A then reads the packet from the internal memory and sends it to the appropriate ports according to the address table. Eventually, IP178A supports the switching function by dropping or forwarding the incoming packets. Block Description The basic function of each block in the block diagram is illustrated in the following context. Hashing unit is responsible to learn and to recognize address. Transmit buffer management and receive buffer management are responsible to store data to or to read data from the internal memory through memory interface unit. Transmit MAC and receive MAC interface to transceivers and Preliminary, Specification subject to change without notice 17
IP178A-DS-P05 Sep. 09, 2002
implement Ethernet protocol. Receive MAC receives the incoming data from transceiver and converts nibble data into double word data. As a 32 bit data is ready, it feeds the data into receive FIFO and requests receive buffer management for data transfer. When receive buffer management receives the request, it gets a empty block from empty buffer management and writes the double word data to the buffer, which is located in the internal SSRAM, through memory interface unit. The incoming packet is fed to hashing unit at the same time. Hashing unit extracts the source address of incoming packet to set up an address table. An incoming packet is dropped or forwarded according to the table. The address table is built in the SSRAM of IP178A. All ports share an empty buffer management. After reset, the empty buffer management provides 8 addresses of empty blocks. When a packet comes in, it searches for a new empty block. After a packet is forwarded, the corresponding blocks are released. Empty buffer management treats the block as an empty block and provides its address to desired receive buffer management. Eight addresses are always ready for receive buffer management.
(Advance Version)
IP178A
Back off Algorithm IP178A provides two parameters to modify its back off algorithm. They are Modbck and Drop16. IP178A implements the IEEE802.3 standard binary exponential back off algorithm (Modbck=0) and modified back off algorithm (Modbck=1) when it works at half duplex mode. If Modbck is set, the maximum back off time is limited to eight-slot time. The minimum defer time is separated into the two periods. The first period consists of the first 64-bit time and the 2 period consists of the rest 32 bit-time. In the case of minimum defer time IP178A transmits a packet after 96-bit time immediately in spite of the status of cable on the 2 period. After 16 consecutive collisions, the transmitting packet is dropped if Drop16 is set.
nd nd
Backpressure The backpressure is used for flow control in half duplex mode if Bk_en is turned on. When the buffer of a port is full, it will start to send jam signals. The remote station will defer transmission after detecting the jam signals.
Carrier based backpressure is sent by IP178A, when the buffer of a port is full. IP178A sends jam packets continuously to defer the remote station. The length of jam packet is 1518 byte and the IPG is equal to 96-bit time. If the port has packets to transmit during this period, it transmits the queuing packet instead of the jam packets. After the queuing packets are transmitted, IP178A resumes to jam the segment by sending jam packets if the buffer of a port is full. If a collision occurs,
Operation Parameter IP178A supports many optional functions. They can be configured to fit different requirements by setting appropriate parameters. These parameters can be fed into IP178A through EEPROM interface or through pins.
the back off algorithm is skipped and the jam packets are generated immediately. The definition of buffer full for carrier base backpressure is there is only one empty buffer for a port.
Flow Control IP178A provides two mode of flow control. Backpressure is for half duplex mode and IEEE802.3x flow control is for full duplex.
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
IEEE 802.3x The IEEE 802.3x is used for flow control in full duplex mode if both IP178A (X_en=1) and the remote station have IEEE802.3x capability. When the level of occupied buffer of a port is over set threshold, it will send a PAUSE frame with maximum delay FFFF. The remote station will stop to transmit the next packet after receiving the PAUSE frame. After level of the occupied buffer is below release threshold, the port sends out a PAUSE frame with zero delay to resume receiving the incoming packets. The remote station is re-enable to transmit packets after receiving the PAUSE frame with zero delay. While level of the occupied buffer of a port is over set threshold, IP178A re-transmits the PAUSE When an incoming PAUSE frame with non-zero delay is received, the port stops the next frame transmission and starts its pause timer. It is re-enabled transmission function either the pause timer is expired or a PAUSE frame with zero delay is received. If another pause frame is received before the timer expires, the timer will be updated with the new value. During this period, only PAUSE frame from IP178A will be transmitted. frame with maximum delay to ensure the pause timer of the remote station does not expire and begins transmission. The IPG between PAUSE frames is 42ms(100M) or 420ms(10M).
PAUSE Frame Format Destination 01-80-C2-00-00-01 6 bytes Source SA 6 bytes Type 8808 2 bytes Opcode 0001 2bytes Pause Timer FFFF(0000) 2 bytes Pad PAD with zero 42 bytes CRC CRC 4 bytes
Preliminary, Specification subject to change without notice 19
IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
Capability Changing If the remote station does not support IEEE802.3x and has full duplex capability, IP178A supports a private mechanism to handle flow control to prevent packet loss. It is called capability changing and is controlled by the parameter Update_r4_en. This function prevents the packet loss due to no IEEE802.3x. When the remote station does not support IEEE802.3x and has full duplex capability and Update_r4_en is When the remote station does not support IEEE802.3x and has full duplex capability and Update_r4_en is turned on, the port changes its ability to half duplex to make the remote station link at half duplex after Nway. IP178A handles the data flow of segment by Conditions REMOTE_IEEE UPDATE_ BK_EN Remote site 802.3X R4_E x x 0 half x x 1 half 1 0 x full/half 1 0 x full/half 0 0 x full/half 0 0 x full/half 1 1 x full/half 1 1 x full/half 0 1 x full/half 0 1 x full/half Result Remote site My site My My back 802.3x pressure half half off off half half off on full full on off full full off off full full off off full full off off full full on off half half off on half half off on half half off on turned off, the port turns off its IEEE802.3x capability and is link at full duplex after Nway. There is no flow control between these two nodes in this application. The detail operation is illustrated in the following table. backpressure. To do this, the port keeps silence to force the remote node link failure and changes its capability to half duplex then restarts Nway. Both side of the segment will be link at half duplex.
X_EN x x 1 0 1 0 1 0 1 0 Aging
My site X X full/half full/half full/half full/half full/half full/half full/half full/half
Broadcast Storm Protection IP178A is able to prevent receiving too many broadcast packets to waste the switch resource. IP178A discards the incoming broadcast packets depending on the setting of Bf_stm_en if the number of broadcast packets from a port exceeds threshold.
IP178A supports address aging. If the address aging is enabled (Agetime0), the learned SA will be cleared if it is not refreshed within the specified aging time.
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
Automatic MDI/MDI-X configuration IP178A supports MDI/MDI-X function if the function is enabled. The RX and TX pairs will be corrected automatically. That is, IP178A can be connected to another devices with either crossover cable or non-crossover cable. IP178A examines the specific bits of VLAN tag and TCP/IP TOS/DS for priority frames if the frame base priority is enabled. The packets will be handled as high priority frames if the value of VLAN tag or TCP/IP TOS/DS field meets the high priority requirement. It is enabled if pin Cos_en is pulled high or EEPROM register 02H[15] is set. The setting in register takes precedence When a cable is plugged, IP178A looks for NLP, FLP or MLT3 signals to make sure if the receive path is correct. If IP178A finds nothing in the receiving path, it crosses over the RX and TX pairs and examines the inputs again. The process will go on until IP178A sees a stable NLP, FLP or MLT3 signals. The process starts prior to the auto-negotiation. VLAN IP178A supports port base VLAN functions if the function is enabled. It separates IP178A into some groups (VLAN). A port is limited to communicate with the ports within the same group (VLAN). Frames will be limited in a VLAN and will not be forwarded to other VLANs. A port The MDI/MDI-X function needs specific type of transformer. The PCB for previous version of IP178A also supports MDI/MDI-X function if the specific type of transformer is adopted. The VLAN function can be enabled even if there is no CoS IP178A supports two type of CoS. One is port base priority function and the other is frame base priority function. A high priority packet will be queued to the high priority queue to guarantee its faster delivery. IP178A supports two levels of priority queues. EEPROM. IP178A supports an easy way to utilize VLAN function without EEPROM. A specific configuration of VLAN is adopted if pin VLAN_ON is pulled high. It is benefit in a router application that an individual LAN port shares a WAN port but doesn't communicate each other. The VLAN group in this mode is illustrated in the pin description of VLAN_ON. The packets received from port 6 or port7 are handled as high priority frames if the port base priority is enabled. It is enabled if pin p6_7_high is pulled high or the bit 02H[14] of EEPROM register is set. The setting in register takes precedence of the setting on pins. The VLAN function is enabled if pin VLAN_on is pulled high or filling the content of EEPROM register 07H~0AH. The setting in register takes precedence of the setting on pins. can be assigned to one or more VLANs. The members (ports) of a VALN are assigned by programming the content of EEPROM register 07H~0AH. of the setting on pins.
Preliminary, Specification subject to change without notice 21
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IP178A
MDI-MDIX
RX IP178A TX
1 2 RJ45 3 6
1 2 3 6
1 2 RJ45 3 6
1 2 3 6
TX LAN card RX
RX IP178A TX
1 2 RJ45 3 6
1 2 3 6
1 2 RJ45 3 6
1 2 3 6
RX Switch TX
IP178A works at MDI mode
RX IP178A TX
1 2 RJ45 3 6
1 2 3 6
1 2 RJ45 3 6
1 2 3 6
TX LAN card RX
RX IP178A TX
1 2 RJ45 3 6
1 2 3 6
1 2 RJ45 3 6
1 2 3 6
RX Switch TX
IP178A works at MDIX mode
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
CoS IP178A Pa ts from cke port6 or port to 7 port 1 port6, port7
High Prio rity Queue Packet with higher s forwardin priority g
Low Prio rity Queue
Packe from ts port to port1 4
Packet with lower s forwardin priority g port 1 port 2 port 3 port 4 port 5
port 0
The port base Cos operation
Prea mble
SF D
DATA
CRC
DA
SA
8100 priority VLAN tag
0800
TOS(type ofservice) IP pack et
The frame format of frame base Cos
IP178A Packets wit low h priority tag
port6, port7
Low Prio rity Queue
High Prio rity Queue Packets with hig her forward priorty ing i
Pa ts with high cke priority tag
Packet with lower s forwardin priority g port 0 port 1
port 2
port 3
port 4
port 5
The frame base Cos operation
Preliminary, Specification subject to change without notice 23
IP178A-DS-P05 Sep. 09, 2002
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IP178A
VLAN IP178A port 7
VLAN 1 VLAN 2
VLAN 3 VLAN 4
VLAN 5 VLAN 6 VLAN 7
port 0
port 1
port 2
port 3
port 4
port 5
port 6
The VALN group in IP178A when VLAN_ON pin is pulled high
port 0
VLAN 1
port 1
VLAN 2
port 2
VLAN 3
port 3
VLAN 4
port 4
VLAN 5
port 5
VLAN 6
port 6
port 7
Each port canbeassig ed n to mor than on VLANs. e e Portsca communicte n a with theone be longing to the same VL AN.
VLAN 7
VLAN 8
The VALN group in IP178A when VLAN registers are enabled
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
MII IP178A supports one MII. When the interface is active (MII_P0_EXT_EN=1), the Phyceiver of port0 is disabled and the switch core interfaces the MII directly. This make IP178A can behave like a Fast Ethernet Phyceiver on port 0. The major difference between the MII and IEEE standard MII are clock and RXER signals. There is only one clock and there is no RXER signal on the interface. For half duplex operation, MCOL is used as a collision during transmission. The following diagram illustrates the MII of IP178A.
MII_CLK
MII_TXCLK MII_RXDV
Switch engine
MII_RXD MII_TXEN MII_TXD
Port 0 PHYceiver (Disabled)
MTXEN MTXD MRXDV Port1 PHYceiver MRXD MCOL Port2 PHYceiver Port3 PHYceiver Port4 PHYceiver Port5 PHYceiver Port6 PHYceiver Port7 PHYceiver
IP178A works at 7TP + 1 MII mode
Preliminary, Specification subject to change without notice 25
IP178A-DS-P05 Sep. 09, 2002
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IP178A
LED Interface IP178A provides four kinds of LED information and two kinds of LED interfaces. The LED information is selected by LED_O_SEL[1:0] pins and the LED interface is selected by DIRECT_LED pin. When IP178A works at direct mode (DIRECT_LED pin pulled high), it drives 24 LED pins directly to provide link, speed and fdx LED. The operation of link, speed and fdx LED are defined by LED_O_SEL[1:0] pins. When IP178A works at scan mode (DIRECT_LED pin pulled low), it drives 12 LED control pins with scan Label PHASE0 PHASE1 PHASE2 PHASE3 LINK_A RX_A FDX_A SPEED_A LINK_B RX_B FDX_B SPEED_B State_1 1 0 0 0 Port0 link Port0 rx Port0 fdx Port0 speed Port4 link Port4 rx Port4 fdx Port4 speed mythology to provide link, speed, fdx and rx LED. The operation of link, speed, fdx and rx LED are defined by LED_O_SEL[1:0] pins. When IP178A works at scan mode, phase pins run periodically to generate state_1 to state_4. Link_a sends out the link status of port0 at state_1 and Link_b sends out the link status of port4 at state_1. IP178A supports rx, fdx and speed LED in the same way. The detail description and waveforms are shown in the following diagram. State_3 0 0 1 0 Port2 link Port2 rx Port2 fdx Port2 speed Port6 link Port6 rx Port6 fdx Port6 speed State_4 0 0 0 1 Port3 link Port3 rx Port3 fdx Port3 speed Port7 link Port7 rx Port7 fdx Port7 speed
State_2 0 1 0 0 Port1 link Port1 rx Port1 fdx Port1 speed Port5 link Port5 rx Port5 fdx Port5 speed
PHASE0 PHASE1 PHASE2
State_1 State_2 State_3 State_4
State_1 State_2 State_3 State_4
State_1
PHASE3
LINK_a
p0
p1
p2
p3
p0
p1
p2
p3
...
(SPEED_a, FDX_a)
LINK_b
p4
p5
p6
p7
p4
p5
p6
p7
...
(SPEED_b, FDX_b)
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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(Advance Version)
IP178A
Application circuit of link LED in scan mode
PHASE0 PHASE1 PHASE2 PHASE3 PHASE0 PHASE1 PHASE2 PHASE3
LINK_b LINK LED[7:4] LINK_a LINK LED[3:0]
Application circuit of link LED in direct mode
VCC
LINK LED[0] LINK LED[1] LINK LED[2] LINK LED[3] LINK LED[4] LINK LED[5] LINK LED[6] LINK LED[7]
Preliminary, Specification subject to change without notice 27
IP178A-DS-P05 Sep. 09, 2002
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IP178A
LED information
IP178A provides four types of LED function for link, rx, fdx, and speed. User can select the desired features by setting Led_o_sel[1:0]. The detail information is list in the LED_O_SEL [1:0] 00 LINK LED[7:0] On Off Flash On Off Flash On Off Flash On Off Flash 10M link ok 10M link fail ACT link ok link fail receive 10M link ok 10M link fail ACT link ok link fail rx/tx Flash Off Flash Off Flash Off Flash Off RX LED[7:0] collision idle rx/tx idle collision idle collision idle
following table. The default value is the same as the IP178A previous version. It is noted that Rx LED is supported in LED scan mode only. FDX LED[7:0] On Off On Off Flash On Off Flash On Off Flash full duplex half duplex full duplex half duplex collision full duplex half duplex collision full duplex half duplex collision SPEED LED[7:0] On Off Flash On Off On Off Flash On Off 100M link ok 100M link fail ACT 100M 10M 100M link ok 10M link fail ACT 100M 10M
01
10
11 (default)
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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(Advance Version)
IP178A
Power on Diagnostic of LED ( LED array = 8 x 4) (0) T = 0 sec
(8) T = 2.00 sec
(9) T = 2.25 sec
(1) T = 0.25 sec
(10) T = 2.50 sec
(2) T = 0.50 sec
(11) T = 2.75 sec
(3) T = 0.75 sec
(12) After T = 3.0 sec, LED becomes normal operation
(4) T = 1.00 sec
(5) T = 1.25 sec
Operation parameters setting IP178A supports two ways to modify its initial values of operation parameters to fit different applications. It read
(6) T = 1.50 sec
the initial value via pins or EPROM interface. The detail description of each pins and each bit in the EEPROM is illustrated in the next paragraph. Some settings are
(7) T = 1.75 sec
duplicated on pins. EEPROM setting takes precedence of resistor setting.
Preliminary, Specification subject to change without notice 29
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IP178A
Initial value set via pins To set the parameter via pins, connect them to VCC or ground through resistors. IP178A reads initial value via configuration pins during the period of reset. An initial value is set to 1 (0) by connecting a pin to VCC (GND) through a 10k (1k) resistor as shown on the following figure. IP178A begins to work after the internal PLL clock active. To make sure the proper operation of PLL, the duration of reset must be more than 1 ms. If there is no setting resistor, IP178A uses the default value. All fields in EEPROM corresponding to the registers of IP178A should be filled with correct value if an EEPROM is used. The initial value of IP178A will be replaced with
PAD PAD
EEPROM Interface During reset, the pins of EEPROM interface are input signals. At the end of reset, IP178A latches the setting on configuration pins and begins to read the content in the EEPROM. The data in EEPROM is valid only if there is a specific pattern 55AA found in the register 0. If there is no valid data in EEPROM, IP178A will keep the value read from resistors setting. After reading the EEPROM, the pins of EEPROM interface are input signals.
the content in EEPROM if it is valid. That is, the EEPROM takes precedence of the pin setting.
To set initial value = 1 To set initial value = 0
IP178A uses a 93C46 EEPROM device. The detail operation of reading EEPROM is illustrated in the following figure.
RESETB
internal system clcok
< 10us EEPROM pins are input EEPROM pins are active to read EEPROM After read EEPROM, EEPROM pins are input if MII port is not enabled.
Power on
Latch setting on pins
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
EEPROM Register Description Offset 00H[15:0] Default Value 55AA Corresponding Pin Description EEPROM enable register This register should be filled with 55AA. IP178A will examine the specified pattern to confirm if there is a valid EEPROM. The initial setting is updated with the content of EEPROM only if the specified pattern 55AA is found. Reserved LED_O_SEL, LED mode selection Bit1 Bit0 LINK a/b RX a/b 0 0 10 Link/act Col 0 1 Link/rt Act 1 0 10 Link/act Col 1 1 Link/act Col
LED output selection register 01H[15:2] 12'b0 01H[1:0] 11 LED_O_SEL[1:0]
FDX a/b Fdx Fdx/col Fdx/col Fdx/col
SPEED a/b 100 link/act Speed 100 link/act Speed
Switch control register 1 02H[15] 1'b0
COS_EN
02H[14]
1'b0
P6_7_HIGH
02H[13] 02H[12:11]
1'b0 00
BP_KIND[1:0]
02H[10] 02H[8] 02H[7] 02H[6:5] 02H[4]
0 0 1 2'b0 1
X_EN BK_EN
Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag are handled as high priority packets. It is enabled only if P6_7_high is disabled. Port6 port7 are set to be high priority port 1: enable, 0: disabled (default) Packets received from port6 or port7 are handled as high priority packets. Reserved Bp_kind, Backpressure type selection It is valid only if Bk_en (02H[4]) is set to 1'b1. 00: carrier base backpressure 01: (reserved) 10: (reserved) Reserved Reserved X_en, IEEE 802.3x flow control enable 1: enable, 0:disable Reserved Bk_en, Backpressure enable 1: enable, 0: disable
Preliminary, Specification subject to change without notice 31
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IP178A
EEPROM Register Description (continued) Offset 02H[3] 02H[2] Default Value 0 0 Corresponding Pin BF_STM_EN Description Reserved Bf_stm_en, Broadcast storm enable 1: enable IP178A drops the incoming packet if the number of broadcast packet in queue is over the threshold. 0: disable Reserved Reserved Duplex of external MII port 1: full (default), 0: half Speed of external MII port 1: 10M (default), 0: 100M Flow control of external MII port 1: on, 0: off (default) External MII port enable 1: enable, 0: disable (default) Reserved Drop16, A port will drop the transmitting packet after 16 consecutive collisions if this function is turned on. 1: drop, 0: not drop It is hashing algorithm selection for 1st layer and 2nd layer at the end of reset. 00: direct and CRC(default) 01: direct and CRC 10: CRC and CRC 11: reserved Agetime, Aging time of address table selection An address tag in hashing table will be removed if this function is turned on and its aging timer expires. 03H[4:3] Aging time note 00 no aging 01 120s 10 240s default 11 480s ALLPASS IP178A forwards all packets. It is for testing only. The default value must be adopted for normal operation. 1: turn on, 0: turn off MODBCK, Turn on modified back off algorithm The maximum back off period is limited to 8-slot time if this function is turned on. 1: turn on, 0: turn off Reserved 32
02H[1:0] 2'b0 Switch control register 2 03H[15:13] 3'b0 03H[12] 1 03H[11] 03H[10] 03H[9] 03H[8] 03H[7] 1 0 0 0 0
MII_P0_FULL MII_P0_SPEED MII_P0_FLOW_CTL MII_P0_EXT_EN DROP16
03H[6:5]
00
HASH_MODE[1:0]
03H[4:3]
10
AGETIME[1:0]
03H[2]
0
ALLPASS
03H[1]
1
MODBCK
03H[0]
0
-
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
(Advance Version)
IP178A
EEPROM Register Description (continued) Offset Default Value Corresponding Pin Description Transceiver control register 04H[15:14] 00 OP1[1:0] OP1 Bit[15:14] are corresponding to op1[1:0] The default value must be adopted for normal operation. OP0 and FORCE_MODE Bit[13:11] are corresponding to op0[1:0] and force_mode The default value must be adopted for normal operation. Summary 04H[15:11] OP1 [1:0] 00 10 11 x x x 1 1 OP0 [1:0] x x x 00 10 11 FORCE_ MODE 0 0 0 0 0 0 FEF_EN Description Port1, 3, 5, 7 nway with all capability, mode0 Port7 FX full duplex, port1, 3, 5 mode0 Port7 FX half duplex, port1, 3, 5 mode0 Port0, 2, 4, 6 nway with all capability, mode0 Port6 FX full duplex, port0, 2, 4 mode0 Port6 FX half duplex, port0, 2, 4 are mode0 Fef_en, Far end fault enable 1: enable, 0: disable Savepw_a_en, Save power mode for auto-negotiation 1: enable, 0: disable The default value must be adopted for normal operation. MDI/MDI-X enable 1: enable, 0:disable
04H[13:11]
000
OP0[1:0], FORCE_ MODE
04H[10] 04H[9]
SAVEPW_A_EN
04H[8] 04H[7:0]
0 8'b0
MDI_MDIX_EN
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IP178A
EEPROM Register Description (continued) Offset Default Value Corresponding Pin Description Transceiver verification register 05H[15:14] 2'b0 Reserved 05H[13] 0 This function is for testing only. The default value must be adopted for normal operation. 05H[12] 1 UPDATE_R4_EN Update_r4_en, Change capability enable A full duplex port will change its capability to half duplex, if the remote node works at full duplex and does not support IEEE802.3x and this function is enabled. 1: enable, 0: disable 05H[11] 0 This function is for testing only. The default value must be adopted for normal operation. 05H[10] 0 This function is for testing only. The default value must be adopted for normal operation. 05H[9] 0 This function is for testing only. The default value must be adopted for normal operation. 05H[8] 0 This function is for testing only. The default value must be adopted for normal operation. 05H[7:6] 00 This function is for testing only. The default value must be adopted for normal operation. 05H[5] 0 This function is for testing only. The default value must be adopted for normal operation. 05H[4] 0 This function is for testing only. The default value must be adopted for normal operation. 05H[3] 1 UTP_DET# Utpdet, UTP detect enable Fewer FLP will be sent out if cable is unplugged and the function is enabled. 1: disable, 0: enable The default value is suggested for normal operation. This function is for testing only. The default value must be adopted for normal operation. This function is for testing only. The default value must be adopted for normal operation. This function is for testing only. The default value must be adopted for normal operation. Reserved This function is for testing only. The default value must be adopted for normal operation. This function is for testing only. The default value must be adopted for normal operation.
05H[2] 05H[1] 05H[0]
0 0 0
-
Testing & verify mode register 06H[15:7] 9'b0 06H[6] 0 06H[5:0] 6'b0
-
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
EEPROM Register Description (continued) Offset Default Value Corresponding Pin VLAN register 1 07H[15:8] 8'hff Description Port1 VLAN look up table The register defines the ports in the same VLAN as port1. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port1 0: a port is not in the same VLAN as port1 Bit8=1, port 0 and port1 are in the same VLAN; Bit9, don't care; Bit10=1, port 2 and port1 are in the same VLAN; Bit11=1, port 3 and port1 are in the same VLAN; Bit12=1, port 4 and port1 are in the same VLAN; Bit13=1, port 5 and port1 are in the same VLAN; Bit14=1, port 6 and port1 are in the same VLAN; Bit15=1, port 7 and port1 are in the same VLAN; Port0 VLAN look up table The register defines the ports in the same VLAN as port0. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port0 0: a port is not in the same VLAN as port0 Bit0, don't care; Bit1=1, port 1 and port0 are in the same VLAN; Bit2=1, port 2 and port0 are in the same VLAN; Bit3=1, port 3 and port0 are in the same VLAN; Bit4=1, port 4 and port0 are in the same VLAN; Bit5=1, port 5 and port0 are in the same VLAN; Bit6=1, port 6 and port0 are in the same VLAN; Bit7=1, port 7 and port0 are in the same VLAN;
07H[7:0]
8'hff
-
Preliminary, Specification subject to change without notice 35
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IP178A
EEPROM Register Description (continued) Offset Default Value Corresponding Pin VLAN register 2 08H[15:8] 8'hff Description Port3 VLAN look up table The register defines the ports in the same VLAN as port3. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port3 0: a port is not in the same VLAN as port3 Bit8=1, port 0 and port3 are in the same VLAN; Bit9=1, port 1 and port3 are in the same VLAN; Bit10=1, port 2 and port3 are in the same VLAN; Bit11, don't care; Bit12=1, port 4 and port3 are in the same VLAN; Bit13=1, port 5 and port3 are in the same VLAN; Bit14=1, port 6 and port3 are in the same VLAN; Bit15=1, port 7 and port3 are in the same VLAN; Port2 VLAN look up table The register defines the ports in the same VLAN as port2. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port2 0: a port is not in the same VLAN as port2 Bit0=1, port 0 and port2 are in the same VLAN; Bit1=1, port 1 and port2 are in the same VLAN; Bit2, don't care; Bit3=1, port 3 and port2 are in the same VLAN; Bit4=1, port 4 and port2 are in the same VLAN; Bit5=1, port 5 and port2 are in the same VLAN; Bit6=1, port 6 and port2 are in the same VLAN; Bit7=1, port 7 and port2 are in the same VLAN;
08H[7:0]
8'hff
-
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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EEPROM Register Description (continued) Offset Default Value Corresponding Pin VLAN register 3 09H[15:8] 8'hff Description Port5 VLAN look up table The register defines the ports in the same VLAN as port5. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port5 0: a port is not in the same VLAN as port5 Bit8=1, port 0 and port5 are in the same VLAN; Bit9=1, port 1 and port5 are in the same VLAN; Bit10=1, port 2 and port5 are in the same VLAN; Bit11=1, port 3 and port5 are in the same VLAN; Bit12=1, port 4 and port5 are in the same VLAN; Bit13, don't care; Bit14=1, port 6 and port5 are in the same VLAN; Bit15=1, port 7 and port5 are in the same VLAN; Port4 VLAN look up table The register defines the ports in the same VLAN as port4. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port4 0: a port is not in the same VLAN as port4 Bit0=1, port 0 and port4 are in the same VLAN; Bit1=1, port 1 and port4 are in the same VLAN; Bit2=1, port 2 and port4 are in the same VLAN; Bit3=1, port 3 and port4 are in the same VLAN; Bit4, don't care; Bit5=1, port 5 and port4 are in the same VLAN; Bit6=1, port 6 and port4 are in the same VLAN; Bit7=1, port 7 and port4 are in the same VLAN;
09H[7:0]
8'hff
-
Preliminary, Specification subject to change without notice 37
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IP178A
EEPROM Register Description (continued) Offset Default Value Corresponding Pin VLAN register 4 0AH[15:8] 8'hff Description Port7 VLAN look up table The register defines the ports in the same VLAN as port7. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port7 0: a port is not in the same VLAN as port7 Bit8=1, port 0 and port7 are in the same VLAN; Bit9=1, port 1 and port7 are in the same VLAN; Bit10=1, port 2 and port7 are in the same VLAN; Bit11=1, port 3 and port7 are in the same VLAN; Bit12=1, port 4 and port7 are in the same VLAN; Bit13=1, port 5 and port7 are in the same VLAN; Bit14=1, port 6 and port7 are in the same VLAN; Bit15, don't care; Port6 VLAN look up table The register defines the ports in the same VLAN as port6. The bit 0~7 are corresponding to port 0~7. 1: a port is in the same VLAN as port6 0: a port is not in the same VLAN as port6 Bit0=1, port 0 and port6 are in the same VLAN; Bit1=1, port 1 and port6 are in the same VLAN; Bit2=1, port 2 and port6 are in the same VLAN; Bit3=1, port 3 and port6 are in the same VLAN; Bit4=1, port 4 and port6 are in the same VLAN; Bit5=1, port 5 and port6 are in the same VLAN; Bit6, don't care; Bit7=1, port 7 and port6 are in the same VLAN;
0AH[7:0]
8'hff
-
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
A summary of EEPROM registers and their corresponding pins Offset 00H[15:0] 01H[1:0] 02H[15] 02H[14] 02H[12:11] 02H[7] 02H[4] 02H[2] 03H[12] 03H[11] 03H[10] 03H[9] 03H[7] 03H[6:5] 03H[4:3] 03H[2] 03H[1] 04H[15] 04H[14] 04H[13] 04H[12] 04H[11] 04H[10] 04H[9] 04H[8] 04H[7:0] 05H[13] 05H[12] 05H[11] 05H[10] 05H[9] 05H[8] 05H[7:6] 05H[5] 05H[4] 05H[3] 05H[2] 05H[1] 05H[0] 06H[6] 06H[5] 06H[4] 06H[3] 06H[2] 06H[1] 06H[0]
IP178A-DS-P05 Sep. 09, 2002
Default 55AA 11 0 0 00 1 1 0 1 1 0 0 0 00 10 0 1 0 0 0 0 0 1 1 0 8'b0 0 1 0 0 0 0 00 0 0 1 0 0 0 0 0 0 0 0 0 0
Corresponding pin LED_O_SEL[1:0] COS_EN P6_7_HIGH BP_KIND[1:0] X_EN BK_EN BF_STM_EN MII_P0_FULL MII_P0_SPEED MII_P0_FLOW_CTL MII_P0_EXT_EN DROP16 HASH_MODE [1:0] AGETIME[1:0] -MODBCK OP1[1] OP1[0] OP0[1] OP0[0] FORCE_MODE FEF_EN SAVEPW_A_EN MDI_MDIX_EN UPDATE_R4_EN UTP_DET# -
Description
Register content PROM ENABLE LED_O_SEL COS_EN P6_7_HIGH BP_KIND X_EN BK_EN BF_STM_EN MII_P0_FULL MII_P0_SPEED MII_P0_FLOW_CTL MII_P0_EXT_EN DROP16 HASH_MODE[1:0] AGETIME ALLPASS MODBCK OP1[1] OP1[0] OP0[1] OP0[0] FORCE_ MODE FEF_EN SAVEPW_A_EN MDI_MDIX_EN UPDATE_R4_EN UTP_DET# -
Preliminary, Specification subject to change without notice 39
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IP178A
A summary of EEPROM registers and their corresponding pins (continued) Offset 07H[15:8] 07H[7:0] 08H[15:8] 08H[7:0] 09H[15:8] 09H[7:0] 0AH[15:8] 0AH[7:0] Default 8'hff 8'hff 8'hff 8'hff 8'hff 8'hff 8'hff 8'hff Corresponding pin Description Register content PORT1 VALN TABLE PORT0 VALN TABLE PORT3 VALN TABLE PORT2 VALN TABLE PORT5 VALN TABLE PORT4 VALN TABLE PORT7 VALN TABLE PORT6 VALN TABLE
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
AC Characteristic
Read EEPROM
EESK
tCS tSK
EECS
tDI
EEDI
1
1
0
A5
A4
A0 tOD
EEDO
0
D15
D14
D0
Parameter TSK TCS TDI TOD
Description Clock period Chip select delay Data input delay Output delay
Min
Typical 5.12
Max 2 2 2000
Units us ns ns ns
Preliminary, Specification subject to change without notice 41
IP178A-DS-P05 Sep. 09, 2002
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IP178A
Absolute Maximum Rating
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to GND. Supply Voltage Input Voltage Output Voltage Storage Temperature Ambient Operating Temperature (Ta) -0.3V to 4.0V -0.3V to 5.0V -0.3V to 5.0V -65C to 150C 0C to 70C
DC Characteristic
Operating Conditions Parameter Supply Voltage Power Consumption Sym. VCC2.5 TXVCC Min. 2.375 2.375 Typ. 2.5 2.5 2.9 2.75 1.55 Max. 2.625 2.625 Unit Conditions V V W All ports link at 10M/ full. W All ports link at 100M/ full. W Unlink situation
Input Clock Parameter Frequency Frequency Tolerance Sym. Min. -50 Typ. 25 Max. +50 Unit MHz PPM Conditions
I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High voltage Sym. VIL VIH VOL VOH Min. 2.0 0.4 2.4 Typ. Max. 0.8 Unit V V V V Conditions
IOH=4mA, VCC=3.3V IOL=4mA, VCC=3.3V
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
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IP178A
TX Transceiver Electrical Characteristics Parameter Peak Differential Output Voltage Signal Amplitude Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot Sym. VP TRF TRFS VO Min. 0.95 98 3 Typ. 1.0 100 4 Max. 1.05 102 5 0.5 0.5 5 Unit V % ns ns ns % Conditions
Order Information
Part No. IP178A PIN 208 PIN PQFP Notice -
Preliminary, Specification subject to change without notice 43
IP178A-DS-P05 Sep. 09, 2002
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IP178A
Package Detail QFP 208L Outline Dimensions
Unit: Inches/mm
Preliminary, Specification subject to change without notice IP178A-DS-P05 Sep. 09, 2002
44

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