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| R XA Spartan-3A Automotive FPGA Family Data Sheet Product Specification DS681 (v1.1) February 3, 2009 Summary The Xilinx Automotive (XA) Spartan(R)-3A family of FPGAs solves the design challenges in most high-volume, cost-sensitive, I/O-intensive automotive electronics applications. The four-member family offers densities ranging from 200,000 to 1.4 million system gates, as shown in Table 1. LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors Enhanced Double Data Rate (DDR) support DDR/DDR2 SDRAM support up to 266 Mb/s Fully compliant 32-/64-bit, 33 MHz PCITM technology support Densities up to 25,344 logic cells, including optional shift register or distributed RAM support Efficient wide multiplexers, wide logic Fast look-ahead carry logic Enhanced 18 x 18 multipliers with optional pipeline IEEE 1149.1/1532 JTAG programming/debug port Up to 576 Kbits of fast block RAM with byte write enables for processor applications Up to 176 Kbits of efficient distributed RAM Clock skew elimination (delay locked loop) Frequency synthesis, multiplication, division High-resolution phase shifting Wide frequency range (5 MHz to over 320 MHz) * Abundant, flexible logic resources Introduction XA devices are available in both extended-temperature Q-Grade (-40C to +125C TJ) and I-Grade (-40C to +100C TJ) and are qualified to the industry recognized AEC-Q100 standard. The XA Spartan-3A family builds on the success of the earlier XA Spartan-3E and XA Spartan-3 FPGA families by increasing the amount of I/O per logic, significantly reducing the cost per I/O. New features improve system performance and reduce the cost of configuration. These XA Spartan-3A family enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic industry. Because of their exceptionally low cost, XA Spartan-3A FPGAs are ideally suited to a wide range of automotive electronics applications, including infotainment, driver information, and driver assistance modules. The XA Spartan-3A family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial mask set costs and lengthy development cycles, while also permitting design upgrades in the field with no hardware replacement necessary because of its inherent programmability, an impossibility with conventional ASICs and ASSPs with their inflexible architecture. * Hierarchical SelectRAMTM memory architecture * Up to eight Digital Clock Managers (DCMs) * * Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing Configuration interface to industry-standard PROMs Low-cost, space-saving SPI serial Flash PROM x8 or x8/x16 parallel NOR Flash PROM Unique Device DNA identifier for design authentication * * * Complete Xilinx ISE(R) and WebPACKTM software support plus Spartan-3A Starter Kit MicroBlazeTM and PicoBlazeTM embedded processor cores BGA packaging, Pb-free ONLY Common footprints support easy density migration Features * * * * Very low cost, high-performance logic solution for high-volume, cost-conscious applications Dual-range VCCAUX supply simplifies 3.3V-only design Suspend, Hibernate modes reduce system power Multi-voltage, multi-standard SelectIOTM interface pins Up to 375 I/O pins or 165 differential signal pairs LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling Selectable output drive, up to 24 mA per pin QUIETIO standard reduces I/O switching noise Full 3.3V 10% compatibility and hot swap compliance 640+ Mb/s data transfer rate per differential I/O Refer to the Spartan-3A FPGA Family Data Sheet (DS529) for a full product description, AC and DC specifications, and package pinout descriptions. Any values shown specifically in this XA Spartan-3A Automotive FPGA Family data sheet override those shown in DS529. For information regarding reliability qualification, refer to RPT103 (Xilinx Spartan-3A Family Automotive Qualification Report) and RPT070 (Spartan-3A Commercial Qualification Report). (c) 2008-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 1 R Key Feature Differences from Commercial XC Devices * AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in both extended temperature I- and Q-Grades Guaranteed to meet full electrical specification over the TJ = -40C to +125C temperature range (Q-Grade) XA Spartan-3A devices are available in the -4 speed grade only * * * * * PCI-66 is not supported in the XA Spartan-3A FPGA product line Platform Flash is not supported within the XA family XA Spartan-3A devices are available in Pb-Free packaging only. MultiBoot is not supported in XA versions of this product. The XA Spartan-3A device must be power cycled prior to reconfiguration. * * Table 1: Summary of XA Spartan-3A FPGA Attributes CLB Array (One CLB = Four Slices) Device System Equivalent Gates Logic Cells Rows Columns Total CLBs Total Slices Distributed RAM bits(1) Block RAM bits(1) Maximum Dedicated Maximum Differential Multipliers DCMs User I/O I/O Pairs XA3S200A XA3S400A XA3S700A XA3S1400A 200K 400K 700K 1400K 4,032 8,064 13,248 25,344 32 40 48 72 16 24 32 40 448 1,792 896 3,584 1,472 5,888 2,816 11,264 28K 56K 92K 176K 288K 360K 360K 576K 16 20 20 32 4 4 8 8 195 311 372 375 90 142 165 165 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Architectural Overview The XA Spartan-3A family architecture consists of five fundamental programmable functional elements: * Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. * Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XA3S700A and XA3S1400A add two DCMs in the middle of the two columns of block RAM and multipliers. The XA Spartan-3A family features a rich network of routing that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. * * * 2 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R IOBs CLB Block RAM DCM IOBs OBs DCM CLBs IOBs DCM Block RAM / Multiplier IOBs Notes: 1. IOBs Multiplier DS312-1_01_032606 The XA3S700A and XA3S1400A have two additional DCMs on both the left and right sides as indicated by the dashed lines. Figure 1: XA Spartan-3A Family Architecture Configuration XA Spartan-3A FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data is stored externally in a SPI serial Flash or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: * Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash * * * * Byte Peripheral Interface (BPI) Up from an industry-standard x8 or x8/x16 parallel NOR Flash Slave Serial, typically downloaded from a processor Slave Parallel, typically downloaded from a processor Boundary Scan (JTAG), typically downloaded from a processor or system tester Additionally, each XA Spartan-3A FPGA contains a unique, factory-programmed Device DNA identifier useful for tracking purposes, anti-cloning designs, or IP protection. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 3 R I/O Capabilities The XA Spartan-3A FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Some of the user I/Os are unidirectional input-only pins as indicated in Table 2. XA Spartan-3A FPGAs support the following single-ended standards: * * * * 3.3V low-voltage TTL (LVTTL) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 3.3V PCI at 33 MHz HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications * SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications XA Spartan-3A FPGAs support the following differential standards: * * * * * LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or 3.3V Bus LVDS I/O at 2.5V TMDS I/O at 3.3V Differential HSTL and SSTL I/O LVPECL inputs at 2.5V or 3.3V Table 2: Available User I/Os and Differential (Diff) I/O Pairs Device XA3S200A XA3S400A XA3S700A XA3S1400A Notes: 1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs. FTG256 User 195 (35) 195 (35) - FGG400 User 311 (63) 311 (63) - FGG484 User 372 (84) 375 (87) Diff 90 (50) 90 (50) - Diff 142 (78) 142 (78) - Diff 165 (93) 165 (93) 4 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Production Status Table 3 indicates the production status of each XA Spartan-3A FPGA by temperature range and speed grade. The table also lists the earliest speed file version required for creating a production configuration bitstream. Later versions are also supported. Table 3: XA Spartan-3A FPGA Family Production Status (Production Speed File) Temperature Range Speed Grade XA3S200A I-Grade Standard (-4) Production (v1.41) Production (v1.41) Production (v1.41) Production (v1.41) Q-Grade Standard (-4) Production (v1.41) Production (v1.41) Production (v1.41) Production (v1.41) Part Number XA3S400A XA3S700A XA3S1400A Package Marking Figure 2 shows the top marking for Spartan-3A FPGAs in BGA packages. The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Mask Revision Code BGA Ball A1 Device Type Package R SPARTAN R Fabrication Code Process Code XA3S200ATM FTG256AGQ0625 D1234567A 4I Date Code Lot Code Speed Grade Temperature Range DS529-1_02_021206 Figure 2: XA Spartan-3A FPGA BGA Package Marking Example Ordering Information XA Spartan-3A FPGAs are available in Pb-free packaging only for all device/package combinations. Pb-Free Packaging Example: Device Type XA3S200A -4 FT G 256 I Temperature Range: Q - Grade (TJ = -40C to 125C) I - Grade (TJ = -40C to 100C) Number of Pins Pb-free DS529-1_04_012009 Speed Grade -4: Standard Performance Package Type DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 5 R Device XA3S200A XA3S400A XA3S700A XA3S1400A Speed Grade -4 Standard Performance FTG256 FGG400 FGG484 Package Type / Number of Pins Temperature Range ( TJ ) 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) I I-Grade (-40C to 100C) 400-ball Fine-Pitch Ball Grid Array (FBGA) 484-ball Fine-Pitch Ball Grid Array (FBGA) Q Q-Grade (-40C to 125C) Notes: 1. The XA Spartan-3A FPGA product line is available in -4 Speed Grade only. DC Electrical Characteristics Absolute Maximum Ratings All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the published parameter values apply to all XA Spartan-3A devices, and AC and DC characteristics are specified using the same numbers for both I-Grade and Q-Grade. Stresses beyond those listed under Table 4: Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. Table 4: Absolute Maximum Ratings Symbol VCCINT VCCAUX VCCO VREF VIN Description Internal supply voltage Auxiliary supply voltage Output driver supply voltage Input reference voltage Voltage applied to all User I/O pins and Dual-Purpose pins Voltage applied to all Dedicated pins Electrostatic Discharge Voltage VESD TJ TSTG Notes: 1. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages. Conditions Min -0.5 -0.5 -0.5 -0.5 Max 1.32 3.75 3.75 VCCO + 0.5 4.6 4.6 Units V V V V V V V V V C C Driver in a high-impedance state -0.95 -0.5 Human body model Charged device model Machine model - - - - -65 2000 500 200 125 150 Junction temperature Storage temperature 6 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Power Supply Specifications Table 5: Supply Voltage Thresholds for Power-On Reset Symbol VCCINTT VCCAUXT VCCO2T Notes: 1. 2. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA's configuration source (SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more information). To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Description Threshold for the VCCINT supply Threshold for the VCCAUX supply Threshold for the VCCO Bank 2 supply Min 0.4 0.8 0.8 Max 1.0 2.0 2.0 Units V V V Table 6: Supply Voltage Ramp Rate Symbol VCCINTR VCCAUXR VCCO2R Notes: 1. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA's configuration source (SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more information). To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Description Ramp rate from GND to valid VCCINT supply level Ramp rate from GND to valid VCCAUX supply level Ramp rate from GND to valid VCCO Bank 2 supply level Min 0.2 0.2 0.2 Max 100 100 100 Units ms ms ms 2. Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data Symbol VDRINT VDRAUX Description VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data Min 1.0 2.0 Units V V DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 7 R General Recommended Operating Conditions Table 8: General Recommended Operating Conditions Symbol TJ VCCINT VCCO (1) VCCAUX VIN Junction temperature Description I-Grade Q-Grade Internal supply voltage Output driver supply voltage Auxiliary supply voltage Input voltage(2) VCCAUX = 2.5 VCCAUX = 3.3 I/O, Input-only and Dual-purpose pins Dedicated pins TIN Notes: 1. 2. 3. This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCO range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards. See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins." Measured between 10% and 90% VCCO. Min -40 -40 1.140 1.100 2.250 3.000 -0.5 -0.5 - Nominal - - 1.200 - 2.500 3.300 - - - Max 100 125 1.260 3.600 2.750 3.600 VCCO+0.5 VCCAUX+0.5 500 Units C C V V V V V V ns Input signal transition time(3) 8 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R General DC Characteristics for I/O Pins Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol IL Description Leakage current at User I/O, Input-only, Dual-Purpose, and Dedicated pins, FPGA powered Leakage current on pins during hot socketing, FPGA unpowered Test Conditions Driver is in a high-impedance state, VIN = 0V or VCCO max, sample-tested All pins except INIT_B, PROG_B, DONE, and JTAG pins when PUDC_B = 1. INIT_B, PROG_B, DONE, and JTAG pins or other pins when PUDC_B = 0. IRPU(2) Current through pull-up resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins. Dedicated pins are powered by VCCAUX. VIN = GND VCCO or VCCAUX = 3.0V to 3.6V VCCO or VCCAUX = 2.3V to 2.7V VCCO = 1.7V to 1.9V VCCO = 1.4V to 1.6V VCCO = 1.14V to 1.26V RPU (2) Min -10 Typ - Max +10 Units A IHS -10 - +10 A A A A A A A k k k k k A A k k k k k k k k k k A pF Add IHS + IRPU -151 -82 -36 -22 -11 5.1 6.2 8.4 10.8 15.3 167 100 5.5 4.1 3.0 2.7 2.4 7.9 5.9 4.2 3.6 3.0 -10 3 -315 -182 -88 -56 -31 11.4 14.8 21.6 28.4 41.1 346 225 10.4 7.8 5.7 5.1 4.5 16.0 12.0 8.5 7.2 6.0 - - 100 -710 -437 -226 -148 -83 23.9 33.1 52.6 74.0 119.4 659 457 20.8 15.7 11.1 9.6 8.1 35.0 26.3 18.6 15.7 12.5 +10 10 115 Equivalent pull-up resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPU per Note 2) VIN = GND VCCO = 3.0V to 3.6V VCCO = 2.3V to 2.7V VCCO = 1.7V to 1.9V VCCO = 1.4V to 1.6V VCCO = 1.14V to 1.26V IRPD (2) Current through pull-down resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins Equivalent pull-down resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPD per Note 2) VIN = VCCO VCCAUX = 3.0V to 3.6V VCCAUX = 2.25V to 2.75V RPD(2) VCCAUX = 3.0V to 3.6V VIN = 3.0V to 3.6V VIN = 2.3V to 2.7V VIN = 1.7V to 1.9V VIN = 1.4V to 1.6V VIN = 1.14V to 1.26V VCCAUX = 2.25V to 2.75V VIN = 3.0V to 3.6V VIN = 2.3V to 2.7V VIN = 1.7V to 1.9V VIN = 1.4V to 1.6V VIN = 1.14V to 1.26V IREF CIN RDT VREF current per pin Input capacitance Resistance of optional differential termination circuit within a differential I/O pair. Not available on Input-only pairs. All VCCO levels - VCCO = 3.3V 10% LVDS_33, MINI_LVDS_33, RSDS_33 LVDS_25, MINI_LVDS_25, RSDS_25 90 VCCO = 2.5V 10% 90 110 - Notes: 1. 2. The numbers in this table are based on the conditions set forth in Table 8. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 9 R Quiescent Current Requirements Table 10: Quiescent Supply Current Characteristics Symbol ICCINTQ Description Quiescent VCCINT supply current Device XA3S200A XA3S400A XA3S700A XA3S1400A ICCOQ Quiescent VCCO supply current XA3S200A XA3S400A XA3S700A XA3S1400A ICCAUXQ Quiescent VCCAUX supply current XA3S200A XA3S400A XA3S700A XA3S1400A Notes: 1. 2. The numbers in this table are based on the conditions set forth in Table 8. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices at ambient room temperature (TA of 25C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a "blank" configuration data file (that is, a design with no functional elements instantiated). For conditions other than those described above (for example, a design including functional elements), measured quiescent current levels will be different than the values in the table. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A FPGA XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode typically saves 40% total power consumption compared to quiescent current. Typical(2) 7 10 13 24 0.2 0.3 0.3 0.3 5 5 6 10 I-Grade Maximum(2) 70 125 185 310 3 4 4 4 15 24 34 58 Q-Grade Maximum(2) 110 230 330 580 4 5 5 5 20 40 60 95 Units mA mA mA mA mA mA mA mA mA mA mA mA 3. 4. 5. 10 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Single-Ended I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards IOSTANDARD Attribute LVTTL LVCMOS33(4) LVCMOS25(4,5) LVCMOS18(4) LVCMOS15(4) LVCMOS12(4) PCI33_3(6) HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II Notes: 1. Descriptions of the symbols used in this table are as follows: VCCO - the supply voltage for output drivers VREF - the reference voltage for setting the input switching threshold VIL - the input voltage that indicates a Low logic level VIH - the input voltage that indicates a High logic level In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when VCCAUX = 3.3V range and for PCI I/O standards. For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 8. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS25 or LVCMOS33 standard depending on VCCAUX. The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration. For information on PCI IP solutions, see http://www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCI IOSTANDARD is not supported on input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics, but no PCI-X IP is supported. VCCO for Drivers(2) Min (V) 3.0 3.0 2.3 1.65 1.4 1.1 3.0 1.4 1.4 1.7 1.7 1.7 1.7 1.7 2.3 2.3 3.0 3.0 Nom (V) 3.3 3.3 2.5 1.8 1.5 1.2 3.3 1.5 1.5 1.8 1.8 1.8 1.8 1.8 2.5 2.5 3.3 3.3 Max (V) 3.6 3.6 2.7 1.95 1.6 1.3 3.6 1.6 1.6 1.9 1.9 1.9 1.9 1.9 2.7 2.7 3.6 3.6 0.68 - 0.8 - - 0.833 0.833 1.15 1.15 1.3 1.3 Min (V) VREF Nom (V) Max (V) VIL Max (V) 0.8 0.8 0.7 VIH Min (V) 2.0 2.0 1.7 0.8 0.8 0.7 0.5 * VCCO VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.125 VREF + 0.125 VREF + 0.150 VREF + 0.150 VREF + 0.2 VREF + 0.2 VREF is not used for these I/O standards 0.4 0.4 0.4 0.3 * VCCO 0.75 0.9 0.9 0.9 1.1 0.900 0.900 1.25 1.25 1.5 1.5 0.9 1.1 - - 0.969 0.969 1.38 1.38 1.7 1.7 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.125 VREF - 0.125 VREF - 0.150 VREF - 0.150 VREF - 0.2 VREF - 0.2 2. 3. 4. 5. 6. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 11 R Table 12: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOSTANDARD Attribute LVTTL(3) 2 4 6 8 12 16 24 LVCMOS33(3) 2 4 6 8 12 16 24(4) LVCMOS25(3) 2 4 6 8 12 16(4) 24(4) LVCMOS18(3) 2 4 6 8 12(4) 16(4) LVCMOS15(3) 2 4 6 8(4) 12(4) LVCMOS12(3) 2 4(4) 6(4) IOL (mA) 2 4 6 8 12 16 24(7) 2 4 6 8 12 16 24 2 4 6 8 12 16 24(7) 2 4 6 8 12 16 2 4 6 8 12 2 4 6 IOH (mA) -2 -4 -6 -8 -12 -16 -24 -2 -4 -6 -8 -12 -16(7) -24(7) -2 -4 -6 -8 -12 -16(7) -24(7) -2 -4 -6(7) -8 -12(7) -16 -2 -4 -6 -8 -12 -2 -4 -6 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.4 VCCO - 0.4 Logic Level Characteristics VOL Max (V) 0.4 VOH Min (V) 2.4 Table 12: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Test Conditions IOSTANDARD Attribute PCI33_3(5) HSTL_I(4) HSTL_III(4) HSTL_I_18 HSTL_II_18(4) HSTL_III_18 SSTL18_I SSTL18_II(4) SSTL2_I SSTL2_II(4) SSTL3_I SSTL3_II Notes: 1. 2. The numbers in this table are based on the conditions set forth in Table 8 and Table 11. Descriptions of the symbols used in this table are as follows: IOL - the output current condition under which VOL is tested IOH - the output current condition under which VOH is tested VOL - the output voltage that indicates a Low logic level VOH - the output voltage that indicates a High logic level VIL - the input voltage that indicates a Low logic level VIH - the input voltage that indicates a High logic level VCCO - the supply voltage for output drivers VREF - the reference voltage for setting the input switching threshold VTT - the voltage applied to a resistor termination Logic Level Characteristics VOL Max (V) 10% VCCO 0.4 0.4 0.4 0.4 0.4 VOH Min (V) 90% VCCO VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 IOL (mA) 1.5 8 24(6) 8 16 24(6) 6.7 13.4 8.1 16.2 8 16 IOH (mA) -0.5 -8 -8 -8 -16(6) -8 -6.7 VTT - 0.475 VTT + 0.475 -13.4 VTT - 0.475 VTT + 0.475 -8.1 -16.2 -8 -16 VTT - 0.61 VTT - 0.80 VTT - 0.6 VTT - 0.8 VTT + 0.61 VTT + 0.80 VTT + 0.6 VTT + 0.8 3. 4. 5. 6. 7. For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see http://www.xilinx.com/products/design_resources/conn_central/ protocols/pci_pcix.htm. The PCI IOSTANDARD is not supported on input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics, but no PCI-X IP is supported. DE-RATE by 5% for TJ above 100oC DE-RATE by 20% for TJ above 100oC 12 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Differential I/O Standards Differential Input Pairs VINP Internal Logic VINN P N Differential I/O Pair Pins VINN VINP GND level 50% VICM VID VICM = Input common mode voltage = VINP + VINN 2 DS529-3_10_012907 VID = Differential input voltage = VINP - VINN Figure 3: Differential Input Voltages Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards IOSTANDARD Attribute LVDS_25(3) LVDS_33(3) BLVDS_25(4) MINI_LVDS_25(3) MINI_LVDS_33(3) LVPECL_25(5) LVPECL_33(5) RSDS_25(3) RSDS_33(3) TMDS_33(3, 4, 7) PPDS_25(3) PPDS_33(3) DIFF_HSTL_I_18 DIFF_HSTL_II_18(8) DIFF_HSTL_III_18 DIFF_HSTL_I DIFF_HSTL_III DIFF_SSTL18_I DIFF_SSTL18_II(8) DIFF_SSTL2_I DIFF_SSTL2_II(8) DIFF_SSTL3_I DIFF_SSTL3_II 2.25 3.0 3.14 2.25 3.0 1.7 1.7 1.7 1.4 1.4 1.7 1.7 2.3 2.3 3.0 3.0 VCCO for Drivers(1) Min (V) Nom (V) Max (V) 2.25 3.0 2.25 2.25 3.0 2.5 3.3 2.5 2.5 3.3 Inputs Only Inputs Only 2.5 3.3 3.3 2.5 3.3 1.8 1.8 1.8 1.5 1.5 1.8 1.8 2.5 2.5 3.3 3.3 2.75 3.6 3.47 2.75 3.6 1.9 1.9 1.9 1.6 1.6 1.9 1.9 2.7 2.7 3.6 3.6 2.75 3.6 2.75 2.75 3.6 VID Min (mV) Nom (mV) Max (mV) 100 100 100 200 200 100 100 100 100 150 100 100 100 100 100 100 100 100 100 100 100 100 100 350 350 300 - - 800 800 200 200 - - - - - - - - - - - - - - 600 600 - 600 600 1000 1000 - - 1200 400 400 - - - - - - - - - - - Min (V) 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 2.7 0.2 0.2 0.8 0.8 0.8 0.68 - 0.7 0.7 1.0 1.0 1.1 1.1 VICM(2) Nom (V) 1.25 1.25 1.3 1.2 1.2 1.2 1.2 1.2 1.2 - - - - - - 0.9 - - - - - - Max (V) 2.35 2.35 2.35 1.95 1.95 1.95 2.8(6) 1.5 1.5 3.23 2.3 2.3 1.1 1.1 1.1 0.9 - 1.1 1.1 1.5 1.5 1.9 1.9 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. The VCCO rails supply only differential output drivers, not input circuits. VICM must be less than VCCAUX. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331. See "External Termination Requirements for Differential I/O," page 15. LVPECL is supported on inputs only, not outputs. Requires VCCAUX = 3.3V 10%. LVPECL_33 maximum VICM = VCCAUX - (VID / 2) Requires VCCAUX = 3.3V 10% for inputs. (VCCAUX - 300 mV) VICM (VCCAUX - 37 mV) These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331. VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in Table 11. Other differential standards do not use VREF. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 13 R Differential Output Pairs VOUTP Internal Logic VOUTN P N Differential I/O Pair Pins VOUTN VOUTP GND level 50% VOH VOD VOCM VOL VOCM = Output common mode voltage = VOUTP + VOUTN 2 VOD = Output differential voltage = VOUTP - VOUTN VOH = Output voltage indicating a High logic level VOL = Output voltage indicating a Low logic levelDS529-3_11_012907 Figure 4: Differential Output Voltages Table 14: DC Characteristics of User I/Os Using Differential Signal Standards VOD IOSTANDARD Attribute LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_HSTL_I DIFF_HSTL_III DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL3_I DIFF_SSTL3_II Min (mV) 247 247 240 300 300 100 100 400 100 100 - - - - - VOCM Max (mV) Min (V) 454 1.125 454 1.125 460 - 600 1.0 600 1.0 400 1.0 400 1.0 800 VCCO - 0.405 400 0.5 400 0.5 - - - - - - - - - - VOH Max (V) 1.375 1.375 - 1.4 1.4 1.4 1.4 VCCO - 0.190 1.4 1.4 - - - - - VOL Max (V) - - - - - - - - - - 0.4 0.4 0.4 0.4 0.4 VTT - 0.475 VTT - 0.475 VTT - 0.61 VTT - 0.81 VTT - 0.6 VTT - 0.8 Typ (mV) 350 350 350 - - - - - - - - - - - - Typ (V) - - 1.30 - - - - - 0.8 0.8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Min (V) - - - - - - - - - - VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VTT + 0.475 VTT + 0.475 VTT + 0.61 VTT + 0.81 VTT + 0.6 VTT + 0.8 Notes: 1. The numbers in this table are based on the conditions set forth in Table 8 and Table 13. 2. See "External Termination Requirements for Differential I/O," page 15. 3. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100 across the N and P pins of the differential signal pair. 4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V 14 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards Bank 0 and 2 Bank 0 Bank 3 Any Bank Bank 0 Bank 1 Bank 2 1/4 th of Bourns Part Number Z0 = 50 CAT16-PT4F4 No VCCO Restrictions LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33, PPDS_25 Bank 2 VCCO = 3.3V LVDS_33, MINI_LVDS_33, RSDS_33, PPDS_33 VCCO = 2.5V LVDS_25, MINI_LVDS_25, RSDS_25, PPDS_25 Z0 = 50 100 DIFF_TERM=No a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint Z0 = 50 VCCO = 3.3V LVDS_33, MINI_LVDS_33, RSDS_33, PPDS_33 VCCO = 3.3V LVDS_33, MINI_LVDS_33, RSDS_33, PPDS_33 VCCO = 2.5V LVDS_25, MINI_LVDS_25, RSDS_25, PPDS_25 VCCO = 2.5V LVDS_25, MINI_LVDS_25, RSDS_25, PPDS_25 Z0 = 50 RDT DIFF_TERM=Yes b) Differential pairs using DIFF_TERM=Yes constraint DS529-3_09_020107 Figure 5: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards BLVDS_25 I/O Standard Any Bank Bank 0 Any Bank Bank 0 Bank 2 1/4 th of Bourns Part Number CAT16-LV4F12 Bank 1 Bank 1 Bank 3 1/4 th of Bourns Part Number CAT16-PT4F4 Bank 3 Bank 2 VCCO = 2.5V 165 140 165 Z0 = 50 100 No VCCO Requirement BLVDS_25 BLVDS_25 Z0 = 50 DS529-3_07_020107 Figure 6: External Termination Resistors for BLVDS_25 I/O Standard TMDS_33 I/O Standard Bank 0 and 2 Bank 0 Any Bank Bank 0 Bank 1 3.3V Bank 2 Bank 3 50 50 Bank 2 VCCO = 3.3V VCCAUX = 3.3V TMDS_33 TMDS_33 DVI/HDMI cable DS529-3_08_020107 Figure 7: External Input Resistors Required for TMDS_33 I/O Standard DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 15 R Device DNA Data Retention, Read Endurance Table 15: Device DNA Identifier Memory Characteristics Symbol DNA_CYCLES Description Number of READ operations or JTAG ISC_DNA read operations. Unaffected by HOLD or SHIFT operations. Minimum 30,000,000 Units Read cycles Switching Characteristics All XA Spartan-3A FPGAs ship in the -4 speed grade. Switching characteristics in this document are designated as Production as shown in Table 16. Production: These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. To create a Xilinx MySupport user account and sign up for automatic E-mail notification whenever this data sheet is updated: * Sign Up for Alerts on Xilinx MySupport http://www.xilinx.com/support/answers/19380.htm Software Version Requirements Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status. FPGA designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a production-quality system. Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates. All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the published parameter values apply to all XA Spartan-3A devices, and AC and DC characteristics are specified using the same numbers for both I-Grade and Q-Grade. Timing parameters and their representative values are selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The XA Spartan-3A FPGA speed files (v1.41), part of the Xilinx Development Software, are the original source for many but not all of the values. The speed grade designations for these files are shown in Table 16. For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. Table 16: XA Spartan-3A FPGA v1.41 Speed Grade Designations Device XA3S200A XA3S400A XA3S700A XA3S1400A Production -4 -4 -4 -4 Table 17 provides the recent history of the XA Spartan-3A FPGA speed files. Table 17: XA Spartan-3A FPGA Speed File Version History Version 1.39 1.40 1.41 ISE Release 10.1.01i 10.1.02i 10.1.03i Description Initial release. Updated input timing adjustments. Updated output timing adjustments. 16 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R I/O Timing Pin-to-Pin Clock-to-Output Times Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path Speed Grade -4 Symbol Description Conditions LVCMOS25(2), 12mA output drive, Fast slew rate, with DCM(3) Device Max Units Clock-to-Output Times TICKOFDCM When reading from the Output Flip-Flop (OFF), the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is in use. XA3S200A XA3S400A XA3S700A XA3S1400A 3.27 3.33 3.50 3.99 5.24 5.12 5.34 5.69 ns ns ns ns ns ns ns ns TICKOF When reading from OFF, the time from the LVCMOS25(2), 12mA active transition on the Global Clock pin to output drive, Fast slew data appearing at the Output pin. The DCM is rate, without DCM not in use. XA3S200A XA3S400A XA3S700A XA3S1400A Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8 and Table 11. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Table 22. If the latter is true, add the appropriate Output adjustment from Table 25. DCM output jitter is included in all measurements. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 17 R Pin-to-Pin Setup and Hold Times Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous) Speed Grade -4 Symbol Setup Times TPSDCM When writing to the Input Flip-Flop (IFF), the time from the setup of data at the Input pin to the active transition at a Global Clock pin. The DCM is in use. No Input Delay is programmed. When writing to IFF, the time from the setup of data at the Input pin to an active transition at the Global Clock pin. The DCM is not in use. The Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = 0, with DCM(4) XA3S200A XA3S400A XA3S700A XA3S1400A LVCMOS25(2), IFD_DELAY_VALUE = 5, without DCM XA3S200A XA3S400A XA3S700A XA3S1400A Hold Times TPHDCM When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is in use. No Input Delay is programmed. When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is not in use. The Input Delay is programmed. LVCMOS25(3), IFD_DELAY_VALUE = 0, with DCM(4) XA3S200A XA3S400A XA3S700A XA3S1400A LVCMOS25(3), IFD_DELAY_VALUE = 5, without DCM XA3S200A XA3S400A XA3S700A XA3S1400A -0.52 -0.29 -0.12 0.00 -0.56 -0.42 -0.75 -0.69 ns ns ns ns ns ns ns ns 2.84 2.68 2.57 2.17 2.76 2.60 2.63 2.41 ns ns ns ns ns ns ns ns Description Conditions Device Min Units TPSFD TPHFD Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8 and Table 11. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the appropriate Input adjustment from the same table. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock's active edge. DCM output jitter is included in all measurements. 4. 18 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Input Setup and Hold Times Table 20: Setup and Hold Times for the IOB Input Path Speed Grade Symbol Setup Times TIOPICK Description Conditions IFD_ DELAY_ VALUE -4 Device Min Units Time from the setup of data at the Input pin LVCMOS25(2) to the active transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed. 0 XA3S200A XA3S400A XA3S700A XA3S1400A 1.81 1.51 1.51 1.74 2.20 2.93 3.78 4.37 4.20 5.23 6.11 6.71 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TIOPICKD Time from the setup of data at the Input pin LVCMOS25(2) to the active transition at the ICLK input of the Input Flip-Flop (IFF). The Input Delay is programmed. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 XA3S200A XA3S400A 2.02 2.67 3.43 3.96 3.95 4.81 5.66 6.19 XA3S700A 1.95 2.83 3.72 4.31 4.14 5.19 6.10 6.73 XA3S1400A 2.17 2.92 3.76 4.32 4.19 5.09 5.98 6.57 DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 19 R Table 20: Setup and Hold Times for the IOB Input Path (Continued) Speed Grade Symbol Hold Times TIOICKP Description Conditions LVCMOS25(2) IFD_ DELAY_ VALUE -4 Device Min Units Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. No Input Delay is programmed. 0 XA3S200A XA3S400A XA3S700A XA3S1400A -0.65 -0.42 -0.67 -0.71 -1.51 -2.09 -2.40 -2.68 -2.56 -2.99 -3.29 -3.61 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TIOICKPD Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. The Input Delay is programmed. LVCMOS25(2) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 XA3S200A XA3S400A -1.12 -1.70 -2.08 -2.38 -2.23 -2.69 -3.08 -3.35 XA3S700A -1.67 -2.27 -2.59 -2.92 -2.89 -3.22 -3.52 -3.81 XA3S1400A -1.60 -2.06 -2.46 -2.86 -2.88 -3.24 -3.55 -3.89 20 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Table 20: Setup and Hold Times for the IOB Input Path (Continued) Speed Grade Symbol Set/Reset Pulse Width TRPW_IOB Notes: 1. 2. 3. Description Conditions IFD_ DELAY_ VALUE -4 Device Min Units Minimum pulse width to SR control input on IOB All 1.61 ns The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8 and Table 11. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Table 22. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock's active edge. Input Propagation Times Table 21: Propagation Times for the IOB Input Path Speed Grade Symbol Description The time it takes for data to travel from the Input pin through the IFF latch to the I output with no input delay programmed Conditions LVCMOS25(2) IFD_ DELAY_ VALUE 0 -4 Device XA3S200A XA3S400A XA3S700A XA3S1400A Max 2.04 1.74 1.74 1.97 Units ns ns ns ns Propagation Times TIOPLI DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 21 R Table 21: Propagation Times for the IOB Input Path (Continued) Speed Grade Symbol TIOPLID Description The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed Conditions LVCMOS25(2) IFD_ DELAY_ VALUE 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 -4 Device XA3S200A Max 2.43 3.16 4.01 4.60 4.43 5.46 6.33 6.94 XA3S400A 2.25 2.90 3.66 4.19 4.18 5.03 5.88 6.42 XA3S700A 2.18 3.06 3.95 4.54 4.37 5.42 6.33 6.96 XA3S1400A 2.40 3.15 3.99 4.55 4.42 5.32 6.21 6.80 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8 and Table 11. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Table 22. 22 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Input Timing Adjustments Table 22: Input Timing Adjustments by IOSTANDARD Add the Adjustment Below Speed Grade -4 0.62 0.54 0 0.83 0.60 0.31 0.45 0.72 0.85 0.69 0.83 0.79 0.71 0.71 0.71 0.71 0.78 0.78 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 22: Input Timing Adjustments by Add the Adjustment Below Speed Grade -4 0.79 0.79 0.79 0.84 0.84 0.80 0.80 0.83 0.83 0.80 0.81 0.81 0.80 0.98 1.05 0.77 1.05 0.76 0.76 0.77 0.77 1.06 1.06 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_HSTL_I DIFF_HSTL_III DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL3_I DIFF_SSTL3_II Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8, Table 11, and Table 13. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 23 R Output Propagation Times Table 23: Timing for the IOB Output Path Speed Grade -4 Symbol Description Conditions Device Max Units Clock-to-Output Times TIOCKP When reading from the Output Flip-Flop LVCMOS25(2), 12 mA output (OFF), the time from the active transition at drive, Fast slew rate the OCLK input to data appearing at the Output pin LVCMOS25(2), 12 mA output drive, Fast slew rate LVCMOS25(2), 12 mA output drive, Fast slew rate All 3.13 ns Propagation Times TIOOP The time it takes for data to travel from the IOB's O input to the Output pin All 2.91 ns Set/Reset Times TIOSRP TIOGSRQ Time from asserting the OFF's SR input to setting/resetting data at the Output pin Time from asserting the Global Set Reset (GSR) input on the STARTUP_SPARTAN3A primitive to setting/resetting data at the Output pin All 3.89 9.65 ns ns Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8 and Table 11. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table 25. 24 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Three-State Output Propagation Times Table 24: Timing for the IOB Three-State Path Speed Grade -4 Symbol Description Conditions Device Max Units Synchronous Output Enable/Disable Times TIOCKHZ TIOCKON(2) Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state Time from the active transition at TFF's OTCLK input to when the Output pin drives valid data LVCMOS25, 12 mA output drive, Fast slew rate All 0.76 ns All 3.06 ns Asynchronous Output Enable/Disable Times TGTS Time from asserting the Global Three State (GTS) input on the STARTUP_SPARTAN3A primitive to when the Output pin enters the high-impedance state LVCMOS25, 12 mA output drive, Fast slew rate All 10.36 ns Set/Reset Times TIOSRHZ TIOSRON(2) Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8 and Table 11. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table 25. Time from asserting TFF's SR input to when the Output pin enters a high-impedance state Time from asserting TFF's SR input at TFF to when the Output pin drives valid data LVCMOS25, 12 mA output drive, Fast slew rate All All 1.86 3.82 ns ns DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 25 R Output Timing Adjustments Table 25: Output Timing Adjustments for IOB Add the Adjustment Below Speed Grade -4 5.58 3.45 3.45 2.26 1.66 1.29 2.97 3.37 2.27 2.27 0.63 0.61 0.59 0.60 27.67 27.67 27.67 16.71 16.67 16.22 12.11 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns QuietIO Fast Table 25: Output Timing Adjustments for IOB (Continued) Add the Adjustment Below Speed Grade -4 5.58 3.30 3.30 2.26 1.29 1.22 2.79 3.72 2.05 2.08 0.53 0.59 0.59 0.51 27.67 27.67 27.67 16.71 16.29 16.18 12.11 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA QuietIO 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS33 Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 26 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Table 25: Output Timing Adjustments for IOB (Continued) Add the Adjustment Below Speed Grade -4 5.33 2.91 2.92 1.23 1.23 0.91 2.31 4.71 2.20 1.49 0.39 0 0.01 0.01 25.92 25.92 25.92 15.57 15.59 14.27 11.37 5.00 3.69 2.91 2.03 1.57 1.19 4.12 2.63 1.91 1.06 0.83 0.63 24.97 24.97 24.08 16.43 14.52 13.41 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 25: Output Timing Adjustments for IOB (Continued) Add the Adjustment Below Speed Grade -4 6.42 3.97 3.21 2.53 2.06 5.83 3.05 1.95 1.60 1.30 34.11 25.66 24.64 22.06 20.64 7.14 4.87 5.67 6.77 5.02 4.09 50.76 43.17 37.31 0.34 0.86 1.16 0.35 0.30 0.47 0.40 0.30 0 -0.05 Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS25 Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA QuietIO 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS18 Slow 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA QuietIO 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS15 Slow 2 mA 4 mA 6 mA 8 mA 12 mA Fast 2 mA 4 mA 6 mA 8 mA 12 mA QuietIO 2 mA 4 mA 6 mA 8 mA 12 mA LVCMOS12 Slow 2 mA 4 mA 6 mA Fast 2 mA 4 mA 6 mA QuietIO 2 mA 4 mA 6 mA PCI33_3 HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 0.17 DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 27 R Table 25: Output Timing Adjustments for IOB (Continued) Add the Adjustment Below Speed Grade -4 1.50 0.47 0.11 1.11 0.41 Input Only 1.73 0.64 0.07 1.28 0.88 0.43 0.41 ns ns ns ns ns ns ns Units ns ns ns ns ns Table 25: Output Timing Adjustments for IOB (Continued) Add the Adjustment Below Speed Grade -4 0.36 1.01 1.16 0.49 0.41 0.91 0.11 1.18 0.28 Units ns ns ns ns ns ns ns ns ns Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 DIFF_HSTL_I_18 DIFF_HSTL_II_18 Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) DIFF_HSTL_III_18 DIFF_HSTL_I DIFF_HSTL_III DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL3_I DIFF_SSTL3_II Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in Table 8, Table 11, and Table 13. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state. Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 26 lists the conditions to use for each standard. The method for measuring Input timing is as follows: A signal that swings between a Low logic level of VL and a High logic level of VH is applied to the Input under test. Some standards also require the application of a bias voltage to the VREF pins of a given bank to properly set the input-switching threshold. The measurement point of the Input signal (VM) is commonly located halfway between VL and VH. The Output test setup is shown in Figure 8. A termination voltage VT is applied to the termination resistor RT, the other end of which is connected to the Output. For each standard, RT and VT generally take on the standard values recommended for minimizing signal reflections. If the standard does not ordinarily use terminations (for example, LVCMOS, LVTTL), then RT is set to 1 M to indicate an open connection, and VT is set to zero. The same measurement point (VM) that was used at the Input is also used at the Output. VT (VREF) FPGA Output RT (RREF) VM (VMEAS) CL (CREF) DS312-3_04_102406 Notes: 1. The names shown in parentheses are used in the IBIS file. Figure 8: Output Test Setup 28 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Table 26: Test Methods for Timing Measurement at I/Os Signal Standard (IOSTANDARD) Single-Ended LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 Rising Falling HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II Differential LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 DIFF_HSTL_I DIFF_HSTL_III DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 0.75 0.9 0.9 0.9 1.1 VICM - 0.125 VICM - 0.125 VICM - 0.125 VICM - 0.125 VICM - 0.125 VICM - 0.3 VICM - 0.3 VICM - 0.1 VICM - 0.1 VICM - 0.1 VICM - 0.1 VICM - 0.1 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VICM + 0.125 VICM + 0.125 VICM + 0.125 VICM + 0.125 VICM + 0.125 VICM + 0.3 VICM + 0.3 VICM + 0.1 VICM + 0.1 VICM + 0.1 VICM + 0.1 VICM + 0.1 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 50 50 1M 50 50 N/A N/A 50 50 50 50 50 50 50 50 50 50 1.2 1.2 0 1.2 1.2 N/A N/A 1.2 1.2 3.3 0.8 0.8 0.75 1.5 0.9 0.9 1.8 VICM VICM VICM VICM VICM VICM VICM VICM VICM VICM VICM VICM VREF VREF VREF VREF VREF 0.75 0.9 0.9 0.9 1.1 0.9 0.9 1.25 1.25 1.5 1.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.75 VREF - 0.75 VREF - 0.75 VREF - 0.75 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.75 VREF + 0.75 VREF + 0.75 VREF + 0.75 0 0 0 0 0 0 Note 3 3.3 3.3 2.5 1.8 1.5 1.2 Note 3 1M 1M 1M 1M 1M 1M 25 25 50 50 50 25 50 50 25 50 25 50 25 0 0 0 0 0 0 0 3.3 0.75 1.5 0.9 0.9 1.8 0.9 0.9 1.25 1.25 1.5 1.5 1.4 1.65 1.25 0.9 0.75 0.6 0.94 2.03 VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF Inputs VREF (V) VL (V) VH (V) RT () Outputs VT (V) Inputs and Outputs VM (V) DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 29 R Table 26: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL3_I DIFF_SSTL3_II Notes: 1. Descriptions of the relevant symbols are as follows: VREF - The reference voltage for setting the input switching threshold VICM - The common mode input voltage VM - Voltage of measurement point on signal transition VL - Low-level test voltage at Input pin VH - High-level test voltage at Input pin RT - Effective termination resistance, which takes on a value of 1 M when no parallel termination is required VT - Termination voltage The load capacitance (CL) at the Output pin is 0 pF for all signal standards. According to the PCI specification. Inputs VREF (V) 0.9 0.9 1.25 1.25 1.5 1.5 VL (V) VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VH (V) VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 RT () 50 50 50 50 50 50 Outputs VT (V) 0.9 0.9 1.25 1.25 1.5 1.5 Inputs and Outputs VM (V) VREF VREF VREF VREF VREF VREF 2. 3. The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet. Delays for a given application are simulated according to its specific load conditions as follows: 1. Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 8. Use parameter values VT, RT, and VM from Table 26. CREF is zero. 2. Record the time to VM. 3. Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load. 4. Record the time to VMEAS. 5. Compare the results of steps 2 and 4. Add (or subtract) the increase (or decrease) in delay to (or from) the appropriate Output standard adjustment (Table 25) to yield the worst-case delay of the PCB trace. Using IBIS Models to Simulate Load Conditions in Application IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 26 (VT, RT, and VM). Do not confuse VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp 30 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Simultaneously Switching Output Guidelines This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins of a given output signal standard that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce. Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality. Table 27 and Table 28 provide the essential SSO guidelines. For each device/package combination, Table 27 provides the number of equivalent VCCO/GND pairs. For each output signal standard and drive strength, Table 28 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines in Table 28 are categorized by package style, slew rate, and output drive current. Furthermore, the number of SSOs is specified by I/O bank. Generally, the left and right I/O banks (Banks 1 and 3) support higher output drive current. Multiply the appropriate numbers from Table 27 and Table 28 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter. SSOMAX/IO Bank = Table 27 x Table 28 The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket. Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs. Table 27: Equivalent VCCO/GND Pairs per Bank Package Style (Pb-free) Device XA3S200A XA3S400A XA3S700A XA3S1400A FTG256 4 4 - - FGG400 - 5 5 - FGG484 - - 5 6 DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 31 R Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (VCCAUX=3.3V) Package Type FTG256, FGG400, FGG484 Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow 2 4 6 8 12 16 24 Fast 2 4 6 8 12 16 24 QuietIO 2 4 6 8 12 16 24 60 41 29 22 13 11 9 10 6 5 3 3 3 2 80 48 36 27 16 13 12 60 41 29 22 13 11 9 10 6 5 3 3 3 2 80 48 36 27 16 13 12 Top, Bottom (Banks 0,2) Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued) Package Type FTG256, FGG400, FGG484 Signal Standard (IOSTANDARD) LVCMOS33 Slow 2 4 6 8 12 16 24 Fast 2 4 6 8 12 16 24 QuietIO 2 4 6 8 12 16 24 Top, Bottom (Banks 0,2) Left, Right (Banks 1,3) Left, Right (Banks 1,3) 76 46 27 20 13 10 - 10 8 5 4 4 2 - 76 46 32 26 18 14 - 76 46 27 20 13 10 9 10 8 5 4 4 2 2 76 46 32 26 18 14 10 32 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued) Package Type FTG256, FGG400, FGG484 Signal Standard (IOSTANDARD) LVCMOS25 Slow 2 4 6 8 12 16 24 Fast 2 4 6 8 12 16 24 QuietIO 2 4 6 8 12 16 24 LVCMOS18 Slow 2 4 6 8 12 16 Fast 2 4 6 8 12 16 QuietIO 2 4 6 8 12 16 Top, Bottom (Banks 0,2) Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued) Package Type FTG256, FGG400, FGG484 Signal Standard (IOSTANDARD) LVCMOS15 Slow 2 4 6 8 12 Fast 2 4 6 8 12 QuietIO 2 4 6 8 12 LVCMOS12 Slow 2 4 6 Fast 2 4 6 QuietIO 2 4 6 PCI33_3 HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II Top, Bottom (Banks 0,2) Left, Right (Banks 1,3) Left, Right (Banks 1,3) 76 46 33 24 18 - - 18 14 6 6 3 - - 76 60 48 36 36 - - 64 34 22 18 - - 18 9 7 4 - - 64 64 48 36 - - 76 46 33 24 18 11 7 18 14 6 6 3 3 2 76 60 48 36 36 36 8 64 34 22 18 13 10 18 9 7 4 4 3 64 64 48 36 36 24 55 31 18 - - 25 10 6 - - 70 40 31 - - 40 - - 31 - - 55 - - 16 - - 17 - 10 7 - 18 - 8 6 55 31 18 15 10 25 10 6 4 3 70 40 31 31 20 40 25 18 31 13 9 55 36 36 16 20 8 17 5 8 15 9 18 9 10 7 DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 33 R Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued) Package Type FTG256, FGG400, FGG484 Signal Standard (IOSTANDARD) LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 22 27 27 22 27 - - - - - Top, Bottom (Banks 0,2) Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued) Package Type FTG256, FGG400, FGG484 Signal Standard (IOSTANDARD) DIFF_HSTL_I DIFF_HSTL_III DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL3_I DIFF_SSTL3_II Notes: 1. Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only supported in top or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3 Generation FPGA User Guide for additional information. The numbers in this table are recommendations that assume sound board lay out practice. Test limits are the VIL/VIH voltage limits for the respective I/O standard. If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs for information on how to perform weighted average SSO calculations. Top, Bottom (Banks 0,2) Left, Right (Banks 1,3) Left, Right (Banks 1,3) Differential Standards (Number of I/O Pairs or Channels) 22 27 4 22 27 - - 4 - - - - 8 - 5 3 - 9 - 4 3 10 4 8 2 4 7 4 9 4 5 3 2. 3. 34 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Configurable Logic Block (CLB) Timing Table 29: CLB (SLICEM) Timing Speed Grade -4 Symbol Description Min Max Units Clock-to-Output Times TCKO When reading from the FFX (FFY) Flip-Flop, the time from the active transition at the CLK input to data appearing at the XQ (YQ) output - 0.68 ns Setup Times TAS TDICK Time from the setup of data at the F or G input to the active transition at the CLK input of the CLB Time from the setup of data at the BX or BY input to the active transition at the CLK input of the CLB 0.36 1.88 - - ns ns Hold Times TAH TCKDI Time from the active transition at the CLK input to the point where data is last held at the F or G input Time from the active transition at the CLK input to the point where data is last held at the BX or BY input 0 0 - - ns ns Clock Timing TCH TCL FTOG The High pulse width of the CLB's CLK signal The Low pulse width of the CLK signal Toggle frequency (for export control) 0.75 0.75 0 - - 667 ns ns MHz Propagation Times TILO The time it takes for data to travel from the CLB's F (G) input to the X (Y) output - 0.71 ns Set/Reset Pulse Width TRPW_CLB Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 8. The minimum allowable pulse width, High or Low, to the CLB's SR input 1.61 - ns DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 35 R Table 30: CLB Distributed RAM Switching Characteristics Speed Grade -4 Symbol Description Min Max Units Clock-to-Output Times TSHCKO Time from the active edge at the CLK input to data appearing on the distributed RAM output - 2.01 ns Setup Times TDS TAS TWS Setup time of data at the BX or BY input before the active transition at the CLK input of the distributed RAM Setup time of the F/G address inputs before the active transition at the CLK input of the distributed RAM Setup time of the write enable input before the active transition at the CLK input of the distributed RAM -0.02 - - - ns ns ns 0.36 0.59 Hold Times TDH TAH, TWH Hold time of the BX and BY data inputs after the active transition at the CLK input of the distributed RAM Hold time of the F/G address inputs or the write enable input after the active transition at the CLK input of the distributed RAM 0.13 0.01 - - ns ns Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input 1.01 - ns Table 31: CLB Shift Register Switching Characteristics Speed Grade -4 Symbol Description Min Max Units Clock-to-Output Times TREG Time from the active edge at the CLK input to data appearing on the shift register output - 4.82 ns Setup Times TSRLDS Setup time of data at the BX or BY input before the active transition at the CLK input of the shift register 0.18 - ns Hold Times TSRLDH Hold time of the BX or BY data input after the active transition at the CLK input of the shift register 0.16 - ns Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input 1.01 - ns 36 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Clock Buffer/Multiplexer Switching Characteristics Table 32: Clock Distribution Switching Characteristics Maximum Speed Grade Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input Frequency of signals distributed on global buffers (all sides) Notes: The numbers in this table are based on the operating conditions set forth in Table 8. Symbol TGIO TGSI FBUFG Minimum - - 0 -4 0.23 0.63 333 Units ns ns MHz 18 x 18 Embedded Multiplier Timing Table 33: 18 x 18 Embedded Multiplier Timing Speed Grade -4 Symbol Description Min Max Units Combinatorial Delay TMULT Combinational multiplier propagation delay from the A and B inputs to the P outputs, assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers unused) - 4.88 ns Clock-to-Output Times TMSCKP_P TMSCKP_A TMSCKP_B Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using the PREG register(2,3) Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using either the AREG or BREG register(2,4) - - 1.30 4.97 ns ns Setup Times TMSDCK_P TMSDCK_A TMSDCK_B Data setup time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(3) Data setup time at the A input before the active transition at the CLK when using the AREG input register(4) Data setup time at the B input before the active transition at the CLK when using the BREG input register(4) 3.98 0.00 0.00 - - - ns ns ns Hold Times TMSCKD_P TMSCKD_A TMSCKD_B Data hold time at the A or B input after the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(3) Data hold time at the A input after the active transition at the CLK when using the AREG input register(4) Data hold time at the B input after the active transition at the CLK when using the BREG input register(4) 0.00 0.45 0.45 - - - ns ns ns DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 37 R Table 33: 18 x 18 Embedded Multiplier Timing (Continued) Speed Grade -4 Symbol Description Min Max Units Clock Frequency FMULT Notes: 1. 2. 3. 4. 5. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations. The PREG register is typically used when inferring a single-stage multiplier. Input registers AREG or BREG are typically used when inferring a two-stage multiplier. The numbers in this table are based on the operating conditions set forth in Table 8. Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG input registers and the PREG output register(1) 0 250 MHz Block RAM Timing Table 34: Block RAM Timing Speed Grade -4 Symbol Description Min Max Units Clock-to-Output Times TRCKO When reading from block RAM, the delay from the active transition at the CLK input to data appearing at the DOUT output - 2.49 ns Setup Times TRCCK_ADDR Setup time for the ADDR inputs before the active transition at the CLK input of the block RAM TRDCK_DIB TRCCK_ENB TRCCK_WEB Setup time for data at the DIN inputs before the active transition at the CLK input of the block RAM Setup time for the EN input before the active transition at the CLK input of the block RAM Setup time for the WE input before the active transition at the CLK input of the block RAM 0.36 0.31 0.77 1.26 - - - - ns ns ns ns Hold Times TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the CLK input TRCKD_DIB TRCKC_ENB TRCKC_WEB Hold time on the DIN inputs after the active transition at the CLK input Hold time on the EN input after the active transition at the CLK input Hold time on the WE input after the active transition at the CLK input 0 0 0 0 - - - - ns ns ns ns Clock Timing TBPWH TBPWL FBRAM Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 8. High pulse width of the CLK signal Low pulse width of the CLK signal 1.79 1.79 - - ns ns Clock Frequency Block RAM clock frequency 0 280 MHz 38 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Digital Clock Manager Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 35 and Table 36) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table 37 through Table 40) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table 35 and Table 36. Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe statistical variation from a mean value. Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of period jitter, the mean value is the clock period. Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero. Delay-Locked Loop Table 35: Recommended Operating Conditions for the DLL Speed Grade -4 Symbol Input Frequency Ranges FCLKIN CLKIN_FREQ_DLL Frequency of the CLKIN clock input CLKIN pulse width as a percentage of the CLKIN period Variation(4) FCLKIN < 150 MHz FCLKIN > 150 MHz - - - - 300 150 1 1 ps ps ns ns FCLKIN < 150 MHz FCLKIN > 150 MHz 5(2) 40% 45% 250(3) 60% 55% MHz - - Input Pulse Requirements CLKIN_PULSE Description Min Max Units Input Clock Jitter Tolerance and Delay Path CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_DLL_HF CLKIN_PER_JITT_DLL CLKFB_DELAY_VAR_EXT Notes: 1. 2. 3. 4. 5. Cycle-to-cycle jitter at the CLKIN input Period jitter at the CLKIN input Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 37. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input. CLKIN input jitter beyond these limits might cause the DCM to lose lock. The DCM specifications are guaranteed when both adjacent DCMs are locked. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 39 R Table 36: Switching Characteristics for the DLL Speed Grade -4 Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 CLKOUT_FREQ_CLK90 CLKOUT_FREQ_2X CLKOUT_FREQ_DV Output Clock Jitter(2,3,4) CLKOUT_PER_JITT_0 CLKOUT_PER_JITT_90 CLKOUT_PER_JITT_180 CLKOUT_PER_JITT_270 CLKOUT_PER_JITT_2X Period jitter at the CLK0 output Period jitter at the CLK90 output Period jitter at the CLK180 output Period jitter at the CLK270 output Period jitter at the CLK2X and CLK2X180 outputs All Frequency for the CLK0 and CLK180 outputs Frequency for the CLK90 and CLK270 outputs Frequency for the CLK2X and CLK2X180 outputs Frequency for the CLKDV output All 5 5 10 0.3125 250 200 334 166 MHz MHz MHz MHz Description Device Min Max Units - - - - - 100 150 150 150 [0.5% of CLKIN period + 100] 150 [0.5% of CLKIN period + 100] ps ps ps ps ps CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing integer division Period jitter at the CLKDV output when performing non-integer division - - ps ps Duty Cycle(4) CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion Phase Alignment(4) CLKIN_CLKFB_PHASE CLKOUT_PHASE_DLL Phase offset between the CLKIN and CLKFB inputs Phase offset between DLL outputs CLK0 to CLK2X (not CLK2X180) All All - [1% of CLKIN period + 350] ps - - 150 [1% of CLKIN period + 100] [1% of CLKIN period + 150] ps ps All others ps - Lock Time LOCK_DLL(3) When using the DLL alone: The time from deassertion at the DCM's Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase 5 MHz < FCLKIN < 15 MHz FCLKIN > 15 MHz All - - 5 600 ms s Delay Lines DCM_DELAY_STEP(5) Finest delay resolution, averaged over all steps All 15 35 ps Notes: 1. 2. 3. 4. 5. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 35. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of "[1% of CLKIN period + 150]". Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250ps. The typical delay step size is 23 ps. 40 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Digital Frequency Synthesizer Table 37: Recommended Operating Conditions for the DFS Speed Grade -4 Symbol Input Frequency Ranges(2) FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency Period jitter at the CLKIN input FCLKFX < 150 MHz FCLKFX > 150 MHz 0.200 333 300 150 1 MHz ps ps ns Input Clock Jitter Tolerance(3) CLKIN_CYC_JITT_FX_LF CLKIN_CYC_JITT_FX_HF CLKIN_PER_JITT_FX Description Min Max Units - - - Notes: 1. 2. 3. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 35. CLKIN input jitter beyond these limits may cause the DCM to lose lock. Table 38: Switching Characteristics for the DFS Speed Grade -4 Symbol Output Frequency Ranges CLKOUT_FREQ_FX(2) Output Clock Jitter(3,4) CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs. All CLKIN 20 MHz Description Frequency for the CLKFX and CLKFX180 outputs Device All Min 5 Typ Max 320 Max Units MHz Use the Spartan-3A Jitter Calculator: www.xilinx.com/s upport/document ation/data_sheets /s3a_jitter_calc.zi p [1% of [1% of CLKFX CLKFX period period + 100] + 200] All [1% of CLKFX period + 350] 200 [1% of CLKFX period + 200] ps CLKIN > 20 MHz Duty Cycle(5,6) CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs, including the BUFGMUX and clock tree duty-cycle distortion ps ps - Phase Alignment(6) CLKOUT_PHASE_FX CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used All All - - ps ps DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 41 R Table 38: Switching Characteristics for the DFS (Continued) Speed Grade -4 Symbol Lock Time LOCK_FX(2, 3) The time from deassertion at the DCM's 5 MHz < FCLKIN Reset input to the rising transition at its < 15 MHz LOCKED output. The DFS asserts LOCKED FCLKIN > 15 MHz when the CLKFX and CLKFX180 signals are valid. If using both the DLL and the DFS, use the longer locking time. All Description Device Min Max 5 450 Units ms s - - Notes: 1. 2. 3. 4. 5. 6. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 37. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a maximum CLKFX jitter of "[1% of CLKFX period + 200]". Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 200 ps] = 300 ps. Phase Shifter Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode Speed Grade -4 Symbol Operating Frequency Ranges PSCLK_FREQ (FPSCLK) PSCLK_PULSE Frequency for the PSCLK input 1 167 MHz Description Min Max Units Input Pulse Requirements PSCLK pulse width as a percentage of the PSCLK period 40% 60% - Table 40: Switching Characteristics for the PS in Variable Phase Mode Symbol Description Phase Shift Amount Units Phase Shifting Range MAX_STEPS(2) Maximum allowed number of CLKIN < 60 MHz DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN CLKIN 60 MHz clock period in ns. If using CLKIN_DIVIDE_BY_2 = TRUE, double the clock effective clock period. Minimum guaranteed delay for variable phase shifting Maximum guaranteed delay for variable phase shifting [INTEGER(10 * (TCLKIN - 3 ns))] [INTEGER(15 * (TCLKIN - 3 ns))] steps FINE_SHIFT_RANGE_MIN FINE_SHIFT_RANGE_MAX [MAX_STEPS * DCM_DELAY_STEP_MIN] [MAX_STEPS * DCM_DELAY_STEP_MAX] ns ns Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 39. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the bottom of Table 36. 42 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Miscellaneous DCM Timing Table 41: Miscellaneous DCM Timing Symbol DCM_RST_PW_MIN DCM_RST_PW_MAX(2) DCM_CONFIG_LAG_TIME(3) Description Minimum duration of a RST pulse width Maximum duration of a RST pulse width Min 3 N/A N/A Maximum duration from VCCINT applied to FPGA configuration successfully completed (DONE pin goes High) and clocks applied to DCM DLL N/A N/A Max - N/A N/A N/A N/A Units CLKIN cycles seconds seconds minutes minutes Notes: 1. 2. 3. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. This specification is equivalent to the Virtex(R)-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs. DNA Port Timing Table 42: DNA_PORT Interface Timing Symbol TDNASSU TDNASH TDNADSU TDNADH TDNARSU TDNARH TDNADCKO TDNACLKF TDNACLKL TDNACLKH Notes: 1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 s. Description Setup time on SHIFT before the rising edge of CLK Hold time on SHIFT after the rising edge of CLK Setup time on DIN before the rising edge of CLK Hold time on DIN after the rising edge of CLK Setup time on READ before the rising edge of CLK Hold time on READ after the rising edge of CLK Clock-to-output delay on DOUT after rising edge of CLK CLK frequency CLK High time CLK Low time Min 1.0 0.5 1.0 0.5 5.0 0 0.5 0 1.0 1.0 Max - - - - 10,000 - 1.5 100 Units ns ns ns ns ns ns ns MHz ns ns DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 43 R Suspend Mode Timing Entering Suspend Mode SUSPEND Input tSUSPENDHIGH_AWAKE Exiting Suspend Mode sw_gwe_cycle sw_gts_cycle tSUSPENDLOW_AWAKE AWAKE Output tSUSPEND_GWE tAWAKE_GWE Flip-Flops, Block RAM, Distributed RAM tSUSPEND_GTS Write Protected tAWAKE_GTS FPGA Outputs FPGA Inputs, Interconnect Defined by SUSPEND constraint tSUSPEND_DISABLE tSUSPEND_ENABLE Blocked DS610-3_08_061207 Figure 9: Suspend Mode Timing Table 43: Suspend Mode Timing Parameters Symbol Description Min Typ Max Units Entering Suspend Mode TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter (suspend_filter:No) TSUSPENDFILTER TSUSPEND_GWE TSUSPEND_GTS TSUSPEND_DISABLE Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled (suspend_filter:Yes) Rising edge of SUSPEND pin until FPGA output pins drive their defined SUSPEND constraint behavior Rising edge of SUSPEND pin to write-protect lock on all writable clocked elements Rising edge of the SUSPEND pin to FPGA input pins and interconnect disabled - +160 - - - 7 +300 10 <5 340 - +600 - - - ns ns ns ns ns Exiting Suspend Mode TSUSPENDLOW_AWAKE TSUSPEND_ENABLE TAWAKE_GWE1 TAWAKE_GWE512 TAWAKE_GTS1 TAWAKE_GTS512 Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not include DCM lock time. Falling edge of the SUSPEND pin to FPGA input pins and interconnect re-enabled Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1. Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512. Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1. Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512. - - - - - - 4 to 108 3.7 to 109 67 14 57 14 - - - - - - s s ns s ns s Notes: 1. 2. These parameters based on characterization. For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. 44 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Configuration and JTAG Timing General Configuration Power-On/Reconfigure Timing VCCINT (Supply) VCCAUX (Supply) VCCO Bank 2 (Supply) PROG_B (Input) INIT_B (Open-Drain) CCLK (Output) DS529-3_01_112906 1.2V 1.0V 2.5V or 3.3V 2.0V 1.0V TPOR TPROG TPL TICCK Notes: 1. 2. 3. The VCCINT, VCCAUX, and VCCO supplies can be applied in any order. The Low-going pulse on PROG_B is optional after power-on. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2). Figure 10: Waveforms for Power-On and the Beginning of Configuration Table 44: Power-On Timing and the Beginning of Configuration -4 Speed Grade Symbol TPOR(2) Description The time from the application of VCCINT, VCCAUX, and VCCO Bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the INIT_B pin The width of the low-going pulse on the PROG_B pin The time from the rising edge of the PROG_B pin to the rising transition on the INIT_B pin All Device Min - Max 18 Units ms s ms ms ms ms ns s TPROG TPL(2) All XA3S200A XA3S400A XA3S700A XA3S1400A 0.5 - - - - 250 0.5 0.5 1 2 2 - 4 TINIT TICCK(3) Minimum Low pulse width on INIT_B output The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin All All Notes: 1. 2. 3. The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all VCCINT, VCCO, and VCCAUX lines. Power-on reset and the clearing of configuration memory occurs during this period. This specification applies only to the Master Serial, SPI, and BPI modes. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 45 R Configuration Clock (CCLK) Characteristics Table 45: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol TCCLK1 TCCLK3 TCCLK6 TCCLK7 TCCLK8 TCCLK10 TCCLK12 TCCLK13 TCCLK17 TCCLK22 TCCLK25 TCCLK27 TCCLK33 TCCLK44 TCCLK50 TCCLK100 Notes: 1. Set the ConfigRate option value when generating a configuration bitstream. Description CCLK clock period by ConfigRate setting ConfigRate Setting 1 (power-on value) 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100 Temperature Range I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade Minimum 1,053 351 174 148 132 104 87 80 61 47 42 35 31 24 19 9.4 Maximum 2,500 833 417 357 313 250 208 192 147 114 100 93 76 57 50 25 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 46 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Table 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol FCCLK1 FCCLK3 FCCLK6 FCCLK7 FCCLK8 FCCLK10 FCCLK12 FCCLK13 FCCLK17 FCCLK22 FCCLK25 FCCLK27 FCCLK33 FCCLK44 FCCLK50 FCCLK100 Description Equivalent CCLK clock frequency by ConfigRate setting ConfigRate Setting 1 (power-on value) 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100 Temperature Range I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade I-Grade & Q-Grade Minimum 0.40 1.20 2.40 2.80 3.20 4.00 4.80 5.20 6.80 8.80 10.00 10.80 13.20 17.60 20.00 40.00 Maximum 0.95 2.85 5.74 6.74 7.58 9.65 11.48 12.49 16.33 21.23 23.59 28.31 32.67 42.47 53.08 106.16 Units MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Table 47: Master Mode CCLK Output Minimum Low and High Time ConfigRate Setting Symbol TMCCL, TMCCH Description Master Mode CCLK Minimum Low and High Time I-Grade & Q-Grade 1 474 3 158 6 7 8 10 12 13 17 22 25 27 33 44 50 8.5 100 4.2 Units 78.4 66.8 59.3 46.6 39.2 36.0 27.6 21.2 19.1 15.9 13.8 10.6 ns Table 48: Slave Mode CCLK Input Low and High Time Symbol TSCCL, TSCCH CCLK Low and High time Description Min 5 Max Units ns DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 47 R Master Serial and Slave Serial Mode Timing PROG_B (Input) INIT_B (Open-Drain) TMCCL TSCCL TMCCH TSCCH CCLK (Input/Output) TDCC DIN (Input) TCCD Bit 0 Bit 1 1/FCCSER Bit n Bit n+1 TCCO DOUT (Output) Bit n-64 Bit n-63 DS312-3_05_103105 Figure 11: Waveforms for Master Serial and Slave Serial Configuration Table 49: Timing for the Master Serial and Slave Serial Configuration Modes Symbol Description Slave/ Master -4 Speed Grade Min Max Units Clock-to-Output Times TCCO The time from the falling transition on the CCLK pin to data appearing at the DOUT pin Both 1.5 10 ns Setup Times TDCC The time from the setup of data at the DIN pin to the rising transition at the CCLK pin Both 7 - ns Hold Times TCCD The time from the rising transition at the CCLK pin to the point when data is last held at the DIN pin Master Slave 0 1.0 - ns Clock Timing TCCH TCCL FCCSER High pulse width at the CCLK input pin Master Slave Low pulse width at the CCLK input pin Master Slave Frequency of the clock signal at the CCLK input pin No bitstream compression With bitstream compression Slave 0 0 See Table 47 See Table 48 See Table 47 See Table 48 100 100 MHz MHz Notes: 1. 2. The numbers in this table are based on the operating conditions set forth in Table 8. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz. 48 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Slave Parallel Mode Timing PROG_B (Input) INIT_B (Open-Drain) TSMCSCC CSI_B (Input) TSMCCW RDWR_B (Input) TMCCH TSCCH CCLK (Input) TSMDCC D0 - D7 (Inputs) TSMCCD 1/FCCPAR TMCCL TSCCL TSMWCC TSMCCCS Byte 0 Byte 1 Byte n Byte n+1 DS529-3_02_051607 Notes: 1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0 - D7 bus. Figure 12: Waveforms for Slave Parallel Configuration Table 50: Timing for the Slave Parallel Configuration Mode -4 Speed Grade Symbol Description Min Max Units Setup Times TSMDCC(2) TSMCSCC TSMCCW The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin Setup time on the CSI_B pin before the rising transition at the CCLK pin Setup time on the RDWR_B pin before the rising transition at the CCLK pin 7 7 15 - - - ns ns ns Hold Times TSMCCD TSMCCCS TSMWCC The time from the rising transition at the CCLK pin to the point when data is last held at the D0-D7 pins The time from the rising transition at the CCLK pin to the point when a logic level is last held at the CSO_B pin The time from the rising transition at the CCLK pin to the point when a logic level is last held at the RDWR_B pin 1.0 0 0 - - - ns ns ns Clock Timing TCCH TCCL FCCPAR The High pulse width at the CCLK input pin The Low pulse width at the CCLK input pin Frequency of the clock signal No bitstream compression at the CCLK input pin With bitstream compression 5 5 0 0 - - 80 80 ns ns MHz MHz Notes: 1. 2. The numbers in this table are based on the operating conditions set forth in Table 8. Some Xilinx documents refer to Parallel modes as "SelectMAP" modes. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 49 R Serial Peripheral Interface Configuration Timing PROG_B (Input) PUDC_B (Input) PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. VS[2:0] (Input) <1:1:1> M[2:0] (Input) Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point these pins become user-I/O pins. TINITM New ConfigRate active TCCLKn TMCCHn <0:0:1> TMINIT INIT_B (Open-Drain) T CCLK1 CCLK TMCCL1 TMCCH1 TMCCLn TCCLK1 TV DIN (Input) Data TCSS Data TDCC Data TCCD Data CSO_B TCCO MOSI Command (msb) TDSU Command (msb-1) T DH Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low. Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B. Shaded values indicate specifications on attached SPI Flash PROM. DS529-3_06_102506 Figure 13: Waveforms for SPI Configuration Table 51: Timing for SPI Configuration Mode Symbol TCCLK1 TCCLKn TMINIT TINITM TCCO TDCC TCCD Initial CCLK clock period CCLK clock period after FPGA loads ConfigRate bitstream option setting Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the rising edge of INIT_B Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the rising edge of INIT_B MOSI output valid delay after CCLK falling clock edge Setup time on the DIN data input before CCLK rising clock edge Hold time on the DIN data input after CCLK rising clock edge 50 0 Description Minimum Maximum See Table 45 See Table 45 - - See Table 49 See Table 49 See Table 49 ns ns Units 50 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Table 52: Configuration Timing Requirements for Attached SPI Serial Flash Symbol TCCS TDSU TDH TV fC or fR Description SPI serial Flash PROM chip-select time SPI serial Flash PROM data input setup time SPI serial Flash PROM data input hold time SPI serial Flash PROM data clock-to-output time Maximum SPI serial Flash PROM clock frequency (also depends on specific read command used) Requirement Units ns ns ns ns MHz T CCS T MCCL1 - T CCO T DSU T MCCL1 - T CCO T DH T MCCH1 T V T MCCLn - T DCC 1 f C -------------------------------T CCLKn ( min ) Notes: 1. 2. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA. Subtract additional printed circuit board routing delay as required by the application. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 51 R Byte Peripheral Interface Configuration Timing PROG_B (Input) PUDC_B (Input) M[2:0] (Input) TMINIT INIT_B (Open-Drain) PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. Mode input pins M[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point the mode pins become user-I/O pins. TINITM <0:1:0> Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low. Pin initially high-impedance (Hi-Z) if PUDC_B input is High. LDC[2:0] HDC CSO_B T INITADDR New ConfigRate active TCCLK1 TCCLKn TCCLK1 CCLK TCCO A[25:0] 000_0000 000_0001 TAVQV D[7:0] (Input) Byte 0 Byte 1 Data Address Address TDCC Data Data Address TCCD Data Shaded values indicate specifications on attached parallel NOR Flash PROM. DS529-3_05_121107 Figure 14: Waveforms for BPI Configuration Table 53: Timing for BPI Configuration Mode Symbol TCCLK1 TCCLKn TMINIT TINITM TINITADDR TCCO TDCC TCCD Initial CCLK clock period CCLK clock period after FPGA loads ConfigRate setting Setup time on M[2:0] mode pins before the rising edge of INIT_B Hold time on M[2:0] mode pins after the rising edge of INIT_B Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted and valid Address A[25:0] outputs valid after CCLK falling edge Setup time on D[7:0] data inputs before CCLK rising edge Hold time on D[7:0] data inputs after CCLK rising edge 50 0 5 Description Minimum Maximum See Table 45 See Table 45 - - 5 See Table 49 See TSMDCC in Table 50 0 - ns ns ns TCCLK1 cycles Units 52 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol TCE (tELQV) TOE (tGLQV) TACC (tAVQV) Description Parallel NOR Flash PROM chip-select time Parallel NOR Flash PROM output-enable time Parallel NOR Flash PROM read access time Requirement Units ns ns ns ns T CE T INITADDR T OE T INITADDR T ACC 50%T CCLKn ( min ) - T CCO - T DCC - PCB T BYTE T INITADDR TBYTE For x8/x16 PROMs only: BYTE# to output valid time(3) (tFLQV, tFHQV) Notes: 1. 2. 3. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA. Subtract additional printed circuit board routing delay as required by the application. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA's LDC2 pin. The resistor value also depends on whether the FPGA's PUDC_B pin is High or Low. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 53 R IEEE 1149.1/1553 JTAG Test Access Port Timing TCCH TCCL TCK (Input) TTMSTCK TTCKTMS 1/FTCK TMS (Input) TTDITCK TTCKTDI TDI (Input) TTCKTDO TDO (Output) DS099_06_040703 Figure 15: JTAG Waveforms Table 55: Timing for the JTAG Test Access Port -4 Speed Grade Symbol Description Min Max Units Clock-to-Output Times TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin 1.0 11.0 ns Setup Times TTDITCK The time from the setup of data at the TDI pin to the rising transition at the TCK pin All devices and functions except those shown below Boundary scan commands (INTEST, EXTEST, SAMPLE) on XA3S700A and XA3S1400A FPGAs 7.0 11.0 7.0 - ns - ns TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin Hold Times TTCKTDI The time from the rising transition at the TCK pin to the point when data is last held at the TDI pin All functions except those shown below Configuration commands (CFG_IN, ISC_PROGRAM) 0 2.0 0 - ns - ns TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the TMS pin Clock Timing TCCH TCCL The High pulse width at the TCK pin The Low pulse width at the TCK pin During ISC_DNA command All functions except ISC_DNA command 5 5 10 10 All operations on XA3S200A and XA3S400A FPGAs and for BYPASS or HIGHZ instructions on all FPGAs All operations on XA3S700A and XA3S1400A FPGAs, except for BYPASS or HIGHZ instructions Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 8. - - 10,000 10,000 33 20 ns ns ns ns MHz TCCHDNA The High pulse width at the TCK pin TCCLDNA The Low pulse width at the TCK pin FTCK Frequency of the TCK signal 0 54 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification R Revision History The following table shows the revision history for this document. Date 04/30/08 05/07/08 02/03/09 Version 1.0 1.0.1 1.1 Initial release. Updated Figure 14, minor edits under Features and Package Marking, Table 20 and 21. * * * * * * * * * * * * Updated "Key Feature Differences from Commercial XC Devices," page 2. Removed MultiBoot description from "Configuration," page 3. Updated to v1.41 in Table 3 and Table 16. Removed -5 high performance (commercial only) speed grade from "Ordering Information," page 5. Replaced VICM with VCCAUX in Note 7 of Table 13. Added versions 1.40 and 1.41 to Table 17. Updated Note 2 in Figure 10. Removed TIOOLP from Table 23. Updated TIOCKHZ and TIOCKON in Table 24. Updated Table 22 and Table 25. Updated SSO number for left and right I/O banks of DIFF_SSTL18_II standard in Table 28. Updated TACC requirement in Table 54. Revision Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS681 (v1.1) February 3, 2009 Product Specification www.xilinx.com 55 R 56 www.xilinx.com DS681 (v1.1) February 3, 2009 Product Specification |
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