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M95040 M95020 M95010
4 Kbit, 2 Kbit and 1 Kbit Serial SPI bus EEPROM with high speed Clock
Feature summary
Compatible with SPI bus serial interface (Positive Clock SPI Modes) Single supply voltage: - 4.5 V to 5.5 V for M950x0 - 2.5 V to 5.5 V for M950x0-W - 1.8 V to 5.5 V for M950x0-R High Speed - 10 MHz Clock rate, 5 ms Write time Status Register Byte and Page Write (up to 16 bytes) Self-timed programming cycle Adjustable size read-only EEPROM area Enhanced ESD Protection More than 1 Million Write cycles More than 40-year data retention Packages - ECOPACK(R) (RoHS compliant) Product list
Part Number M95040 M95040 M95040-W M95040-R M95020 M95020 M95020-W M95020-R M95010 M95010 M95010-W M95010-R
SO8 (MN) 150 mil width

TSSOP8 (DW) 169 mil width
Table 1.
Reference
UFDFPN8 (MB) 2 x 3mm
November 2006
Rev 7
1/42
www.st.com 1
Contents
M95040, M95020, M95010
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8.1 2.8.2 2.8.3 2.8.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 4.3 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Protection and Protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 6.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 6.3.2 6.3.3 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M95040, M95020, M95010
Contents
6.4 6.5 6.6 6.7
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 7.2 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 9 10 11 12
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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List of tables
M95040, M95020, M95010
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions (M950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M950x0-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M950x0-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M950x0-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC characteristics (M950x0, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC characteristics (M950x0, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC characteristics (M950x0-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics (M950x0-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC characteristics (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 37 UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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M95040, M95020, M95010
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hold Condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 36 TSSOP8 - 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 37 UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Summary description
M95040, M95020, M95010
1
Summary description
The M95040 is a 4 Kbit (512 x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2 and Figure 1. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). WRITE instructions are disabled by Write Protect (W). In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram
VCC
D C S W HOLD M95xxx
Q
VSS
AI01789C
Figure 2.
8-pin package connections
M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790D
VCC HOLD C D
1. See Section 10: Package mechanical for package dimensions, and how to identify pin-1.
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M95040, M95020, M95010 Table 2.
C D Q S W HOLD VCC VSS
Summary description
Signal names
Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
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Signal description
M95040, M95020, M95010
2
Signal description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals can be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 13 to Table 17). These signals are described next.
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
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M95040, M95020, M95010
Signal description
2.6
Write Protect (W)
This input signal is used to control whether the memory is write protected. When Write Protect (W) is held Low, writes to the memory are disabled, but other operations remain enabled. Write Protect (W) must either be driven High or Low, but must not be left floating.
2.7
VSS ground
VSS is the reference for the VCC supply voltage.
2.8
Supply voltage (VCC)
VCC is the supply voltage.
2.8.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9 and Table 10). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
2.8.2
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) signal is not allowed to float and must follow the VCC voltage. The S line should therefore be connected to VCC via a suitable pull-up resistor. In addition, the Chip Select (S) input offers a built-in safety feature, as it is both edge sensitive and level sensitive. Practically this means that after power-up, the device cannot become selected until a falling edge has first been detected on Chip Select (S). So the Chip Select (S) signal must first have been High, and then gone Low before the first operation can be started.
2.8.3
Internal device reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any instruction until VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Section 9: DC and AC parameters).
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Signal description
M95040, M95020, M95010
When VCC has passed the POR threshold voltage, the device is reset and in the following state:

in Standby Power mode deselected (at next Power-up, a falling edge is required on Chip Select (S) before any instruction can be executed) not in the Hold Condition Status register state: - - the Write Enable Latch (WEL) is reset to 0 the Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are at the same logic level as when the device was last powered down (they are non-volatile bits)
2.8.4
Power-down
At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. At Power-down, the device must be deselected and in Standby Power mode (that is there should be no internal Write cycle in progress). Chip Select (S) should be allowed to follow the voltage applied on VCC.
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M95040, M95020, M95010
Connecting to the SPI bus
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance.
Figure 3.
Bus master and memory devices on the SPI bus
VSS VCC R(2) SDO
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1)
SDI SCK CQD VCC VSS R(2) SPI Memory Device R(2) SPI Memory Device CQD VCC VSS R(2) SPI Memory Device CQD VCC VSS
Bus Master
CS3
CS2 CS1 S W HOLD S W HOLD S W HOLD
AI12304
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. 2. These pull-up resistors, R, ensure that the M950x0 are not selected if the Bus Master leaves the S line in the highimpedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (that is when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met).
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Connecting to the SPI bus
M95040, M95020, M95010
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) SPI modes supported
Figure 4.
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
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M95040, M95020, M95010
Operating features
4
4.1
Operating features
Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (C) already being Low (as shown in Figure 5). The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 5 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low. Figure 5. Hold Condition activation
C
HOLD
Hold Condition
Hold Condition
AI02029D
4.2
Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. This register contains a number of control bits and status bits, as shown in Table 5. For a detailed description of the Status Register bits, see Section 6.3: Read Status Register (RDSR).
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Operating features
M95040, M95020, M95010
4.3
Data Protection and Protocol control
To help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. The main security measures can be summarized as follows:

The WEL bit is reset at power-up. Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile Write cycle (in the memory array or in the Status Register). Accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the next rising edge of Serial Clock (C). For this, "the last bit of the instruction" can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except in the case of RDSR and READ instructions). Moreover, the "next rising edge of CLOCK" might (or might not) be the next bus transaction for some other device on the bus. When a Write cycle is in progress, the device protects it against external interruption by ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is complete. Table 3. Write-Protected block size
Array Addresses Protected Protected Block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory M95040 none 180h - 1FFh 100h - 1FFh 000h - 1FFh M95020 none C0h - FFh 80h - FFh 00h - FFh M95010 none 60h - 7Fh 40h - 7Fh 00h - 7Fh
Status Register Bits
14/42
M95040, M95020, M95010
Memory organization
5
Memory organization
The memory is organized as shown in Figure 6. Figure 6.
HOLD W S C D Q Control Logic
Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
AI01272C
15/42
Instructions
M95040, M95020, M95010
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 4. If an invalid instruction is sent (one not contained in Table 4), the device automatically deselects itself. Table 4. Instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction Format 0000 X110(1) 0000 X100(1) 0000 X101(1) 0000 X001(1) 0000 A8011(2) 0000 A8010(2)
Instruction WREN WRDI RDSR WRSR READ WRITE
1. X = Don't Care.
2. A8 = 1 for the upper half of the memory array of the M95040, and 0 for the lower half, and is Don't Care for other devices.
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. Figure 7. Write Enable (WREN) sequence
S 0 C Instruction D High Impedance Q
AI01441D
1
2
3
4
5
6
7
16/42
M95040, M95020, M95010
Instructions
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion Write Protect (W) line being held Low. Write Disable (WRDI) sequence
S 0 C Instruction D High Impedance Q
AI03790D
Figure 8.
1
2
3
4
5
6
7
17/42
Instructions
M95040, M95020, M95010
6.3
Read Status Register (RDSR)
One of the major uses of this instruction is to allow the MCU to poll the state of the Write In Progress (WIP) bit. This is needed because the device will not accept further WRITE or WRSR instructions when the previous Write cycle is not yet finished. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current state of the bits in the Status Register is shifted out, on Serial Data Out (Q). The Read Cycle is terminated by driving Chip Select (S) High. The Status Register may be read at any time, even during a Write cycle (whether it be to the memory area or to the Status Register). All bits of the Status Register remain valid, and can be read using the RDSR instruction. However, during the current Write cycle, the values of the non-volatile bits (BP0, BP1) become frozen at a constant value. The updated value of these bits becomes available when a new RDSR instruction is executed, after completion of the Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write In Progress (WIP)) are dynamically updated during the on-going Write cycle. Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. Table 5.
b7 1 1 1 1 BP1 BP0 WEL
Status Register format
b0 WIP
Block Protect Bits Write Enable Latch Bit Write In Progress Bit
18/42
M95040, M95020, M95010 Figure 9.
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instructions
Read Status Register (RDSR) sequence
0
7
AI01444D
19/42
Instructions
M95040, M95020, M95010
6.4
Write Status Register (WRSR)
This instruction has no effect on bits b7, b6, b5, b4, b1 and b0 of the Status Register. As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and data byte are then shifted in on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). If this condition is not met, the Write Status Register (WRSR) instruction is not executed. The self-timed Write Cycle starts, and continues for a period tW (as specified in Table 18 to Table 22), at the end of which the Write in Progress (WIP) bit is reset to 0. The instruction is not accepted, and is not executed, under the following conditions:

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write Cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven High, after the eighth bit, b0, of the data byte has been latched in if Write Protect (W) is Low.
Figure 10. Write Status Register (WRSR) sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI01445B
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
20/42
M95040, M95020, M95010
Instructions
6.5
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 4. The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven Low, an internal bit-pointer is automatically incremented at each clock cycle, and the corresponding data bit is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Table 6. Address range bits
Device Address Bits M95040 A8-A0 M95020 A7-A0 M95010 A6-A0
Figure 11. Read from Memory Array (READ) sequence
S 0 C Instruction Byte Address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 Data Out 7 6 5 4 3 2 1 0
AI01440E
High Impedance Q
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
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Instructions
M95040, M95020, M95010
6.6
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High after the rising edge of Serial Clock (C) that latches the last data bit, and before the next rising edge of Serial Clock (C) occurs anywhere on the bus. In the case of Figure 12, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in Table 18 to Table 22), at the end of which the Write in Progress (WIP) bit is reset to 0. If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13, the next byte of input data is shifted in. In this way, all the bytes from the given address to the end of the same page can be programmed in a single instruction. If Chip Select (S) still continues to be driven Low, the next byte of input data is shifted in, and is used to overwrite the byte at the start of the current page. The instruction is not accepted, and is not executed, under the following conditions:

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and before the next rising edge of Serial Clock (C) occurs anywhere on the bus) if Write Protect (W) is Low or if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Figure 12. Byte Write (WRITE) sequence
S 0 C Instruction Byte Address Data Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
High Impedance Q
AI01442D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
22/42
M95040, M95020, M95010 Figure 13. Page Write (WRITE) sequence
S 0 C Instruction Byte Address Data Byte 1 1 2 3 4 5 6 7 8
Instructions
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
7
S 10+8N 11+8N 12+8N 13+8N 14+8N 15+8N 8+8N 9+8N
136
137
138
139
140
141 2
142 1
24 25 26 27 28 29 30 31 C Data Byte 2
Data Byte N
Data Byte 16
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
0
AI01443D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
6.7
Cycling
143
23/42
Power-up and delivery states
M95040, M95020, M95010
7
7.1
Power-up and delivery states
Power-up state
After Power-up, the device is in the following state:

low power Standby Power mode deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). not in the Hold Condition the Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0
The BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1 and BP0) bits are initialized to 0.
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M95040, M95020, M95010
Maximum rating
8
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7.
Symbol TA TSTG TLEAD VO VI VCC VESD
Absolute maximum ratings
Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Output Voltage Input Voltage Supply Voltage Electrostatic Discharge Voltage (Human Body model)(2) Min. -40 -65 see note -0.50 -0.50 -0.50 -4000 Max. 130 150
(1)
Unit C C C V V V V
VCC+0.6 6.5 6.5 4000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500, R2=500)
25/42
DC and AC parameters
M95040, M95020, M95010
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply Voltage Ambient Operating Temperature (Device Grade 6) Ambient Operating Temperature (Device Grade 3)
Operating conditions (M950x0)
Parameter Min. 4.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 9.
Symbol VCC TA
Operating conditions (M950x0-W)
Parameter Supply Voltage Ambient Operating Temperature (Device Grade 6) Ambient Operating Temperature (Device Grade 3) Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 10.
Symbol VCC TA
Operating conditions (M950x0-R)
Parameter Supply Voltage Ambient Operating Temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 11.
Symbol CL
AC test measurement conditions
Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Min. 30 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 14. AC test measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
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M95040, M95020, M95010 Table 12.
Symbol COUT CIN
DC and AC parameters
Capacitance
Parameter Output Capacitance (Q) Input Capacitance (D) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V VIN = 0V Min. Max. 8 8 6 Unit pF pF pF
1. Sampled only, not 100% tested, at TA=25C and a frequency of 5MHz.
Table 13.
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH
DC characteristics (M950x0, Device Grade 6)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby Power mode) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 10 MHz, VCC = 5 V, Q = open S = VCC, VCC = 5 V, VIN = VSS or VCC -0.45 0.7 VCC Min. Max. 2 2 5 2 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Table 14.
Symbol ILI ILO ICC
DC characteristics (M950x0, Device Grade 3)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby Power mode) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open S = VCC, VIN = VSS or VCC VCC = 5 V -0.45 0.7 VCC Min. Max. 2 2 3 Unit A A mA
ICC1 VIL VIH VOL VOH
5 0.3 VCC VCC+1 0.4
A V V V V
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DC and AC parameters Table 15.
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH
M95040, M95020, M95010 DC characteristics (M950x0-W, Device Grade 6)
Parameter Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open S = VCC, VIN = VSS or VCC VCC = 2.5 V -0.45 0.7 VCC IOL = 1.5 mA, VCC = 2.5 V IOH = -0.4 mA, VCC = 2.5 V 0.8 VCC Min. Max. 2 2 2 1 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby Power mode) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Table 16.
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH
DC characteristics (M950x0-W, Device Grade 3)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby Power mode) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.5 mA, VCC = 2.5 V IOH = -0.4 mA, VCC = 2.5 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open S = VCC, VIN = VSS or VCC VCC = 2.5 V -0.45 0.7 VCC Min. Max. 2 2 2 2 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
Table 17.
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH
DC characteristics (M950x0-R)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby Power mode) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 0.15 mA, VCC = 1.8 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC Test Condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1 VCC/0.9. VCC at 2 MHz, VCC = 1.8 V, Q = open S = VCC, VIN = VSS or VCC, VCC = 1.8 V -0.45 0.7 VCC Min. Max. 2 2 2 1 0.3VCC VCC+1 0.3 Unit A A mA A V V V V
28/42
M95040, M95020, M95010 Table 18. AC characteristics (M950x0, Device Grade 6)
DC and AC parameters
Test conditions specified in Table 11 and Table 8 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL
(1)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency
Parameter
Min. D.C. 15 15 40 25 15 40 40
Max. 10
Unit MHz ns ns ns ns ns ns ns
S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time
tCLH tCLL tRC tFC tDSU tDH
Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock Low Setup Time before HOLD Active Clock Low Setup Time before HOLD not Active
tCLCH(2) tCHCL(2) tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
1 1 15 15 15 20 0 0 25 35 0 20 20 25 35 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ(2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Table 19. AC characteristics (M950x0, Device Grade 3)
M95040, M95020, M95010
Test conditions specified in Table 11 and Table 8 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL(1) tCLCH tCHCL
(2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time
tCLH tCLL tRC tFC tDSU tDH
Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock Low Setup Time before HOLD Active Clock Low Setup Time before HOLD not Active
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ(2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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M95040, M95020, M95010 Table 20. AC characteristics (M950x0-W, Device Grade 6)
DC and AC parameters
Test conditions specified in Table 11 and Table 9 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL(1) tCLCH tCHCL
(2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time
tCLH tCLL tRC tFC tDSU tDH
Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock Low Setup Time before HOLD Active Clock Low Setup Time before HOLD not Active
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ(2) tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ(2) tW
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Table 21. AC characteristics (M950x0-W, Device Grade 3)
M95040, M95020, M95010
Test conditions specified in Table 11 and Table 9 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL
(1)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time
tCLH tCLL tRC tFC tDSU tDH
Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock Low Setup Time before HOLD Active Clock Low Set-up Time before HOLD not Active
tCLCH(2) tCHCL(2) tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ(2) tCLQV tCLQX tQLQH(2) tQHQL
(2)
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time
tHHQV tHLQZ(2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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M95040, M95020, M95010 Table 22. AC characteristics (M950x0-R)
DC and AC parameters
Test conditions specified in Table 11 and Table 10 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL(1) tCLCH tCHCL
(2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency
Parameter
Min. D.C. 200 200 200 200 200 200 200
Max. 2
Unit MHz ns ns ns ns ns ns ns
S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time
tCLH tCLL tRC tFC tDSU tDH
Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock Low Setup Time before HOLD Active Clock Low Setup Time before HOLD not Active
1 1 40 50 140 90 0 0 250 180 0 100 100 100 250 10
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ(2) tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ(2) tW
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Figure 15. Serial input timing
M95040, M95020, M95010
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 16. Hold timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQV tHHCH
D
HOLD
AI01448B
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M95040, M95020, M95010 Figure 17. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
DC and AC parameters
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
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Package mechanical
M95040, M95020, M95010
10
Package mechanical
Figure 18. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 23.
SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data
millimeters inches Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 - 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 - 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
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M95040, M95020, M95010
Package mechanical
Figure 19. TSSOP8 - 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 24.
TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data
millimeters inches Max. 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
Symbol
Typ. A A1 A2 b c CP D e E E1 L L1 N (number of pins)
Min.
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Package mechanical
M95040, M95020, M95010
Figure 20. UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale.
Table 25.
UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3mm, package mechanical data
millimeters inches Max 0.60 0.05 0.30 0.010 0.079 1.55 1.65 0.05 3.00 0.15 0.50 0.45 - 0.40 0.25 - 0.50 0.15 0.30 8 0.012 8 0.020 0.018 0.118 0.006 - 0.016 0.010 - 0.020 0.006 0.061 0.065 0.002 Typ 0.022 Min 0.020 0.000 0.008 Max 0.024 0.002 0.012
Symbol Typ A A1 b D D2 ddd E E2 e L L1 L3 N (number of pins) 0.25 2.00 0.55 Min 0.50 0.00 0.20
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M95040, M95020, M95010
Part numbering
11
Part numbering
Table 26.
Example: Device Type M95 = SPI serial access EEPROM Device Function 040 = 4 Kbit (512 x 8) 020 = 2 Kbit (256 x 8) 010 = 1 Kbit (128 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MB = UFDFPN8 (MLP8) 2 x 3mm Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with High Reliability Certified Flow(1). Automotive temperature range (-40 to 125 C) Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P or G = ECOPACK(R) (RoHS compliant) Process(2) /W, /G or /S = F6SP36%
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Used only for Device Grade 3
Ordering information scheme
M95040 - W MN 6 T P /W
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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Revision history
M95040, M95020, M95010
12
Revision history
Table 27.
Date 10-May-2000
Document revision history
Version 2.2 Changes s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab 9. Wording changes, according to the standard glossary Illustrations and Package Mechanical data updated Temperature range `3' added to the -W supply voltage range in DC and AC characteristics Document reformatted using the new template Description of chip deselect after 8th clock pulse made more explicit Position of A8 in Read Instruction Sequence Figure corrected. Load Capacitance CL changed Minimum values for tCHHL and tCHHH changed. Description of Read from Memory Array (READ) instruction corrected, and clarified New products, identified by the process letter W, added Correction to current products, identified by the process letter K not L. ICC changed in DC characteristics, and tCHHL, tCHHH substituted in AC characteristics Voltage range -S upgraded by removing it, and adding the -R voltage range in its place Temperature range 5 removed. Table of contents, and Pb-free options added. VIL(min) improved to -0.45V VIL(max) and tCLQV(max) changed Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature information clarified for RoHS compliant devices. New 5V and 2.5V devices, with process letter W, promoted from preliminary data to full data. Device Grade 3 clarified, with reference to HRCF and automotive environments
16-Mar-2001
2.3
19-Jul-2001 11-Oct-2001 26-Feb-2002 27-Sep-2002 24-Oct-2002 24-Feb-2003 28-May-2003
2.4 3.0 3.1 3.2 3.3 3.4 3.5
25-Jun-2003
3.6
21-Nov-2003 02-Feb-2004
4.0 4.1
01-Mar-2004
5.0
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M95040, M95020, M95010 Table 27.
Date
Revision history
Document revision history (continued)
Version Changes Product List summary table added. Process identification letter "G" information added. Order information for Tape and Reel changed to T. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX corrected to tHHQV. Signal Description updated. 10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified Document converted to new template, Table 5: Status Register format moved to below Section 6.3: Read Status Register (RDSR). PDIP package removed. UFDFPN8 (MB) package added (see Figure 20 and Table 25) and SO8N package specifications updated (see Figure 18 and Table 23). Packages are ECOPACK(R) compliant. Section 6.7: Cycling added. Section 2.8: Supply voltage (VCC) added and information removed below Section 4: Operating features. Figure 3: Bus master and memory devices on the SPI bus modified. TLEAD parameter modified, Note 1 changed, and TA added to Table 7: Absolute maximum ratings. Characteristics of previous product identified by process letter K removed. CL modified in Table 11: AC test measurement conditions. Note removed below Table 13 and Table 14. Information in Table 17 is no longer Preliminary data, ICC, ICC1 and VIL modified. End timing line of tSHQZ moved in Figure 17. tCHHL and tCHHH changed to tCLHL and tCLHH, respectively in Figure 16, Table 18, Table 19, Table 20, Table 21 and Table 22. Plating Technology and Process updated in Table 26: Ordering information scheme.
05-Oct-2004
6.0
06-Nov-2006
7
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M95040, M95020, M95010
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