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19-3594; Rev 0; 2/05
KIT ATION EVALU ABLE AVAIL
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
General Description Features
6 Configurable Input Voltage Detectors Programmable Thresholds 0.5V to 3.05V (in 10mV Increments) or 1V to 5.8V (in 20mV Increments) Primary UV and Secondary UV/OV Thresholds One Configurable Watchdog Timer from 6.25ms to 102.4s Configurable RESET, UV/OV, and WDO Outputs Three Programmable Outputs Open-Drain or Weak Pullup RESET, UV/OV, and WDO Active-Low Output Logic Timing Delays from 25s to 1600ms Margining Disable and Manual Reset Controls Internal 1.25V Reference or External Reference Input 10-Bit Internal ADC Samples the Input Voltage Detectors, VCC and Auxiliary Input 512-Bit User EEPROM Endurance: 100,000 Erase/Write Cycles Data Retention: 10 Years SMBus/I2C-Compatible Serial Configuration/Communication Interface 1% Threshold Accuracy
MAX6884/MAX6885
The MAX6884/MAX6885 EEPROM-configurable, multivoltage power-supply supervisors monitor six voltagedetector inputs, one auxiliary input, and one watchdog input, and feature three programmable outputs for highly configurable power-supply monitoring applications. Manual reset and margin disable inputs offer additional flexibility. Each voltage-detector input offers a programmable primary undervoltage and secondary undervoltage/overvoltage threshold. Voltage-detector inputs IN1-IN6 monitor voltages from 1V to 5.8V in 20mV increments or 0.5V to 3.05V in 10mV increments. Programmable outputs RESET, UV/OV, and WDO provide system resets/interrupts. Programmable output options include open-drain or weak pullup. Programmable timing delay blocks configure each output to wait between 25s and 1600ms after their respective assertion-causing conditions have been cleared. A fault register logs condition-causing events (undervoltage, overvoltage, manual reset, etc.). An internal 10-bit, 1% accurate ADC (MAX6884 only) converts the voltages at IN1-IN6, AUXIN, and V CC through a multiplexer that automatically sequences through all inputs every 200ms. An SMBusTM/I2C-compatible serial data interface programs and communicates with the configuration EEPROM, configuration registers, internal 512-bit user EEPROM, and reads the ADC registers (MAX6884 only) and fault registers. The MAX6884/MAX6885 are available in a 5mm x 5mm x 0.8mm 20-pin thin QFN package and operate over the extended temperature range (-40C to +85C).
Ordering Information
PART MAX6884ETP MAX6885ETP TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 20 Thin QFN 20 Thin QFN PKG CODE T2055-5 T2055-5
Applications
Telecommunications/Central-Office Systems Networking Systems Servers/Workstations Base Stations Storage Equipment Multimicroprocessor/Voltage Systems
Pin Configurations and Typical Operating Circuit appear at end of data sheet.
Selector Guide
PART MAX6884ETP MAX6885ETP VOLTAGEDETECTOR INPUTS 6 6 INTERNAL ADC Yes No PROGRAMMABLE REFERENCE INPUT OUTPUTS 3 3 Yes No AUXILIARY INPUT Yes No
________________________________________________________________ Maxim Integrated Products
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) IN1-IN6, VCC, RESET, UV/OV, WDO........................-0.3V to +6V WDI, MR, MARGIN, SDA, SCL, A0...........................-0.3V to +6V AUXIN, DBP, REFIN .................................................-0.3V to +3V Input/Output Current (all pins)..........................................20mA Continuous Power Dissipation (TA = +70C) 20-Pin (5mm x 5mm) Thin QFN (derate 21.3mW/C above +70C) .............................1702mW Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN1-VIN4 or VCC = 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER Operating Voltage Range Undervoltage Lockout Digital Bypass Voltage VUVLO VDBP SYMBOL CONDITIONS Voltage on either one of IN1-IN4 or VCC to guarantee the device is fully operational Minimum voltage on one of IN1-IN4 or VCC to guarantee device is EEPROM configured No load VIN1 = 5.8V, IN2-IN6 = GND, no load Supply Current ICC Writing to configuration registers or EEPROM, no load VIN1-VIN6 (in 20mV increments) Threshold Range VTH VIN1-VIN6 (in 10mV increments) VIN1-VIN6 (Inputs high impedance; in 3.3mV increments) VIN_ = 2.5V to 5.8V (20mV increments) VIN_ = 1V to 2.5V (20mV increments) VIN_ = 1.25V to 3.05V (10mV increments) VIN_ = 0.5V to 1.25V (10mV increments) VIN_ = 2.5V to 5.8V (20mV increments) VIN_ = 1V to 2.5V (20mV increments) VIN_ = 1.25V to 3.05V (10mV increments) VIN_ = 0.5V to 1.25V (10mV increments) 1.0 0.50 0.167 -1 -25 -1 -12.5 -1.5 -25 -1.5 -12.5 2.48 2.55 0.9 1.1 MIN 2.7 TYP MAX 5.8 2.5 2.67 1.2 1.5 5.8 3.05 1.017 +1 +25 +1 +12.5 +1.5 +25 +1.5 +12.5 % mV % mV % mV % mV V UNITS V V V mA mA
TA = +25C to +85C, (VIN_ falling)
IN1-IN6 Threshold Accuracy
TA = -40C to +85C, (VIN_ falling)
2
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VIN1-VIN4 or VCC = 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER Threshold Hysteresis Threshold Tempco Threshold Differential Nonlinearity IN_ Input Impedance IN_ Input Leakage Current Power-Up Delay IN_ to RESET or UV/OV Delay SYMBOL VTH-HYST VTH/C VTH DNL RIN IIN_LKG tD-PO tD-R For VIN_ < highest of VIN1-IN4 and VIN_ < VCC IN_ high impedance VCC VUVLO IN_ falling/rising, 100mV overdrive 000 001 010 RESET and UV/OV Timeout Period (Tables 6 and 7) tRP, tUP 011 100 101 110 111 RESET, UV/OV, WDO Output Low RESET, UV/OV, WDO Output Open-Drain Leakage Current RESET, UV/OV, WDO Output Pullup Resistance MR, MARGIN, WDI Input Voltage MR Input Pulse Width MR Glitch Rejection RPU VIL VIH tMR 1.4 1 100 ISINK = 4mA, output asserted Output high impedance VRESET, VUV/OV, VWDO = 2V -1 6.6 10 1.406 5.625 22.5 45 180 360 1440 20 0.025 1.5625 6.25 25 50 200 400 1600 1.719 6.875 27.5 55 220 440 1760 0.4 +1 15.0 0.6 V A k V s ns ms -1 130 -150 200 CONDITIONS MIN TYP 0.3 10 +1 300 +150 2.5 MAX UNITS % VTH ppm/C LSB k nA ms s
MAX6884/MAX6885
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
ELECTRICAL CHARACTERISTICS (continued)
(VIN1-VIN4 or VCC = 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER MR to RESET or UV/OV Delay MR to Internal VDBP Pullup Current MARGIN to DBP Pullup Current WDI Pulldown Current WDI Input Pulse Width SYMBOL tD-MR IMR IMARGIN IWDI tWDI 000 001 010 Watchdog Timeout Period (Table 8) tWD 011 100 101 110 111 Reference Input Voltage Range Reference Input Resistance VREF RREF MAX6884 only VREF = 1.25V, MAX6884 only IN1-IN6, VCC; LSB = 7.32mV, MAX6884 only ADC Range ADCRANGE IN1-IN6; LSB = 3.66mV, MAX6884 only AUXIN, IN1-IN6 high-impedance mode; LSB = 1.2mV, MAX6884 only Internal reference, MAX6884 only External reference, MAX6884 only (Note 5) MAX6884 only (Note 6) Converts all six IN_ inputs, AUXIN, and VCC, MAX6884 only VAUXIN = 1.25V, MAX6884 only -1 1 200 266 +1 0.8 2.0 1 ISINK = 3mA 0.4 10 0 0 0 VMR = 1.4V VMARGIN = 1.4V VWDI = 0.6V 5 5 5 50 5.625 22.5 90 360 1.44 5.76 23.04 92.16 1.225 6.25 25 100 400 1.60 6.40 25.60 102.40 1.25 500 5.8 3.746 1.25 1.0 1.0 %FSR LSB ms A V V A V pF V 6.875 27.5 110 440 1.76 7.04 28.16 112.64 1.275 V k s ms CONDITIONS MIN TYP 200 10 10 10 15 15 15 MAX UNITS ns A A A ns
ADC Total Unadjusted Error (Note 4) ADC Differential Nonlinearity ADC Total Monitoring Cycle Time AUXIN Input Leakage Current Logic-Input Low Voltage Logic-Input High Voltage Input Leakage Current Output-Voltage Low Input/Output Capacitance
TUE DNL tC IAUXIN VIL VIH ILKG VOL CI/O
SERIAL INTERFACE LOGIC (SDA, SCL, A0)
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
TIMING CHARACTERISTICS
(VIN1-VIN4 or VCC = 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TIN1 = +25C.) (Notes 1, 2, 3)
PARAMETER Serial Clock Frequency Clock Low Period Clock High Period Bus Free Time START Setup Time START Hold Time STOP Setup Time Data In Setup Time Data In Hold Time Receive SCL/SDA Minimum Rise Time Receive SCL/SDA Maximum Rise Time Receive SCL/SDA Minimum Fall Time Receive SCL/SDA Maximum Fall Time Transmit SDA Fall Time Pulse Width of Spike Suppressed EEPROM Byte Write Cycle Time SYMBOL fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tR tF tF tF tSP tWR (Note 7) (Note 7) (Note 7) (Note 7) CBUS = 400pF (Note 5) (Note 8) (Note 9) 20 + 0.1 x CBUS 50 11 1.3 0.6 1.3 0.6 0.6 0.6 100 30 20 + 0.1 x CBUS 300 20 + 0.1 x CBUS 300 300 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s s ns ns ns ns ns ns ns ns ms
MAX6884/MAX6885
TIMING CHARACTERISTICS (Figure 6)
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
100% production tested at TA = +25C and TA = +85C. Specifications at TA = -40C are guaranteed by design. Device may be supplied from IN1-IN4 or VCC. The internal supply voltage, measured at VCC, equals the maximum of IN1-IN4. VIN_ > 0.3 x ADC range. Does not include the inaccuracy of the 1.25V input reference voltage (MAX6884 only). DNL is implicitly guaranteed by design in a converter. CBUS = total capacitance of one bus line in picofarads. Rise and fall times are measured between 0.1 x VBUS and 0.9 x VBUS. Note 8: Input filters on SDA, SCL, and A0 suppress noise spikes <50ns. Note 9: An additional cycle is required when writing to configuration memory for the first time.
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Typical Operating Characteristics
(VIN1-VIN4 or VCC = 5V, AUXIN = WDI = GND, MARGIN = MR = DBP. Typical values are at TA = +25C, unless otherwise noted.)
VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE
MAX6884 toc01
IN1-IN4 SUPPLY CURRENT vs. IN1-IN4 SUPPLY VOLTAGE
MAX6884 toc02
NORMALIZED RESET OR UV/0V TIMEOUT PERIOD vs. TEMPERATURE
NORMALIZED RESET TIMEOUT PERIOD 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -40 -15 10 35 60 85
MAX8664 toc03
1.00 0.95 SUPPLY CURRENT (mA) TA = +85C 0.90 0.85 0.80 0.75 0.70 2.6 3.6 4.6 5.6 SUPPLY VOLTAGE (V) TA = -40C TA = +25C
1.00 0.95 SUPPLY CURRENT (mA) 0.90 0.85 0.80 0.75 0.70 2.6 3.6 4.6 5.6 SUPPLY VOLTAGE (V) TA = -40C TA = +25C
1.020
TA = +85C
TEMPERATURE (C)
IN_ TO RESET OR UV/OV PROPAGATION DELAY vs. TEMPERATURE
MAX6884toc04
NORMALIZED WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
NORMALIZED WATCHDOG TIMEOUT PERIOD
MAX8664 toc05
NORMALIZED IN_ THRESHOLD vs. TEMPERATURE
1.004 NORMALIZED IN_ THRESHOLD 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995
MAX6884 toc06
30 29 PROPAGATION DELAY (s) 28 27 26 25 24 23 22 21 20
100mV OVERDRIVE
1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -40 -15 10 35 60
1.005
-40
-15
10
35
60
85
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
MAXIMUM IN_ TRANSIENT vs. IN_ THRESHOLD OVERDRIVE
MAX6884 toc07
OUTPUT VOLTAGE LOW vs. SINK CURRENT
MAX8664 toc08
OUTPUT VOLTAGE HIGH vs. SOURCE CURRENT (WEAK PULLUP)
2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.05 0.10 0.15 0.20 0.25 SOURCE CURRENT (mA)
MAX8664 toc09
200 MAXIMUM TRANSIENT DURATION (s) 175 150 125 100 75 50 25 0 1 10 100 RESET OR UV/OV ASSERTS ABOVE THIS LINE
400 350 OUTPUT VOLTAGE LOW (mV) 300 250 200 150 100 50 0
OUTPUT VOLTAGE HIGH (V)
1000
0
2
4
6
8
10
12
14
0.30
IN_ THRESHOLD OVERDRIVE (mV)
SINK CURRENT (mA)
6
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Typical Operating Characteristics (continued)
(VIN1-VIN4 or VCC = 5V, AUXIN = WDI = GND, MARGIN = MR = DBP. Typical values are at TA = +25C, unless otherwise noted.)
MR TO RESET OR UV/OV OUTPUT PROPAGATION DELAY vs. TEMPERATURE
MAX6884 toc10
ADC ACCURACY vs. TEMPERATURE
0.4 TOTAL UNADJUSTED ERROR (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 VAUXIN = 1V VIN5 = 2V, 10mV/STEP RANGE VIN1 = 5V, 20mV/STEP RANGE
MAX6884 toc11
3.00 2.75 PROPAGATION DELAY (s) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 -40 -15 10 35 60
0.5
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
Pin Description
PIN MAX6884 1 MAX6885 1 NAME RESET FUNCTION Reset Output. Configurable, active-low, open drain, or weak pullup. RESET assumes its programmed conditional output state when VCC exceeds UVLO (2.5V). Watchdog Timer Output. Configurable, active-low, open drain, or weak pullup. WDO asserts when WDI is not toggled with a valid high-to-low or low-to-high transition within the watchdog timeout period. Undervoltage/Overvoltage Output. Configurable, active-low, open drain, or weak pullup. UV/OV assumes its programmed conditional output state when VCC exceeds UVLO (2.5V). Ground Watchdog Timer Input. Logic input for the watchdog timer function. If WDI is not toggled with a valid low-to-high or high-to-low transition within the watchdog timeout period, WDO asserts. Progam initial and normal watchdog timeout periods from 6.25ms to 102.4s. WDI is internally pulled down to GND through a 10A current sink. Manual Reset Input. Program MR to assert RESET and/or UV/OV when MR is asserted. Leave MR unconnected or connect to DBP if unused. MR is internally pulled up to DBP through a 10A current source.
2
2
WDO
3 4
3 4
UV/OV GND
5
5
WDI
6
6
MR
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Pin Description (continued)
PIN MAX6884 MAX6885 NAME FUNCTION Margin Input. MARGIN holds RESET, UV/OV, and WDO in their existing states when MARGIN is driven low. Leave MARGIN unconnected or connect to DBP if unused. MARGIN is internally pulled up to DBP through a 10A current source. MARGIN overrides MR if both are asserted at the same time. Serial Data Input/Output (Open Drain). SDA requires an external pullup resistor. Serial-Interface Clock Input. SCL requires an external pullup resistor. Serial Address Input 0. Allows up to 2 devices to share a common bus. Connect A0 to ground or the serial-interface power supply. Reference Voltage Input. Program the device for external or internal reference. Connect an external +1.225V to +1.275V reference to REFIN when using an external reference. Leave REFIN unconnected when using the internal reference. Auxiliary Input. A 10-bit ADC converts the input voltage at AUXIN. The high-impedance AUXIN input accepts input voltages up to 1.25V. AUXIN does not affect programmable outputs. No Connection. Not internally connected. Internal Power-Supply Voltage. Bypass VCC to GND with a 1F ceramic capacitor as close to the device as possible. VCC supplies power to the internal circuitry. VCC is internally powered from the highest of the monitored IN1-IN4 voltages. Do not use VCC to supply power to external circuitry. To externally supply VCC, see the Powering the MAX6884/MAX6885 section. Internal Digital Power-Supply Voltage. Bypass DBP to GND with a 1F ceramic capacitor. DBP supplies power to the EEPROM memory, the internal logic circuitry, and the programmable outputs. Do not use DBP to supply power to external circuitry. Voltage-Detector Input 6. Program two thresholds per voltage-detector input (undervoltage UV and undervoltage/overvoltage UV/OV). Program IN6 detector thresholds from 1V to 5.8V in 20mV increments, 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN6 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage-Detector Input 5. Program two thresholds per voltage-detector input (undervoltage UV and undervoltage/overvoltage UV/OV). Program IN5 detector thresholds from 1V to 5.8V in 20mV increments, 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN5 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage-Detector Input 4. Program two thresholds per voltage-detector input (undervoltage UV and undervoltage/overvoltage UV/OV). Program IN4 detector thresholds from 1V to 5.8V in 20mV increments, 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN4 to GND with a 0.1F capacitor installed as close to the device as possible. Program the device to receive power through IN1-IN4 inputs or VCC (see the Powering the MAX6884/MAX6885 section).
7
7
MARGIN
8 9 10
8 9 10
SDA SCL A0
11
--
REFIN
12 --
-- 11, 12
AUXIN N.C.
13
13
VCC
14
14
DBP
15
15
IN6
16
16
IN5
17
17
IN4
8
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
Pin Description (continued)
PIN MAX6884 MAX6885 NAME FUNCTION Voltage-Detector Input 3. Program two thresholds per voltage-detector input (undervoltage UV and undervoltage/overvoltage UV/OV). Program IN3 detector thresholds from 1V to 5.8V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN3 to GND with a 0.1F capacitor installed as close to the device as possible. Program the device to receive power through IN1-IN4 inputs or VCC (see the Powering the MAX6884/MAX6885 section). Voltage-Detector Input 2. Program two thresholds per voltage-detector input (undervoltage UV and undervoltage/overvoltage UV/OV). Program IN2 detector thresholds from 1V to 5.8V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN2 to GND with a 0.1F capacitor installed as close to the device as possible. Program the device to receive power through IN1-IN4 inputs or VCC (see the Powering the MAX6884/MAX6885 section). Voltage-Detector Input 1. Program two thresholds per voltage-detector input (undervoltage UV and undervoltage/overvoltage UV/OV). Program IN1 detector thresholds from 1V to 5.8V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN1 to GND with a 0.1F capacitor installed as close to the device as possible. Program the device to receive power through IN1-IN4 inputs or VCC (see the Powering the MAX6884/MAX6885 section). Exposed Paddle. Internally connected to GND. Connect EP to GND or leave floating.
MAX6884/MAX6885
18
18
IN3
19
19
IN2
20
20
IN1
--
--
EP
Detailed Description
The MAX6884/MAX6885 EEPROM-configurable, multivoltage supply supervisors monitor six voltage-detector inputs, one auxiliary input, and one watchdog input, and feature three programmable outputs for highly configurable, power-supply monitoring applications (see Table 1 for programmable features). Manual reset and margin disable inputs offer additional flexibility. Each voltage detector provides a programmable primary undervoltage and secondary undervoltage/overvoltage threshold. Program thresholds from 0.5V to 3.05V in 10mV increments, 1.0V to 5.8V in 20mV increments, or from 0.1667V to 1.0167V in 3.3mV increments. To achieve thresholds from 0.1667V to 1.0167V in 3.3mV increments, the respective input voltage detector must be programmed for high impedance and an external voltage-divider must be connected. A fault register logs undervoltage and overvoltage conditions for each voltage-detector input.
An internal 10-bit ADC (MAX6884 only) converts voltages at IN1-IN6, AUXIN, and VCC through a multiplexer that automatically sequences through all inputs every 200ms. Access the device's internal 512-bit user EEPROM, configuration EEPROM, configuration registers, ADC registers, and fault registers through an SMBus/I 2 C-compatible serial interface (see the SMBus/I2C-Compatible Serial Interface section). The MAX6884/MAX6885 also feature an accurate internal 1.25V reference. For greater accuracy, connect an external 1.25V reference to REFIN (MAX6884 only). Program outputs RESET, UV/OV, and WDO for opendrain or weak pullup. Program RESET and UV/OV to assert on any voltage-detector input, MR, or each other. RESET can also depend on WDO. Programmable timing delay blocks configure each output to wait between 25s and 1600ms before deasserting. Fault registers log the assertion of RESET, UV/OV, and WDO.
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
The MAX6884/MAX6885 feature a watchdog timer with programmable initial and normal timeout periods from 6.25ms to 102.4s. WDO asserts when WDI is not toggled from high-to-low or low-to-high within the appropriate watchdog timeout period. Program WDO to assert RESET. Program the MAX6884/MAX6885 to receive power through IN1-IN4 or V CC (see the Powering the MAX6884/MAX6885 section). Outputs remain asserted while the voltage that is supplying the device is below UVLO (2.5V) and above 1V (see Figure 1).
Table 1. Programmable Features
FEATURE * * * * * DESCRIPTION Primary undervoltage threshold Secondary undervoltage or overvoltage threshold 1V to 5.8V thresholds in 20mV increments 0.5V to 3.05V thresholds in 10mV increments 0.1667V to 1.017V thresholds in 3.3mV increments in high-impedance mode
Input Voltages IN1-IN6
Programmable Output RESET
Programmable Output UV/OV Programmable Output WDO Watchdog Timer
* Dependency on IN1-IN6, MR, UV/OV, and/or WDO * Active-low, weak pullup, or open-drain output * Programmable timeout periods of 25s, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms, or 1.6s * Dependency on IN1-IN6, MR, and/or RESET * Active-low, weak pullup, or open-drain output * Programmable timeout periods of 25s, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms, or 1.6s * Active-low, weak pullup, or open-drain output * Initial watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s * Normal watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s * Watchdog enable/disable * Programs whether the device is powered from the highest IN_ input or from an external supply connected to VCC * Program RESET or UV/OV to assert while MR is asserted * * * * * * * * Internal +1.25V reference voltage Goes high impedance when internal reference is selected External reference voltage input from 1.225V to 1.275V Sets ADC voltage range Samples voltages at IN1-IN6, AUXIN, and VCC Completes conversion of all eight inputs in 200ms Reference voltage sets ADC range Read ADC data from SMBus/I2C interface
VCC Power Mode Manual Reset Input MR
Reference Input REFIN
10-Bit ADC*
Write Disable Configuration Lock
* Locks user EEPROM based on RESET or UV/OV assertion * Locks configuration registers and EEPROM
*ADC does not affect programmable outputs.
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
IN_
COMPARATORS
LOGIC NETWORK FOR OUTPUTS
OUTPUT STAGES
RESET UV/OV WDO
MR MARGIN
WATCHDOG TIMER (ADC MUX) AUXIN, VCC SDA, SCL SERIAL INTERFACE (ADC) (ADC REGISTERS)
WDI, RESET
REGISTER BANK EEPROM (USER AND CONFIG)
A0 ANALOG BLOCK DIGITAL BLOCK BOOT CONTROLLER
MAX6884 MAX6885
( ) MAX6884 ONLY
Figure 1. Top-Level Block Diagram
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Functional Diagram
WDI
MARGIN
MR
2.55V LDO IN1 IN_ DETECTOR
RESET OUTPUT
WEAK PULLUP OR OPEN-DRAIN SWITCH 10k RESET
PROGRAMMABLE ARRAY
RESET TIMING BLOCK UV/OV TIMING BLOCK UV/OV OUTPUT UV/OV WDO
IN2 IN3 IN4 IN5 IN6 REFIN (N.C.) AUXIN (N.C.)
IN2 DETECTOR IN3 DETECTOR IN4 DETECTOR IN5 DETECTOR IN6 DETECTOR
WATCHDOG TIMING BLOCK MAIN OSCILLATOR
WDO OUTPUT
ADC MUX
ADC TIMING
VCC 1F 2.55V LDO
VIRTUAL DIODES
ADC
ADC REGISTERS IN1 IN2 IN3 IN4 IN5 IN6 VCC AUXIN
EEPROM CHARGE PUMP CONFIG CONFIG REGISTERS EEPROM USER EEPROM
1.25V REFERENCE
(MAX6884 ONLY) SDA SERIAL INTERFACE SCL A0
DBP 1F
MAX6884 MAX6885
( ) MAX6885 ONLY GND *SEE THE EXTERNAL VOLTAGE-DIVIDER SECTION FOR HIGH-IMPEDANCE ARCHITECTURE.
12
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
Powering the MAX6884/MAX6885
The MAX6884/MAX6885 derive power from the voltagedetector inputs: IN1-IN4 or through an externally supplied VCC. A virtual diode-ORing scheme selects the positive input that supplies power to the device (see the Functional Diagram). The highest input voltage on IN1-IN4 supplies power to the device. One of VIN1-VIN4 must be at least 2.7V to ensure proper operation. Internal hysteresis ensures that the supply input that initially powered the device continues to power the device when multiple input voltages are within 50mV of each other. VCC powers the analog circuitry and is the bypass connection for the MAX6884/MAX6885 internal supply. Bypass V CC to GND with a 1F ceramic capacitor installed as close to the device as possible. The internal supply voltage, measured at VCC, equals the maximum of IN1-IN4. If VCC is externally supplied, VCC must be at least 200mV higher than any voltage applied to IN-IN4 and VCC must be brought up first. VCC always powers the device when all IN_ are factory set as "ADJ." Do not use the internally generated VCC to provide power to external circuitry. Externally supply power through VCC. To externally supply power through VCC: 1) Apply a voltage to only one of VCC (2.7V to 5.5V) or IN1-IN4 (2.7V to 5.8V). 2) Program the internal/external VCC Power EEPROM at 96h, Bit[5] = 1 (see Table 2). 3) Power down the device. Subsequent power-ups and software reboots require an externally supplied VCC to ensure the device is fully operational.
ADC (MAX6884 Only)
An internal 10-bit ADC (MAX6884 only) converts voltages at IN1-IN4, AUXIN, and VCC through a multiplexer that automatically sequences through all inputs every 200ms. Registers 18h to 27h store the ADC data (see Table 3). Read the ADC data from the MAX6884 with the serial interface. The ADC has no effect on programmable outputs RESET, UV/OV, or WDO.
MAX6884/MAX6885
Inputs
The MAX6884/MAX6885 offer the following inputs: voltage-detector inputs IN1-IN4, auxiliary input AUXIN (MAX6884 only), manual reset input MR, margin input MARGIN, and reference input REFIN (MAX6884 only). IN1-IN6 The MAX6884/MAX6885 offer six voltage-detector inputs: IN1-IN6. Each voltage-detector input offers a programmable primary undervoltage threshold and a secondary undervoltage/overvoltage threshold. Program thresholds from 0.5V to 3.05V in 10mV increments, 1.0V to 5.8V in 20mV increments, or from 0.1667V to 1.0167V in 3.3mV increments. Use the following equations to program thresholds in the appropriate registers:
- 1V V X = TH 0.02V
for 1V to 5.8V range in 20mV increments (program bits R0Fh[5:0]).
- 0.5V V X = TH 0.01V
Table 2. Internal/External VCC
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION
for 0.5V to 3.05V range in 10mV increments (program bits R0Fh[5:0]).
- 0.1667V V X = TH 0.0033V
[5] 16h 96h [2] [4] [6]
1 = VCC Powered 0 = IN1-IN4 or VCC Powered Not Used Not Used Not Used
for 0.1667V to 1.0167V in 3.3mV increments (see the External Voltage-Divider section). where VTH is the desired threshold voltage and X is the decimal code for the desired threshold (see Table 4). To set a threshold for the 1V to 5.8V range, X must equal 240 or less. Set the secondary threshold for an undervoltage or overvoltage threshold by programming bits R0Eh[5:0]. To achieve thresholds in between the 10mV and 20mV steps or to monitor voltages higher than 5.8V, program a voltage-detector input for high impedance through bits R10h[5:0] and add a resister voltage-divider (see the External Voltage-Divider section).
13
The MAX6884/MAX6885 also generate a digital supply voltage (DBP) for the internal logic circuitry and the EEPROM. Bypass DBP to GND with a 1F ceramic capacitor installed as close to the device as possible. The nominal DBP output voltage is 2.55V. Do not use DBP to provide power to external circuitry.
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Table 3. ADC Registers (MAX6884 Only)
REGISTER ADDRESS 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h BIT RANGE [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] DESCRIPTION ADC IN1 Conversion Result (8 MSBs) ADC IN1 Conversion Result (2 LSBs) Not Used ADC IN2 Conversion Result (8 MSBs) ADC IN2 Conversion Result (2 LSBs) Not Used ADC IN3 Conversion Result (8 MSBs) ADC IN3 Conversion Result (2 LSBs) Not Used ADC IN4 Conversion Result (8 MSBs) ADC IN4 Conversion Result (2 LSBs) Not Used ADC IN5 Conversion Result (8 MSBs) ADC IN5 Conversion Result (2 LSBs) Not Used ADC IN6 Conversion Result (8 MSBs) ADC IN6 Conversion Result (2 LSBs) Not Used ADC AUXIN Conversion Result (8 MSBs) ADC AUXIN Conversion Result (2 LSBs) Not Used ADC VCC Conversion Result (8 MSBs) ADC VCC Conversion Result (2 LSBs) Not Used
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Table 4. IN1-IN6 Threshold Register Settings
REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh EEPROM MEMORY ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh BIT RANGE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [0] [1] 0Eh 8Eh [2] [3] [4] [5] [7:6] [0] [1] 0Fh 8Fh [2] [3] [4] [5] [7:6] [0] [1] 10h 90h [2] [3] [4] [5] [7:6] DESCRIPTION IN1 Primary Undervoltage Detector Threshold (see equations in the IN1-IN6 section) IN2 Primary Undervoltage Detector Threshold IN3 Primary Undervoltage Detector Threshold IN4 Primary Undervoltage Detector Threshold IN5 Primary Undervoltage Detector Threshold IN6 Primary Undervoltage Detector Threshold IN1 Secondary Undervoltage/Overvoltage Detector Threshold (see equations in the IN1-IN6 section) IN2 Secondary Undervoltage/Overvoltage Detector Threshold IN3 Secondary Undervoltage/Overvoltage Detector Threshold IN4 Secondary Undervoltage/Overvoltage Detector Threshold IN5 Secondary Undervoltage/Overvoltage Detector Threshold IN6 Secondary Undervoltage/Overvoltage Detector Threshold IN1 Secondary Undervoltage or Overvoltage Selection 0 = Undervoltage 1 = Overvoltage IN2 Secondary Undervoltage or Overvoltage Selection IN3 Secondary Undervoltage or Overvoltage Selection IN4 Secondary Undervoltage or Overvoltage Selection IN5 Secondary Undervoltage or Overvoltage Selection IN6 Secondary Undervoltage or Overvoltage Selection Not Used IN1 Voltage Threshold Range 0 = 1V to 5.8V (20mV steps) 1 = 0.5V to 3.05V (10mV steps) IN2 Voltage Threshold Range IN3 Voltage Threshold Range IN4 Voltage Threshold Range IN5 Voltage Threshold Range IN6 Voltage Threshold Range Not Used IN1 Input Impedance 0 = Normal Mode 1 = High-Z Mode (connect external resistor voltage-divider) IN2 Input Impedance IN3 Input Impedance IN4 Input Impedance IN5 Input Impedance IN6 Input Impedance Not Used
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
External Voltage-Divider To achieve thresholds from 0.1667V to 1.0167V in 3.3mV increments, program the respective input voltage detector for high impedance and use an external voltage-divider (see Figure 2). Set voltage-detector inputs for high impedance by programming bits R10h[5:0]. Design the resistor voltage-divider to scale the input voltage to between 0.1667V and 1.0167V at the input of the device. In this way, voltages higher than 5.8V and in between the 10mV and 20mV steps can be monitored. Program R00h through R0Eh to adjust the thresholds between 0.1667V and 1.0167V in 3.3mV steps. AUXIN (MAX6884 Only) The AUXIN high-impedance analog input is intended to monitor additional system voltages not required for reset purposes. The internal 10-bit ADC converts the voltage at AUXIN and stores the data in the ADC registers (see Table 3). AUXIN does not affect any of the programmable outputs. The AUXIN input accepts power-supply voltages or other system voltages scaled to the 1.25V ADC input voltage range.
MR Program RESET and/or UV/OV to assert when manual reset input MR is brought low (see Tables 5 and 6). Outputs programmed to assert when MR is brought low remain asserted after MR is brought high for their respective programmed timeout periods. An internal 10A current source pulls MR to V DBP . Leave MR unconnected or connect to DBP if unused. MARGIN MARGIN allows system-level testing while power supplies exceed the normal ranges. Drive MARGIN low to hold the programmable outputs in their existing state while system-level testing occurs. Leave MARGIN unconnected or connect to DBP if unused. An internal 10A current source pulls MARGIN to VDBP. The internal ADC continues to convert voltages while MARGIN is low. The state of each programmable output does not change while MARGIN = GND. MARGIN overrides MR if both are asserted at the same time.
REFIN (MAX6884 Only) The MAX6884/MAX6885 feature an internal 1.25V voltage reference. The voltage reference sets the threshold of the voltage detectors and provides a reference voltage for the internal ADC. Program the MAX6884 to use an internal or external reference by programming bit R16h[7] (see Table 5). Leave REFIN unconnected when using the internal reference. REFIN accepts an external reference in the 1.225V to 1.275V range.
VIN MAX6884 MAX6885
IN_
Table 5. Internal/External Reference
PRIMARY REGISTER
REGISTER ADDRESS
EEPROM MEMORY ADDRESS
BIT RANGE
DESCRIPTION
16h
SECONDARY REGISTER
96h
[7]
1 = Enable External Reference 0 = Enable Internal Reference
Figure 2. External Voltage-Divider Architecture
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
Programmable Outputs
The MAX6884/MAX6885 feature three programmable active-low outputs: RESET, UV/OV, and WDO. Program each output for open-drain or weak pullup. An internal 10k resistor connected from each output to a 2.55V internal LDO provides a weak pullup. During power-up, the outputs are held low for 1V < VCC < VUVLO. Any output programmed to depend on no condition always remains in its active state. For example, if the state of UV/OV is not programmed to depend on any condition, UV/OV will always be low. Figure 3 shows a timing diagram of a typical relationship between a monitored input voltage and outputs RESET and UV/OV. RESET and UV/OV are a function of only IN1. Table 6). As an example, RESET may depend on the IN3 primary undervoltage threshold, MR, UV/OV, and WDO. Write 1's to R11h[1:0], R11h[4], and R12h[7] to configure as indicated. IN3 must be above the undervoltage threshold, MR must be high, UV/OV must be deasserted, and WDO must be deasserted to be a logic "1," then RESET deasserts. The logic state of RESET, in this example, is equivalent to the logical statement: IN3 * MR * UV/OV * WDO RESET remains low for its programmed timeout period (t RP ) after all assertion-causing conditions are removed. Program timeout periods for RESET from 25s to 1600ms (see Table 6). Configure RESET for open-drain or weak pullup through bit R12h[0].
MAX6884/MAX6885
RESET Program RESET to depend on MR, UV/OV, WDO, or any programmable primary voltage-detector input (see
SECONDARY THRESHOLD (OVERVOLTAGE) VIN1 PRIMARY THRESHOLD
UV/OV tUP
RESET tRP
Figure 3. Output Timing Diagram
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Table 6. Programmable RESET Options
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION 1 = RESET Assertion Depends on MR 0 = RESET Assertion Does Not Depend on MR 1 = RESET Assertion Depends on UV/OV 0 = RESET Assertion Does Not Depend on UV/OV 1 = RESET Assertion Depends on IN1 Primary Undervoltage 0 = RESET Assertion Does Not Depend on IN1 Primary Undervoltage 1 = RESET Assertion Depends on IN2 Primary Undervoltage 0 = RESET Assertion Does Not Depend on IN2 Primary Undervoltage 1 = RESET Assertion Depends on IN3 Primary Undervoltage 0 = RESET Assertion Does Not Depend on IN3 Primary Undervoltage 1 = RESET Assertion Depends on IN4 Primary Undervoltage 0 = RESET Assertion Does Not Depend on IN4 Primary Undervoltage 1 = RESET Assertion Depends on IN5 Primary Undervoltage 0 = RESET Assertion Does Not Depend on IN5 Primary Undervoltage 1 = RESET Assertion Depends on IN6 Primary Undervoltage 0 = RESET Assertion Does Not Depend on IN6 Primary Undervoltage RESET Output Type 1 = Open Drain 0 = Weak Pullup RESET Deassertion Time Delay 000 = 25s 001 = 1.56ms 010 = 6.25ms 011 = 25ms 100 = 50ms 101 = 200ms 110 = 400ms 111 = 1600ms Not Used 1 = RESET Assertion Depends on WDO Assertion 0 = RESET Assertion Does Not Depend on WDO Assertion
[0] [1] [2] [3] 11h 91h [4] [5] [6] [7]
[0]
12h
92h
[3:1]
[6:4] [7]
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
UV/OV Program UV/OV to depend on MR, RESET, or any programmable secondary voltage detector input (see Table 7). As an example, UV/OV may depend on the IN1 secondary overvoltage threshold, MR, and RESET. Write 1's to R13h[2:0] and R0Eh[1] to configure as indicated. IN1 must be below the overvoltage threshold, MR must be high, and RESET must be deasserted to be a logic "1,"
then UV/OV deasserts. The logic state of UV/OV, in this example, is equivalent to the logical statement: IN1 * MR * RESET UV/OV remains low for its programmed time delay (tUP) after all assertion-causing conditions are removed. Program time delays for UV/OV from 25s to 1600ms (see Table 7). Configure UV/OV for open drain or weak pullup through bit R14h[0].
MAX6884/MAX6885
Table 7. Programmable UV/OV Options
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION 1 = UV/OV Assertion Depends on MR 0 = UV/OV Assertion Does Not Depend on MR 1 = UV/OV Assertion Depends on RESET 0 = UV/OV Assertion Does Not Depend on RESET 1 = UV/OV Assertion Depends on IN1 Secondary Undervoltage/Overvoltage Threshold 0 = UV/OV Assertion Does Not Depend on IN1 Secondary Undervoltage/Overvoltage Threshold 1 = UV/OV Assertion Depends on IN2 Secondary Undervoltage/Overvoltage Threshold 0 = UV/OV Assertion Does Not Depend on IN2 Secondary Undervoltage/Overvoltage Threshold 1 = UV/OV Assertion Depends on IN3 Secondary Undervoltage/Overvoltage Threshold 0 = UV/OV Assertion Does Not Depend on IN3 Secondary Undervoltage/Overvoltage Threshold 1 = UV/OV Assertion Depends on IN4 Secondary Undervoltage/Overvoltage Threshold 0 = UV/OV Assertion Does Not Depend on IN4 Secondary Undervoltage/Overvoltage Threshold 1 = UV/OV Assertion Depends on IN5 Secondary Undervoltage/Overvoltage Threshold 0 = UV/OV Assertion Does Not Depend on IN5 Secondary Undervoltage/Overvoltage Threshold 1 = UV/OV Assertion Depends on IN6 Secondary Undervoltage/Overvoltage Threshold 0 = UV/OV Assertion Does Not Depend on IN6 Secondary Undervoltage/Overvoltage Threshold UV/OV Output Type 1 = Open Drain 0 = Weak Pullup UV/OV Deassertion Time Delay 000 = 25s 001 = 1.56ms 010 = 6.25ms 011 = 25ms 100 = 50ms 101 = 200ms 110 = 400ms 111 = 1600ms Unused
[0] [1]
[2]
[3] 13h 93h [4]
[5]
[6]
[7]
[0]
14h
94h [3:1]
[7:4]
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
WDO The MAX6884/MAX6885 offer a separate output for the watchdog timer system. WDO is active low and programmable for open-drain or weak pullup. Program WDO to assert RESET when the watchdog timer expires. See the Configuring the Watchdog Timer section for a complete description of the watchdog timer system.
if it stalls. The output of the watchdog timer (WDO) connects to the reset input or a nonmaskable interrupt of the P. Program R15h to configure the watchdog timer functions (see Table 8). The watchdog timer features independent initial and normal watchdog timeout periods between 6.25ms and 102.4s (see Figure 4). The initial watchdog timeout period (t WDI) is active immediately after power-up, after a reset event takes place, after enabling the watchdog timer, or after the watchdog timer expires. The initial watchdog timeout period allows the P to perform its initialization process.
Configuring the Watchdog Timer
A watchdog timer monitors microprocessor (P) software execution for a stalled condition and resets the P
2.5V VCC OR IN1-IN4 WDO
RESET
WDI tD-PO tRP *tWDI tWD *tWDI
RESET NOT DEPENDENT ON WDO
2.5V VCC OR IN1-IN4 WDO
RESET
WDI tD-PO tRP *tWDI tWD WDO CONNECTED TO MR. tRP *tWDI
*tWDI IS THE INITIAL WATCHDOG TIMEOUT PERIOD.
Figure 4. Watchdog Timing Diagrams 20 ______________________________________________________________________________________
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
The normal watchdog timeout period (tWD) is active after the initial watchdog timer and continues to be active until the watchdog timer expires. The normal watchdog timeout period monitors a pulsed output of the P that indicates when normal processor behavior occurs. If no pulse occurs during the normal watchdog timeout period, this indicates that the processor has stopped operating or is stuck in an infinite execution loop and WDO asserts. Disable or enable the watchdog timer through R15h[7]. If RESET is programmed to depend on WDO and the watchdog timer expires, WDO will assert for a short pulse, just long enough to assert RESET (typically less than 5s; see Figure 4). If WDO is not programmed to depend on RESET and the watchdog timer expires, WDO will remain asserted until a low-to-high or high-tolow edge occurs on WDI. Program WDO for open-drain or weak pullup (see Table 8). Fault Register Registers 28h to 2Ah store all fault conditions including undervoltage, overvoltage, and watchdog timer faults (see Table 9). Fault registers are read-only and lose contents upon power removal. The first read command from the fault registers after power-up gives invalid data. Reading the fault register clears all fault flags in the register.
MAX6884/MAX6885
Table 8. Watchdog Register Settings
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE WDO Output Type 1 = Open Drain 0 = Weak Pullup Initial Watchdog Timeout 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4ms 110 = 25.6s 111 = 102.4s Normal Watchdog Timeout 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 1100 = 1.6s 101 = 6.4ms 110 = 25.6s 111 = 102.4s Watchdog Enable 1 = Enabled 0 = Disabled DESCRIPTION
[0]
[3:1]
15h
95h
[6:4]
[7]
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Table 9. Fault Registers (28h-2Ah)
REGISTER ADDRESS BIT RANGE [0] [1] [2] 28h [3] [4] [5] [7:6] [0] [1] [2] 29h [3] [4] [5] [7:6] [0] 2Ah [1] [6:2] [7] DESCRIPTION 1 = IN1 Voltage Falls Below Primary Undervoltage Threshold 1 = IN2 Voltage Falls Below Primary Undervoltage Threshold 1 = IN3 Voltage Falls Below Primary Undervoltage Threshold 1 = IN4 Voltage Falls Below Primary Undervoltage Threshold 1 = IN5 Voltage Falls Below Primary Undervoltage Threshold 1 = IN6 Voltage Falls Below Primary Undervoltage Threshold Unused 1 = IN1* Voltage Falls Below Secondary Threshold 1 = IN2* Voltage Falls Below Secondary Threshold 1 = IN3* Voltage Falls Below Secondary Threshold 1 = IN4* Voltage Falls Below Secondary Threshold 1 = IN5* Voltage Falls Below Secondary Threshold 1 = IN6* Voltage Falls Below Secondary Threshold Unused 1 = UV/OV Has Been Asserted 1 = RESET Has Been Asserted Unused 1 = WDO Has Been Asserted
*Does not matter if set as undervoltage or overvoltage.
Configuration Lock Lock the configuration register bank and configuration EEPROM contents after initial programming by setting the lock bit high (see Table 10). Locking the configuration prevents write operations to configuration EEPROM and configuration registers except the configuration lock bit. Set the lock bit to 0 to reconfigure the device.
Write Disable A unique write disable feature protects the MAX6884/MAX6885 from inadvertent user EEPROM writes. As input voltages that power the serial interface, a P, or any other writing devices fall, unintentional data may be written onto the data bus. The user EEPROM write-disable function (see Table 11) ensures that unintentional data does not corrupt the MAX6884/ MAX6885 user EEPROM data.
Table 10. Configuration Lock Bit
REGISTER ADDRESS 16h EEPROM MEMORY ADDRESS 96h BIT RANGE DESCRIPTION 1 = Configuration Locked 0 = Configuration Unlocked
[3]
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Table 11. User EEPROM Write Disable Bits
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION 1 = User EEPROM Writes Disabled on RESET Assertion 0 = User EEPROM Writes Enabled on RESET Assertion 1 = User EEPROM Writes Disabled on UV/OV Assertion 0 = User EEPROM Writes Enabled on UV/OV Assertion
[1] 16h 96h [0]
Configuration Register Bank and EEPROM
The configuration registers can be directly modified by the serial interface without modifying the EEPROM after the power-up procedure terminates and the configuration EEPROM data has been loaded into the configuration register bank. Use the write byte or block write protocols to write directly to the configuration registers. Changes to the configuration registers take effect immediately and are lost upon power removal. At device power-up, the register bank loads configuration data from the EEPROM. Configuration data may be directly altered in the register bank during application development, allowing maximum flexibility. Transfer the new configuration data, byte by byte, to the configuration EEPROM with the write byte protocol. The next device power-up or software reboot automatically loads the new configuration. See Table 12 for a complete register map. Configuration EEPROM The configuration EEPROM addresses range from 80h to 97h. Write data to the configuration EEPROM to set up the MAX6884/MAX6885 automatically upon power-up. Data transfers from the configuration EEPROM to the
configuration registers when VCC exceeds UVLO during power-up or after a software reboot. After VCC exceeds UVLO, an internal 1MHz clock starts after a 5s delay, and data transfer begins. Data transfer disables access to the configuration registers and EEPROM. The data transfer from EEPROM to configuration registers takes 2.5ms maximum. Read configuration EEPROM and configuration register data any time after power-up or software reboot. Write commands to the configuration EEPROM and configuration registers are allowed at any time after power-up or software reboot unless the configuration lock bit is set (see Table 10). When the configuration lock bit is set, all write access to EEPROM and registers is disabled with the exception of the configuration lock bit itself. The maximum cycle time to write a single byte in EEPROM is 11ms (max). User EEPROM The 512-bit user EEPROM addresses range from 40h to 7Fh (see Figure 11). Store revision data, board revision data, or other data in these registers. The maximum cycle time to write a single byte is 11ms (max). Disable writes to the user EEPROM during RESET or UV/OV assertion by programming bit R16h[1] or R16h[0], respectively (see Table 11).
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Table 12. Register Map
REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h EEPROM MEMORY ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h -- -- -- -- -- -- -- -- -- -- -- -- -- READ/ WRITE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R DESCRIPTION IN1 Primary Undervoltage Detector Threshold (Table 4) IN2 Primary Undervoltage Detector Threshold (Table 4) IN3 Primary Undervoltage Detector Threshold (Table 4) IN4 Primary Undervoltage Detector Threshold (Table 4) IN5 Primary Undervoltage Detector Threshold (Table 4) IN6 Primary Undervoltage Detector Threshold (Table 4) IN1 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4) IN2 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4) IN3 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4) IN4 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4) IN5 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4) IN6 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4) Unused. Returns 0h when read. Unused. Returns 0h when read. Secondary Threshold Undervoltage/Overvoltage Selection (Table 4) Threshold Range Selection (Table 4) High-Z Mode Selection (Table 4) RESET Dependency Selection (Table 6) RESET Output Type, Timeout Period, and WDO Dependency Selection (Table 6) UV/OV Dependency Selection (Table 7) UV/OV Output Type and Timeout Period (Table 7) Watchdog Initial and Normal Timeout Selection (Table 8) Internal/External VCC (Table 2), Internal/External Reference (Table 5), Configuration Lock Bit (Table 10), User EEPROM Write Disable (Table 11) Unused (Table 5) ADC Conversion Data for IN1 (8 MSBs) (Table 3) ADC Conversion Data for IN1 (2 LSBs) (Table 3) ADC Conversion Data for IN2 (8 MSBs) (Table 3) ADC Conversion Data for IN2 (2 LSBs) (Table 3) ADC Conversion Data for IN3 (8 MSBs) (Table 3) ADC Conversion Data for IN3 (2 LSBs) (Table 3) ADC Conversion Data for IN4 (8 MSBs) (Table 3) ADC Conversion Data for IN4 (2 LSBs) (Table 3) ADC Conversion Data for IN5 (8 MSBs) (Table 3) ADC Conversion Data for IN5 (2 LSBs) (Table 3) ADC Conversion Data for IN6 (8 MSBs) (Table 3) ADC Conversion Data for IN6 (2 LSBs) (Table 3) ADC Conversion Data for AUXIN (8 MSBs) (Table 3)
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EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Table 12. Register Map (continued)
REGISTER ADDRESS 25h 26h 27h 28h 29h 2Ah EEPROM MEMORY ADDRESS -- -- -- -- -- -- READ/ WRITE R R R R R R DESCRIPTION ADC Conversion Data for AUXIN (2 LSBs) (Table 3) ADC Conversion Data for VCC (8 MSBs) (Table 3) ADC Conversion Data for VCC (2 LSBs) (Table 3) Fault Flags for Primary Voltage Detectors (Table 9) Fault Flags for Secondary Voltage Detectors (Table 9) Fault Flags for RESET, UV/OV, and WDO (Table 9)
00h
REGISTER BANK CONFIGURATION DATA (R/W)
80h
CONFIGURATION EEPROM
40h
USER EEPROM
17h 18h
97h ADC AND FAULT REGISTERS (READ ONLY)
impedance states until the device is reconfigured by the user). Each device requires configuration before full power is applied to the system. Below is a general step-by-step procedure for programming the MAX6884/MAX6885: 1) Apply a supply voltage to IN1-IN4 or VCC, depending on the programmed configuration (see the Powering the MAX6884/MAX6885 section). The applied voltage must be 2.7V or higher. 2) Transmit data through the serial interface. Write to the configuration registers first to ensure the device is configured properly (see the Write Byte and Block Write sections). 3) Use the read word protocol to read back the data from the configuration registers to verify the data was written (see the Receive Byte and Block Read sections). 4) Write the same data written to the configuration registers to the appropriate configuration EEPROM registers. After completing EEPROM configuration, apply full power to the system to begin normal operation. The nonvolatile EEPROM stores the configuration information while power is off. Software Reboot A software reboot restores the EEPROM configuration to the volatile registers without cycling the power supplies. Use the send byte command with data byte C4h to initiate a software reboot. The 2.5ms (max) power-up delay also applies after a software reboot.
2Ah
7Fh
Figure 5. Memory Map
Configuring the MAX6884/MAX6885
The MAX6884/MAX6885 factory-default configuration sets all registers to 00h except for bits R91h[0], R92h[0], R93h[0], R94h[0], R95h[0], which are set to 1. This configuration sets all three programmable outputs (RESET, UV/OV, WDO) as open drain, and RESET and UV/OV dependent on MR (putting all outputs into high-
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25
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
SMBus/I2C-Compatible Serial Interface The MAX6884/MAX6885 feature an I2C/SMBus-compatible 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX6884/MAX6885 and the master device at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The MAX6884/MAX6885 are transmit/ receive slave-only devices, relying upon a master device to generate a clock signal. The master device (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX6884/ MAX6885 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (SR) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7k resistors for most applications. Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (see Figure 7), otherwise the MAX6884/MAX6885 register a START or STOP condition (see Figure 8) from the master. SDA and SCL idle high when the bus is not busy.
SDA tBUF tSU:STA tLOW SCL tHIGH tHD:STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tHD:STA tSU:STO
tSU:DAT
Figure 6. Serial Interface Timing
SDA
SDA
SCL SCL S P
DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID
START CONDITION
STOP CONDITION
Figure 7. Bit Transfer 26
Figure 8. Start and Stop Conditions
______________________________________________________________________________________
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
Start and Stop Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START (S) condition (see Figure 8) by transitioning SDA from high to low while SCL is high. The master device issues a STOP (P) condition (see Figure 8) by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 11). Early STOP Conditions The MAX6884/MAX6885 recognize a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP condition. Repeated START Conditions A REPEATED START (SR) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation (see Figure 11). SR may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX6884/MAX6885 serial interface supports continuous write operations with or without an SR condition separating them. Continuous read operations require SR conditions because of the change in direction of data flow. Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The MAX6884/MAX6885 generate an ACK when receiving an address or data by pulling SDA low during the 9th clock period (see Figure 9). When transmitting data, such as when the master device reads data back from the MAX6884/MAX6885, the MAX6884/ MAX6885 wait for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. The MAX6884/MAX6885 generate a NACK after the command byte during a software reboot, while writing to the EEPROM, or when receiving an illegal memory address. Slave Address The MAX6884/MAX6885 slave address conforms to the following table:
SA7 (MSB) 1 SA6 0 SA5 1 SA4 0 SA3 0 SA2 A0 SA1 X SA0 (LSB) R/W
MAX6884/MAX6885
X = Don't care.
START CONDITION 1 2
CLOCK PULSE FOR ACKNOWLEDGE
SCL
8
9
SDA BY TRANSMITTER
S SDA BY RECEIVER
Figure 9. Acknowledge ______________________________________________________________________________________ 27
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
SA7 through SA4 represent the standard 2-wire interface address (1010); for devices with EEPROM, SA2 corresponds to the A0 address inputs of the MAX6884/ MAX6885 (hardwired as logic-low or logic-high). SA0 is a read/write flag bit (0 = write, 1 = read). The A0 address input allows up to two MAX6884/ MAX6885s to connect to one bus. Connect A0 to GND or to the 2-wire serial-interface power supply (see Figure 10). Send Byte The send byte protocol allows the master device to send one byte of data to the slave device (see Figure 11). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send an address that is not allowed or if the device is writing data to EEPROM or is booting. If the master sends C0h, the data is ACK, because this could be the start of the block write protocol, and the slave expects following data byte. If the master sends a STOP condition, the internal address pointer does not change. If the master sends C1h, this signifies that the block read protocol is expected, and a repeated START condition should follow. The device reboots if the master sends C4h. The send byte procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit data byte. 5) The addressed slave asserts an ACK on SDA. 6) The master sends a STOP condition. Write Byte The write byte protocol allows the master device to write a single byte in the register bank or in the EEPROM (see Figure 11). The write byte/word procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit command code. 5) The addressed slave asserts an ACK on SDA. 6) The master sends an 8-bit data byte. 7) The addressed slave asserts an ACK on SDA. 8) The master sends a STOP condition. To write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. The command code must be in the 00h to 2Fh range. The data byte is written to the register bank if the command code is valid. The slave generates a NACK at step 5 if the command code is invalid or any internal operations are ongoing. To write a single byte of data to the user or configuration EEPROM, the 8-bit command code and a single 8-bit data byte are sent. Block Write The block write protocol allows the master device to write a block of data (1 to 16 bytes) to the EEPROM or to the register bank (see Figure 11). The destination address must already be set by the send byte protocol and the command code must be C0h. If the number of bytes to be written causes the address pointer to exceed 2Fh for the configuration register or 9Fh for the configuration EEPROM, the address pointer stops incrementing, overwriting the last memory address with the remaining bytes of data. Only the last data byte sent is stored in 17h (as 2Fh is read only and a write cause no change in the content). If the number of bytes to be written exceeds the address pointer 9Fh for the user EEPROM, the address pointer stops incrementing and continues writing exceeding data to the last address. Only the last data is actually written to 9Fh. The block write procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends the 8-bit command code for block write (C0h). 5) The addressed slave asserts an ACK on SDA. 6) The master sends the 8-bit byte count (1 to 16 bytes) N. 7) The addressed slave asserts an ACK on SDA. 8) The master sends 8 bits of data. 9) The addressed slave asserts an ACK on SDA. 10) Repeat steps 8 and 9 N - 1 times. 11) The master generates a STOP condition.
SDA START SCL
1 MSB
0
1
0
0
A0
x LSB
R/W
ACK
Figure 10. Slave Address 28 ______________________________________________________________________________________
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
Read Byte The read byte protocol allows the master device to read the register or an EEPROM location (user or configuration) content of the MAX6884/MAX6885 (see Figure 11). The read byte procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on the data line. 4) The master sends 8 data bits.
SEND BYTE FORMAT S ADDRESS WR ACK 7 BITS 0 DATA 8 BITS ACK P
5) The active slave asserts an ACK on the data line. 6) The master sends a repeated start condition. 7) The master sends the 7-bit slave ID plus a read bit (high). 8) The addressed slave asserts an ACK on the data line. 9) The slave sends 8 data bits. 10) The master asserts a NACK on the data line. 11) The master generates a STOP condition.
MAX6884/MAX6885
RECEIVE BYTE FORMAT S ADDRESS WR ACK 7 BITS 1 DATA 8 BITS DATA BYTE: READS DATA FROM THE REGISTER COMMANDED BY THE LAST READ BYTE OR WRITE BYTE TRANSMISSION. ALSO DEPENDENT ON A SEND BYTE. ACK P
SLAVE ADDRESS: DATA BYTE: PRESETS THE EQUIVALENT TO CHIP- INTERNAL ADDRESS POINTER . SELECT LINE OF A 3WIRE INTERFACE WRITE BYTE FORMAT S ADDRESS WR ACK 7 BITS 0 COMMAND 8 BITS ACK DATA 8 BITS
SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3WIRE INTERFACE
ACK
P
COMMAND BYTE: SLAVE ADDRESS: EQUIVALENT TO CHIP- SELECTS REGISTER YOU SELECT LINE OF A 3- ARE WRITING TO WIRE INTERFACE BLOCK WRITE FORMAT S
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE IF THE COMMAND IS BELOW 50h. IF THE COMMAND is 80h, 81h, or 82h, THE DATA BYTE PRESETS THE LSB OF AN EEPROM ADDRESS. P
BYTE ADDRESS WR ACK COMMAND ACK COUNT = N ACK DATA BYTE ACK DATA BYTE ACK DATA BYTE ACK *** 1 N 7 BITS 0 8 BITS 8 BITS 8 BITS 8 BITS 8 BITS
COMMAND BYTE: SLAVE ADDRESS: EQUIVALENT TO CHIP- PREPARES DEVICE SELECT LINE OF A 3- FOR BLOCK OPERATION WIRE INTERFACE BLOCK READ FORMAT S
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE . COMMAND BYTE
BYTE ADDRESS WR ACK COMMAND ACK SR ADDRESS WR ACK COUNT = 16 ACK DATA BYTE ACK DATA BYTE ACK DATA BYTE ACK *** 1 N 7 BITS 0 8 BITS COMMAND BYTE: PREPARES DEVICE FOR BLOCK OPERATION 7 BITS 1 10h 8 BITS 8 BITS 8 BITS
P
SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3WIRE INTERFACE S = START CONDITON P = STOP CONDITION SHADED = SLAVE TRANSMISSION SR = REPEATED START CONDTION
SLAVE ADDRESS: DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE EQUIVALENT TO CHIP- COMMAND BYTE SELECT LINE OF A 3WIRE INTERFACE
Figure 11. SMBus/I2C Protocols ______________________________________________________________________________________ 29
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Note that once the read has been done, the internal pointer is increased by one, unless a memory boundary is hit. If the device is busy or if the address is not an allowed one, the command code is NACKed and the internal address pointer is not altered. The master must then interrupt the communication issuing a STOP condition. Block Read The block read protocol allows the master device to read a block of 16 bytes from the EEPROM or register bank (see Figure 11). Read fewer than 16 bytes of data by issuing an early STOP condition from the master, or by generating a NACK with the master. Previous actions through the serial interface predetermine the first source address. It is suggested to use a send byte protocol, before the block read, to set the initial read address. The block read protocol is initiated with a command code of C1h. The block read procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends 8 bits of the block read command (C1h). 5) The slave asserts an ACK on SDA, unless busy. 6) The master generates a repeated START condition. 7) The master sends the 7-bit slave address and a read bit (high). 8) The slave asserts an ACK on SDA. 9) The slave sends the 8-bit byte count (16). 10) The master asserts an ACK on SDA. 11) The slave sends 8 bits of data. 12) The master asserts an ACK on SDA. 13) Repeat steps 8 and 9 15 times. 14) The master generates a STOP condition. Address Pointers Use the send byte protocol to set the register address pointers before read and write operations. For the configuration registers, valid address pointers range from 00h to 2Fh. Register addresses outside of this range result in a NACK being issued from the MAX6884/ MAX6885. When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 2Fh. If the address pointer is already 2Fh, and more data bytes are being sent, these subsequent bytes overwrite address 2Fh repeatedly, but no data will be left in 2Fh as this is a read-only address. For the configuration EEPROM, valid address pointers range from 80h to 9Fh. When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 9Fh. If the address pointer is already 9Fh, and more data bytes are being sent, these subsequent bytes overwrite address 9Fh repeatedly, leaving only the last data byte sent stored at this register address. For the user EEPROM, valid address pointers range from 40h to 7Fh. As for the configuration EEPROM, block write and block read protocols can also be used. The internal address pointer will automatically increment up to the user EEPROM boundary 7Fh where the pointer moves to the first address of the configuration memory section 80h, as there is no forbidden address in the middle.
Applications Information
Configuration Download at Power-Up
The configuration of the MAX6884/MAX6885 (undervoltage/overvoltage thresholds, reset time delays, watchdog behavior, programmable output conditions and configurations, etc.) at power-up depends on the contents of the EEPROM. The EEPROM is comprised of buffered latches that store the configuration. The local volatile memory latches lose their contents at powerdown. Therefore, at power-up, the device configuration must be restored by downloading the contents of the EEPROM (nonvolatile memory) to the local latches. This download occurs in a number of steps: 1) Programmable outputs are high impedance with no power applied to the device. 2) When V CC or IN1-IN4 (see the Powering the MAX6884/MAX6885 section) exceeds +1V, all programmable outputs are asserted low. 3) When VCC or IN1-IN4 exceeds UVLO (2.5V), the configuration EEPROM starts to download its contents to the volatile configuration registers. The download takes 2.5ms (max). The programmable outputs assume their programmed conditional output state when VCC or IN1-IN4 exceeds the UVLO (see the Powering the MAX6884/MAX6885 section). 4) Any attempt to communicate with the device prior to this download completion results in a NACK being issued from the MAX6884/MAX6885.
30
______________________________________________________________________________________
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
Layout and Bypassing
For better noise immunity, bypass each of the voltagedetector inputs to GND with a 0.1F capacitor installed as close to the device as possible. Bypass VCC and DBP to GND with 1F capacitors installed as close to the device as possible. VCC (when not externally supplied) and DBP are internally generated voltages and should not be used to supply power to external circuitry.
Configuration Latency Period
A delay of less than 5s occurs between writing to the configuration registers and the time when these changes actually take place, except when changing one of the voltage-detector thresholds. Changing a voltage-detector threshold typically takes 150s. When changing EEPROM contents, a software reboot or cycling of power is required for these changes to transfer to volatile memory.
MAX6884/MAX6885
Typical Operating Circuit
12V DC-DC 1 DC-DC 2 DC-DC 3
12V 5V 3.3V 2.5V
DC-DC 4
1.8V
DC-DC 5
1.5V
DC-DC 6 RPU RPU SDA SCL RESET LOGIC OUTPUT LOGIC INPUT LOGIC INPUT P
1.2V
IN1 3.3V ALWAYS ON VCC
IN2
IN3
IN4
IN5
IN6 SDA SCL RESET
DBP
MAX6884 MAX6885
WDI WDO UV/OV
MARGIN *AUXIN TEMP SENSOR *REFIN A0 GND
MR
*MAX6884 ONLY
______________________________________________________________________________________
31
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Pin Configurations
TOP VIEW
IN1 IN4 IN1 IN5 IN4 IN2 IN3 IN2 IN3 IN5
20
RESET WDO UV/OV GND WDI
19
18
17
16 15 14
IN6 DBP VCC AUXIN REFIN RESET WDO UV/OV GND WDI
20 1 2 3 4 5 6
MR
19
18
17
16 15 14
IN6 DBP VCC N.C. N.C.
1 2 3 4 5 6
MR
MAX6884
*EXPOSED PAD
13 12 11
MAX6885
*EXPOSED PAD
13 12 11
7
MARGIN
8
SDA
9
SCL
10
A0
7
MARGIN
8
SDA
9
SCL
10
A0
THIN QFN
*EXPOSED PAD CONNECTED TO GND.
THIN QFN
*EXPOSED PAD CONNECTED TO GND.
Chip Information
PROCESS: BiCMOS
32
______________________________________________________________________________________
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX6884/MAX6885
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
XXXXX
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
1
2
______________________________________________________________________________________
33
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits MAX6884/MAX6885
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 -
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** **
NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
** SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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