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VND1NV04 VNN1NV04 - VNS1NV04
OMNIFET II fully autoprotected Power MOSFET
Features
Parameter Max on-state resistance (per ch.) Current limitation (typ) Drain-source clamp voltage

Symbol RON ILIMH VCLAMP
Value 250 m 1.7 A 40 V
1 2 2
3 1
TO-252 (DPAK)
3
Linear current limitation Thermal shutdown Short circuit protection Integrated clamp Low current drawn from input pin Diagnostic feedback through input pin ESD protection Direct access to the gate of the Power MOSFET (analog driving) Compatible with standard Power MOSFET
SOT-223
SO-8
Description
The VND1NV04, VNN1NV04, VNS1NV04 are monolithic devices designed in STMicroelectronics VIPower M0-3 Technology, intended for replacement of standard Power MOSFETs from DC up to 50 KHz applications. Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments. Fault feedback can be detected by monitoring the voltage at the input pin.
Table 1.
Device summary Order codes Tube Tube (lead free) VND1NV04-E Tape and reel VND1NV04TR VNN1NV04TR VNS1NV04TR Tape and reel (lead free) VND1NV04TR-E -
Package TO-252 (DPAK) SOT-223 SO-8 VND1NV04 VNN1NV04 VNS1NV04
April 2009
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Contents
VND1NV04 - VNN1NV04 - VNS1NV04
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 Overvoltage clamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Linear current limiter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Over temperature and short circuit protection . . . . . . . . . . . . . . . . . . . . . 16 Status feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 4.3 DPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 5.2 5.3 5.4 5.5 5.6 DPAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SO8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DPAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SOT-223 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DPAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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List of figures
VND1NV04 - VNN1NV04 - VNS1NV04
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance vs. input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance vs. input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain-source on resistance vs. Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input voltage vs. input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-off drain-source voltage slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized on resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized input threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Normalized current limit vs. junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DPAK PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DPAK Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . 17 DPAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DPAK thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SOT-223 Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . 20 SOT-223 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . 20 SOT-223 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SO-8 Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . 22 SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO-8 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DPAK package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SOT-223 mechanical data & package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SOT-223 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SO-8 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
DRAIN
2 Overvoltage Clamp
INPUT
1
Gate Control
Over Temperature
Linear Current Limiter
3
SOURCE
Figure 2.
Configuration diagram (top view) (a)
SOURCE SOURCE SOURCE INPUT
1
8
DRAIN DRAIN DRAIN
4
5
DRAIN
a. For the pins configuration related to SOT-223 and DPAK see outline at page 1.
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Electrical specifications
VND1NV04 - VNN1NV04 - VNS1NV04
2
Electrical specifications
Figure 3. Current and voltage conventions
ID VDS
DRAIN IIN RIN INPUT SOURCE
VIN
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document. Table 2.
Symbol VDSn VINn IINn IDn IRn VESD1 VESD2 Ptot Tj Tc Tstg
Absolute maximum ratings
Parameter Drain-source voltage (VINn=0 V) Input voltage Input current Value SOT-223 SO-8 DPAK Unit V V mA A A V V 35 W C C C
Internally clamped Internally clamped +/-20 330 Internally limited -3 4000 16500 7 8.3 Internally limited Internally limited -55 to 150
RIN MINn Minimum input series impedance Drain current Reverse DC output current Electrostatic discharge (R=1.5 K, C=100 pF) Electrostatic discharge on output pins only (R=330 , C=150 pF) Total dissipation at Tc=25 C Operating junction temperature Case operating temperature Storage temperature
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Electrical specifications
2.2
Thermal data
Table 3.
Symbol Rthj-case Rthj-lead Rthj-amb
Thermal data
Max value Parameter SOT-223 Thermal resistance junction-case Thermal resistance junction-lead Thermal resistance junction-ambient 70
(1)
Unit SO-8 DPAK 3.5 15 65
(1)
18
C/W C/W
54
(1)
C/W
1. When mounted on a standard single-sided FR4 board with 50 mm2 of Cu (at least 35 m thick) connected to all DRAIN pins
2.3
Electrical characteristics
Table 4.
Symbol
Electrical characteristics
Parameter Test conditions Min Typ Max Unit
Off (-40 CIDSS
A
On (-40 CDynamic (Tj=25 C, unless otherwise specified) gfs (1) COSS Forward transconductance Output capacitance VDD=13 V; ID=0.5 A VDS=13 V; f=1 MHz; VIN=0 V 2 90 S pF
Switching (Tj=25 C, unless otherwise specified)
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Electrical specifications Table 4.
Symbol td(on) tr td(off) tf td(on) tr td(off) tf
VND1NV04 - VNN1NV04 - VNS1NV04
Electrical characteristics (continued)
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Turn-on delay time Rise time Turn-off delay time Fall time VDD=15 V; ID=1.5 A Vgen=5 V; Rgen=RIN MIN=330 VDD=12 V; ID=0.5 A; VIN=5 V Igen=2.13 mA (see Figure 7) VDD=15 V; ID=0.5 A Vgen=5 V; Rgen=2.2 K (see Figure 4) VDD=15 V; ID=0.5 A Vgen=5 V; Rgen=RIN MIN=330 (see Figure 4) Test conditions Min Typ 70 170 350 200 0.25 1.3 1.8 1.2 5 5 Max 200 500 1000 600 1.0 4.0 5.5 4.0 Unit ns ns ns ns s s s s A/s nC
(dI/dt)on Turn-on current slope Qi Total input charge
Source drain diode (Tj=25 C, unless otherwise specified) VSD(1) trr Qrr IRRM Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD=0.5 A; dI/dt=6 A/s VDD=30 V; L=200 H (see Figure 5) ISD=0.5 A; VIN=0 V 0.8 205 100 0.7 V ns nC A
Protections (-40 CEas
55
mJ
1. Pulsed: pulse duration = 300 s, duty cycle 1.5 %
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VND1NV04 - VNN1NV04 - VNS1NV04 Figure 4. Switching time test circuit for resistive load
Electrical specifications
VD Rgen Vgen
ID 90%
tr td(on)
10% td(off)
tf t
Vgen
t
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Electrical specifications Figure 5. Test circuit for diode recovery times
VND1NV04 - VNN1NV04 - VNS1NV04
A D I
A
FAST DIODE
OMNIFET
S B
L=100uH B
330 Rgen
I
D
VDD
OMNIFET
S
Vgen
8.5
Figure 6.
Unclamped inductive load test circuits
RGEN
VIN PW
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VND1NV04 - VNN1NV04 - VNS1NV04 Figure 7. Input charge test circuit
Electrical specifications
VIN
GEN
ND8003
Figure 8.
Unclamped inductive waveforms
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Electrical specifications
VND1NV04 - VNN1NV04 - VNS1NV04
2.4
Figure 9.
Vsd (mV)
1000
Electrical characteristics curves
Source-drain diode forward characteristics Figure 10. Static drain-source on resistance
Rds(on) (ohms)
4.5 4
Tj=-40C
950
Vin=2.5V
Vin=0V
900
3.5 3 2.5
850
2
800
1.5 1
Tj=25C Tj=150C
750
0.5 0
700 0 2 4 6 8 10 12 14
0
0.05
0.1
0.15
0.2
0.25
0.3
Id (A)
Id(A)
Figure 11.
Derating curve
Figure 12. Static drain-source on resistance vs. input voltage (part 1/2)
Rds(on) (mohms)
500 450 400 350 300 250 200
Tj=25C
Id=0.5A
Tj=150C
150 100 50 0 3 3.5 4 4.5 5 5.5 6 6.5 7
Tj=-40C
Vin(V)
Figure 13. Static drain-source on resistance vs. input voltage (part 2/2)
Rds(on) (mohms)
500 450 400 350 300 250 200
Tj=-40C Tj=25C Tj=150C
Figure 14. Transconductance
Gfs (S)
6 5.5 5
Id=1.5A Id=1A
Vds=13V
Tj=-40C Tj=25C
4.5 4 3.5 3 2.5
Tj=150C
150 100 50 0 3 3.5 4 4.5 5 5.5
Id=1.5A Id=1A Id=1.5A Id=1A
2 1.5 1 0.5 0
6
6.5
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Vin(V)
Id(A)
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Electrical specifications
Figure 15. Static drain-source on resistance vs. Id
Rds(on) (mohms)
500 450 400 350 300 250 200 150 100 50 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Tj=25C Vin=5V Vin=3.5V Tj=-40C Vin=5V Vin=3.5V Tj=150C Vin=5V Vin=3.5V
Figure 16. Transfer characteristics
Idon(A)
2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5
Tj=25C
Vds=13.5V
Tj=150C Tj=-40C
Id(A)
Vin(V)
Figure 17. Turn-on current slope (part 1/2)
di/dt(A/us)
6
Figure 18. Turn-on current slope (part 2/2)
di/dt(A/us)
1.4
5
4
Vin=5V Vdd=15V Id=1.5A
1.2
1
Vin=3.5V Vdd=15V Id=1.5A
3
0.8
2
0.6
1
0.4
0 0 500 1000 1500 2000 2500
0.2 0 500 1000 1500 2000 2500
Rg(ohm)
Rg(ohm)
Figure 19. Input voltage vs. input charge
Figure 20. Turn-off drain source voltage slope (part 1/2)
dv/dt(V/us)
350 300
Vin (V)
6
5
Vds=12V Id=0.5A
4
250 200
Vin=5V Vdd=15V Id=0.5A
3
150
2
100
1
50
0 0 1 2 3 4 5 6
0 0 500 1000 1500 2000 2500
Qg (nC)
Rg(ohm)
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Electrical specifications
VND1NV04 - VNN1NV04 - VNS1NV04
Figure 21. Turn-off drain-source voltage slope Figure 22. Capacitance variations (part 2/2)
dv/dt(V/us)
350 300 250 200 150 100 50 0 0 500 1000 1500 2000 2500
C(pF)
225 200
Vin=3.5V Vdd=15V Id=0.5A
175 150 125 100 75 50 0 5 10 15 20
f=1MHz Vin=0V
25
30
35
Rg(ohm)
Vds(V)
Figure 23. Switching time resistive load (part 1/2)
t(us)
2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 0 250 500 750 1000 1250 1500 1750 2000 2250 2500
Figure 24. Switching time resistive load (part 2/2)
t(ns)
550 500
Vdd=15V Id=0.5A Vin=5V
td(off)
450 400
tr
Vdd=15V Id=0.5A Rg=330ohm
tr tf
350 300 250 200 150
td(off)
tf
td(on)
100 50 0 3.25
td(on)
3.5
3.75
4
4.25
4.5
4.75
5
5.25
Rg(ohm)
Vin(V)
Figure 25. Output characteristics
Figure 26. Normalized on resistance vs. temperature
Rds(on) (mOhm)
2.25
ID(A)
2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 11 12
Vin=3V Vin=5.5V Vin=4.5V Vin=3.5V
2 1.75 1.5 1.25 1 0.75 0.5 -50 -25
Vin=5V Id=0.5A
0
25
50
75
100
125
150
175
VDS(V)
Tc (C)
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Electrical specifications
Figure 27. Normalized input threshold voltage Figure 28. Normalized current limit vs. vs. temperature junction temperature
Vinth (V)
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175
Ilim (A)
5
Vds=Vin Id=1mA
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Vin=5V Vds=13V
Tc (C)
Tc (C)
Figure 29. Step response current limit
Tdlim(us)
2.4
2.3
Vin=5V Rg=330ohm
2.2
2.1
2
1.9 5 10 15 20 25 30 35
Vdd(V)
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Protection features
VND1NV04 - VNN1NV04 - VNS1NV04
3
Protection features
During normal operation, the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path. The device then behaves like a standard Power MOSFET and can be used as a switch from DC up to 50 KHz. The only difference from the user's standpoint is that a small DC current IISS (typ. 100 A) flows into the input pin in order to supply the internal circuitry. The device integrates:
3.1
Overvoltage clamp protection
Internally set at 45 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.
3.2
Linear current limiter circuit
Limits the drain current ID to Ilim whatever the input pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the over temperature threshold Tjsh.
3.3
Over temperature and short circuit protection
These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Over temperature cutout occurs in the range 150 to 190 C, a typical value being 170 C. The device is automatically restarted when the chip temperature falls of about 15 C below shutdown temperature.
3.4
Status feedback
In the case of an over temperature fault condition (Tj > Tjsh), the device tries to sink a diagnostic current Igf through the input pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the input pin driver is not able to supply the current Igf, the input pin will fall to 0 V. This will not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current IISS. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL logic circuit.
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Package and PCB thermal data
4
4.1
Package and PCB thermal data
DPAK thermal data
Figure 30. DPAK PC board
1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm,PCB thickness = 2 mm, Cu thickness=35 m , Copper areas: from minimum pad layout to 16 cm2).
Figure 31. DPAK Rthj-amb vs. PCB copper area in open box free air condition
90 80 70 60 50 40 30 0 2 4 6 8 10
PCB Cu heat sink area ( cm^ 2) - ( refer t o PCB layout )
footprint
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Package and PCB thermal data
VND1NV04 - VNN1NV04 - VNS1NV04
Figure 32. DPAK thermal impedance junction ambient single pulse
ZTH ( C/ W)
100
Footprint 6 cm2
10
1
0,1 0,0001
0,001
0,01
0,1 1 Time ( s)
10
100
1000
Equation 1: pulse calculation formula Z =R +Z (1 - )
TH
TH
THtp
where = tP/T Figure 33. DPAK thermal fitting model of a single channel
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VND1NV04 - VNN1NV04 - VNS1NV04 Table 5. DPAK thermal parameter
Area/island (cm2) R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W*s/C) C2 (W*s/C) C3 (W*s/C) C4 (W*s/C) C5 (W*s/C) C6 (W*s/C) 0.25 0.8 1.6 0.8 2 15 61
Package and PCB thermal data
6
24
0.00006 0.0005 0.01 0.3 0.45 0.8 5
4.2
SOT-223 thermal data
Figure 34. SOT-223 PC board
.
1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm,PCB thickness = 2 mm, Cu thickness=35 m , Copper areas: from minimum pad layout to 0.8 cm2).
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Package and PCB thermal data
VND1NV04 - VNN1NV04 - VNS1NV04
Figure 35. SOT-223 Rthj-amb vs. PCB copper area in open box free air condition
140 130 120 110 100 90 80 70 60 0 0,5 1 1,5 2 2,5
PCB Cu heat sink area ( cm^ 2) - ( refer t o PCB layout )
footprint
Figure 36. SOT-223 thermal impedance junction ambient single pulse
ZTH ( C/ W)
1000
Footprint
100
2 cm2
10
1
0,1 0,0001
0,001
0,01
0,1 1 Time ( s)
10
100
1000
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Doc ID 7381 Rev 2
VND1NV04 - VNN1NV04 - VNS1NV04 Equation 2: pulse calculation formula Z =R +Z (1 - )
Package and PCB thermal data
TH
TH
THtp
where = tP/T Figure 37. SOT-223 thermal fitting model of a single channel
Table 6.
SOT-223 thermal parameter
Area/island (cm2)
R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W*s/C) C2 (W*s/C) C3 (W*s/C) C4 (W*s/C) C5 (W*s/C) C6 (W*s/C)
FP
0.8 1.6 4.5 24 0.1 100 0.00006 0.0005 0.03 0.16 1000 0.5
2
45
2
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Package and PCB thermal data
VND1NV04 - VNN1NV04 - VNS1NV04
4.3
SO-8 thermal data
Figure 38. SO-8 PC board
1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm,PCB thickness = 2 mm, Cu thickness=35 m , Copper areas: from minimum pad layout to 2 cm2).
Figure 39. SO-8 Rthj-amb vs. PCB copper area in open box free air condition
105
footprint
95
85
75
65 0 0,5 1 1,5 2 2,5
PCB Cu heat sink area ( cm^ 2) - ( refer t o PCB layout )
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Package and PCB thermal data
Figure 40. SO-8 thermal impedance junction ambient single pulse
ZTH (C/ W ) 1000
100
Footprint 2 cm2
10
1
0,1 0,0001
0,001
0,01
0,1
1
10
100
1000
Time (s)
Equation 3: pulse calculation formula Z =R +Z (1 - )
TH
TH
THtp
where = tP/T Figure 41. SO-8 thermal fitting model of a single channel
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Package and PCB thermal data
VND1NV04 - VNN1NV04 - VNS1NV04
Table 7.
SO-8 thermal parameter
Area/island (cm2)
R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W*s/C) C2 (W*s/C) C3 (W*s/C) C4 (W*s/C) C5 (W*s/C) C6 (W*s/C)
FP
0.8 2.6 3.5 21 16 58 0.00006 0.0005 0.0075 0.045 0.35 1.05
2
28
2
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Package and packing information
5
Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
5.1
DPAK mechanical data
Figure 42. DPAK package dimensions
P032P
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Package and packing information Table 8. DPAK mechanical data
VND1NV04 - VNN1NV04 - VNS1NV04
mm. Dim. Min.
A A1 A2 B B2 C C2 D D1 E E1 e G H L2 L4 R V2 Package weight 0 0.60 0.2 8 Gr. 0.29 4.40 9.35 0.8 1.00 6.40 4.7 2.28 4.60 10.10 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 5.1 6.60
Typ.
Max.
2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20
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Package and packing information
5.2
SOT-223 mechanical data
Figure 43. SOT-223 mechanical data & package outline
5.3
SO8 mechanical data
Table 9.
Dim. Min.
A A1 A2 0.10 1.25
SO-8 mechanical data
mm Typ. Max.
1.75 0.25
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Package and packing information Table 9.
Dim. Min.
b c D(1) E E1(2) e h L L1 k ccc 0 0.25 0.40 0.28 0.17 4.80 5.80 3.80
VND1NV04 - VNN1NV04 - VNS1NV04
SO-8 mechanical data (continued)
mm Typ. Max.
0.48 0.23 4.90 6.00 3.90 1.27 0.50 1.27 1.04 8 0.10 5.00 6.20 4.00
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.
Figure 44. SO-8 package dimension
0016023 D
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VND1NV04 - VNN1NV04 - VNS1NV04
Package and packing information
5.4
DPAK packing information
The devices can be packed in tube or tape and reel shipments (see the Device summary on page 1 ).
DPAK FOOTPRINT
A
TUBE SHIPMENT (no suffix)
C
B
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm.
75 3000 532 6 21.3 0.6
TAPE AND REEL SHIPMENT (suffix "13TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 16.4 60 22.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 16 4 8 1.5 1.5 7.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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Package and packing information
VND1NV04 - VNN1NV04 - VNS1NV04
5.5
SOT-223 packing information
Figure 45. SOT-223 tape and reel shipment (suffix "TR")
Reel dimensions
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 12.4 60 18.4
Tape dimensions
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D (+ 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
All dimensions are in mm.
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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Package and packing information
5.6
SO8 packing information
Figure 46. SO-8 tube shipment (no suffix)
B C
A
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
All dimensions are in mm.
100 2000 532 3.2 6 0.6
Figure 47. SO-8 tape and reel shipment (suffix "TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D (+ 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
All dimensions are in mm.
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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Revision history
VND1NV04 - VNN1NV04 - VNS1NV04
6
Revision history
Table 10.
Date
Feb-2003 16-Apr-2009
Document revision history
Revision
1 2 Initial release. Added Table 1: Device summary on page 1 and Section 4: Package and PCB thermal data Updated Section 5: Package and packing information on page 25
Changes
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VND1NV04 - VNN1NV04 - VNS1NV04
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