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M5481
LED DISPLAY DRIVER
FEATURES SUMMARY 2 DIGIT LED DRIVER (14 segments)
CURRENT GENERATOR OUTPUTS (no registor required) CONTINUOUS BRIGHTNESS CONTROL SERIAL DATA INPUT DATA ENABLE WIDE SUPPLY VOLTAGE OPERATION TLL COMPATIBILITY APPLICATION EXAMPLES MICROPROCESSOR DISPLAYS INDUSTRIAL CONTROL INDICATOR RELAY DRIVER INSTRUMENTATION READOUTS
through a variable resistor connected either to VDD or to a separate supply of 13.2V maximum. The M5481 is a pin-to-pin replacement of the NS MM 5481. Figure 1. Package

PDIP20 (Plastic package)
DESCRIPTION The M5481 is a monolithic MOS integrated circuit produced with a N-channel silicon gate technology. It uses the M5450 die packaged in a 20-pin plastic package copper frame, making it ideal for a 1-digit display. A single pin controls the LED display brightness by setting a reference current Figure 2. Pin Connections
Output Bit 8 Output Bit 7 Output Bit 6 Output Bit 5 Output Bit 4 Output Bit 3 Output Bit 2 Output Bit 1 Brightness Control VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Output Bit 9 Output Bit 10 Output Bit 11 Output Bit 12 Output Bit 13 VSS Output Bit 14 Data Enable Data In Clock
REV. 2 April 2004 1/10
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Figure 3. Block Diagram
VDD Brightness Control 100k Output Bit 14 Output Bit 1
10
14
8
9 1nF
35 Output Buffers
35 Latches Data Enable Serial Data
Load
13 12
35-Bit Shift Register
Clock
11 15
Reset
Table 1. Absolute Maximum Ratings
Symbol VDD VI VO(off) IO PTOT Tj TOP TSTG Supply Voltage Input Voltage Off State Output Voltage Output Sink Current Total Package Power Dissipation at 25C Total Package Power Dissipation at 85C Junction Temperature Operating Temperature Range Storage Temperature Range Parameter Value - 0.3 to 15 - 0.3 to 15 15 40 1.5 800 150 - 25 to 85 - 65 to 150 Unit V V V mA W mW C C C
Note: Stresses exceeding those listed under "Absolute Maximum Ratings" may cause permanent damage to the device and affect its reliability.
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Table 2. Static Electrical Characteristics (Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified)
Symbol VDD IDD VI Parameter Supply Voltage Supply Current Input Voltage Logical "0" Level Logical "1" Level IB VB VO(off) IO Brightness Input Current (note 2) Brightness Input Voltage (pin 9) Off State Out. Voltage Out. Sink Current (note 3) Segment OFF Segment ON VO = 3V VO = 1V (note 4) Brightness In. = 0A Brightness In. = 100A Brightness In. = 750A fclock IO
Note: 1. 2. 3. 4.
Test Conditions VDD = 13.2V 10A Input Bias 4.75 VDD 5.25 VDD > 5.25 Input Current = 750A, Tamb = 25C
Min. 4.5 - 0.3 2.2 VDD - 2 0 3
Typ.
Max. 13.2 7 0.8 VDD VDD 0.75 4.3 13.2 10
Unit V mA V V V mA V V A A mA mA MHz %
0 2 12 0 2,7 15
10 4 25 0.5 20
Input Clock Frequency Output Matching (note 1)
Output matching is calculated as the percent variation from I MAX + IMIN/2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. Absolute maximum for each output should be limited to 40mA. The VO voltage should be regulated by the user.
FUNCTIONAL DESCRIPTION The M5481 uses the M5450 die which is packaged to operate 2-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 1nF capacitor should
be connected to brightness control (pin 9) to prevent possible oscillations. A block diagram is shown on Figure 3. The output current is typically 20 times greater than the current into pin 9, which is set by an external variable resistor. The latter is an internal limiting resistor of 400 nominal value. Figure 4 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a LOAD is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into the latches.
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Figure 4. Input Data Format
1 CLOCK START DATA BIT 1 BIT 34 BIT 35 36
LOAD (INTERNAL)
RESET (INTERNAL)
At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static master slave configurations. There is no clear for the master portion of the first shift register, thus allowing continuous operation. There must be a complete set of 36 clocks or the shift registers will not clear. When power is first applied to the chip an internal power ON reset signal is generated which resets all registers and all latches. The START bit and the first clock reset the chip to its normal operation. Figure 5 shows the timing relationships between Data, Clock and DATA ENABLE. A maximum clock frequency of 0.5MHz is assumed. Table 3 shows the Output Data Format for the M5481. Because it uses only 14 of the possible outputs, 21 of the bits (including bit 35 which was already unused in the M5450) are "Don't Cares" . For applications where a lesser number of outputs are used it is possible to either increase the current per output or operate the part at higher than 1V Vout. The following equation can be used for calculations.
Tj = [(Vout) (ILED) (No. of segments) + VDD x 7mA] x (80C/W) + Tamb where: Tj = junction temperature (150Cmax) Vout = voltage at the LED driver outputs ILED = LED current 80C/W = thermal coefficient of the package Tamb = ambiant temperature Figure 5.
CLOCK
DATA 300ns (min.)
DATA ENABLE 100ns (min.)
Table 3. Serial Data Bus / Outputs Correspondance
5451 5481 5450 5481 35 X 17 X 34 X 16 8 33 X 15 7 32 X 14 6 31 X 13 5 30 14 12 X 29 13 11 X 28 X 10 X 27 X 9 X 26 X 8 4 25 X 7 3 24 12 23 11 6 2 22 10 5 1 21 9 4 X 20 X 3 X 19 X 2 X 18 X 1 X START START START START
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TYPICAL APPLICATION Figure 6. BASIC electronically tuned TV system
LED DISPLAY
14 SEGMENTS
M5481
DISPLAY DRIVER
KEYBOARD
PROCESSOR
PLL SYNTHESIZER
POWER DISSIPATION OF THE IC The power dissipation of the IC can be limited using different configurations. Figure 7.
+VC
In this application R must be chosen taking into account the worst operating conditions. R is determined by the maximum number of segments activated.
V -V -V C DMAX OMIN R = ---------------------------------------------------------------N L MAX D
R
ID VD
VOUT
The worst case condition for the device is when roughly half of the maximum number of segments are activated. It must be checked that the total power dissipation does not exceed the absolute maximum ratings of the device. In critical cases more resistors can be used in conjunction with groups of segments.In this case the current variation in the single resistor is reduced and Ptot limited.
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Figure 8.
+VC
Figure 9.
+VC
VOUT+ VD
In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly chosen. The total power dissipation of the IC depends only, in first approximation, on the number of segments activated.
In this configuration VOUT+VD is constant. the total power dissipation of the IC depends only on the number of segments activated.
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PART NUMBERING Table 4. Order Codes
Part Number M5481 B7 Package PDIP Temperature Range -25 to 85 C
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PACKAGE MECHANICAL Table 5. PDIP20 - Mechanical Data
Symbol A a1 B b b1 C D E e e3 e4 F I L N R1 R2 K K1 K2 Z Typ 3.25 1.39 0.381 0.20 5.20 24.9 7.8 2.29 22.60 7.36 6.22 3.42 3.17 millimeters Min 3.30 0.508 0.457 0.254 5.33 25.15 8.5 2.54 22.86 7.62 6.35 3.68 3.30 7d 0.152 0.762 1.524 0.762 0.762 1.27 Max 3.35 1.65 0.533 0.30 5.46 25.4 9.1 2.79 23.11 7.87 6.50 3.93 3.42 Typ 0.128 0.055 0.015 0.008 0.205 0.980 0.307 0.090 0.890 0.290 0.245 0.135 0.125 inches Min 0.130 0.020 0.018 0.010 0.210 0.990 0.335 0.100 0.900 0.300 0.250 0.145 0.130 7d 0.006 0.030 0.060 0.030 0.030 0.050 Max 0.132 0.065 0.021 0.012 0.215 1.000 0.358 0.110 0.910 0.310 0.255 0.155 0.135
1.34
0.053
Figure 10. PDIP20 - Package Dimensions
R1 N e4 N
Note: Drawing is not to scale
K1 I K2 A a1 b R1 B e Z e3 D 20 1 R2 11 10 L
Tie Bar Center
N K C F E b1
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REVISION HISTORY Table 6. Revision History
Date October-2000 14-Apr-2004 Revision 1 2 First Issue Stylesheet update. No content change. Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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