View MAX5978_4905868.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-5328; Rev 0; 7/10
TION KIT EVALUA BLE AVAILA
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
General Description
The MAX5978 hot-swap controller provides complete protection for systems with a supply voltage from 0 to 16V. The device includes four programmable LED outputs. The IC provides two programmable levels of overcurrent circuit-breaker protection: a fast-trip threshold for a fast turn-off, and a lower slow-trip threshold for a delayed turn-off. The maximum overcurrent circuitbreaker threshold range is set with a trilevel logic input (IRNG), or by programming through the I2C interface. The IC is an advanced hot-swap controller that monitors voltage and current with an internal 10-bit ADC, which is continuously multiplexed to convert the output voltage and current at 10ksps. Each 10-bit sample is stored in an internal circular buffer so that 50 past samples of each signal can be read back through the I2C interface at any time or after a fault condition. The device includes five user-programmable digital comparators to implement overcurrent warning and two levels of overvoltage/undervoltage detection. When measured values violate the programmable limits, an external ALERT output is asserted. In addition to the ALERT signal, the IC can be programmed to deassert the powergood signal and/or turn off the external MOSFET. The IC features four I/Os that can be independently configured as general-purpose input/outputs (GPIOs) or as open-drain LED drivers with programmable blinking. These four I/Os can be configured for any mix of LED driver or GPIO function. The device is available in a 32-pin thin QFN-EP package and operates over the -40NC to +85NC extended temperature range.
Features
S Hot-Swap Controller Operates from 0 to 16V S 10-Bit ADC Monitors Load Voltage and Current S Circular Buffers Store 5ms of Current and Voltage
MAX5978
Measurements
S Internal Charge Pump Generates n-Channel
MOSFET Gate Drive
S Internal 500mA Gate Pulldown Current for Fast
Shutdown
S VariableSpeed/BilevelTM Circuit-Breaker
Protection
S Precision-Voltage Enable Input S Alert Output Indicates Fault and Warning
Conditions
S Open-Drain Power-Good Output with
Programmable Polarity
S Open-Drain Fault Output S Four Open-Drain General-Purpose Outputs Sink
25mA to Directly Drive LEDs
S Programmable LED Flashing Function S Latched-Off Fault Management S 400kHz I2C Interface S Small, 5mm x 5mm, 32-Pin TQFN-EP Package
Applications
Blade Servers DC Power Metering Disk Drives/DASD/Storage Systems Soft-Switch for ASICs, FPGAs, and Microcontrollers Network Switches/Routers
Ordering Information
PART MAX5978ETJ+ TEMP RANGE -40NC to +85NC PIN-PACKAGE 32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
VariableSpeed/Bilevel is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
ABSOLUTE MAXIMUM RATINGS
IN, SENSE, MON, GATE to AGND ...................... -0.3V to +30V LED_ to AGND .....................................................-0.3V to +16V PG, ON, ALERT, FAULT, SDA, SCL to AGND .......-0.3V to +6V REG, DREG, IRNG, MODE, PROT, A_ to AGND ...-0.3V to +4V REG to DREG ......................................................-0.3V to +0.3V HWEN, POL to AGND ............................-0.3V to (VREG + 0.3V) GATE to MON ........................................................-0.3V to +6V GND, DGND to AGND ........................................-0.3V to +0.3V SDA, ALERT Current ...................................... -20mA to +50mA LED_ Current ................................................ -20mA to +100mA GATE, MON, GND Current .............................................750mA *As per JEDEC51 Standard (Multilayer Board). Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All Other Pins Input/Output Current ..................................20mA Continuous Power Dissipation (TA = +70NC)* 32-Pin TQFN (derate 34.5mW/NC above +70NC) ..... 2759mW* Junction-to-Ambient Thermal Resistance (BJA) (Note 1).....+29NC/W Operating Temperature Range ........................ -40NC to +85NC Junction Temperature .................................................. +150NC Storage Temperature Range ......................... -65NC to +150NC Lead Temperature (soldering, 10s) ...............................+300NC Soldering Temperature (reflow) .....................................+260NC
ELECTRICAL CHARACTERISTICS
(VIN = 2.7V to 16V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VIN = 3.3V and TA = +25NC.) (Note 2) PARAMETER Supply Input Voltage Range Hot-Swap Voltage Range Supply Current Internal LDO Output Voltage Undervoltage Lockout Undervoltage-Lockout Hysteresis MON, SENSE Input Voltage Range SENSE Input Current MON Input Current Current Measurement LSB Voltage VSENSE, VMON = 16V VSENSE, VMON = 16V 25mV range 50mV range 100mV range VMON = 0V VSENSE - VMON = 5mV VSENSE - VMON = 20mV -6.57 -6.71 -9.71 -10.24 -4.24 -4.53 -4.50 -4.20 IIN REG UVLO UVLOHYS IREG = 0 to 5mA, VIN = 2.7V to 16V VIN rising 100 2.49 SYMBOL VIN CONDITIONS MIN 2.7 0 2.5 2.53 TYP MAX 16 16 4 2.6 2.6 UNITS V V mA V V mV
CURRENT-MONITORING FUNCTION 0 32 180 24.34 48.39 96.77 +6.22 +6.82 +8.92 +9.36 +3.78 +5.36 +4.00 +4.50 %FS %FS FV 16 75 280 V FA FA
Current Measurement Error (25mV Range)
VSENSE - VMON = 5mV VMON = 2.5V to 16V VSENSE - VMON = 20mV VSENSE - VMON = 10mV VMON = 0V VSENSE - VMON = 40mV VSENSE - VMON = 10mV VMON = 2.5V to 16V VSENSE - VMON = 40mV
Current Measurement Error (50mV Range)
2
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 2.7V to 16V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VIN = 3.3V and TA = +25NC.) (Note 2) PARAMETER Current Measurement Error (100mV Range) SYMBOL VMON = 0V CONDITIONS VSENSE - VMON = 20mV VSENSE - VMON = 80mV MIN -2.70 -3.63 -3.14 -3.80 -2.106 -2.986 -3.000 -3.500 -3.1188 -4.873 -3.2668 -4.7 -4.7987 -8.9236 -4.9991 -8.262 -1.7965 -1.86 -2.149 -2.2285 -2.3992 -2.5146 -2.4716 -2.7421 -3.3412 -3.8762 -3.2084 -3.8424 2 2.4 1.2 0.8 ms TYP MAX +2.43 +4.56 +3.19 +3.93 +0.888 +0.641 +1.000 +1.500 +0.926 +0.3421 +0.9228 +1.0212 +1.1812 +0.202 +0.6374 +1 +1.5496 +1.5916 +1.9868 +1.9982 +1.8723 +2.1711 +2.181 +2.1152 +2.989 +3.6789 +2.7798 +2.6483 Fs mV mV mV mV mV mV %FS UNITS
MAX5978
VSENSE - VMON = 20mV VMON = 2.5V to 16V VSENSE - VMON = 80mV VMON = 0V Circuit breaker, DAC = 102 Circuit breaker, DAC = 255 Circuit breaker, DAC = 102 Circuit breaker, DAC = 102 Circuit breaker, DAC = 255
Fast Current-Limit Threshold Error (25mV Range)
VMON = 2.5V to 16V Circuit breaker, DAC = 255 VMON = 0V
Fast Current-Limit Threshold Error (50mV Range)
Circuit breaker, DAC = 102 VMON = 2.5V to 16V Circuit breaker, DAC = 255 VMON = 0V Circuit breaker, DAC = 102 Circuit breaker, DAC = 255
Fast Current-Limit Threshold Error (100mV Range)
Circuit breaker, DAC = 102 VMON = 2.5V to 16V Circuit breaker, DAC = 255 VMON = 0V Circuit breaker, DAC = 102 Circuit breaker, DAC = 255
Slow Current-Limit Threshold Error (25mV Range)
Circuit breaker, DAC = 102 VMON = 2.5V to 16V Circuit breaker, DAC = 255 VMON = 0V Circuit breaker, DAC = 102 Circuit breaker, DAC = 255
Slow Current-Limit Threshold Error (50mV Range)
Circuit breaker, DAC = 102 VMON = 2.5V to 16V Circuit breaker, DAC = 255 VMON = 0V Circuit breaker, DAC = 102 Circuit breaker, DAC = 255
Slow Current-Limit Threshold Error (100mV Range) Fast Circuit-Breaker Response Time Slow Current-Limit Response Time THREE-STATE INPUTS A1, A0, IRNG, MODE, PROT Low Current A1, A0, IRNG, MODE, PROT High Current A1, A0, IRNG, MODE, PROT Open Current A1, A0, IRNG, MODE, PROT Low Voltage IIN_LOW IIN_HIGH IFLOAT
Circuit breaker, DAC = 102 VMON = 2.5V to 16V Circuit breaker, DAC = 255 tFCB Overdrive = 10% of current-sense range Overdrive = 4% of current-sense range tSCB Overdrive = 8% of current-sense range Overdrive = 16% of current-sense range
Input voltage = 0.4V Input voltage = VREG - 0.2V Maximum source/sink current for open state Relative to AGND
-40 40 -4 +4 0.4
FA FA FA V
3
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 2.7V to 16V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VIN = 3.3V and TA = +25NC.) (Note 2) PARAMETER A1, A0, IRNG, MODE, PROT High Voltage TWO-STATE INPUTS HWEN, POL Input Logic Low Voltage HWEN, POL Input Logic High Voltage HWEN, POL Input Current ON Input Voltage ON Input Hysteresis ON Input Current TIMING 50 MON-to-PG Delay Register configurable (see Tables 30a and 30b) 100 200 400 CHARGE PUMP (GATE) Charge-Pump Output Voltage Charge-Pump Output Source Current GATE Discharge Current OUTPUT (FAULT, PG, ALERT) Output-Voltage Low Output Leakage Current LED INPUT/OUTPUT LED_ Input Threshold Low Level LED_ Input Threshold High Level LED_ Output Low LED_ Input Leakage Current (Open Drain) LED_ Weak Pullup Current ADC PERFORMANCE Resolution Maximum Integral Nonlinearity ADC Total Monitoring Cycle Time INL 95 10 1 100 110 Bits LSB Fs VIL VIH VOH IGPIO_IX IPU_WEAK ILED_ = 25mA VLED_ = 16V VLED_ = VIN - 0.65V -1 2 1.4 0.7 +1 0.4 V V V FA FA VGATE - VMON = 2V ISINK = 3.2mA Relative to VMON, IGATE = 0V 4.5 4 5.3 5 500 0.2 1 5.5 6 V FA mA V FA ms VON VONHYS -100 VREG - 0.4 -1 0.582 0.592 4 +100 +1 0.602 0.4 V V FA V % nA SYMBOL CONDITIONS Relative to VREG MIN -0.24 TYP MAX UNITS V
4
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 2.7V to 16V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VIN = 3.3V and TA = +25NC.) (Note 2) PARAMETER SYMBOL 16V range MON LSB Voltage 8V range 4V range 2V range 16V range MON Code 000H to 001H Transition Voltage I2C INTERFACE Serial-Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Setup Time START Condition Hold Time STOP Condition Setup Time Clock High Period Clock Low Period Data Setup Time Data Hold Time Output Fall Time Pulse Width of Spike Suppressed SDA, SCL Input High Voltage SDA, SCL Input Low Voltage SDA, SCL Input Hysteresis SDA, SCL Input Current SDA, SCL Input Capacitance SDA Output Voltage VOL ISINK = 4mA fSCL tBUF tSU:STA tHD:STA tSU:STO tHIGH tLOW tSU:DAT tHD:DAT tOF tSP VIH VIL VHYST -1 15 0.4 0.22 +1 1.8 0.8 Transmit Receive CBUS = 10pF to 400pF 50 1.3 0.6 0.6 0.6 0.6 1.3 100 100 300 900 250 400 kHz Fs Fs Fs Fs Fs Fs ns ns ns ns V V V FA pF V 8V range 4V range 2V range CONDITIONS MIN 15.23 7.655 3.811 1.899 10 4.7 2 0.5 TYP 15.49 7.743 3.875 1.934 25 12 6 3 MAX 15.69 7.811 3.933 1.966 41 21 12 5.5 mV mV UNITS
MAX5978
5
Note 2: All devices 100% production tested at TA = +25NC. Limits over the temperature range are guaranteed by design.
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Typical Operating Characteristics
(VIN = 3.3V, TA = +25NC, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5978 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX5978 toc02
2.9 2.8 SUPPLY CURRENT (mA) 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -40 -15 10 35 60
5.15 GATE-DRIVE VOLTAGE (V) 5.10 5.05 5.00 4.95 4.90 4.85
VGATE REFERRED TO VMON
SUPPLY CURRENT (mA)
2.45 HOT-SWAP CHANNEL ON 2.40
2.35
HOT-SWAP CHANNEL OFF
2.30 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V)
85
4.80 0 2 4 6 8 VMON (V) 10 12 14 16
TEMPERATURE (C)
GATE-DRIVE VOLTAGE vs. VIN
MAX5978 toc04
GATE-DRIVE CURRENT vs. (VGATE - VMON)
MAX5978 toc05
GATE-DRIVE DISCHARGE CURRENT vs. (VGATE - VMON)
GATE-DRIVE DISCHARGE CURRENT (A) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 (VGATE - VMON) (V)
MAX5978 toc06
5.10 5.05 (VGATE - VMON) (V) 5.00 4.95 4.90 4.85 0 2 4 6 8 VIN (V) 10 12 14 VMON = 12V VMON = 3.3V
10 9 GATE-DRIVE CURRENT (A) 8 7 6 5 4 3 2 1 0
1.0
16
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 (VGATE - VMON) (V)
SLOW-COMPARATOR TURN-OFF TIME vs. VOLTAGE OVERDRIVE
MAX5978 toc07
SLOW-COMPARATOR THRESHOLD VOLTAGE ERROR vs. TEMPERATURE
MAX5978 toc08
ON THRESHOLD VOLTAGE vs. TEMPERATURE
0.59 ON THRESHOLD VOLTAGE (V) 0.58 0.57 0.56 0.55 0.54 0.53 0.52 0.51 0.50 FALLING RISING
MAX5978 toc09
3.00 2.50 TURN-OFF TIME (ms) 2.00 1.50 1.00 0.50 0 0 1
THRESHOLD VOLTAGE ERROR (%)
25mV SENSE RANGE, DAC = 191, VTH,ST = 9.36mV
10 8 6 4 2 0 -2 -4 -6 -8 25mV SENSE RANGE -40 -15 10 35 60 -10 100mV SENSE RANGE 50mV SENSE RANGE
0.60
2
3
4
5
85
-40
-15
10
35
60
85
(VSENSE - VMON) - VTH,ST (mV)
TEMPERATURE (C)
TEMPERATURE (C)
6
MAX5978 toc03
2.50
GATE-DRIVE VOLTAGE vs. VMON
5.20
3.0
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Typical Operating Characteristics (continued)
(VIN = 3.3V, TA = +25NC, unless otherwise noted.)
TURN-OFF WAVEFORM (SLOW-COMPARATOR FAULT)
MAX5978 toc10 MAX5978 toc11
MAX5978
STARTUP WAVEFORM
VON 2V/div VGATE 5V/div VMON 5V/div
ILOAD 2A/div VGATE 10V/div
VPG 5V/div ILOAD 2A/div 10ms/div
VMON_ 10V/div VFAULT 5V/div 400s/div
TURN-OFF WAVEFORM (FAST-COMPARATOR FAULT/SHORT-CIRCUIT RESPONSE)
MAX5978 toc12
VOLTAGE BUFFER vs. TIME
14 VOLTAGE BUFFER (V) 12 10 8 6 4 2 0 CIRCULAR BUFFER CONTENT AT SLOW-TRIP FAULT MON = 16V, CURRENT SENSE = 50mV
MAX5978 toc13
16
ILOAD 5A/div
VGATE 10V/div
VMON 10V/div VFAULT 5V/div
100s/div
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5 2.0 2.5
TIME (ms)
SLOW-COMPARATOR FAULT EVENT
MAX5978 toc14
VOLTAGE ADC ACCURACY vs. MON VOLTAGE
0.8 VOLTAGE ADC ACCURACY (%FS) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 MON_ VOLTAGE RANGE = 4V
MAX5978 toc15
ILOAD 2A/div
1.0
VGATE 10V/div VMON 10V/div VFAULT 5V/div 400s/div
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VMON (V)
7
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Typical Operating Characteristics (continued)
(VIN = 3.3V, TA = +25NC, unless otherwise noted.)
CURRENT ADC ACCURACY vs. (VSENSE - VMON)
MAX5978 toc16
CURRENT BUFFER vs. TIME
MAX5978 toc17
VOLTAGE BUFFER vs. TIME
0.4 0.3 VOLTAGE BUFFER (V) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 VOLTAGE DATA AT SHORT CIRCUIT ON POWER-UP DEFAULT SETTING VMON = 16V
MAX5978 toc18
5 4 CURRENT ADC ACCURACY (%FS) 3 2 1 0 -1 -2 -3 -4 -5 0
10 9 8 CURRENT BUFFER (A) 7 6 5 4 3 2 1 0 -2.5 -2.0 -1.5 -1.0 -0.5 0 DEFAULT SETTING
0.5
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (VSENSE - VMON) (mV)
0.5 1.0 1.5 2.0 2.5
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5 2.0 2.5
TIME (ms)
TIME (ms)
STARTUP INTO SHORT LOAD
MAX5978 toc19
INPUT LEAKAGE CURRENT vs. MON VOLTAGE
180 INPUT-LEAKAGE CURRENT (A)
MAX5978 toc20
200 160 140 120 100 80 60 40 20 0 ISENSE IMON
VON 5V/div ILOAD 5A/div VGATE 2V/div VMON 1V/div VFAULT 5V/div 4ms/div
0
2
4
6
8 VMON (V)
10
12
14
16
8
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Pin Configuration
FAULT ALERT HWEN SDA SCL
MAX5978
TOP VIEW
I.C.
24 DGND 25 I.C. 26 I.C. 27 LED4 28 LED3 29 GND 30 I.C. 31 I.C. 32 1 IRNG
23
PG
22
21
20
19
18
ON 17 16 15 14 13 DREG POL LED2 LED1 GND GATE MON SENSE 12 11 10 9 8 PROT
MAX5978
+
2 IN 3 AGND 4 REG 5 BIAS 6 A1
EP
7 A0
TQFN
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME IRNG IN AGND REG BIAS A1 A0 PROT SENSE MON GATE GND LED1 LED2 FUNCTION Three-State Current-Sense Range Selection Input. Set the circuit-breaker threshold range by connecting to DGND, DREG, or leave unconnected. Power-Supply Input. Connect to a voltage from 2.7V to 16V. Bypass IN to AGND with a 1FF ceramic capacitor. Analog Ground. Connect all GND and DGND to AGND externally using a star connection. Internal Regulator Output. Bypass REG to ground with a 1FF ceramic capacitor. Connect only to DREG and logic-input pullup resistors. Do not use to power external circuitry. BIAS Input. Connect BIAS to REG. Three-State I2C Address Input 1 Three-State I2C Address Input 0 Protection Behavior Input. Three-state input sets one of three different response options for undervoltage and overvoltage events. Current-Sense Input. Connect SENSE to the source of an external MOSFET and to one end of RSENSE. Voltage-Monitoring Input Gate-Drive Output. Connect to the gate of an external n-channel MOSFET. Gate-Discharge Current Ground Return. Connect all GND and DGND to AGND externally using a star connection. LED1 Driver LED2 Driver
9
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Pin Description (continued)
PIN 15 16 17 18 19 20 21 22 23, 26, 27, 31, 32 24 25 28 29 30 -- NAME POL DREG ON FAULT SDA SCL ALERT PG I.C. FUNCTION Polarity Select Input. Connect POL to DREG for an active-high power-good (PG) output, or connect POL to GND for active-low PG output. Logic Power-Supply Input. Connect to REG externally through a 10I resistor and bypass to DGND with a 1FF ceramic capacitor. Precision Turn-On Input Active-Low Open-Drain Fault Output. FAULT asserts low if an overcurrent event occurs. I2C Serial Data Input/Output I2C Serial Clock Input Open-Drain Alert Output. ALERT goes low during a fault to notify the system of an impending failure. Open-Drain Power-Good Output Internally Connected. Connect to ground. Hardware Enable Input. Connect to REG or DGND. State is read upon power-up as VIN crosses the UVLO threshold and sets enable register bits with this value. After UVLO, this input becomes inactive until power is cycled. Digital Ground. Connect all GND and DGND to AGND externally using a star connection. LED Driver 4 LED Driver 3 Ground Exposed Pad. EP is internally grounded. Connect EP to the ground plane using a star connection.
HWEN DGND LED4 LED3 GND EP
10
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Typical Operating Circuit
VCC VCC
INT I/O
MAX5978
P
SDA SCLK I/O
VCC 4.7kI 4.7kI
VS
VIN = 2.7V TO 16V
R1 ID SETTING R2 R3
R1ON
FAULT ALERT
ON R2ON
SDA
SCL
IN
A0
A1
PG
V+
RLED3 V+ Q1 GATE LED3 SENSE RLED2 RLED1 RSENSE TO LOAD MON LED1 LED2
DGND DREG AGND POL PROT IRNG BIAS REG
RLED4
MAX5978
LED4
GND
10I 1F
1F
HWEN
CONFIGURATION SETTINGS
11
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Functional Diagram
DREG FAULT
MAX5978
SCOMP FROM CONFIGURATION REGISTERS ATTENUATOR
PG
FCOMP IRNG SENSE CS AMP MON LOGIC BLOCK CHARGE PUMP 2MHz 5A GATE GATE PULLDOWN GND UVLO OSCILLATOR VOLTAGE SCALING DAC SELECT REF 1V
LED_
HWEN ON POL PROT
MUX
BIAS SDA SCL
I2C
A0 A1 ALERT
IN REG LDO IREF 10-BIT ADC (SAR) AGND DGND CIRCULAR BUFF
12
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Detailed Description
The MAX5978 includes a set of registers that are accessed through the I2C interface. Some of the registers are read only and some of the registers are read and write registers that can be updated to configure the device for a specific operation. See Tables 1a and 1b for the register maps. Depending on the configuration of the EN1 and EN2 bits, when VIN is above the VUVLO threshold and the ON input reaches its internal threshold, the device turns on the external n-channel MOSFET for the hot-swap channel, allowing power to flow to the load. The channel is enabled depending on the output of a majority function. EN1, EN2, and ON are the inputs to the majority function and the channel is enabled when two or more of these inputs are 1: (Channel enabled) = (EN1 x EN2) + (EN1 x ON) + (EN2 x ON) Inputs ON and EN2 can be set externally; the initial state of the EN2 bit in register chxen is set by the state of the HWEN input when VIN rises above VUVLO. The ON input connects to an internal precision analog comparators with a 0.6V threshold. Whenever VON is above 0.6V, the ON bit in register status1[0] is set to 1. Inputs EN1 and EN2 can be set using the I2C interface; the EN1 bit has a default value of 0. This makes it possible to enable or disable the hot-swap channel with or without using the I2C interface (see Tables 2, 3a, and 3b).
MAX5978
Hot-Swap Channel On-Off Control
Table 1a. Register Address Map (Channel Specific)
REGISTER NAME adc_cs_msb adc_cs_lsb adc_mon_msb adc_mon_lsb min_cs_msb min_cs_lsb max_cs_msb max_cs_lsb min_mon_msb min_mon_lsb max_mon_msb max_mon_lsb uv1th_msb uv1th_lsb uv2th_msb uv2th_lsb ov1thr_msb ov1thr_lsb ov2thr_msb ov2thr_lsb oithr_msb oithr_lsb dac_fast cbuf_ba_v cbuf_ba_i DESCRIPTION High 8 bits ([9:2]) of latest current-signal ADC result Low 2 bits ([1:0]) of latest current-signal ADC result High 8 bits ([9:2]) of latest voltage-signal ADC result Low 2 bits ([1:0]) of latest voltage-signal ADC result High 8 bits ([9:2]) of current-signal minimum value Low 2 bits ([1:0]) of current-signal minimum value High 8 bits ([9:2]) of current-signal maximum value Low 2 bits ([1:0]) of current-signal maximum value High 8 bits ([9:2]) of voltage-signal minimum value Low 2 bits ([1:0]) of voltage-signal minimum value High 8 bits ([9:2]) of voltage-signal maximum value Low 2 bits ([1:0]) of voltage-signal maximum value High 8 bits ([9:2]) of undervoltage warning (UV1) threshold Low 2 bits ([1:0]) of undervoltage warning (UV1) threshold High 8 bits ([9:2]) of undervoltage critical (UV2) threshold Low 2 bits ([1:0]) of undervoltage critical (UV2) threshold High 8 bits ([9:2]) of overvoltage warning (OV1) threshold Low 2 bits ([1:0]) of overvoltage warning (OV1) threshold High 8 bits ([9:2]) of overvoltage critical (OV2) threshold Low 2 bits ([1:0]) of overvoltage critical (OV2) threshold High 8 bits ([9:2]) of overcurrent warning threshold Low 2 bits ([1:0]) of overcurrent warning threshold Fast-comparator threshold DAC setting Base address for block read of 50-sample voltage-signal data buffer Base address for block read of 50-sample current-signal data buffer REGISTER NUMBER 0x00 0x01 0x02 0x03 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x2E 0x46 0x47 RESET VALUE 0x00 0x00 0x00 0x00 0xFF 0x03 0x00 0x00 0xFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0x03 0xFF 0x03 0xFF 0x03 0xBF -- -- READ/ WRITE R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
13
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Table 1b. Register Address Map (General)
REGISTER NAME mon_range cbuf_chx_store ifast2slow status0 status1 status2 status3 fault0 fault1 fault2 pgdly fokey foset chxen dgl_i dgl_uv dgl_ov cbufrd_hibyonly cbuf_dly_stop peak_log_rst peak_log_hold LED_flash LED_ph_pu LED_state MON input range setting Selective enabling of circular buffer Current threshold fast-to-slow ratio setting Slow-trip and fast-trip comparators status register PROT, MODE, and ON inputs status register Fast-trip threshold maximum range setting bits, from IRNG threestate input LATCH, POL, ALERT, and PG status register Status register for undervoltage detection (warning or critical) Status register for overvoltage detection (warning or critical) Status register for overcurrent detection (warning) Delay setting between MON measurement and PG assertion Load register with 0xA5 to enable force-on function Register that enables force-on function Channel enable bits OC deglitch enable bits UV deglitch enable bits OV deglitch enable bits Circular buffers readout mode: 8 bit or 10 bit Circular buffer stop delay; number of samples recorded to the circular buffer after channel shutdown Reset control bits for peak-detection registers Hold control bits for peak-detection registers LED flash/GPIO enable register LED phase/weak pullup enable register LED pins voltage state register (LED pins set open) DESCRIPTION ADDRESS (HEX CODE) 0x18 0x19 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 RESET VALUE 0x00 0x0F 0x0F 0x00 -- -- -- 0x00 0x00 0x00 0x00 0x00 0x00 -- 0x00 0x00 0x00 0x0F 0x19 0x00 0x00 0x0F 0x00 -- READ/ WRITE R/W R/W R/W R R R/W R R/C R/C R/C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Table 2. chxen Register Format
Description: Resister Title: Register Address: R -- Bit 7 R -- Bit 6 Channel enable bits chxen 0x3B R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W EN2 Bit 1 R/W EN1 Bit 0 RESET VALUE -- --
14
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Table 3a. Register Function
REGISTER ADDRESS BIT RANGE ON input state 1 = ON above 600mV channel enable threshold [1:0] 0 = ON below 600mV channel enable threshold Bit 0: ON input state Bit 1: unused 0x32 [4] Unused Voltage critical behavior (PROT input) 00 = Assert ALERT upon UV/OV critical (same as UV/OV warning behavior) [7:6] 01 = Assert ALERT and deassert PG upon UV/OV critical 10 = Assert ALERT, deassert PG, and shut down channel upon UV/OV critical 11 = (Not possible) DESCRIPTION
MAX5978
Table 3b. status1 Register Format
Description: Resister Title: Register Address: R prot[1] Bit 7 R prot[0] Bit 6 Fault-detection behavior (three-state PROT input) and ON input status register status1 0x32 R -- Bit 5 R Unused Bit 4 R -- Bit 3 R -- Bit 2 R Unused Bit 1 R ON Bit 0 RESET VALUE -- --
Figure 1 shows the detailed logic operation of the hotswap enable signals EN1, EN2, and ON, as well as the effect of various fault conditions. An input undervoltage threshold control for enabling the hot-swap channel can be implemented by placing a resistive divider between the drain of the hot-swap MOSFET and ground, with the midpoint connected to ON. The turn-on threshold voltage for the channel is then: VEN = 0.6V x (R1 + R2)/R2 The maximum rating for the ON input is 6V; do not exceed this value. When all conditions for channel turn-on are met, the external n-channel MOSFET switch is fully enhanced with a typical gate-to-source voltage of 5V to ensure a low drain-to-source resistance. The charge pump at the GATE driver sources 5FA to control the output voltage turn-on voltage slew rate. An external capacitor can be added from GATE to GND to further reduce the
voltage slew rate. Placing a 1kI resistor in series with this capacitance prevents the added capacitance from increasing the gate turn-off time. Total inrush current is the load current summed with the product of the gatevoltage slew rate dV/dt and the load capacitance. To determine the output dV/dt during startup, divide the GATE pullup current IG(UP) by the gate-to-ground capacitance. The voltage at the source of the external MOSFET follows the gate voltage, so the load dV/dt is the same as the gate dV/dt. Inrush current is the product of the dV/dt and the load capacitance. The time to start up tSU is the hot-swap voltage VS divided by the output dV/dt. Be sure to choose an external MOSFET that can handle the power dissipated during startup. The inrush current is roughly constant during startup and the voltage drop across the MOSFET (drain to source) decreases linearly as the load capacitance charges. The resulting power dissipation is, therefore, roughly equivalent to a single pulse of magnitude (VS x inrush current)/2 and
Startup
15
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
ON
FORCE-ON BIT EN1 BIT
EN2 BIT
CHANNEL ENABLED
ANALOG SLOW TRIP ANALOG FAST TRIP
S R
Q Q 200ms DELAY, THEN PULSE
UV/OV CRITICAL
S R
Q Q
PROT
Figure 1. Channel On-Off Control Logic Functional Schematic
duration tSU. Refer to the thermal resistance charts in the MOSFET data sheet to determine the junction temperature rise during startup, and ensure that this does not exceed the maximum junction temperature for worstcase ambient conditions. As the channel is turned on and during normal operation, two analog comparators are used to detect an overcurrent condition by sensing the voltage across an external resistor connected between SENSE and MON. If the voltage across the sense resistor is less than the slow-trip and fast-trip circuit-breaker thresholds, the GATE output remains high. If either of the thresholds is exceeded due to an overcurrent condition, the gate of the MOSFET is pulled down to MON by an internal 500mA current source. The higher of the two comparator thresholds, the fast trip, is set by an internal 8-bit DAC (see Table 7), within one of three configurable full-scale current-sense
Circuit-Breaker Protection
ranges: 25mV, 50mV, or 100mV (see Tables 6a and 6b). The 8-bit fast-trip threshold DAC can be programmed from 40% to 100% of the selected full-scale currentsense range. The slow-trip threshold follows the fast-trip threshold as one of four programmable ratios, set by the ifast2slow register (see Tables 4a and 4b). The fast-trip threshold is always higher than the slow-trip threshold, and the fast-trip comparator responds very quickly to protect the system against sudden, severe overcurrent events. The slower response of the slowtrip comparator varies depending upon the amount of overdrive beyond the slow-trip threshold. If the overdrive is small and short lived, the comparator will not shut down the affected channel. As the overcurrent event increases in magnitude, the response time of the slowtrip comparator decreases. This scheme provides good noise rejection and spurious overcurrent transients near the slow-trip threshold, while aggressively protecting the system against larger overcurrent events that occur as a result of a load fault.
16
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Table 4a. ifast2slow Register Format
Description: Resister Title: Register Address: R -- Bit 7 R -- Bit 6 Current threshold fast-to-slow setting bits ifast2slow 0x30 R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W FS1 Bit 1 R/W FS0 Bit 0 RESET VALUE 0x0F --
MAX5978
Table 4b. Setting Fast-Trip to Slow-Trip Threshold Ratio
FS1 0 0 1 1 FS0 0 1 0 1 FAST-TRIP TO SLOW-TRIP RATIO (%) 125 150 175 200
To select and set the device slow-trip and fast-trip comparator thresholds, use the following procedure: 1) Select one of four ratios between the fast-trip threshold and the slow-trip threshold: 200%, 175%, 150%, or 125%. A system that experiences brief but large transient load currents should use a higher ratio, whereas a system that operates continuously at higher average load currents might benefit from a smaller ratio to ensure adequate protection. The ratio is set by writing to the ifast2slow register. (The default setting on power-up is 200%.)
Setting Circuit-Breaker Thresholds
range is initially set upon power-up by the state of the IRNG input, but can be altered at any time by writing to the status2 register. For maximum accuracy and best measurement resolution, select the lowest current-sense range that is larger than the VTH,FT value calculated in step 3. 5) Program the fast-trip and slow-trip thresholds by writing an 8-bit value to the dac_fast register. This 8-bit value is determined from the desired VTH,ST value that was calculated in step 2, the threshold ratio from step 1, and the current-sense range from step 4: DAC = VTH,ST x 255 x (ifast2slow ratio)/ (IRNG current-sense range) The device provides a great deal of system flexibility because the current-sense range, DAC setting, and threshold ratio can be changed "on the fly" for systems that must protect a wide range of interchangeable load devices, or for systems that control the allocation of power to smart loads. Table 5 shows the specified ranges for the fast-trip and slow-trip thresholds for all combinations of current-sense range and threshold ratio. When an overcurrent event causes the device to shut down the power channel, the open-drain FAULT output alerts the system. Figure 2 shows the operation and faultmanagement flowchart.
2) Determine the slow-trip threshold VTH,ST based on the anticipated maximum continuous load current during normal operation, and the value of the current-sense resistor. The slow-trip threshold should include some margin (possibly 20%) above the maximum load current to prevent spurious circuit-breaker shutdown and to accommodate passive component tolerances: VTH,ST = RSENSE x ILOAD,MAX x 120% 3) Calculate the necessary fast-trip threshold VTH,FT based on the ratio set in step 1: VTH,FT = VTH,ST x (ifast2slow ratio) 4) Select one of the three maximum current-sense ranges: 25mV, 50mV, or 100mV. The current-sense
17
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Table 5. Specified Current-Sense and Circuit-Breaker Threshold Ranges
IRNG INPUT DAC OUTPUT RANGE (DEFAULT = FULL SCALE) (mV) FAST-TRIP THRESHOLD RANGE (mV) GAIN (2 BIT) (VFAST/ VSLOW) ifast2slow (DEFAULT = 11) 00 (125%) Low 10 to 25 10 to 25 01 (150%) 10 (175%) 11 (200%) 00 (125%) High 20 to 50 20 to 50 01 (150%) 10 (175%) 11 (200%) 00 (125%) Unconnected 40 to 100 40 to 100 01 (150%) 10 (175%) 11 (200%) SLOW-TRIP THRESHOLD RANGE (mV) 8.00 to 20.00 6.67 to 16.67 5.71 to 14.29 5.00 to 12.50 16.00 to 40.00 13.33 to 33.33 11.48 to 28.57 10.00 to 25.00 32.00 to 80.00 26.67 to 66.67 22.86 to 57.14 20.00 to 50.00
Table 6a. IRNG Input Status Register Format
Description: Resister Title: Register Address: R -- Bit 7 R -- Bit 6 Fast-trip threshold maximum range-setting bits, from IRNG three-state input status2 0x33 R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W IRNG1 Bit 1 R/W IRNG0 Bit 0 RESET VALUE -- --
Table 6b. Setting Current-Sense Range
IRNG PIN STATE Low High Open IRNG1 1 0 0 IRNG0 0 1 0 MAXIMUM CURRENT-SENSE SIGNAL (mV) 25 50 100
Table 7. dac_ch_ Register Format
Description: Register Title: Register Addresses: R/W DAC[7] Bit 7 R/W DAC[6] Bit 6 Fast-comparator threshold DAC setting dac_fast 0x2E R/W DAC[5] Bit 5 R/W DAC[4] Bit 4 R/W DAC[3] Bit 3 R/W DAC[2] Bit 2 R/W DAC[1] Bit 1 R/W DAC[0] Bit 0 RESET VALUE 0xBF --
18
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
VIN > 2.7V
YES
READ, PROT, A0, A1, HWEN, IRNG INPUTS, CLEAR FLAGS
ARE 2 OR MORE OF 3 ENABLE SET?
YES CHANNEL ENABLED
NO
NO
START CIRCULAR BUFFER
CONTINUOUSLY SAMPLE VOLTAGE AND CURRENT, UPDATE MIN-MAX VALUES, HANDLE I2C COMMUNICATIONS, STORE SAMPLES TO CIRCULAR BUFFERS... NORMAL OPERATION ASSERT PG AFTER ADJUSTABLE DELAY YES
ENABLE GATE PULLUP
MON > UV1 AND UV2?
NO CIRCUIT-BREAKER TRIP? YES ARE 2 OR MORE OF 3 ENABLE SET? YES UV, OV, OR OC WARNING OR CRITICAL YES
NO NO SET FAULT, CLEAR PG, AND SHUT DOWN THE CHANNEL CLEAR PG AND SHUT DOWN THE CHANNEL
NO
SET ALERT, PG PER PROT INPUT
YES
PROT INPUT = GND
BUFFER STOP-DELAY EXPIRED
YES
STOP CIRCULAR BUFFER NO READ IRNG INPUT, CLEAR FLAGS, CLEAR ALERT, CLEAR FAULT NORMAL OPERATION
NO
NO
ARE 2 OR MORE OF 3 ENABLE SET?
YES CHANNEL ENABLED YES ARE 2 OR MORE OF 3 ENABLE SET?
NO
Figure 2. Operation and Fault-Management Flowchart for Hot-Swap Channel
19
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
The current-sense signal is sampled by the internal 10-bit, 10ksps ADC, and the most recent results are stored in registers for retrieval through the I2C interface. The current conversion values are 10 bits wide, with the 8 high-order bits written to one 8-bit register and the 2 low-order bits written to the next-higher 8-bit register address (Tables 8 and 9). This allows use of just the high-order byte in applications where 10-bit precision is not required. This split 8-bit/2-bit storage scheme is used
Digital Current Monitoring
throughout the device for ADC conversion results and digital comparator thresholds. Once the PG output is asserted, the current-sense samples are continuously compared to the programmable overcurrent warning register value. If the measured current value exceeds the warning level, the ALERT output is asserted. The device response to this digital comparator is not altered by the setting of the PROT input (Tables 10 and 11).
Table 8. ADC Current-Conversion Results Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R inew_9 Bit 7 R inew_8 Bit 6 Most recent current-conversion result, high-order bits [9:2] adc_cs_msb 0x00 R inew_7 Bit 5 R inew_6 Bit 4 R inew_5 Bit 3 R inew_4 Bit 2 R inew_3 Bit 1 R inew_2 Bit 0 RESET VALUE 0x00 --
Table 9. ADC Current-Conversion Results Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Most recent current-conversion result, low-order bits [0:1] adc_cs_ lsb 0x01 R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R inew_1 Bit 1 R inew_0 Bit 0 RESET VALUE 0x00 --
Table 10. Overcurrent Warning Threshold Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R/W oi_9 Bit 7 R/W oi_8 Bit 6 Overcurrent warning threshold high-order bits [9:2] oithr_msb 0x22 R/W oi_7 Bit 5 R/W oi_6 Bit 4 R/W oi_5 Bit 3 R/W oi_4 Bit 2 R/W oi_3 Bit 1 R/W oi_2 Bit 0 RESET VALUE 0xFF --
Table 11. Overcurrent Warning Threshold Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R/W -- Bit 7 20 R/W -- Bit 6 Overcurrent warning threshold low-order bits [1:0] oithr_lsb 0x23 R/W -- Bit 5 R/W -- Bit 4 R/W -- Bit 3 R/W -- Bit 2 R/W oi_1 Bit 1 R/W oi_0 Bit 0 RESET VALUE 0x03 --
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Current-sense measurement values from the ADC are continuously compared with the contents of minimumand maximum-value registers, and if the most recent measurement exceeds the stored maximum, or is less than the stored minimum, the corresponding register
Minimum and Maximum Value Detection for Current-Measurement Values
is updated with the new value. These "peak-detection" registers are read/write accessible through the I2C interface (Tables 12-15). The minimum-value registers are reset to 0xFF and the maximum-value registers are reset to 0x00. These reset values are loaded upon startup of the channel or at any time as commanded by register peak_log_rst (Table 35).
MAX5978
Table 12. ADC Minimum Current-Conversion Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R imin_9 Bit 7 R imin_8 Bit 6 Minimum current-conversion result high-order bits [9:2] min_cs_msb 0x08 R imin_7 Bit 5 R imin_6 Bit 4 R imin_5 Bit 3 R imin_4 Bit 2 R imin_3 Bit 1 R imin_2 Bit 0 RESET VALUE 0xFF --
Table 13. ADC Minimum Current-Conversion Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Minimum current-conversion result low-order bits [1:0] min_cs_ lsb 0x09 R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R imin_1 Bit 1 R imin_0 Bit 0 RESET VALUE 0x03 --
Table 14. ADC Maximum Current-Conversion Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R imax_9 Bit 7 R imax_8 Bit 6 Maximum current-conversion result high-order bits [9:2] max_cs_msb 0x0A R imax_7 Bit 5 R imax_6 Bit 4 R imax_5 Bit 3 R imax_4 Bit 2 R imax_3 Bit 1 R imax_2 Bit 0 RESET VALUE 0x00 --
Table 15. ADC Maximum Current-Conversion Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Maximum current-conversion result low-order bits [1:0] max_cs_lsb 0x0B R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R imax_1 Bit 1 R imax_0 Bit 0 RESET VALUE 0x00 --
21
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
The voltage at the load (MON input) is sampled by the internal ADC. The MON full-scale voltage can be set to 16V, 8V, 4V, or 2V by writing to register mon_range. The default range is 16V (Tables 16 and 17). The most recent voltage-conversion results can be read from the adc_mon_msb and adc_mon_lsb registers (see Tables 18 and 19).
Digital Voltage Monitoring and Power-Good Output
The most recent voltage values are continuously compared to four programmable limits, comprising two undervoltage (UV) levels (see Tables 20 to 23) and two overvoltage (OV) levels (see Tables 24 to 27). If PG is asserted and the voltage is outside the warning limits, the ALERT output is asserted low. Depending on the status of the prot[] bits in register status1[7:6], the
Digital Undervoltage- and OvervoltageDetection Thresholds
Table 16. ADC Voltage Monitor Settings Register Format
Description: Register Title: Register Addresses: R/W -- Bit 7 R/W -- Bit 6 ADC voltage monitor full-scale range settings (for MON input) mon_range 0x18 R/W -- Bit 5 R/W -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W MON_rng1 Bit 1 R/W MON_rng0 Bit 0 RESET VALUE 0x00 --
Table 17. ADC Full-Scale Voltage Setting
MON_rng1 0 0 1 1 MON_rng0 0 1 0 1 ADC FULL-SCALE VOLTAGE (V) 16 8 4 2
Table 18. ADC Voltage-Conversion Result Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R vnew_9 Bit 7 R vnew_8 Bit 6 Most recent voltage-conversion result, high-order bits [9:2] adc_mon_msb 0x02 R vnew_7 Bit 5 R vnew_6 Bit 4 R vnew_5 Bit 3 R vnew_4 Bit 2 R vnew_3 Bit 1 R vnew_2 Bit 0 RESET VALUE 0x00 --
Table 19. ADC Voltage-Conversion Result Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Most recent voltage-conversion result, low-order bits [1:0] adc_mon_lsb 0x03 R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R vnew_1 Bit 1 R vnew_0 Bit 0 RESET VALUE 0x00 --
22
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
device can also deassert the PG output or turn off the external MOSFET when the voltage is outside the critical limits (see Figure 3). Table 28 shows the behavior for the three possible states of the PROT input. Note that the PROT input does not affect the device response to the UV or OV warning digital comparators; it only determines the system response to the critical digital comparators (see Tables 3a, 3b, and 28). In a typical application, the UV1 and OV1 thresholds would be set closer to the nominal output voltage, and the UV2 and OV2 thresholds would be set further from nominal. This provides a "progressive" response to a voltage excursion. However, the thresholds can be configured in any arrangement or combination as desired to suit a given application.
MAX5978
OV2 CRITICAL THRESHOLD
OV1 WARNING THRESHOLD VMON NORMAL RANGE
UV1 WARNING THRESHOLD
UV2 CRITICAL THRESHOLD
Figure 3. Graphical Representation of Typical UV and OV Thresholds Configuration
Table 20. Undervoltage Warning Threshold Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R/W uv1_9 Bit 7 R/W uv1_8 Bit 6 Undervoltage warning threshold high-order bits [9:2] uv1th_msb 0x1A R/W uv1_7 Bit 5 R/W uv1_6 Bit 4 R/W uv1_5 Bit 3 R/W uv1_4 Bit 2 R/W uv1_3 Bit 1 R/W uv1_2 Bit 0 RESET VALUE 0x00 --
Table 21. Undervoltage Warning Threshold Register Format (Low-Order Bits)
Description: Register Titles: Register Addresses: R -- Bit 7 R -- Bit 6 Undervoltage warning threshold low-order bits [1:0] uv1th_Isb 0x1B R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R/W uv1_1 Bit 1 R/W uv1_0 Bit 0 RESET VALUE 0x00 -- 23
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Table 22. Undervoltage Critical Threshold Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R/W uv2_9 Bit 7 R/W uv2_8 Bit 6 Undervoltage critical threshold high-order bits [9:2] uv2th_msb 0x1C R/W uv2_7 Bit 5 R/W uv2_6 Bit 4 R/W uv2_5 Bit 3 R/W uv2_4 Bit 2 R/W uv2_3 Bit 1 R/W uv2_2 Bit 0 RESET VALUE 0x00 --
Table 23. Undervoltage Critical Threshold Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Undervoltage critical threshold low-order bits [1:0] uv2th_lsb 0x1D R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R/W uv2_1 Bit 1 R/W uv2_0 Bit 0 RESET VALUE 0x00 --
Table 24. Overvoltage Warning Threshold Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R/W ov1_9 Bit 7 R/W ov1_8 Bit 6 Overvoltage warning threshold high-order bits [9:2] ov1thr_msb 0x1E R/W ov1_7 Bit 5 R/W ov1_6 Bit 4 R/W ov1_5 Bit 3 R/W ov1_4 Bit 2 R/W ov1_3 Bit 1 R/W ov1_2 Bit 0 RESET VALUE 0xFF --
Table 25. Overvoltage Warning Threshold Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Overvoltage warning threshold low-order bits [1:0] ov1thr_lsb 0x1F R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R/W ov1_1 Bit 1 R/W ov1_0 Bit 0 RESET VALUE 0x03 --
Table 26. Overvoltage Critical Threshold Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R/W ov2_9 Bit 7 24 R/W ov2_8 Bit 6 Overvoltage critical threshold high-order bits [9:2] ov2thr_msb 0x20 R/W ov2_7 Bit 5 R/W ov2_6 Bit 4 R/W ov2_5 Bit 3 R/W ov2_4 Bit 2 R/W ov2_3 Bit 1 R/W ov2_2 Bit 0 RESET VALUE 0xFF --
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Table 27. Overvoltage Critical Threshold Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Overvoltage critical threshold low-order bits [1:0] ov2thr_lsb 0x21 R -- Bit 5 R -- Bit 4 R -- Bit 3 R/W -- Bit 2 R/W ov2_1 Bit 1 R/W ov2_0 Bit 0 RESET VALUE 0x03 --
MAX5978
Table 28. PROT Input and prot[] Bits
PROT INPUT STATE Low High Unconnected prot[1] 0 0 1 prot[0] 0 1 0 UV/OV WARNING ACTION Assert ALERT Assert ALERT Assert ALERT UV/OV CRITICAL ACTION Assert ALERT, clear PG, shut down channel Assert ALERT, clear PG Assert ALERT
Table 29. status3 Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Power-good status register: POL, ALERT, and power-good bits status3 0x34 R POL Bit 5 R/W ALERT Bit 4 R -- Bit 3 R -- Bit 2 R Unused Bit 1 R pg[0] Bit 0 RESET VALUE -- --
Table 30a. Power-Good Assertion Delay-Time Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Power-good assertion delay-time register pgdly 0x38 R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W pgdly1 Bit 1 R/W pgdly0 Bit 0 RESET VALUE 0x00 --
Table 30b. Power-Good Assertion Delay
pgdly1 0 0 1 1 pgdly0 0 1 0 1 PG ASSERTION DELAY (ms) 50 100 200 400
a power-good condition, regardless of the POL setting, which only affects the PG output pin polarity. The opendrain PG output can be configured for active-high or active-low status indication by the state of the POL input (see Table 29). The POL input sets the value of status3[5], which is a read-only bit; the state of the POL input can be changed at any time during operation and the polarity of the PG output changes accordingly. The assertion of the PG output is delayed by a userselectable time delay of 50ms, 100ms, 200ms, or 400ms (see Tables 30a and 30b).
25
The PG output is asserted when the voltage at MON is between the undervoltage and overvoltage critical limits. The status of the power-good signal is maintained in register status3[0]. A value of 1 in the pg[] bit indicates
Power-Good Detection and PG Output
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
All voltage-measurement values are compared with the contents of minimum- and maximum-value registers, and if the most recent measurement exceeds the stored maximum or is less than the stored minimum, the corresponding register is updated with the new value. These
Minimum and Maximum Value Detection for Voltage-Measurement Values
peak-detection registers are read accessible through the I2C interface (see Tables 31 to 34). The minimum-value registers are reset to 0xFF, and the maximum-value registers are reset to 0x00. These reset values are loaded upon startup or at any time as commanded by register peak_log_rst (see Table 35).
Table 31. ADC Minimum Voltage Conversion Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R vmin_9 Bit 7 R vmin_8 Bit 6 Minimum voltage conversion result, high-order bits [9:2] min_mon_msb 0x0C R vmin_7 Bit 5 R vmin_6 Bit 4 R vmin_5 Bit 3 R vmin_4 Bit 2 R vmin_3 Bit 1 R vmin_2 Bit 0 RESET VALUE 0xFF --
Table 32. ADC Minimum Voltage-Conversion Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Minimum voltage-conversion result, low-order bits [1:0] min_mon_lsb 0x0D R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R vmin_1 Bit 1 R vmin_0 Bit 0 RESET VALUE 0x03 --
Table 33. ADC Maximum Voltage-Conversion Register Format (High-Order Bits)
Description: Register Title: Register Addresses: R vmax_9 Bit 7 R vmax_8 Bit 6 Maximum voltage-conversion result, high-order bits [9:2] max_mon_msb 0x0E R vmax_7 Bit 5 R vmax_6 Bit 4 R vmax_5 Bit 3 R vmax_4 Bit 2 R vmax_3 Bit 1 R vmax_2 Bit 0 RESET VALUE 0x00 --
Table 34. ADC Maximum Voltage-Conversion Register Format (Low-Order Bits)
Description: Register Title: Register Addresses: R -- Bit 7 R -- Bit 6 Maximum voltage-conversion result, low-order bits [1:0] max_mon_lsb 0x0F R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R vmax_1 Bit 1 R vmax_0 Bit 0 RESET VALUE 0x00 --
26
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Using the Voltage and Current PeakDetection Registers The voltage and current minimum- and maximum-value records in register locations 0x08 through 0x17 can be reset by writing a 1 to the appropriate location in register peak_log_rst (see Table 35). The minimum-value registers are reset to 0xFF, and the maximum-value registers are reset to 0x000. As long as a bit in peak_log_rst is 1, the corresponding peak-detection registers are disabled and are "cleared" to their power-up reset values. The voltage and current minimum- and maximum-detection register contents can be "held" by setting bits in register peak_log_hold (see Table 36). Writing a 1 to a location in peak_log_hold locks the register contents for the corresponding signal and stops the min/max detection and logging; writing a 0 enables the detection and logging. Note that the peakdetection registers cannot be cleared while they are held by register peak_log_hold. The combination of these two control registers allows the user to monitor voltage and current peak-to-peak values during a particular time period.
MAX5978
Table 35. Peak-Detection Reset-Control Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Reset control bits for peak-detection registers peak_log_rst 0x41 R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W v_rst Bit 1 R/W i_rst Bit 0 RESET VALUE 0x00 --
Table 36. Peak-Detection Hold-Control Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Hold control bits for peak-detection registers peak_log_hold 0x42 R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W Ch0_v_hld Bit 1 R/W Ch0_i_hld Bit 0 RESET VALUE 0x00 --
27
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Table 37. OI Warning Comparators Deglitch Enable Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Deglitch enable register for overcurrent warning digital comparators dgl_i 0x3C R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R/W Unused Bit 1 R/W dgl_i Bit 0 RESET VALUE 0x00 --
Table 38. UV Warning and Critical Comparators Deglitch Enable Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Deglitch enable register for undervoltage warning and critical digital comparators dgl_uv 0x3D R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W dgl_uv2 Bit 1 R/W dgl_uv1 Bit 0 RESET VALUE 0x00 --
Table 39. OV Warning and Critical Comparators Deglitch Enable Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Deglitch enable register for overvoltage warning and critical digital comparators dgl_ov 0x3E R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W dgl_ov2 Bit 1 R/W dgl_ov1 Bit 0 RESET VALUE 0x00 --
The five digital comparators (undervoltage/overvoltage warning and critical, overcurrent warning) all have a user-selectable deglitching feature that requires two consecutive positive compares before the device takes action as determined by the particular compare and the setting of the PROT input. The deglitching functions are enabled or disabled by registers dgl_i, dgl_uv, and dgl_ov (Tables 37, 38, and 39). Writing a 1 to the appropriate bit location in these registers enables the deglitch function for the corresponding digital comparator. The device features two 10-bit "circular buffers" (in volatile memory) that contain a history of the 50 most-recent voltage and current digital-conversion results. These circular buffers can be read back through the I2C interface.
Deglitching of Digital Comparators
The recording of new data to the buffer for a given signal is stopped under any of the following conditions: * Thehot-swapchannelisshutdownbecauseofafault condition. * A read of the circular buffer base address is performed through the I2C interface. * Thehot-swapchannelisturnedoffbyacombination of the EN1, EN2, or ON signals. The buffers allow the user to recall the voltage and current waveforms for analysis and troubleshooting. The buffer contents are accessed through the I2C interface at two fixed addresses in the device register address space (see Table 40). Each buffer can also be stopped under user control by register cbuf_chx_store (see Table 41).
Circular Buffer
28
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
The contents of a buffer can be retrieved as a block read of either fifty 10-bit values (spanning 2 bytes each) or of 50 high-order bytes, depending on the per-signal bit settings of register cbufrd_hibyonly (see Table 42). If the circular buffer contents are retrieved as 10-bit data, the first byte read-out is the high-order 8 bits of the 10-bit sample, and the second byte read-out contains the 2 least-significant bits (LSBs) of the sample. This is repeated for each of the 50 samples in the buffer. Thus, 2 bytes must be read for each 10-bit sample retrieved. Conversely, if the buffer contents are retrieved as 8-bit data, then each byte read-out contains the 8 MSBs of each successive sample. It is important to remember that in 10-bit mode, 100 bytes must be read to extract the entire buffer contents, but in 8-bit mode, only 50 bytes must be read. The circular buffer system has a user-programmable "stop delay" that specifies a certain number of sample cycles to continue recording to the buffer after a shutdown occurs. This delay value is stored in register cbuf_dly_stop[5:0] (see Table 43). The default (reset) value of the buffer stop delay is 25 samples, which means that an equal number of samples are stored in the buffer preceding and following the moment of the shutdown event. The buffer stop delay is analogous to an oscilloscope trigger delay because it allows the device to record what happened both immediately before and after a shutdown. In other words, when the contents of a circular buffer are read out of the device, the shutdown event is by default located in the middle of the recorded data. The balance of data before and after an event can be altered by writing a different value (between 0 and 50) to the buffer stop-delay register. In the event of an overcurrent, undervoltage, or overvoltage condition that results in the shutdown of the hotswap channel, the device remains latched off.
MAX5978
Latched-Off Fault Management
To restart the latched-off channel, the user must either cycle power to the IN input, or toggle the ON pin, EN1 bit, or the EN2 bit.
Table 40. Circular Buffer Read Addresses
ADDRESS 0x46 0x47 NAME cbuf_ba_v cbuf_ba_i DESCRIPTION Base address for voltage buffer block read Base address for current buffer block read
Table 41. Circular Buffer Control Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Circular buffer run-stop control register (per-buffer control: 1 = run, 0 = stop) cbuf_chx_store 0x19 R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W Ch0_i_run Bit 1 R/W Ch0_v_run Bit 0 RESET VALUE 0x0F --
Table 42. Circular Buffer Resolution Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Circular buffer read-out resolution: high-order byte only, or 8-2 split 10-bit data (per-buffer control: 1 = high-order byte output, 0 = full-resolution 10-bit output) cbufrd_hibyonly 0x3F R -- Bit 5 R -- Bit 4 R/W Unused Bit 3 R/W Unused Bit 2 R/W i_res Bit 1 R/W v_res Bit 0 RESET VALUE 0x0F --
29
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Table 43. Circular Buffer Stop-Delay Register Format
Description: Register Title: Register Address: R 0 Bit 7 R 0 Bit 6 Circular buffer stop delay: any integer number between 0 and 50 samples that are to be recorded to a buffer after a shutdown event, before the buffer stops storing new data cbuf_dly_stop 0x40 R/W Stop_dly[5] Bit 5 R/W Stop_dly[4] Bit 4 R/W Stop_dly[3] Bit 3 R/W Stop_dly[2] Bit 2 R/W Stop_dly[1] Bit 1 R/W Stop_dly[0] Bit 0 RESET VALUE 0x19 --
Table 44. Force-On Control Register Format
Description: Register Title: Register Address: R 0 Bit 7 R 0 Bit 6 Force-on control register foset 0x3A R 0 Bit 5 R 0 Bit 4 R 0 Bit 3 R 0 Bit 2 R/W Unused Bit 1 R/W fo Bit 0 RESET VALUE 0x00 --
Table 45. Force-On Key Register Format
Description: Register Title: Register Address: R/W fokey[7] Bit 7 R/W fokey[6] Bit 6 Force-on key register (must contain 0xA5 to unlock force-on feature) fokey 0x39 R/W fokey[5] Bit 5 R/W fokey[4] Bit 4 R/W fokey[3] Bit 3 R/W fokey[2] Bit 2 R/W fokey[1] Bit 1 R/W fokey[0] Bit 0 RESET VALUE 0x00 --
When the force-on bit is set to 1 in register foset[0] (see Table 44), the channel is enabled regardless of the ON pin voltage or the EN1 and EN2 bits in register chxen. In forced-on operation, all functions operate normally with the notable exception that the channel does not shut down due to any fault conditions that may arise. There is a force-on key register fokey that must be set to 0xA5 in order for the force-on function to become active (see Table 45). If this register contains any value other
Force-On Function
than 0xA5, writing 1 to the force-on bits in register foset has no effect. This provides protection against accidental force-on operation that might otherwise be caused by an erroneous I2C write. The device provides detailed information about any fault conditions that have occurred. The FAULT output specifically indicates a circuit-breaker shutdown event, while the ALERT output is asserted whenever a problem has occurred that requires attention or interaction.
Fault Logging and Indications
30
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
If a fault event occurs (digital UV warning/critical, digital OV warning/critical, or digital overcurrent warning), the fault is logged by setting a corresponding bit in registers fault0, fault1, or fault2 (see Tables 46, 47, and 48). Likewise, circuit-breaker shutdown events are logged in register status0[7:0] (see Table 49).
Fault Dependency
IFAULTS indicates the overcurrent status from slow comparator. IFAULTF indicates overcurrent status from fast comparator. The status of FAULT reflects the OR operation of IFAULTS and IFAULTF. These fault register bits latch upon a fault condition, and must be reset manually by restarting as described in the Latched-Off Fault Management section.
MAX5978
Table 46. Undervoltage Status Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Undervoltage digital-compare status register (warning [0] and critical [4] undervoltage eventdetection status) fault0 0x35 R/C Unused Bit 5 R/C uv1 Bit 4 R -- Bit 3 R -- Bit 2 R/C Unused Bit 1 R/C uv1 Bit 0 RESET VALUE 0x00 --
Table 47. Overvoltage Status Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Overvoltage digital-compare status register (warning [0] and critical [4] overvoltage event-detection status) fault1 0x36 R/C Unused Bit 5 R/C ov2 Bit 4 R -- Bit 3 R -- Bit 2 R/C Unused Bit 1 R/C ov1 Bit 0 RESET VALUE 0x00 --
Table 48. Overcurrent Warning Status Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Overcurrent digital-compare status register (overcurrent warning event-detection status) fault2 0x37 R -- Bit 5 R -- Bit 4 R -- Bit 3 R -- Bit 2 R/C Unused Bit 1 R/C oi Bit 0 RESET VALUE 0x00 --
Table 49. Circuit-Breaker Event Logging Register Format
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 Circuit-breaker slow- and fast-trip event logging status0 0x31 R Unused Bit 5 R IFAULTS Bit 4 R -- Bit 3 R -- Bit 2 R Unused Bit 1 R IFAULTF Bit 0 RESET VALUE 0x00 -- 31
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
When an overcurrent event (fast trip or slow trip) causes the device to shut down the hot-swap channel, an opendrain FAULT output is asserted low. Note that the FAULT output is not asserted for shutdowns caused by critical undervoltage or overvoltage events. The FAULT output is cleared when the channel is disabled by pulling ON low or by clearing the bits in register chxen. ALERT is an open-drain output that is asserted low any time that a fault or other condition requiring attention has occurred. The state of the ALERT output is also indicated by status3[4]. The ALERT output is the logical NOR of registers 0x31, 0x35, 0x36, and 0x37, so when the ALERT output goes low, the system microcontroller should query these registers through the I2C interface to determine the cause of the ALERT assertion.
FAULT Output
The device has four open-drain LED drivers/user-programmable GPIOs. When programmed as LED drivers, each driver can sink up to 25mA of current. Table 50 shows the register that enables the drivers as either LED drivers or GPIOs. When any of the LED_ Set bit in the register is set to 1, the corresponding open-drain LED driver is turned off. The LED_Flash bits enable each corresponding LED driver to flash on and off at 1Hz frequency regardless of the condition of the corresponding LED_ Set bit. Bits 7-4 in Table 51 set the LED flashing drivers to be either in-phase or out-of-phase with the internal 1Hz clock. Bits 3-0 enable the 4FA pullup current to the corresponding output. Table 52 shows the LED state register. The LED state register is a read-only register. When the LEDs are disabled, the pins are configured as GPIOs. Applying an external voltage below 0.4V sets the GPIOs low and, applying an external voltage above 1.4V, sets the GPIOs high.
LED Set Registers
ALERT Output
Table 50. LED_Flash/GPIO Enable Register
Description: Register Title: Register Address: R/W LED4 Flash Bit 7 R/W LED3 Flash Bit 6 LED_ flash/GPIO enable register LED_flash 0x43 R/W LED2 Flash Bit 5 R/W LED1 Flash Bit 4 R/W LED4 Set Bit 3 R/W LED3 Set Bit 2 R/W LED2 Set Bit 1 R/W LED1 Set Bit 0 RESET VALUE 0x0F --
Table 51. LED Phase/Weak Pullup Enable Register
Description: Register Title: Register Address: R/W LED4 Phase Bit 7 R/W LED3 Phase Bit 6 LED phase/weak pullup enable LED_ph_pu 0x44 R/W LED2 Phase Bit 5 R/W LED1 Phase Bit 4 R/W LED4 Weak PU Bit 3 R/W LED3 Weak PU Bit 2 R/W LED2 Weak PU Bit 1 R/W LED1 Weak PU Bit 0 RESET VALUE 0x00 --
32
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Table 52. LED State Register
Description: Register Title: Register Address: R -- Bit 7 R -- Bit 6 LED state register LED_state 0x45 R -- Bit 5 R -- Bit 4 R LED4 Voltage Bit 3 R LED3 Voltage Bit 2 R LED2 Voltage Bit 1 R LED1 Voltage Bit 0 RESET VALUE -- --
MAX5978
SDA tBUF tHD:STA tSU:STO
tSU:DAT tLOW SCL tHIGH tHD:STA tR START CONDITION tF tHD:DAT
tSU:STA
REPEATED START CONDITION
STOP CONDITION
START CONDITION
Figure 4. Serial-Interface Timing Details
The device features an I2C-compatible serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL allow bidirectional communication between the device and the master device at clock rates from 100kHz to 400kHz. The I2C bus can have several devices (e.g., more than one device, or other I2C devices in addition to the device) attached simultaneously. The A0 and A1 inputs set one of nine possible I2C addresses (see Table 53). The 2-wire communication is fully compatible with existing 2-wire serial interface systems; Figure 4 shows the interface timing diagram. The device is a transmit/ receive slave-only device, relying upon a master device
I2C Serial Interface
to generate a clock signal. The master device (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the device by transmitting the proper address followed by command and/ or data words. Each transmit sequence is framed by a START (S) or Repeated START (SR) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is a logic input/opendrain output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7kI for most applications.
33
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Table 53. Device Slave Address Settings
ADDRESS INPUT STATE A1 Low Low Low High High High Open Open Open A0 Low High Open Low High Open Low High Open ADDR 7 0 0 0 0 0 0 0 0 0 ADDR 6 1 1 1 1 1 1 1 1 1 ADDR 5 1 1 1 1 1 1 1 1 1 I2C ADDRESS BITS ADDR 4 1 1 1 0 0 0 0 0 0 ADDR 3 0 0 0 1 1 1 0 0 0 ADDR 2 1 0 0 1 0 0 1 0 0 ADDR 1 0 1 0 0 1 0 0 1 0 ADDR 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W
SDA
SDA
SCL SCL S P STOP CONDITION
DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID
START CONDITION
Figure 5. Bit Transfer
Figure 6. START and STOP Conditions
Bit Transfer Each clock pulse transfers 1 data bit. The data on SDA must remain stable while SCL is high (see Figure 5); otherwise, the device registers a START or STOP condition (see Figure 6) from the master. SDA and SCL idle high when the bus is not busy. START and STOP Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START condition (see Figure 3) by transitioning SDA from high to low while SCL is high. The master device issues a STOP condition (see Figure 6) by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a Repeated START condition is generated, such as in the block read protocol (see Figure 7).
34
Early STOP Conditions The device recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal I2C format. At least one clock pulse must separate any START and STOP condition. Repeated START Conditions A Repeated START (SR) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation (see Figure 4). SR may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The device serial interface supports continuous write operations with or without an SR condition separating them. Continuous read operations require SR conditions because of the change in direction of data flow.
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
SEND BYTE FORMAT S ADDRESS 7 BITS WR 0 ACK DATA 8 BITS DATA BYTE-PRESETS THE INTERNAL ADDRESS POINTER. ACK P WRITE WORD FORMAT S ADDRESS 7 BITS WR 0 ACK COMMAND 8 BITS COMMAND BYTE- MSB OF THE EEPROM REGISTER BEING WRITTEN. ACK DATA 8 BITS ACK DATA 8 BITS ACK P
SLAVE ADDRESS- EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. RECEIVE BYTE FORMAT S ADDRESS 7 BITS WR 1
SLAVE ADDRESS- EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. WRITE BYTE FORMAT
DATA BYTE-FIRST BYTE IS THE LSB OF THE EEPROM ADDRESS. SECOND BYTE IS THE ACTUAL DATA.
ACK
DATA 8 BITS
ACK
P
S
ADDRESS 7 BITS
WR 0
ACK
COMMAND 8 BITS
ACK
DATA 8 BITS
ACK
P
SLAVE ADDRESS- EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE.
DATA BYTE-READS DATA FROM THE REGISTER COMMANDED BY THE LAST READ BYTE OR WRITE BYTE TRANSMISSION. ALSO DEPENDENT ON A SEND BYTE.
SLAVE ADDRESS- EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE.
COMMAND BYTE- SELECTS REGISTER BEING WRITTEN.
BLOCK WRITE FORMAT S ADDRESS 7 BITS WR 0 ACK COMMAND ACK 8 BITS COMMAND BYTE- PREPARES DEVICE FOR BLOCK OPERATION. BYTE COUNT = N 8 BITS ACK DATA BYTE 1 8 BITS ACK DATA BYTE ... 8 BITS ACK DATA BYTE N 8 BITS
DATA BYTE-DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE IF THE COMMAND IS BELOW 50h. IF THE COMMAND IS 80h, 81h, or 82h, THE DATA BYTE PRESETS THE LSB OF AN EEPROM ADDRESS.
ACK
P
SLAVE ADDRESS- EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. BLOCK READ FORMAT S ADDRESS 7 BITS WR 0 ACK
DATA BYTE-DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE.
COMMAND 8 BITS
ACK
SR
ADDRESS 7 BITS
WR 1
ACK
BYTE COUNT = 16 10h
ACK
DATA BYTE ACK 1 8 BITS
DATA BYTE ACK ... 8 BITS
DATA BYTE ACK N 8 BITS
P
SLAVE ADDRESS- COMMAND BYTE- EQUIVALENT TO CHIP- PREPARES DEVICE SELECT LINE OF A FOR BLOCK 3-WIRE INTERFACE. OPERATION.
SLAVE ADDRESS- EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE.
DATA BYTE-DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE.
S = START CONDITION P = STOP CONDITION
SHADED = SLAVE TRANSMISSION Sr = REPEATED START CONDITION
Figure 7. SMBus/I2C Protocols
35
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The device generates an ACK when receiving an address or data by pulling SDA low during the 9th clock period (see Figure 8). When transmitting data, such as when the master device reads data back from the device, the device waits for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. The device generates a NACK after the slave address during a software reboot or when receiving an illegal memory address. Send Byte The send byte protocol allows the master device to send 1 byte of data to the slave device (see Figure 7). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send an address that is not allowed. If the master sends a STOP condition, the internal address pointer does not change. The send byte procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit data byte. 5) The addressed slave asserts an ACK on SDA. 6) The master sends a STOP condition. Write Byte The write byte/word protocol allows the master device to write a single byte in the register bank or to write to a series of sequential register addresses. The write byte procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit command code. 5) The addressed slave asserts an ACK on SDA. 6) The master sends an 8-bit data byte. 7) The addressed slave asserts an ACK on SDA. 8) The addressed slave increments its internal address pointer. 9) The master sends a STOP condition or repeats steps 6, 7, and 8. To write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. The data byte is written to the register bank if the command code is valid.
START CONDITION 1 2
CLOCK PULSE FOR ACKNOWLEDGE
SCL
8
9
SDA BY TRANSMITTER
S SDA BY RECEIVER
Figure 8. Acknowledge
36
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers
Table 54. Circular Buffer Readout Sequence
READ-OUT ORDER Chronological Number 1ST OUT 1 2ND OUT 2 ... ... 48TH OUT 48 49TH OUT 49 50TH OUT 0
MAX5978
The slave generates a NACK at step 5 if the command code is invalid. The command code must be in the 0x00 to 0x45 range. The internal address pointer returns to 0x00 after incrementing from the highest register address. Receive Byte The receive-byte protocol allows the master device to read the register content of the device (see Figure 7). The EEPROM or register address must be preset with a send-byte protocol first. Once the read is complete, the internal pointer increases by one. Repeating the receive byte protocol reads the contents of the next address. The receive-byte procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a read bit (high). 3) The addressed slave asserts an ACK on SDA. 4) The slave sends 8 data bits. 5) The slave increments its internal address pointer. 6) The master asserts an ACK on SDA and repeats steps 4, 5 or asserts a NACK and generates a STOP condition. The internal address pointer returns to 0x00 after incrementing from the highest register address. Address Pointers Use the send-byte protocol to set the register address pointers before read and write operations. For the configuration registers, valid address pointers range from 0x00 to 0x45, and the circular buffer addresses are 0x46 to 0x49. Register addresses outside this range result in a NACK being issued from the device.
The circular buffer read operation is similar to the receive-byte operation. The read operation is triggered after any one of the circular buffer base addresses is loaded. During a circular buffer read, although all is transparent from the external world, internally the autoincrement function in the I2C controller is disabled. Thus, it is possible to read one of the circular buffer blocks with a burst read without changing the virtual internal address corresponding to the base address. Once the master issues a NACK, the circular reading stops, and the default functions of the I2C slave bus controller are restored. In 8-bit read mode, every I2C read operation shifts out a single sample from the circular buffer. In 10-bit mode, two subsequent I2C read operations shift out a single 10-bit sample from the circular buffer, with the high-order byte read first, followed by a byte containing the rightshifted 2 least-significant bits. Once the master issues a NACK, the read circular buffer operation terminates and normal I2C operation returns. The data in the circular buffers is read back with the next-to-oldest sample first, followed by progressively more recent samples until the most recent sample is retrieved, followed finally by the oldest sample (see Table 54).
Circular Buffer Read
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 90-0012
32 TQFN-EP
T3255+4
21-0140
37
0 to 16V, Hot-Swap Controller with 10-Bit Current, Voltage Monitor, and 4 LED Drivers MAX5978
Revision History
REVISION NUMBER 0 REVISION DATE 7/10 Initial release DESCRIPTION PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38
(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX5978

	To Download MAX5978 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .