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| Features * High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture - 130 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 20 MIPS Throughput at 20 MHz - On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory segments - 32K Bytes of In-System Self-programmable Flash program memory - 1K Bytes EEPROM - 2K Bytes Internal SRAM - Write/Erase cyles: 10,000 Flash/100,000 EEPROM - Data retention: 20 years at 85C/100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - Programming Lock for Software Security JTAG (IEEE std. 1149.1 compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Four PWM Channels - 8-channel, 10-bit ADC - Programmable Serial USART - Master/Slave SPI Serial Interface - Universal Serial Interface with Start Condition Detector - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Interrupt and Wake-up on Pin Change Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated Oscillator - External and Internal Interrupt Sources - Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages - 54/69 Programmable I/O Lines - 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP Speed Grade: - ATmega325PV/ATmega3250PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V - ATmega325P/3250P: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Temperature range: - -40C to 85C Industrial Ultra-Low Power Consumption - Active Mode: 420 A at 1 MHz, 1.8V - Power-down Mode: 40 nA at 1.8V - Power-save Mode: 750 nA at 1.8V * * * 8-bit Microcontroller with 32K Bytes In-System Programmable Flash ATmega325P/V ATmega3250P/V * Preliminary * * * * 8023FS-AVR-07/09 1. Pin Configurations Figure 1-1. Pinout ATmega3250P TQFP PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PH7 (PCINT23) PH6 (PCINT22) PH5 (PCINT21) PH4 (PCINT20) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) AGND AVCC AREF GND DNC DNC DNC DNC DNC VCC PA0 PA1 77 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 DNC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 VCC GND DNC (PCINT24) PJ0 (PCINT25) PJ1 DNC DNC DNC DNC (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 INDEX CORNER 76 75 74 73 72 71 70 69 68 67 66 65 64 PA2 PA3 PA4 PA5 PA6 PA7 PG2 PC7 PC6 DNC PH3 (PCINT19) PH2 (PCINT18) PH1 (PCINT17) PH0 (PCINT16) DNC DNC DNC DNC PC5 PC4 PC3 PC2 PC1 PC0 PG1 PG0 ATmega3250 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 PD6 (OC2A/PCINT15) PB7 (PCINT26) PJ2 (PCINT27) PJ3 (PCINT28) PJ4 (PCINT29) PJ5 (TOSC2) XTAL2 (TOSC1) XTAL1 (PCINT30) PJ6 (ICP1) PD0 (INT0) PD1 GND PD2 PD3 PD4 PD5 VCC DNC DNC DNC (T1) PG3 (T0) PG4 2 ATmega325P/3250P 8023FS-AVR-07/09 RESET/PG5 DNC PD7 50 ATmega325P/3250P Figure 1-2. Pinout ATmega325P PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) AVCC AREF GND GND VCC PA0 PA1 50 61 60 59 58 57 56 55 54 53 52 51 64 63 62 49 PA2 DNC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 1 2 INDEX CORNER 3 4 5 6 7 8 9 10 11 12 13 14 15 16 22 23 24 25 26 27 28 (OC2A/PCINT15) PB7 17 (T1) PG3 18 (T0) PG4 19 RESET/PG5 20 VCC 21 29 PD5 30 PD6 31 PD7 32 48 PA3 47 PA4 46 PA5 45 PA6 44 PA7 43 PG2 42 PC7 ATmega325 41 PC6 40 PC5 39 PC4 38 PC3 37 PC2 36 PC1 35 PC0 34 PG1 33 PG0 PD3 GND (TOSC2) XTAL2 (TOSC1) XTAL1 (ICP1) PD0 (INT0) PD1 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. Overview The ATmega325P/3250P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega325P/3250P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. PD2 PD4 3 8023FS-AVR-07/09 2.1 Block Diagram Block Diagram Figure 2-1. GND VCC PF0 - PF7 PA0 - PA7 PC0 - PC7 PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND AREF ADC CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER DATA DIR. REG. PORTH TIMING AND CONTROL PORTH DRIVERS ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER PH0 - PH7 DATA REGISTER PORTH BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS PROGRAMMING LOGIC INSTRUCTION DECODER INTERRUPT UNIT XTAL1 XTAL2 DATA DIR. REG. PORTJ CONTROL LINES ALU EEPROM PORTJ DRIVERS AVR CPU STATUS REGISTER PJ0 - PJ6 DATA REGISTER PORTJ USART UNIVERSAL SERIAL INTERFACE SPI ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD DATA REG. PORTG DATA DIR. REG. PORTG + - PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE0 - PE7 PB0 - PB7 PD0 - PD7 PG0 - PG4 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 4 ATmega325P/3250P 8023FS-AVR-07/09 RESET ATmega325P/3250P The ATmega325P/3250P provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Powersave mode, the asynchronous timer, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega325P/3250P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega325P/3250P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison between ATmega325P and ATmega3250P The ATmega325P and ATmega3250P differs only in memory sizes, pin count and pinout. Table 2-1 on page 5 summarizes the different configurations for the four devices. Table 2-1. Device ATmega325P ATmega3250P Configuration Summary Flash 32K bytes 32K bytes EEPROM 1K bytes 1K bytes RAM 2K bytes 2K bytes General Purpose I/O Pins 54 69 5 8023FS-AVR-07/09 2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2.3.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega325P/3250P as listed on page 71. 2.3.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega325P/3250P as listed on page 74. 2.3.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up 6 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega325P/3250P as listed on page 75. 2.3.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.3.9 Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega325P/3250P as listed on page 75. 2.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3250P as listed on page 75. 2.3.11 Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3250P as listed on page 75. 7 8023FS-AVR-07/09 2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in "System and Reset Characterizations" on page 308. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. 8 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 9 8023FS-AVR-07/09 Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 10 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P 28. Register Summary Note: Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) Registers with bold type only available in ATmega3250P. Bit 6 PORTJ6 DDJ6 PINJ6 PORTH6 DDH6 PINH6 - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTJ DDRJ PINJ PORTH DDRH PINH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR0 UBRR0H Bit 7 PORTH7 DDH7 PINH7 - Bit 5 PORTJ5 DDJ5 PINJ5 PORTH5 DDH5 PINH5 - Bit 4 PORTJ4 DDJ4 PINJ4 PORTH4 DDH4 PINH4 - Bit 3 PORTJ3 DDJ3 PINJ3 PORTH3 DDH3 PINH3 - Bit 2 PORTJ2 DDJ2 PINJ2 PORTH2 DDH2 PINH2 - Bit 1 PORTJ1 DDJ1 PINJ1 PORTH1 DDH1 PINH1 - Bit 0 PORTJ0 DDJ0 PINJ0 PORTH0 DDH0 PINH0 - Page 88 88 88 87 88 88 USART0 Data Register USART0 Baud Rate Register High 182 186 342 8023FS-AVR-07/09 Address (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) Name UBRR0L Reserved UCSR0C UCSR0B UCSR0A Reserved Reserved Reserved Reserved Reserved USIDR USISR USICR Reserved ASSR Reserved Reserved OCR2A TCNT2 Reserved TCCR2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L Bit 7 RXCIE0 RXC0 USISIF USISIE - Bit 6 UMSEL0 TXCIE0 TXC0 USIOIF USIOIE - Bit 5 UPM01 UDRIE0 UDRE0 USIPF USIWM1 - Bit 4 UPM00 RXEN0 FE0 USIDC USIWM0 EXCLK - Bit 3 USBS0 TXEN0 DOR0 USICNT3 USICS1 AS2 - Bit 2 UCSZ01 UCSZ02 UPE0 USICNT2 USICS0 TCN2UB - Bit 1 UCSZ00 RXB80 U2X0 USICNT1 USICLK OCR2UB - Bit 0 UCPOL0 TXB80 MPCM0 - Page 186 184 183 182 USART0 Baud Rate Register Low USI Data Register USICNT0 USITC TCR2UB - 199 199 200 151 Timer/Counter 2 Output Compare Register A Timer/Counter2 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 - 151 151 149 Timer/Counter1 Output Compare Register B High Timer/Counter1 Output Compare Register B Low Timer/Counter1 Output Compare Register A High Timer/Counter1 Output Compare Register A Low Timer/Counter1 Input Capture Register High Timer/Counter1 Input Capture Register Low 132 132 132 132 133 133 343 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P Address (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) Name TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved PCMSK3 Reserved Reserved TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 Reserved EICRA Reserved Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved Reserved OCR0A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 132 132 Timer/Counter1 High Timer/Counter1 Low FOC1A ICNC1 COM1A1 ADC7D REFS1 ADEN FOC1B ICES1 COM1A0 ADC6D REFS0 ACME ADSC COM1B1 ADC5D ADLAR ADATE WGM13 COM1B0 ADC4D MUX4 ADIF WGM12 ADC3D MUX3 ADIE CS12 ADC2D MUX2 ADTS2 ADPS2 CS11 WGM11 AIN1D ADC1D MUX1 ADTS1 ADPS1 CS10 WGM10 AIN0D ADC0D MUX0 ADTS0 ADPS0 131 130 128 205 222 218 204/222 220 221 221 ADC Data Register High ADC Data Register Low PCINT23 PCINT15 PCINT7 CLKPCE I PCINT30 PCINT22 PCINT14 PCINT6 T PCINT29 ICIE1 PCINT21 PCINT13 PCINT5 H PCINT28 PCINT20 PCINT12 PCINT4 WDCE S PCINT27 PCINT19 PCINT11 PCINT3 PRTIM1 CLKPS3 WDE V PCINT26 OCIE1B PCINT18 PCINT10 PCINT2 PRSPI CLKPS2 WDP2 N PCINT25 OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 ISC01 PSUSART0 CLKPS1 WDP1 Z PCINT24 TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 ISC00 - 62 152 133 104 62 62 62 59 Oscillator Calibration Register [CAL7..0] PRADC CLKPS0 WDP0 C 36 44 36 51 13 15 15 Stack Pointer High Stack Pointer Low SPMIE JTD IDRD/OCDR7 ACD SPIF SPIE RWWSB BODS OCDR6 ACBG WCOL SPE BODSE OCDR5 ACO DORD RWWSRE PUD JTRF OCDR4 ACI MSTR BLBSET WDRF SM2 OCDR3 ACIE CPOL PGWRT BORF SM1 OCDR2 ACIC CPHA PGERS IVSEL EXTRF SM0 OCDR1 ACIS1 SPR1 SPMEN IVCE PORF SE OCDR0 ACIS0 - 269 56/85/255 50 43 228 204 162 SPI Data Register SPI2X SPR0 162 160 27 27 General Purpose I/O Register General Purpose I/O Register - Timer/Counter0 Output Compare A 104 344 8023FS-AVR-07/09 Address 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name TCNT0 Reserved TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Reserved Reserved Reserved Reserved TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 FOC0A TSM - Bit 6 WGM00 - Bit 5 COM0A1 - Bit 4 COM0A0 - Bit 3 WGM01 - Bit 2 CS02 - Bit 1 CS01 PSR2 Bit 0 CS00 PSR10 Page 104 102 105/153 23 23 23 Timer/Counter0 EEPROM Address Register High EEPROM Address Register Low EEPROM Data Register PCIE3 PCIF3 PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 PCIE2 PCIF2 PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 PCIE1 PCIF1 ICF1 PING5 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 PCIE0 PCIF0 PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 EERIE PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 EEMWE OCF1B PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 EEWE OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 EERE INT0 INTF0 TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 General Purpose I/O Register 24 28 60 61 153 133 105 87 87 87 87 87 87 86 86 87 86 86 86 86 86 86 85 85 85 85 85 85 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega325P/3250P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 345 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P 29. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 R1:R0 (Rd x Rr) << BRANCH INSTRUCTIONS 346 8023FS-AVR-07/09 Mnemonics BRVC BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH k k k Operands Description Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr Flags None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1/2 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 BIT AND BIT-TEST INSTRUCTIONS P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT Rd, P P, Rr Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port 347 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P Mnemonics PUSH POP NOP SLEEP WDR BREAK Operands Rr Rd Push Register on Stack Description STACK Rr Rd STACK Pop Register from Stack No Operation Sleep Watchdog Reset Break Operation Flags None None None #Clocks 2 2 1 1 1 N/A MCU CONTROL INSTRUCTIONS (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None 348 8023FS-AVR-07/09 30. Ordering Information 30.1 ATmega325P Power Supply 1.8 - 5.5V 2.7 - 5.5V Ordering Code(2) ATmega325PV-10AU ATmega325PV-10MU ATmega325P-20AU ATmega325P-20MU Package Type(1) 64A 64M1 64A 64M1 Operational Range Industrial (-40C to 85C) Industrial (-40C to 85C) 10 20 Notes: Speed (MHz)(3) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 26-1 on page 306 and Figure 26-2 on page 306. Package Type 64A 64M1 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 349 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P 30.2 ATmega3250P Power Supply 1.8 - 5.5V 2.7 - 5.5V Ordering Code(2) ATmega3250PV-10AU ATmega3250P-20AU Package Type(1) 100A 100A Operational Range Industrial (-40C to 85C) Industrial (-40C to 85C) 10 20 Notes: Speed (MHz)(3) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 26-1 on page 306 and Figure 26-2 on page 306. Package Type 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 350 8023FS-AVR-07/09 31. Packaging Information 31.1 64A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0~7 A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 64A REV. B R 351 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P 31.2 64M1 D Marked Pin# 1 ID E C TOP VIEW SEATING PLANE A1 A K L D2 Pin #1 Corner 0.08 C SIDE VIEW 1 2 3 Option A Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Option B Pin #1 Chamfer (C 0.30) E2 MIN 0.80 - 0.18 8.90 5.20 8.90 5.20 NOM 0.90 0.02 0.25 9.00 5.40 9.00 5.40 0.50 BSC MAX 1.00 0.05 0.30 9.10 5.60 9.10 5.60 NOTE A A1 b D K b e Option C D2 Pin #1 Notch (0.20 R) E E2 e L BOTTOM VIEW 0.35 1.25 0.40 1.40 0.45 1.55 Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. K 5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. G R 352 8023FS-AVR-07/09 31.3 100A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0~7 A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.17 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.50 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 100A REV. C R 353 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P 32. Errata 32.1 ATmega325P rev. A * Interrupts may be lost when writing the timer registers in the asynchronous timer. * Using BOD disable will make the chip reset. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 2. Using BOD disable will make the chip reset. If the part enters sleep with the BOD turned off with the BOD disable option enabled, a BOD reset will be generated at wakeup and the chip will reset. Problem Fix/Workaround Do not use BOD disable 32.2 ATmega325P rev. B * Interrupts may be lost when writing the timer registers in the asynchronous timer. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 32.3 ATmega325P rev. C * Interrupts may be lost when writing the timer registers in the asynchronous timer. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workoround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 354 8023FS-AVR-07/09 32.4 ATmega3250P rev. A * Interrupts may be lost when writing the timer registers in the asynchronous timer. * Using BOD disable will make the chip reset. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 2. Using BOD disable will make the chip reset. If the part enters sleep with the BOD turned off with the BOD disable option enabled, a BOD reset will be generated at wakeup and the chip will reset. Problem Fix/Workaround Do not use BOD disable 32.5 ATmega3250P rev. B * Interrupts may be lost when writing the timer registers in the asynchronous timer. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 32.6 ATmega3250P rev. C * Interrupts may be lost when writing the timer registers in the asynchronous timer. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 355 ATmega325P/3250P 8023FS-AVR-07/09 ATmega325P/3250P 33. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 33.1 Rev.8023F- 07/09 1. 2. Updated "Errata" on page 354. Updated the last page with Atmel's new addresses. 33.2 Rev.8023E- 06/08 1. 2. 3. 4. 5. 6. 7. Updated description of "Stack Pointer" on page 15. Updated description of "Low-frequency Crystal Oscillator" on page 32. Added notes to the overview section of "External Interrupts" on page 58. Updated address of "PORTA - Port A Data Register" on page 85. Bullet five updated in "Asynchronous Operation of Timer/Counter2" on page 147. Updated "System and Reset Characterizations" on page 308. Added Errata for "ATmega325P rev. C" on page 354 and "ATmega3250P rev. C" on page 355. 33.3 Rev.8023D - 08/07 1. 2. Added "Data Retention" on page 10. Updated Device and JTAG ID in "Signature Bytes" on page 274. 33.4 Rev.8023C - 08/07 1. Updated "Errata" on page 354. 33.5 Rev.8023B - 08/07 1. 2. 3. 4. Updated "Features" on page 1. Updated DEVICE and JTAG ID in Table 25-6 on page 274 Updated "System and Reset Characterizations" on page 308. Updated "Typical Characteristics" on page 314 33.6 Rev.8023A - 12/06 1. Initial version. 356 8023FS-AVR-07/09 |
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