View NLAST4053DTR2G_4881789.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NLAST4053 Analog Multiplexer/ Demultiplexer
TTL Compatible, Triple 2:1 Analog Switch-Multiplexer Improved Process, Sub-Micron Silicon Gate CMOS
The NLAST4053 is an improved version of the MC14053 and MC74HC4053 fabricated in sub-micron Silicon Gate CMOS technology for lower RDS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to 3 V to pass a 6 VPP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie VEE, pin 7 to ground. For dual supply operation, VEE is tied to a negative voltage, not to exceed maximum ratings. Translation is provided in the device, the Address and Inhibit pins are standard TTL level compatible. For CMOS compatibility see NLAS4053. Pin for pin compatible with all industry standard versions of 4053.'
http://onsemi.com MARKING DIAGRAM
16 TSSOP-16 DT SUFFIX CASE 948F 1 A L Y W = = = = Assembly Location Wafer Lot Year Work Week AST 4053 ALYW
* Improved RDS(on) Specifications * Pin for Pin Replacement for MAX4053 and MAX4053A *
- One Half the Resistance Operating at 5.0 Volts Single or Dual Supply Operation - Single 3-5 Volt Operation, or Dual 3 Volt Operation - With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic, - No Translators Needed - Address and Inhibit Pins are Over-Voltage Tolerant and May Be - Driven Up +6 V Regardless of VCC Address and Inhibit Pins are Standard TTL Compatible - Greatly Improved Noise Margin Over MAX4053 and MAX4053A - True TTL Compatibility VIL = 0.8 V, VIH = 2.0 V Improved Linearity Over Standard HC4053 Devices Packages
ORDERING INFORMATION
Device NLAST4053DTR2G Package TSSOP-16 (Pb-Free) Shipping 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
*
* * Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin * This is a Pb-Free Device
(c) Semiconductor Components Industries, LLC, 2008
1
February, 2008 - Rev. 1
Publication Order Number: NLAST4053/D
NLAST4053
NOB VCC 16 COMB COMC 15 14 NOC 13 NCC 12 AddC AddB 11 10 AddA 9 NCB NOA COMA NCA COMB COMC NOC NCC
1 NOB
2 NCB
3 NOA
4
5
6
7 VEE
8 GND Enable C B A
COMA NCA Inhibit
Figure 1. Pin Connection (Top View) Figure 2. Logic Diagram
TRUTH TABLE
Inhibit C 1 0 X don't care 0 Address B X don't care 0 A X don't care 0 All switches open COMA-NCA, COMB-NCB, COMC-NCC COMA-NOA, COMB-NCB, COMC-NCC COMA-NCA, COMB-NOB, COMC-NCC COMA-NOA, COMB-NOB, COMC-NCC COMA-NCA, COMB-NCB, COMC-NOC COMA-NOA, COMB-NCB, COMC-NOC COMA-NCA, COMB-NOB, COMC-NOC COMA-NOA, COMB-NOB, COMC-NOC ON SWITCHES*
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
*NO, NC, and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well in either direction.
http://onsemi.com
2
NLAST4053
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I I I I I I I I I I I I I I I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I I I I I I I I I I I I I I I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol Parameter Value Unit V V V V VEE Negative DC Supply Voltage (Referenced to GND) -7.0 to )0.5 -0.5 to )7.0 -0.5 to )7.0 VCC VIS Positive DC Supply Voltage (Note 1) Analog Input Voltage Digital Input Voltage (Referenced to GND) (Referenced to VEE) VEE -0.5 to VCC )0.5 -0.5 to 7.0 $50 VIN I (Referenced to GND) DC Current, Into or Out of Any Pin Storage Temperature Range mA C C C TSTG TL TJ -65 to )150 260 )150 143 164 164 500 450 450 Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance qJA SOIC TSSOP QSOP SOIC TSSOP QSOP C/W PD Power Dissipation in Still Air, mW MSL FR Moisture Sensitivity Level 1 Flammability Rating Oxygen Index: 30% - 35% UL 94 V-0 @ 0.125 in u2000 u200 u1000 $300 VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) V ILATCH-UP Latch-Up Performance Above VCC and Below GND at 125C (Note 5) mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The absolute value of VCC $|VEE| 7.0. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VEE Negative DC Supply Voltage Positive DC Supply Voltage Analog Input Voltage Digital Input Voltage Parameter (Referenced to GND) Min -5.5 2.5 2.5 Max GND 5.5 6.6 Unit V V V V
III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I
VCC VIS TA (Referenced to GND) (Referenced to VEE) VEE 0 -55 0 0 VCC 5.5 125 100 20 VIN (Note 6) (Referenced to GND) Operating Temperature Range, All Package Types C tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.0 V $ 0.3 V VCC = 5.0 V $ 0.5 V ns/V 6. Unused digital inputs may not be left open. All digital inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
http://onsemi.com
3
NLAST4053
DC CHARACTERISTICS - Digital Section (Voltages Referenced to GND)
VCC V 3.0 4.5 5.5 3.0 4.5 5.5 VIN = 6.0 or GND Address and Inhibit, and VIS = VCC or GND 0 V to 6.0 V 6.0 Guaranteed Limit -55 to 25C 1.6 2.0 2.0 0.5 0.8 0.8 $0.1 4.0 v85C 1.6 2.0 2.0 0.5 0.8 0.8 $1.0 40 v125C 1.6 2.0 2.0 0.5 0.8 0.8 $1.0 80 Unit V
Symbol VIH
Parameter Minimum High-Level Input Voltage, Address and Inhibit Inputs Maximum Low-Level Input Voltage, Address and Inhibit Inputs Maximum Input Leakage Current, Address and Inhibit Inputs Maximum Quiescent Supply Current (per Package)
Condition
VIL
V
IIN ICC
mA mA
DC ELECTRICAL CHARACTERISTICS - Analog Section
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIII II I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I
Symbol Parameter Test Conditions VCC V 3.0 4.5 3.0 3.0 4.5 3.0 VEE V Guaranteed Limit -55 to 25CIII v125C v85C 86 37 26 108 46 33 20 2.0 15 120 55 37 20 2.0 15 Unit W RON Maximum "ON" Resistance VIN = VIL or VIH, VIS = VEE to VCC |IS| = 10 mA (Figures 4 thru 9) VIN = VIL or VIH, |IS| = 10 mA, 0 0 -3.0 0 0 -3.0 DRON Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package VIS = 2.0 V VIS = 3.0 V VIS = 2.0 V 15 2.0 10 W Rflat(ON) COM-NO On-Resistance Flatness Maximum Off-Channel Leakage Current Vcom = 1, 2, 3.5 V Vcom = -2, 0, 2 V 4.5 3.0 0 -3.0 0 -3.0 24 2.0 24 2.0 35 3.0 W INC(OFF) INO(OFF) Switch Off VIN = VIL or VIH VIO = VCC -1.0 V or VEE +1.0 V (Figure 17) 6.0 3.0 0.1 0.1 5.0 5.0 100 100 nA ICOM(ON) Maximum On-Channel Leakage Current, Channelto-Channel Switch On VIO = VCC -1.0 V or VEE +1.0 V (Figure 17) 6.0 3.0 0 -3.0 0.1 0.1 5.0 5.0 100 100 nA
http://onsemi.com
4
NLAST4053
AC CHARACTERISTICS (Input tr = tf = 3 ns)
II I II I IIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I
Guaranteed Limit Symbol Parameter Test Conditions VCC V 3.0 4.5 3.0 VEE V -55 to 25C Min 1.0 1.0 1.0 Typ* 6.5 5.0 3.5 v85C v125C Unit ns tBBM Minimum Break-Before-Make Time VIN = VIL or VIH VIS = VCC RL = 300 W, CL = 35 pF (Figure 19) 0.0 0.0 -3.0 *Typical Characteristics are at 25C.
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Guaranteed Limit VCC V 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 VEE V 0 0 0 -3.0 0 0 0 -3.0 0 0 0 -3.0 -55 to 25C Min Typ Max 40 28 23 23 40 28 23 23 40 28 23 23 v85C Min Max 45 30 25 25 45 30 25 25 45 30 25 25 v125C Min Max 50 35 30 28 50 35 30 28 50 35 30 28 Unit ns
Symbol tTRANS
Parameter Transition Time (Address Selection Time) (Figure 18) Turn-on Time (Figures 14, 15, 20, and 21) Enable to NO or NC Turn-off Time (Figures 14, 15, 20, and 21) Enable to NO or NC
tON
ns
tOFF
ns
Typical @ 25C, VCC = 5.0 V CIN CNO or CNC CCOM C(ON) Maximum Input Capacitance,Select Inputs Analog I/O Common I/O Feedthrough 8 10 10 1.0 pF
http://onsemi.com
5
NLAST4053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
VCC V 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 5.0 3.0 VEE V 0.0 0.0 0.0 -3.0 0.0 0.0 0.0 -3.0 0.0 0.0 0.0 -3.0 0.0 -3.0 Typ 25C 145 165 180 180 -93 -93 -93 -93 -2 -2 -2 -2 9.0 12 Unit MHz
Symbol BW
Parameter Maximum On-Channel Bandwidth or Minimum Frequency Response Off-Channel Feedthrough Isolation
Condition VIS = 1/2 (VCC - VEE) Source Amplitude = 0 dBm (Figures 10 and 22) f = 100 kHz; VIS = 1/2 (VCC - VEE) Source = 0 dBm (Figures 12 and 22) VIS = 1/2 (VCC - VEE) Source = 0 dBm (Figures 10 and 22) VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns RIS = 0 W, CL= 1000 pF, Q = CL * DVOUT (Figures 16 and 23) fIS = 1 MHz, RL = 10 KW, CL = 50 pF, VIS = 5.0 VPP sine wave VIS = 6.0 VPP sine wave (Figure 13)
VISO
dB
VONL
Maximum Feedthrough On Loss
dB
Q
Charge Injection
pC
THD
Total Harmonic Distortion THD + Noise
% 6.0 3.0 0.0 -3.0 0.10 0.05
http://onsemi.com
6
NLAST4053
100 10 80 1 0.1 0.01 0.001 0.0001 0.00001 -40 VCC = 3.0 V 20 VCC = 5.0 V -20 0 20 60 80 100 120 0 -4.0 -2.0 0 2.0 VIS (VDC) 4.0 6.0 RON (W) ICC (nA) 60 2.0 V 100
40 $3.3 V 3.0 V 4.5 V 5.5 V
Temperature (C)
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
50
Figure 4. RON versus VCC, Temp = 255C
100 90 80 70 RON (W) 60 50 40 30 20 10 0 -55C 85C 25C RON (W) 125C
125C 40 25C 85C
30
20 -55C 10 0
0.5
1.0 VCom (V)
1.5
2.0
0
0.5
1.0
1.5 VCom (V)
2.0
2.5
3.0
Figure 5. Typical On Resistance VCC = 2.0 V, VEE = 0 V
25 125C 20 85C 20 15 25 85C
Figure 6. Typical On Resistance VCC = 3.0 V, VEE = 0 V
125C
RON (W)
RON (W)
15
25C 10 -55C 5
10
25C
-55C
5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCom (V)
0 0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCom (V)
Figure 7. Typical On Resistance VCC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance VCC = 5.5 V, VEE = 0 V
http://onsemi.com
7
NLAST4053
25 125C 20 85C
RON (W)
15
10
25C
-55C
5
0 -4
-2
0 VCom (V)
2
4
Figure 9. Typical On Resistance VCC = 3.0 V, VEE = -3.0 V
50 40 30 BANDWIDTH (dB) 20 10 0 -10 -20 -30 -40 -50 0.1 1.0 10 100 FREQUENCY (mHz) BANDWIDTH (ON-RESPONSE) PHASE SHIFT (Deg)
90 72 54 36 18 0 -18 -36 -54 -72 -90 0.1 1.0 10 100 FREQUENCY (mHz) PHASE SHIFT
Figure 10. Bandwidth
Figure 11. Phase Shift
0 -10 OFF ISOLATION 10 dB/DIV -20 DISTORTION (%) -30 -40 -50 -60 -70 -80 -90 -100 0.1 1.0 10 100 FREQUENCY (mHz)
0
3.0 5.5 0.1 $3.3 4.5
0.01 10 100 1000 10000 10000 FREQUENCY (mHz)
Figure 12. Off Isolation
Figure 13. Total Harmonic Distortion
http://onsemi.com
8
NLAST4053
30 TA = 25C 25 20 TIME (ns) 15 10 5 0 2.5 tOFF (ns) tON (ns) 25 20 15 10 5 0 -55 tON tOFF 30 VCC = 4.5 V
TIME (ns)
3
3.5
4
4.5
5
-40
25 Temperature (C)
85
125
VCC (VOLTS)
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0 2.5
100
10
2.0 Q (pC) 1.5 1.0 0.5 0 -0.5 0 1
LEAKAGE (nA)
VCC = 5 V
1
ICOM(ON)
0.1
VCC = 3 V
0.01
ICOM(OFF) VCC = 5.0 V INO(OFF)
0.001
2 VCOM (V)
3
4
5
-55
-20
25
70
85
125
TEMPERATURE (C)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
http://onsemi.com
9
NLAST4053
VCC 0.1 mF VEE Output VOUT 300 W 35 pF VCC Output Address Select Pin VEE 10% 90% VCC Input 0V 50% 50%
ttrans
ttrans
Figure 18. Channel Selection Propagation Delay
DUT VCC 0.1 mF 300 W Output VOUT 35 pF Input
VCC GND tBMM 90% Output 90% of VOH
Address Select Pin
GND
Figure 19. tBBM (Time Break-Before-Make)
VCC DUT VCC 0.1 mF Open Output VOUT 300 W 35 pF Output GND tON tOFF Input 0V VOH 90% 90% 50% 50%
Input
Enable
Figure 20. tON/tOFF
http://onsemi.com
10
NLAST4053
VCC DUT Output Open 300 W VOUT 35 pF Input
VCC 50% 0V VCC Output VOL tOFF 10% tON 10% 50%
Input
Enable
Figure 21. tON/tOFF
50 W Reference Input Output 50 W Generator 50 W DUT Transmitted
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. VISO = Off Channel Isolation = 20 Log VONL = On Channel Loss = 20 Log VOUT VIN for VIN at 100 kHz
VOUT for VIN at 100 kHz to 50 MHz VIN
Bandwidth (BW) = the frequency 3 dB below VONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL
http://onsemi.com
11
NLAST4053
DUT Open Output VIN
VCC GND CL Output Off Off DVOUT
VIN
On
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V 16 VCC 16 +3.0 V VCC
VEE GND
7 8
VEE GND -3.0 V
7 8
Figure 24. 5.0 Volts Single Supply VCC = 5.0 V, VEE = 0
Figure 25. Dual Supply VCC = 3.0 V, VEE = -3.0 V
http://onsemi.com
12
NLAST4053
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE B
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -VN F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
SOLDERING FOOTPRINT
7.06 1
16X
0.36
16X
1.26
http://onsemi.com
13
EEE CCC EEE CCC
M
9
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
0.65 PITCH
DIMENSIONS: MILLIMETERS
NLAST4053
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
http://onsemi.com
14
NLAST4053/D

▲Up To Search▲

Price & Availability of NLAST4053DTR2G

	To Download NLAST4053DTR2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .