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19-5294; Rev 0; 8/10
TION KIT EVALUA BLE ILA AVA
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
General Description
The MAX11206/MAX11207 are ultra-low-power (< 300FA active current), high-resolution, serial-output ADCs. These devices provide the highest resolution per unit power in the industry, and are optimized for applications that require very high dynamic range with low power, such as sensors on a 4mA to 20mA industrial control loop. Optional input buffers provide isolation of the signal inputs from the switched capacitor sampling network allowing these converters to be used with high-impedance sources without compromising available dynamic range or linearity. The devices provide a high-accuracy internal oscillator that requires no external components. When used with the specified data rates, the internal digital filter provides more than 100dB rejection of 50Hz or 60Hz line noise. The devices are configurable using the SPITM interface and include four GPIOs that can be used for external mux control. The MAX11206 includes digital programmable gain of 1 to 128. The MAX11206/MAX11207 operate over the -40NC to +85NC temperature range, and are available in a 16-pin QSOP package. S 20-Bit Noise-Free Resolution S S S S 570nVRMS Noise at 10sps, 3.6VFS Input 3ppm INL (typ), 10ppm (max) No Missing Codes Ultra-Low Power Dissipation Operating-Mode Current Drain < 300A (max) Sleep-Mode Current Drain < 0.4A Programmable Gain (1 to 128) (MAX11206) Four SPI-Controlled GPIOs for External Mux Control 2.7V to 3.6V Analog Supply Voltage Range 1.7V to 3.6V Digital and I/O Supply Voltage Range Fully Differential Signal and Reference Inputs High-Impedance Inputs Optional Input Buffers on Both Signal and Reference Inputs > 100dB (min) 50Hz/60Hz Rejection SPI-, QSPITM-, MICROWIRETM-Compatible Serial Interface On-Demand Offset and Gain Self-Calibration and System Calibration User-Programmable Offset and Gain Registers -40C to +85C Operating Temperature Range 2kV ESD Protection Lead(Pb)-Free and RoHS-Compliant QSOP Package
Features
MAX11206/MAX11207
S S S S S S
S S S S S S S
Applications
Sensor Measurement (Temperature and Pressure) Portable Instrumentation Battery Applications Weigh Scales
Ordering Information
PART MAX11206EEE+ MAX11207EEE+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 16 QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
RESOLUTION (BITS) 24 20 18 16 4-WIRE SPI, 16-PIN QSOP, PROGRAMMABLE GAIN MAX11210 MAX11206 MAX11209 MAX11213 4-WIRE SPI, 16-PIN QSOP MAX11200 MAX11207 MAX11211 MAX11203 2-WIRE SERIAL, 10-PIN MAX MAX11201 (with buffers) MAX11202 (without buffers) MAX11208 MAX11212 MAX11205
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND ....................................................-0.3V to +3.9V AVDD to GND.......................................................-0.3V to +3.9V DVDD to GND ......................................................-0.3V to +3.9V Analog Inputs (AINP, AINN, REFP, REFN) to GND ............................................. -0.3V to (VAVDD + 0.3V) Digital Inputs and Digital Outputs to GND ............................................. -0.3V to (VDVDD + 0.3V) ESDHB (AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, CS, SCLK, DIN, RDY/DOUT, GND, GPIO_) ........... Q2kV (Note 1) Continuous Power Dissipation (TA = +70NC) 16-Pin QSOP (derate 8.3mW/NC above +70NC)..........667mW Operating Temperature Range .......................... -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -55NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER STATIC PERFORMANCE Noise-Free Resolution (Notes 2, 3) Noise (Notes 2, 3) Integral Nonlinearity Zero Error Zero Drift Full-Scale Error Full-Scale Error Drift Power-Supply Rejection ANALOG INPUTS/REFERENCE INPUTS DC rejection Common-Mode Rejection Normal-Mode 50Hz Rejection Normal-Mode 60Hz Rejection Common-Mode Voltage Range CMR NMR50 NMR60 50Hz/60Hz rejection at 120sps 50Hz/60Hz rejection at 1sps to 15sps LINEF = 1, for 1sps to 15sps (Notes 6, 7) LINEF = 0, for 1sps to 15sps (Notes 6, 7) AIN buffers disabled 90 90 144 100 100 VGND 144 144 VAVDD dB dB V 123 dB AVDD DC rejection DVDD DC rejection 70 90 After self and system calibration, VREFP - VREFN = 2.5V (Note 5) -20 0.05 80 100 NFR VN INL 120sps 10sps 120sps 10sps At 10sps (Note 4) After self and system calibration, VREFP - VREFN = 2.5V -10 -10 50 +20 19 20 2.1 0.55 +10 +10 Bits FVRMS ppmFSR ppmFSR nV/NC ppmFSR ppmFSR/ NC dB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Buffers disabled Low input voltage Buffers enabled Absolute Input Voltage Buffers disabled High input voltage Buffers enabled DC Input Leakage AIN Dynamic Input Current REF Dynamic Input Current AIN Input Capacitance REF Input Capacitance AIN Voltage Range Input Sampling Rate fS Sleep mode Buffer disabled Buffer enabled Buffer disabled Buffer enabled Buffer disabled Buffer disabled Unipolar Bipolar LINEF = 0 LINEF = 1 Buffers disabled REF Voltage Range Buffers enabled LINEF = 0 LINEF = 1 Input leakage current VIL VIH VHYS 60Hz line frequency External Clock 55Hz line frequency 50Hz line frequency LOGIC OUTPUTS (RDY/DOUT, GPIO1-GPIO4) Output Low Level VOL IOL = 1mA; also tested for VDVDD = 3.6V Output High Level Leakage Current Output Capacitance VOH IOH = 1mA; also tested for VDVDD = 3.6V High-impedance state High-impedance state 0.9 x VDVDD Q500 9 0.7 x VDVDD 200 2.4576 2.25275 2.048 0.4 V V nA pF MHz 0 0.1 246 204.8 Q1 0.3 x VDVDD 0 -VREF 246 204.8 VAVDD VAVDD - 0.1 V MIN TYP VGND 30mV VGND + 100mV VAVDD + 30mV VAVDD 100mV Q1 Q1.4 Q20 Q2.1 Q30 5 7.5 VREF +VREF FA FA/V nA FA/V nA pF pF V kHz MAX UNITS
MAX11206/MAX11207
V
REF Sampling Rate
kHz
LOGIC INPUTS (SCLK, CLK, DIN, GPIO1-GPIO4) Input Current Input Low Voltage Input High Voltage Input Hysteresis FA V V mV
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3
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER POWER REQUIREMENTS Analog Supply Digital Supply Total Operating Current AVDD Sleep Current AVDD Operating Current DVDD Sleep Current DVDD Operating Current SPI TIMING CHARACTERISTICS SCLK Frequency SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Low to 1st SCLK Rise Setup CS High to 17th SCLK Setup CS High After 16th SCLK Falling Edge Hold CS Pulse-Width High DIN to SCLK Setup DIN Hold After SCLK RDY/DOUT Transition Valid After SCLK Fall RDY/DOUT Remains Valid After SCLK Fall RDY/DOUT Valid Before SCLK Rise CS Rise to RDY/DOUT Disable CS Fall to RDY/DOUT Valid fSCLK tCP tCH tCL tCSS0 tCSS1 tCSH1 tCSW tDS tDH tDOT tDOH tDOL tDOD tDOE Output transition time, data changes on falling edge of SCLK Output hold time allows for negative edge data read tDOL = tCL - tDOT CLOAD = 20pF Default value of RDY is 1 for minimum specification; maximum specification for valid 0 on RDY/DOUT Maximum time after RDY asserts to read DATA register; tCNV is the time for one conversion 0 3 40 25 40 60% duty cycle at 5MHz 200 80 80 40 40 3 40 40 0 40 5 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Buffers disabled Buffers enabled VAVDD VDVDD AVDD + DVDD Buffers disabled Buffers enabled 2.7 1.7 235 255 0.15 185 205 0.25 50 2 65 2 235 3.6 3.6 300 V V FA FA FA FA FA SYMBOL CONDITIONS MIN TYP MAX UNITS
DATA Fetch Note Note Note Note 2: 3: 4: 5:
tDF
0
tCNV 60 x tCP
These specifications are not fully tested and are guaranteed by design and/or characterization. VAINP = VAINN. ppmFSR is parts per million of full scale. Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps. Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and lower or continuous data rate of 60sps/50sps. 4 ______________________________________________________________________________________
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
Typical Operating Characteristics
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = 2.5V; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (NO BUFFERS ENABLED)
MAX11203/13 toc01
MAX11206/MAX11207
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (SIGNAL OR REFERENCE BUFFERS ENABLED)
240 220
CURRENT (A)
MAX11203/13 toc02
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (SIGNAL AND REFERENCE BUFFERS ENABLED)
MAX11203/13 toc03
260 240 220
CURRENT (A)
LINEF = 0, LINEF = 1
260
280 260
TA = +85C TA = +25C TA = -45C SIGNAL BUFFERS
TA = +85C
CURRENT (A)
TA = +85C TA = +25C TA = -45C LINEF = 1
240 220 200 180 160
200 180 160 140 120 2.70 2.85 3.00 3.15 3.30 3.45 3.60 AVDD VOLTAGE (V)
200 180 160 140 120 2.70 2.85
TA = +25C
TA = -45C
3.00
3.15
3.30
3.45
3.60
2.70
2.85
3.00
3.15
3.30
3.45
3.60
AVDD VOLTAGE (V)
AVDD VOLTAGE (V)
ANALOG SLEEP CURRENT vs. AVDD VOLTAGE
MAX11203/13 toc04
ACTIVE SUPPLY CURRENT vs. TEMPERATURE (LINEF = 0)
MAX11203/13 toc05
ACTIVE SUPPLY CURRENT vs. TEMPERATURE (LINEF = 1)
MAX11203/13 toc06
1.0 0.8 CURRENT (A) 0.6 0.4
TA = -45C, +25C, +85C
300 250 200
300 250 200 150 100
TOTAL VAVDD = 3.0V
TOTAL VAVDD = 3.0V
CURRENT (A)
150 100
TA = -45C
0.2
VDVDD = 1.8V
50
50 0
CURRENT (A)
VDVDD = 1.8V
TA = +85C
0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD VOLTAGE (V)
0 -45 -25 -5 15 35 55 75 95 TEMPERATURE (C)
-45
-25
-5
15
35
55
75
95
TEMPERATURE (C)
SLEEP CURRENT vs. TEMPERATURE
MAX11203/13 toc07
DIGITAL ACTIVE CURRENT vs. DVDD VOLTAGE
MAX11203/13 toc08
DIGITAL SLEEP CURRENT vs. DVDD VOLTAGE
MAX11203/13 toc09
1.0 0.8 CURRENT (A) 0.6 0.4 0.2
130 120 110
CURRENT (A)
LINEF = 0, LINEF = 1 TA = -45C, +25C, +85C TA = +85C LINEF = 0
3.0 2.5 2.0 1.5 1.0 0.5 0
CURRENT (A)
100 90 80 70 60 50 40
TA = -45C TA = +25C TA = +85C
TOTAL DVDD AVDD
TA = -45C
LINEF = 1
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 DVDD VOLTAGE (V)
0 -45 -25 -5 15 35 55 75 95 TEMPERATURE (C)
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 DVDD VOLTAGE (V)
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5
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = 2.5V; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5
INTERNAL OSCILLATOR FREQUENCY vs. AVDD VOLTAGE
3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 2.70 2.85 3.00
MAX11203/13 toc11 MAX11203/13 toc10
INTEGRAL NONLINEARITY vs. INPUT VOLTAGE
8 6 4 INL (ppmFSR) 2 0 -2 -4 -6 -8 -10
VAVDD = 3.0V
VIN(CM) = 1.8V
FREQUENCY (MHz)
FREQUENCY (MHz)
LINEF = 0
LINEF = 0
TA = +85C
TA = -45C
LINEF = 1
LINEF = 1
TA = +25C
-45
-25
-5
15
35
55
75
95
3.15
3.30
3.45
3.60
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5 2.0 2.5
TEMPERATURE (C)
AVDD VOLTAGE (V)
INPUT VOLTAGE (V)
TUE vs. INPUT VOLTAGE
MAX11203/13 toc13
10 8 6 4 INL (ppmFSR) 2 0 -2 -4 -6 -8 -10
PSRR vs. FREQUENCY (DATA RATE 120sps)
-20 -40 PSRR (dB) -60 -80 -100 -120
MAX11203/13 toc14
VIN(CM) = 1.8V TA = -45C TA = +85C
0
TA = +25C
AVDD DVDD
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5 2.0 2.5
-140 1 10 100 1000 10,000 100,000 FREQUENCY (Hz)
INPUT VOLTAGE (V)
PSRR vs. FREQUENCY (DATA RATE 10sps)
MAX11203/13 toc15
CMRR vs. FREQUENCY
-20 -40 CMRR (dB) -60 -80 -100 -120 -140
MAX11203/13 toc16
0 -20 -40 PSRR (dB) -60 -80 -100 -120 -140 1 10 100 1000
0
AVDD
120sps 10sps
DVDD
10,000 100,000
1
10
100
1000
10,000 100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
6
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MAX11203/13 toc12
10
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
Functional Diagram
MAX11206/MAX11207
AVDD DVDD GND
TIMING
CLOCK GENERATOR
CLK
AINP PROGRAMMABLE GAIN* 1-128 DIGITAL LOGIC AND SERIALINTERFACE CONTROLLER
CS
AINN
DIGITAL FILTER (SINC4) 3RD-ORDER DELTA-SIGMA MODULATOR
SCLK
DIN
RDY/DOUT
REFP GPIO1 REFN
MAX11206* MAX11207
GPIO2 GPIO GPIO3 GPIO4
*PROGRAMMABLE GAIN ONLY AVAILABLE ON THE MAX11206.
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7
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
Pin Configuration
TOP VIEW
GPIO1 1 GPIO2 2 GPIO3 3 GND 4 REFP 5 REFN 6 AINN 7 AINP 8
MAX11206 MAX11207
+
16 GPIO4 15 CLK 14 SCLK 13 RDY/DOUT 12 DIN 11 CS 10 DVDD 9 AVDD
QSOP
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME GPIO1 GPIO2 GPIO3 GND REFP REFN AINN AINP AVDD DVDD CS DIN FUNCTION General-Purpose I/O 1. Register controllable using SPI. General-Purpose I/O 2. Register controllable using SPI. General-Purpose I/O 3. Register controllable using SPI. Ground. Ground reference for analog and digital circuitry. Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage between AVDD and GND. Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a voltage between AVDD and GND. Negative Fully Differential Analog Input Positive Fully Differential Analog Input Analog Supply Voltage. Connect a supply voltage between +2.7V and +3.6V with respect to GND. Digital Supply Voltage. Connect a digital supply voltage between +1.7V and +3.6V with respect to GND. Active-Low, Chip-Select Logic Input Serial-Data Input. Data present at DIN is shifted to the device's internal registers at the rising edge of the serial clock at SCLK, when the device is accessed for an internal register write or for a command operation.
13 14 15 16
Data Ready Output/Serial-Data Output. This output serves a dual function. In addition to the serial-data RDY/DOUT output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/ DOUT changes on the falling edge of SCLK. SCLK CLK GPIO4 Serial-Clock Input. Apply an external serial clock to SCLK. External Clock Signal Input. When external clock mode is selected (EXTCLK = 1), provide a 2.4576MHz or 2.048MHz clock signal at CLK. Other frequencies can be used, but the data rate and digital filter notch frequencies scale accordingly. General-Purpose I/O 4. Register controllable using SPI.
8
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
Detailed Description
The MAX11206/MAX11207 are ultra-low-power (< 300FA active), high-resolution, low-speed, serial-output ADCs. These ADCs provide the highest resolution per unit power in the industry, and are optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. Optional input buffers provide isolation of the signal inputs from the switched capacitor sampling network, allowing the devices to be used with very high impedance sources without compromising available dynamic range. The devices provide a high-accuracy internal oscillator, which requires no external components. When used with the specified data rates, the internal digital filter provides more than 144dB rejection of 50Hz or 60Hz line noise. The devices are highly configurable using the SPI interface and include four GPIOs for external mux control. The devices accept two analog inputs (AINP, AINN) in buffered or unbuffered mode. The input buffer isolates the inputs from the capacitive load presented by the modulator, allowing for high source-impedance analog transducers. The value of the SIGBUF bit in the CTRL1 register determines whether the input buffer is enabled or disabled. See Table 12. The modulator input range is programmable for bipolar (-VREF to +VREF) or unipolar (0 to VREF) ranges. The U/B bit in the CTRL1 register configures the MAX11206/ MAX11207 for unipolar or bipolar transfer functions. See Table 12. The devices incorporate a highly stable internal oscillator that provides the system clock. The system clock runs the internal state machine and is trimmed to 2.4576MHz or 2.048MHz. The internal oscillator clock is divided down to run the digital and analog timing. The LINEF bit in the CTRL1 register determines the internal oscillator frequency. See Tables 10 and 12. Set LINEF = 0 to select the 2.4576MHz oscillator and LINEF = 1 to select the
MAX11206/MAX11207
Input Voltage Range
System Clock
Analog Inputs
Table 1. Continuous Conversion with SCYCLE Bit = 0
RATE[2:0] 100 101 110 111 DATA RATE* (sps) LINEF = 0 60 120 240 480 LINEF = 1 50 100 200 400 BIPOLAR NFR (BITS) 20.0 20.0 19.5 19.0 BIPOLAR ENOB (BITS) 20.0 20.0 20.0 20.0 UNIPOLAR NFR (BITS) 19.5 19.0 18.5 18.0 UNIPOLAR ENOB (BITS) 20.0 20.0 20.0 20.0 OUTPUT NOISE (VRMS) 0.74 1.03 1.45 2.21
*LINEF = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the clock frequency to 2.048MHz and the input sampling frequency to 204.8kHz.
Table 2. Single-Cycle Conversion with SCYCLE Bit = 1
RATE[2:0] 000 001 010 011 100 101 110 111 SINGLE-CYCLE DATA RATE* (sps) LINEF = 0 1 2.5 5 10 15 30 60 120 LINEF = 1 0.833 2.08 4.17 8.33 12.5 25 50 100 BIPOLAR NFR (BITS) 20.0 20.0 20.0 20.0 20.0 20.0 19.5 19.0 BIPOLAR ENOB (BITS) 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 UNIPOLAR NFR (BITS) 20.0 20.0 20.0 19.9 19.5 19.0 18.5 18.0 UNIPOLAR ENOB (BITS) 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 OUTPUT NOISE (VRMS) 0.21 0.27 0.39 0.55 0.74 1.03 1.45 2.21
*LINEF = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the clock frequency to 2.048MHz and the input sampling frequency to 204.8kHz. _______________________________________________________________________________________ 9
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
2.048MHz oscillator. The 2.4576MHz oscillator provides maximum 60Hz rejection, and the 2.048MHz oscillator provides maximum 50Hz rejection. See Figures 1 and 2. For optimal simultaneous 50Hz and 60Hz rejection, apply a 2.25275MHz external clock at CLK. The devices provide differential inputs REFP and REFN for an external reference voltage. Connect the external reference directly across the REFP and REFN to obtain the differential reference voltage. The common-mode voltage range for VREFP and VREFN is between 0 and VAVDD. The devices accept reference inputs in buffered or unbuffered mode. The value of the REFBUF bit in the CTRL1 register determines whether the reference buffer is enabled or disabled. See Table 12. The devices include reference and signal input buffers capable of reducing the average input current from 2.1FA/V on the reference inputs and from 1.4FA/V on the analog inputs to a constant 30nA current on the reference inputs and 20nA current on the analog inputs. The reference and signal input buffers can be selected individually by programming the CTRL1 register bits REFBUF and SIGBUF. When enabled, the reference and input signal buffers require an additional 20FA from the AVDD supply pin. The devices utilize power-on reset (POR) supply-monitoring circuitry on both the digital supply (DVDD) and the analog supply (AVDD). The POR circuitry ensures proper device default conditions after either a digital or analog power sequencing event. The digital POR trigger threshold is approximately 1.2V and has 100mV of hysteresis. The analog POR trigger threshold is approximately 1.25V and has 100mV of hysteresis. Both POR circuits have lowpass filters that prevent high-frequency supply glitches from triggering the POR. The devices provide two sets of calibration registers which offer the user several options for calibrating their system. The calibration register value defaults are all zero, which require a user to either perform a calibration or program the register through the SPI interface to use them. The on-chip calibration registers are enabled or disabled by programming the NOSYSG, NOSYSO, NOSCG, and NOSCO bits in the CTRL3 register. The default values for these calibration control bits are 1, which disables the use of the internal calibration registers. The devices power up with the internal calibration registers disabled, and therefore a full-scale input produces a result of 60% of the full-scale digital range. To use the full-scale digital range a calibration must be performed. The first level of calibration is the self-calibration where the part performs the required connections to zero and full-scale internally. This level of calibration is typically sufficient for 1FV of offset accuracy and 2ppm of fullscale accuracy. The self-calibration routine does not include the source resistance effects from the signal source driving the input pins, which can change the offset and gain of the system. A second level of calibration is available where the user can calibrate a system zero scale and system full scale by presenting a zero-scale signal or a full-scale signal to the input pins and initiating a system zero scale or system gain calibration command. A third level of calibration allows for the user to write to the internal calibration registers through the SPI interface to achieve any digital offset or scaling the user requires with the following restrictions. The range of digital offset correction is QVREF/4. The range of digital gain correction is from 0.5 to 1.5. The resolution of offset correction is 0.5 LSB. The calibration operations are controlled with the CAL1 and CAL0 bits in the command byte. The user requests a self-calibration by setting the CAL1 bit to 0 and CAL0 bit to 1. A self-calibration requires 200ms to complete, and both the SCOC and SCGC registers contain the values that correct the chip output for zero scale and full scale. The user requests a system zero-scale calibration by setting the CAL1 bit to 1 and the CAL0 bit to 0 and presents a system zero-level signal to the input pins. The SOC register contains the values that correct the chip zero scale. The system zero calibration requires 100ms to complete, and the SOC register contains values that correct the chip zero scale. The user requests a system full-scale calibration by setting the CAL1 bit to 1 and the CAL0 bit to 1 and presents a system full-scale signal level to the input pins. The system full-scale calibration requires 100ms to complete, and the SGC register contains values that correct for the chip full-scale value. See Tables 3a and 3b for an example of a self-calibration sequence and a system calibration sequence.
Reference
Buffers
Power-On Reset (POR)
Calibration
10
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
Table 3a. Example of Self-Calibration
REGISTER NOSYSG NOSYSO STEP DESCRIPTION SCOC 0x000000 0x000000 0x00007E SCGC 0x000000 0x000000 0xBFD345 SOC 0x000000 0x000000 0x000000 SGC 0x000000 0x000000 0x000000 BIT NOSCG NOSCO 1 0 0
MAX11206/MAX11207
1 2 3
Initial power-up Enable self-calibration registers Self-calibration, DIN = 10010000
1 1 1
1 1 1
1 0 0
Table 3b. Example of System Calibration
REGISTER NOSYSG NOSYSO STEP DESCRIPTION SCOC 0x000000 0x000000 0x00007E 0x00007E 0x00007E 0x00007E 0x00007E SCGC 0x000000 0x000000 0xBFD345 0xBFD345 SOC 0x000000 0x000000 0x000000 0x000000 SGC 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 BIT NOSCG 1 0 0 0 0 0 0 NOSCO 1 0 0 0 0 0 0
1 2 3 4 5 6 7
Initial power-up Enable self-calibration registers Self-calibration, DIN = 10010000 Enable system offset register System-calibration offset, DIN = 1010000 Enable system gain register System-calibration gain, DIN = 1011000
1 1 1 1 1 0 0
1 1 1 0 0 0 0
0xBFD345 0xFFEE1D 0xBFD345 0xFFEE1D
0xBFD345 0xFFEE1D 0x81CB5B
The devices offer software-selectable internal oscillator frequencies as well as software-selectable output data rates. The LINEF bit in the CTRL1 register (Table 12) determines the internal oscillator frequency. The RATE bits in the command byte (Table 8) determine the ADC's output data rate. The devices also offer the option of running in zero latency single-cycle conversion mode (Table 2) or continuous conversion mode (Table 1). Set SCYCLE = 0 in the CTRL1 register (Table 12) to run in continuous conversion mode and SCYCLE = 1 for singlecycle conversion mode. Single-cycle conversion mode gives an output result with no data latency. The devices output data up to 100sps (2.048MHz internal oscillator) or 120sps (2.4576MHz internal oscillator) with no data latency. In continuous conversion mode, the output data rate is four times the single-cycle conversion mode, for sample rates up to 400sps or 480sps. In continuous conversion mode, the output data requires three additional 24-bit cycles to settle from an input step. The devices include a SINC4 digital filter that produces spectral nulls at the multiples of the data rate. For all data rates less than 30sps, a spectral null occurs at the
Noise vs. Data Rate
line frequency of 60Hz and is guaranteed to attenuate 60Hz normal-mode components by more than 100dB. Simultaneous 50Hz and 60Hz attenuation can be accomplished by using an external clock with a frequency of 2.25275MHz. This guarantees a minimum of 80dB rejection at 50Hz and 85dB rejection at 60Hz. The SINC4 filter has a -3dB frequency equal to 24% of the data rate. See Figures 1 and 2. The devices provide four GPIO ports. When set as outputs, these digital I/Os can be used to drive the digital inputs to a multiplexer or multichannel switch. Figure 3 details an example where four single-ended signals are multiplexed in a break-before-make switching sequence, using the MAX313, a quad SPST analog switch. The devices' GPIO ports are configurable through the CTRL2 register. See Table 13. To select AIN1, write the command to CTRL2 according to Table 4a. This selects all GPIOs as outputs, as well as setting all logic signals to 0 except the selected channel AIN1. To select channel AIN3 next, it is a good idea to set all switches to a high-impedance state first (see Table 4b). Then select channel AIN3 by driving IN3 high (see Table 4c).
11
GPIOs
Digital Filter
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
NORMAL MODE REJECTION DATA RATE 10.0sps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (Hz)
NORMAL MODE REJECTION DATA RATE 120.0sps
Figure 1. Normal-Mode Frequency Response (2.4576MHz Oscillator, LINEF = 0)
GAIN (dB)
GAIN (dB)
NORMAL MODE REJECTION DATA RATE 8.333sps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0
NORMAL MODE REJECTION DATA RATE 100.000sps
GAIN (dB)
GAIN (dB)
200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (Hz)
Figure 2. Normal-Mode Frequency Response (2.048MHz Oscillator, LINEF = 1)
Table 4a. Data Command to Select Channel AIN1 in Figure 3
BIT BIT NAME VALUE B7 DIR4 1 B6 DIR3 1 B5 DIR2 1 B4 DIR1 1 B3 DIO4 0 B2 DIO3 0 B1 DIO2 0 B0 DIO1 1
Table 4b. Set All Channels High Impedance in Figure 3
BIT BIT NAME VALUE B7 DIR4 1 B6 DIR3 1 B5 DIR2 1 B4 DIR1 1 B3 DIO4 0 B2 DIO3 0 B1 DIO2 0 B0 DIO1 0
12
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
MAX313 LOGIC 0 1 SWITCH OFF ON
It is not always necessary to transition to a high-impedance state between channel selections, but depends on the source analog signals as well as the control structure of the multiplexed switches. The MAX11206 offers programmable gain settings that can be digitally set to 1, 2, 4, 8, 16, 32, 64, or 128. The DGAIN_ bits in the CTRL3 register (see Table 14) configure the digital gain setting and control the input referred gain. The MAX11206's input range is 0V to VREF/ gain (unipolar) or VREF/gain (bipolar). The MAX11206 always outputs 20 bits of data. But as this is a digital programmable gain, the noise floor remains constant, depending on the output rate setting. At an output rate of 10sps, as shown in Figure 4, the noise floor is such that all gain settings from 1 to 64 provide 20 bits of noise-free resolution. A gain setting of 128 at 10sps means the LSB is below the noise floor. The MAX11206 digital gain is beneficial for low-voltage applications that only require a small portion of the 0V to VREF or VREF ranges.
MAX11206/MAX11207
Digital Programmable Gain (MAX11206)
IN1 IN2 AIN1 AIN2 AIN3 AIN4 IN3 IN4
GPIO1 GPIO2 GPIO3 GPIO4
MAX313
COM1 COM2 COM3 COM4
MAX11206
AINP AINN
Figure 3. MAX11206 GPIOs Drive an External 4-Channel Switch (MAX313)
Table 4c. Data Command to Select Channel AIN3 in Figure 3
BIT BIT NAME VALUE B7 DIR4 1 B6 DIR3 1 B5 DIR2 1 B4 DIR1 1 B3 DIO4 0 B2 DIO3 1 B1 DIO2 0
NOISE FLOOR REMAINS CONSTANT AT 0.55VRMS
B0 DIO1 0
VREF = 3V 20-BIT OUTPUT DATA CYCLE LSB
SUB-LSBs MSB
BITS USED FOR GAIN = 1
BITS USED FOR GAIN = 2
BITS USED FOR GAIN = 16
BITS USED FOR GAIN = 128
Figure 4. MAX11206 Digital Programmable Gain Example (10sps Output Rate)
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13
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
The MAX11206/MAX11207 interface is fully compatible with SPI-, QSPI-, and MICROWIRE-standard serial interfaces. The SPI interface provides access to nine on-chip registers that are 8 or 24 bits wide. Drive CS low to transfer data in and out of the devices. Clock in data at DIN on the rising edge of SCLK. The RDY/DOUT output serves two functions: conversion status and data read. To find the conversion status, assert CS low and read the RDY/DOUT output; the conversion
Serial-Digital Interface
is in progress if the RDY/DOUT output reads logic-high and the conversion is complete if the RDY/DOUT output reads logic-low. Data at RDY/DOUT changes on the falling edge of SCLK and is valid on the rising edge of SCLK. DIN and DOUT are transferred MSB first. Drive CS high to force DOUT high impedance and cause the devices to ignore any signals on SCLK and DIN. Connect CS low for 3-wire operation. Figures 5, 6, and 7 show the SPI timing diagrams.
tCSH0 CS
tDS tCSS0 tDH tCL
tCP tCH
tCSH1
tCSW
tCSS1
SCLK
0
1
8
DIN
X
1 tDOE
0
CAL1
CAL0
IMPD
RATE2
RATE1
RATE0 tDOD HIGH-Z
RDY/DOUT
HIGH-Z
Figure 5. SPI Command Byte
SPI REGISTER ACCESS WRITE tCSH0 tCSS0 CS SCLK DIN HIGH-Z RDY/DOUT 0 X 1 1 tDOE 1 X RS3 RS2 RS1 RS0
tDS tDH
tCP tCL tCH
tCSW tCSH1 tCSS1 8 W/R 9 D7 D6 D5 D4 D3 D2 D1 16 D0 tDOD HIGH-Z
Figure 6. SPI Register Access Write
14
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
tCSS0
CS SCLK DIN HIGH-Z RDY/DOUT X 1 1 tDOE D7 D6 D5 D4 D3 D2 D1 D0 1 X RS3 RS2 RS1 RS0
tDS tDH
tCP
tDOT tDO1
tCL
tDOH
tDOD
tCH
8 9
tCSS1
16
W/R
X
X
X
X
X
X
X
X HIGH-Z
Figure 7. SPI Register Access Read
Command Byte Communication between the user and the device is conducted through SPI using a command byte. The command byte consists of two modes differentiated as command modes and data modes. Command modes and data modes are further differentiated by decoding the remaining bits in the command byte. The mode selected is determined by the MODE bit. If the MODE bit is 0, then the user is requesting either a conversion, calibration, or power-down; see Table 5. If the MODE bit is 1, then the user is selecting a data command and can either read from or write to a register; see Table 6. The Status register (STAT1) is a read-only register and provides general chip operational status to the user. If the user attempts to calibrate the system and overranges the internal signal scaling, then a gain overrange condition is flagged with the SYSOR bit. The last data rate programmed for the ADC is available in the RATE bits. If the input signal has exceeded positive or negative full scale, this condition is flagged with the OR and UR bits. If the modulator is busy converting, then the MSTAT bit is set. If a conversion result is ready for readout, the RDY bit is set; see Table 11. The Control 1 register (CTRL1) is a read/write register, and the bits determine the internal oscillator frequency, unipolar or bipolar input range, selection of an internal or external clock, enabling or disabling the reference and input signal buffers, the output data format (offset binary
or two's complement), and single-cycle or continuous conversion mode. See Table 12. The Control 2 register (CTRL2) is a read/write register, and the bits configure the GPIOs as inputs or outputs and their values. See Table 13. The Control 3 register (CTRL3) is a read/write register, and the bits determine the MAX11206 programmable gain setting and the calibration register settings for both the MAX11206 and MAX11207. See Table 14. The Data register (DATA) is a read-only register. Data is output from RDY/DOUT on the next 24 SCLK cycles once CS is forced low. The data bits transition on the falling edge of SCLK. Data is output MSB first, and is offset binary or two's complement, depending on the setting of the FORMAT bit in the CTRL1 register. See Table 15. The System Offset Calibration register (SOC) is a read/ write register, and the bits contain the digital value that corrects the data for system zero scale. See Table 17. The System Gain Calibration register (SGC) is a read/ write register, and the bits contain the digital value that corrects the data for system full scale. See Table 18. The Self-Cal Offset Calibration register (SCOC) is a read/ write register, and the bits contain the value that corrects the data for chip zero scale. See Table 19. The Self-Cal Gain Calibration register (SCGC) is a read/ write register, and the bits contain the value that corrects the data for chip full scale. See Table 20.
B4 B3 IMPD B2 RATE2 B1 RATE1 B0 RATE0
Table 5. Command Byte (MODE = 0)
BIT BIT NAME B7 START = 1 B6 MODE = 0 B5 CAL1 CAL0
Table 6. Command Byte (MODE = 1)
BIT BIT NAME B7 START = 1 B6 MODE = 1 B5 0 B4 RS3 B3 RS2 B2 RS1 B1 RS0 B0 W/R
Note: The START bit is used to synchronize the data from the host device. The START bit is always 1. ______________________________________________________________________________________ 15
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
Table 7. Operating Mode (MODE Bit)
MODE BIT SETTING 0 1 OPERATING MODE The command byte initiates a conversion or an immediate power-down. See Tables 5 and 8. The device interprets the command byte as a register access byte, which is decoded as per Tables 6 and 9.
Table 8. Command Byte (MODE = 0, LINEF = 0)
COMMAND Self-calibration cycle System offset calibration cycle System gain calibration Immediate power-down Convert 1sps Convert 2.5sps Convert 5sps Convert 10sps Convert 15sps Convert 30sps Convert 60sps Convert 120sps START 1 1 1 1 1 1 1 1 1 1 1 1 MODE 0 0 0 0 0 0 0 0 0 0 0 0 CAL1 0 1 1 0 0 0 0 0 0 0 0 0 CAL0 1 0 1 0 0 0 0 0 0 0 0 0 IMPD 0 0 0 1 0 0 0 0 0 0 0 0 RATE2 0 0 0 0 0 0 0 0 1 1 1 1 RATE1 0 0 0 0 0 0 1 1 0 0 1 1 RATE0 0 0 0 0 0 1 0 1 0 1 0 1
Table 9. Register Selection (MODE = 1)
RS3 0 0 0 0 0 0 0 0 1 RS2 0 0 0 0 1 1 1 1 0 RS1 0 0 1 1 0 0 1 1 0 RS0 0 1 0 1 0 1 0 1 0 REGISTER ACCESS STAT1 CTRL1 CTRL2 CTRL3 DATA SOC SGC SCOC SCGC POWER-ON RESET STATUS 0x00 0x02 0x0F 0x1E 0x000000 0x000000 0x000000 0x000000 0x000000 REGISTER SIZE (BITS) 8 8 8 8 24 24 24 24 24
16
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
Table 10. Register Address Map
REGISTER ADDRESS R/W NAME SEL (RS[3:0]) STAT1 CTRL1 CTRL2 CTRL3 DATA R R/W R/W R/W R 0x0 0x1 0x2 0x3 0x4 B7 SYSOR LINEF DIR4 DGAIN2* B6 RATE2 U/B DIR3 DGAIN1* B5 RATE1 EXTCLK DIR2 DGAIN0* B4 RATE0 REFBUF DIR1 NOSYSG B3 OR SIGBUF DIO4 NOSYSO B2 UR FORMAT DIO3 NOSCG B1 MSTAT DIO2 NOSCO B0 RDY DIO1 RESERVED
MAX11206/MAX11207
SCYCLE RESERVED
D[19:16] D[15:8] D[7:0] B[23:16] SOC R/W 0x5 B[15:8] B[7:0] B[23:16] SGC R/W 0x6 B[15:8] B[7:0] B[23:16] SCOC R/W 0x7 B[15:8] B[7:0] B[23:16] SCGC R/W 0x8 B[15:8] B[7:0] *These DGAIN_ bits set the digital gain for the MAX11206. These bits are don't-care bits for the MAX11207.
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
STAT1: Status Register
Table 11. STAT1 Register (Read Only)
BIT BIT NAME DEFAULT B7 SYSOR 0 B6 RATE2 0 B5 RATE1 0 B4 RATE0 0 B3 OR 0 B2 UR 0 B1 MSTAT 0 B0 RDY 0
SYSOR: The system gain overrange bit, when set to 1, indicates that a system gain calibration was over range. The SCGC calibration coefficient is maximum value of 1.9999999. This bit, when set to 1, indicates that the full-scale value out of the converter is likely not available. RATE[2:0]: The data rate bits indicate the conversion rate that corresponds to the result in the DATA register or the rate that was used for calibration coefficient calculation. If the previous conversions were done at a different rate, the RATE[2:0] bits indicate a rate different than the rate of the conversion in progress. OR: The overrange bit, OR, is set to 1 to indicate the conversion result has exceeded the maximum value of the converter and that the result has been clipped or limited to the maximum value. The OR bit is set to 0 to indicate the conversion result is within the full-scale range of the device. UR: The underrange bit, UR, is set to 1 to indicate the conversion result has exceeded the minimum value of the converter and that the result has been clipped or limited to the minimum value. The UR bit is set to 0 to indicate the conversion result is within the full-scale range of the device. MSTAT: The measurement status bit, MSTAT is set to 1 when a signal measurement is in progress. When MSTAT = 1, a conversion, self-calibration, or system calibration is in progress and indicates that the modulator is busy. When the modulator is not converting, the MSTAT bit is set to 0. RDY: The RDY ready bit is set to 1 to indicate that a conversion result is available. Reading the DATA register resets the RDY bit to 0 only after another conversion has been initiated. If the DATA has not been read before another conversion is initiated, the RDY bit remains 1; if the DATA is read before another conversion is initiated, the RDY bit resets to 0. If the DATA for the previous conversion is read during a following conversion, the RDY bit is reset immediately after the DATA read operation has completed.
18
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
CTRL1: Control 1 Register The byte-wide CTRL1 register is a bidirectional read/write register. The byte written to the CTRL1 register indicates if the part converts continuously or single cycle, if an external or internal clock is used, if the reference and signal buffers are activated, the format of the data when in bipolar mode, and if the analog signal input range is unipolar or bipolar.
MAX11206/MAX11207
Table 12. CTRL1 Register (Read/Write)
BIT BIT NAME DEFAULT B7 LINEF 0 B6 U/B 0 B5 EXTCLK 0 B4 REFBUF 0 B3 SIGBUF 0 B2 FORMAT 0 B1 SCYCLE 1 B0 UNUSED 0
LINEF: Use the line frequency bit, LINEF, to select if the data rate is centered for 50Hz power mains or 60Hz power mains. To select data rates for 50Hz power mains, write 1 to LINEF and to select data rates for 60Hz power mains, write 0 to LINEF. U/B: The unipolar/bipolar bit, U/B, selects if the input range is unipolar or bipolar. A 1 in this bit location selects a unipolar input range and a 0 selects a bipolar input range. EXTCLK: The external clock bit, EXTCLK, controls the selection of the system clock. A 1 enables an external clock as system clock, whereas as a 0 enables the internal clock. REFBUF: The reference buffer bit, REFBUF, enables/disables the reference buffers. A 1 enables the reference buffers. A 0 powers down the reference buffers and the reference inputs bypass the reference buffers when driving the ADC. SIGBUF: The signal buffer, SIGBUF, enables/disables the signal buffers. A 1 enables the signal buffer. A 0 powers down the signal buffers and the analog signal inputs bypass the signal buffers when driving the ADC. FORMAT: The format bit, FORMAT, controls the digital format of the data. Unipolar data is always in offset binary format. The bipolar format is two's complement if the FORMAT bit is set to 0 or offset binary if the FORMAT bit is set to 1. SCYCLE: The single-cycle bit, SCYCLE, determines if the device runs in "no-latency" single-conversion mode (SCYCLE = 1) or if the device runs in "latent" continuous-conversion mode (SCYCLE = 0). When in single-cycle conversion mode, the device completes one no-latency conversion and then powers down into a leakage-only state. When in continuous-conversion mode, the part is continuously converting and the first three data from the part are incorrect due to the SINC4 filter latency. Important Note: When operating in continuous-conversion mode (SCYCLE = 0), it is recommended to keep CS low to properly detect the end of conversion. The end of conversion is signaled by RDY/DOUT changing from 0 to 1. The transition of RDY/DOUT from 0 to 1 must be used to synchronize the DATA register read back. If the RDY/DOUT output is not used to synchronize the DATA read back, a timing hazard exists where the DATA register is updated internally after a conversion has completed simultaneously with the DATA register being read out, causing an incorrect read of DATA.
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19
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
CTRL2: Control 2 Register The byte-wide CTRL2 register is a bidirectional read/write register. The byte written to the CTRL2 register controls the direction and values of the digital I/O ports.
Table 13. CTRL2 Register (Read/Write)
BIT BIT NAME DEFAULT B7 DIR4 0 B6 DIR3 0 B5 DIR2 0 B4 DIR1 0 B3 DIO4 1 B2 DIO3 1 B1 DIO2 1 B0 DIO1 1
DIR[4:1]: The direction bits configure the direction of the DIO bit. When a DIR bit is set to 0, the associated DIO bit is configured as an input and the value returned by a read of the DIO bit is the value being driven on the associated GPIO. When a DIR bit is set to 1, the associated DIO bit is configured as an output and the GPIO port is driven to a logic value of the associated DIO bit. DIO[4:1]: The data input/output bits are bits associated with the GPIO ports. When a DIO is configured as an input, the value read from the DIO bit is the logic value being driven at the GPIO port. When the direction is configured as an output, the GPIO port is driven to a logic value associated with the DIO bit. CTRL3: Control 3 Register The byte-wide CTRL3 register is a bidirectional read/write register. The CTRL3 register controls the operation and
Table 14. CTRL3 Register (Read/Write)
BIT BIT NAME DEFAULT B7 DGAIN2* 0 B6 DGAIN1* 0 B5 DGAIN0* 0 B4 NOSYSG 1 B3 NOSYSO 1 B2 NOSCG 1 B1 NOSCO 1 B0 RESERVED 0
*These DGAIN_ bits are don't-care bits for the MAX11207.
calibration of the device. DGAIN[2:0] (MAX11206 only): The digital gain bits control the input referred gain. With a gain of 1, the input range is 0 to VREF (unipolar) or VREF (bipolar). As the gain in increased by 2x, the input range is reduced to 0 to VREF/gain or VREF/gain. Digital gain is applied to the final offset and gain-calibrated digital data. The DGAIN[2:0] bits decode to digital gains as follows: 000 001 010 011 = = = = 1 2 4 8 100 101 110 111 = = = = 16 32 64 128
NOSYSG: The no-system gain bit, NOSYSG, controls the system gain calibration coefficient. A 1 in this bit location disables the use of the system gain value when computing the final offset and gain corrected data value. A 0 in this location enables the use of the system gain value when computing the final offset and gain corrected data value. NOSYSO: The no system offset bit, NOSYSO, controls the system offset calibration coefficient. A 1 in this location disables the use of the system offset value when computing the final offset and gain corrected data value. A 0 in this location enables the use of the system offset value when computing the final offset and gain corrected data value. NOSCG: The no self-calibration gain bit, NOSCG, controls the self-calibration gain calibration coefficient. A 1 in this location disables the use of the self-calibration gain value when computing the final offset and gain corrected data value. A 0 in this location enables the use of the self-calibration gain value when computing the final offset and gain corrected data value. NOSCO: The no self-calibration offset bit, NOSCO, controls the use of the self-calibration offset calibration coefficient. A 1 in this location disables the use of the self-calibration offset value when computing the final offset and gain corrected data value. A 0 in this location enables the use of the self-calibration offset value when computing the final offset and gain corrected data value.
20 _____________________________________________________________________________________
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
DATA: Data Register The data register is a 24-bit read-only register. Any attempt to write data to the data register has no effect. The data read from this register is clocked out MSB first. The data register holds the conversion result. D19 is the MSB, and D0 is the LSB. The result is stored in a format according to the FORMAT bit in the CTRL1 register. The data format while in unipolar mode is always straight binary. In straight binary format, the most negative value is 0x00000 (VAINP - VAINN = 0V), the midscale value is 0x80000 (VAINP - VAINN = VREF/2), and the most positive value is 0xFFFFF (VAINP - VAINN = VREF). In bipolar mode, if the FORMAT bit = 1, then the data format is offset binary. If the FORMAT bit = 0, then the data format is two's complement. In two's complement the negative full-scale value is 0x80000 (VAINP - VAINN = -VREF), the midscale is 0x00000 (VAINP - VAINN = 0V), and the positive full scale is 0x7FFFF (VAINP - VAINN = VREF). Any input exceeding the available input range is limited to the minimum or maximum data value.
MAX11206/MAX11207
Table 15. DATA Register (Read Only)
BIT DEFAULT BIT DEFAULT BIT DEFAULT D19 0 D11 0 D3 0 D18 0 D10 0 D2 0 D17 0 D9 0 D1 0 D16 0 D8 0 D0 0 D15 0 D7 0 0 0 D14 0 D6 0 0 0 D13 0 D5 0 0 0 D12 0 D4 0 0 0
Table 16a. Output Data Format for the Unipolar Input Range
INPUT VOLTAGE VAINP - VAINN VREF DIGITAL OUTPUT CODE FOR UNIPOLAR RANGE STRAIGHT BINARY FORMAT 0xFFFFF 0xFFFFE
1 VREF x 1 - 20 2 - 1
VREF 0
2 20 - 1
0x00001 0x00000
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21
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
Table 16b. Output Data Formats for the Bipolar Input Range
INPUT VOLTAGE VAINP - VAINN VREF 1 VREF x 1 - 19 2 - 1 2 19 - 1 0 2 19 - 1 1 -VREF x 1 - 2 19 - 1 -VREF -VREF VREF DIGITAL OUTPUT CODE FOR BIPOLAR RANGES OFFSET BINARY FORMAT 0xFFFFF 0xFFFFE TWO'S COMPLEMENT FORMAT 0x7FFFF 0x7FFFE
0x80001 0x80000 0x7FFFF
0x00001 0x00000 0xFFFFF
0x00001 0x00000
0x80001 0x80000
SOC: System Offset Calibration Register The system offset calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB (most significant bit) first. This register holds the system offset calibration value. The format is always in two's complement binary format. A write to the system-calibration register is allowed. The value written remains valid until it is either rewritten or until an on-demand system-calibration operation is performed, which overwrites the usersupplied value. The system offset calibration value is subtracted from each conversion result provided the NOSYSO bit in the CTRL3 register is set to 0. The system offset calibration value is subtracted from the conversion result after self-calibration but before system gain correction. The system offset calibration value is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes.
Table 17. SOC Register (Read/Write)
BIT DEFAULT BIT DEFAULT BIT DEFAULT B23 0 B15 0 B7 0 B22 0 B14 0 B6 0 B21 0 B13 0 B5 0 B20 0 B12 0 B4 0 B19 0 B11 0 B3 0 B18 0 B10 0 B2 0 B17 0 B9 0 B1 0 B16 0 B8 0 B0 0
22
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
SGC: System Gain Calibration Register The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB first. This register holds the system gain calibration value. The format is always in two's complement binary format. A write to the system-calibration register is allowed. The written value remains valid until it is either rewritten or until an on-demand system-calibration operation is performed, which overwrites the user-supplied value. The system gain calibration value is used to scale the offset corrected conversion result, provided the NOSYSG bit in the CTRL3 register is set to 0. The system gain calibration value scales the offset-corrected result by up to 2x or corrects a gain error of approximately -50%. The amount of positive gain error that can be corrected is determined by modulator overload characteristics, which can be as much as +25%. The gain is corrected to within 2 LSB.
MAX11206/MAX11207
Table 18. SGC Register (Read/Write)
BIT DEFAULT BIT DEFAULT BIT DEFAULT B23 0 B15 0 B7 0 B22 0 B14 0 B6 0 B21 0 B13 0 B5 0 B20 0 B12 0 B4 0 B19 0 B11 0 B3 0 B18 0 B10 0 B2 0 B17 0 B9 0 B1 0 B16 0 B8 0 B0 0
SCOC: Self-Calibration Offset Register The self-calibration offset register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB first. This register holds the self-calibration offset value. The format is always in two's complement binary format. A write to the self-calibration offset register is allowed. The written value remains valid until it is either rewritten or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value. The self-calibration offset value is subtracted from each conversion result provided the NOSCO bit in the CTRL3 register is set to 0. The self-calibration offset value is subtracted from the conversion result before the self-calibration gain correction and before the system offset and gain correction. The self-calibration offset value is also applied prior to the 2x scale factor associated with unipolar mode.
Table 19. SCOC Register (Read/Write)
BIT DEFAULT BIT DEFAULT BIT DEFAULT B23 0 B15 0 B7 0 B22 0 B14 0 B6 0 B21 0 B13 0 B5 0 B20 0 B12 0 B4 0 B19 0 B11 0 B3 0 B18 0 B10 0 B2 0 B17 0 B9 0 B1 0 B16 0 B8 0 B0 0
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
SCGC: Self-Calibration Gain Register The self-calibration gain register is a 24-bit read/write register. The data written/read to/from this register is clocked in/out MSB first. This register holds the self-calibration gain calibration value. The format is always in two's complement binary format. A write to the self-calibration register is allowed. The written value remains valid until it is either rewritten or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value. Any attempt to write to this register during an active calibration operation is ignored. The self-calibration gain value is used to scale the self-calibration offset corrected conversion result before the system offset and gain calibration values have been applied, provided the NOSCG bit in the CTRL3 register is set to 0. The self-calibration gain value scales the self-calibration offset corrected conversion result by up to 2x or can correct a gain error of approximately -50%. The gain is corrected to within 2 LSB.
Table 20. SCGC Register (Read/Write)
BIT DEFAULT BIT DEFAULT BIT DEFAULT B23 0 B15 0 B7 0 B22 0 B14 0 B6 0 B21 0 B13 0 B5 0 B20 0 B12 0 B4 0 B19 0 B11 0 B3 0 B18 0 B10 0 B2 0 B17 0 B9 0 B1 0 B16 0 B8 0 B0 0
Table 21. Data Rates for All Combinations of RATE[2:0] (LINEF = 0)
RATE[2:0] 000 001 010 011 100 101 110 111 SINGLE-CYCLE DATA RATE (sps) 1 2.5 5 10 15 30 60 120 CONTINUOUS DATA RATE (sps) -- -- -- -- 60 120 240 480
Table 22. Data Rates for All Combinations of RATE[2:0] (LINEF = 1)
RATE[2:0] 000 001 010 011 100 101 110 111 SINGLE-CYCLE DATA RATE (sps) 0.833 2.08 4.17 8.33 12.5 25 50 100 CONTINUOUS DATA RATE (sps) -- -- -- -- 50 100 200 400
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
Applications Information
IREF1 = K x IREF2 IREF2
MAX11206/MAX11207
See Figure 8 for the RTD temperature measurement circuit and Figure 9 for a resistive bridge measurement circuit. Adding more active circuitry to the analog input signal path is not always the best solution to a small-signal problem. Sometimes, increasing the dynamic range of an active device can lead to a simpler solution that also helps power consumption and linearity. Often, circuit designers immediately look for an external op amp or programmable gain amplifier (PGA) when confronted with coupling low-amplitude signals to sampled digital systems. In many cases, choosing an ADC with more dynamic range and better low-noise performance yields a solution that works better, simpler, and with less power. One such example is measurements from a strain gauge in a Wheatstone bridge configuration. Assuming a differential output signal from the bridge in Figure 10, the bridge's output voltage varies from 5mV to 105mV, while the noise of the bridge itself limits the sensitivity to approximately 1FV. This gives approximately 100,000 discrete levels that are available for quantization, a feat accomplished quite well with any ADC having 17 bits or more of usable resolution. However, as it is not likely that a 21-bit ADC will have an input range of 105mV, a gain stage is needed to boost the signal to span the input range of the ADC (typically between 3V and 5V). This solution requires finding an amplifier and associated passives that meet the overall system noise and linearity needs. Also, the power consumed in the gain stage may equal or surpass that of the ADC itself, a fact that is significant in systems where power consumption is severely constrained, such as portable sensors or 4-20mA loops. The low-noise floor of the MAX11206 family of 16-/18-/20bit devices gives the designer the ability to use simple binary shifting (digital gain) of the data word to align the sample range with the available code space. Digital gain is internally available in the MAX11206.
REFP RREF IREF1 REFN AINP RRTD AINN GND
MAX11206 MAX11207
Figure 8. RTD Temperature Measurement Circuit
AVDD REFP REFN AINP
MAX11206 MAX11207
AINN
Figure 9. Resistive Bridge Measurement Circuit
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25
20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO MAX11206/MAX11207
AVDD
Chip Information
PROCESS: BiCMOS
Package Information
20-BIT ADC RSTRAIN
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 16 QSOP PACKAGE CODE OUTLINE NO. 21-0055 LAND PATTERN NO. 90-0167
E16+4
AVDD
AINP
RSTRAIN AINN
MAX11206
Figure 10. The MAX11206 ADC Eliminates an External Gain Stage.
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20-Bit, Single-Channel, Ultra-Low-Power, DeltaSigma ADCs with Programmable Gain and GPIO
Revision History
REVISION NUMBER 0 REVISION DATE 8/10 Initial release DESCRIPTION PAGES CHANGED --
MAX11206/MAX11207
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
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2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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