 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * Number of keys: up to 16 keys, and one slider (constructed from 2 to 8 keys) * Number of I/O lines: 11 (3 dedicated - configurable for input or output, 8 shared output only), PWM control for LED driving * Technology: patented spread-spectrum charge-transfer (transverse mode) * Key outline sizes: 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible * Key spacings: 8 mm or wider, center to center (panel thickness dependent) * Slider design: 2 to 8 keys placed in sequence, same design as keys * Electrode design: two-part electrode shapes (drive-receive); wide variety of possible * * * * * * * * * * * * * layouts PCB layers required: one layer (with jumpers), two layers (no jumpers) Electrode materials: PCB, FPCB, silver or carbon on film, ITO on film Panel materials: plastic, glass, composites, painted surfaces (low particle density metallic paints possible) Adjacent metal: compatible with grounded metal immediately next to keys Panel thickness: up to 3 mm glass, 2.5 mm plastic (key size dependent) Key sensitivity: individually settable via simple commands over I2C-compatible interface Interface: I2C-compatible slave mode (100kHz) Moisture tolerance: best in class Power: 1.8 V to 5.5 V Package: 28-pin 4 x 4 mm MLF RoHS compliant Signal processing: self-calibration, auto drift compensation, noise filtering, Adjacent Key SuppressionTM technology Applications: laptop, mobile, consumer appliances, PC peripheral etc. Patents: AKSTM (patented Adjacent Key SuppressionTM) technology QMatrixTM (patented charge-transfer method) QSlideTM (patented charge-transfer method) (patent-pending QSlide sensing configuration) This datasheet is applicable to revision 4R0 chips only QSlideTM, 16-key QMatrixTM Sensor IC AT42QT2160 * 1. Overview The AT42QT2160-MMU (QT2160) is designed for use with up to 16 keys and a slider (constructed from 2 keys up to 8 keys). There are three dedicated General Purpose Input/Outputs (GPIOs) which can be used as inputs for mechanical switches etc. or as driven outputs. There are eight shared General Purpose Outputs (GPOs) (X0...X7) which are driven outputs only. There is PWM control for all GPIO/GPOs. The QMatrixTM technology employs transverse charge-transfer sensing electrode designs which can be made very compact and are easily wired. Charge is forced from an emitting electrode into the overlying panel dielectric, and then collected on a receiver electrode. This directs the charge into a sampling capacitor which is then converted directly to digital form, without the use of amplifiers. The keys are configured in a matrix format that minimizes the number of required scan lines and device pins. The key electrodes can be designed into a conventional Printed Circuit Board (PCB) or Flexible Printed Circuit Board (FPCB) as a copper pattern, or as printed conductive ink on plastic film. 9502A-AT42-07/08 2. Pinout and Pin Listing Description 2.1 Pinout Description GPIO1 I2CA1 SDA RST SCL Y1A Y0A GPIO2 GPIO3 VDD VSS X6 X7 CHANGE 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 I2CA0 Y1B Y0B VSS VDD VDD X5 QT2160 18 17 16 89 SMP VRef 15 10 11 12 13 14 X1 X3 X4 X0 X2 2.2 Pin Listing Description Table 2-1.Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Function GPIO2 GPIO3 Vdd Vss X6 X7 CHANGE Vref SMP X0 X1 X2 X3 I/O I/O I/O P P O O OD P O O O O O Comments General purpose input/output 2 General purpose input/output 3 Power Supply ground X matrix drive line / shared GPO X6 X matrix drive line / shared GPO X7 State change notification Supply ground Sample output. X matrix drive line / shared GPO X0 X matrix drive line / shared GPO X1 X matrix drive line / shared GPO X2 X matrix drive line / shared GPO X3 If Unused, Connect To... Leave open Leave open Leave open Leave open Leave open Leave open Leave open 2 AT42QT2160 9502A-AT42-07/08 AT42QT2160 Table 2-1.Pin Listing (continued) Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function X4 X5 Vdd Vdd Vss Y0B Y1B I2CA0 I2CA1 SDA SCL RST Y0A Y1A GPIO1 I/O O O P P P I/O I/O I I OD OD I I/O I/O I/O Comments X matrix drive line / shared GPO X4 X matrix drive line / shared GPO X5 Power Power Supply ground Y line connection Y line connection I2C-compatible address select I2C-compatible address select Serial Interface Data Serial Interface Clock Reset low; has internal 30k - 60k pullup Y line connection Y line connection General purpose input/output 1 If Unused, Connect To... Leave open Leave open Leave open Leave open Leave open or Vdd Leave open Leave open 3. Introduction The QT2160 device is a digital burst mode charge-transfer (QT) sensor designed specifically for matrix layout touch controls; it includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions. Only a few external parts are required for operation. The entire circuit can be built within a few square centimeters of single-sided PCB area. CEM-1 and FR1 punched, single-sided materials can be used for the lowest possible cost. The PCB's rear can be mounted flush on the back of a glass or plastic panel using a conventional adhesive, such as 3M VHB two-sided adhesive acrylic film. The QT2160 employs transverse charge-transfer (QT) sensing, a technology that senses changes in electrical charge forced across two electrode elements by a pulse edge (see Figure 3-1). The QT2160 allows a wide range of key sizes and shapes to be mixed together in a single touch panel. The device uses an I2C-compatible interface to allow key data to be extracted and to permit individual key parameter setup. The command structure is designed to minimize the amount of data traffic while maximizing the amount of information conveyed. In addition to normal operating and setup functions the device can also report back actual signal strengths. 3 9502A-AT42-07/08 Figure 3-1. Field Flow Between X and Y Elements overlying panel X element Y elem ent 3.1 Keys and Slider The QT2160 is capable of a maximum of 16 keys. These can be located anywhere within an electrical grid of 8X and 2Y scan lines. A lesser number of enabled keys will cause any unused acquisition burst timeslots to be pared from the sampling sequence, to optimize acquire speed and lessen power consumption. Thus, if only 8 keys are actually enabled, only 8 timeslots are used for scanning. Additional processing can be done on the keys to form a slider. The slider will have to start at X0 and use only Y0. The slider can consist of a minimum of 2 keys and a maximum of 8 keys. 3.2 Enabling/Disabling Keys Keys can be enabled by setting a nonzero burst length. A zero burst length disables the key. 4. Hardware and Functional 4.1 Matrix Scan Sequence The circuit operates by scanning each key sequentially, key by key. Key scanning begins with location X = 0, Y = 0 (key 0). X axis keys are known as rows while Y axis keys are referred to as columns although this has no reflection on actual wiring. Keys are scanned sequentially by row, for example the sequence X0Y0 X1Y0...X7Y0, X0Y1, X1Y1... etc. Keys are also numbered from 0...15. Key 0 is located at X0Y0. Table 4-1 shows the key numbering. Table 4-1. Y0 Y1 Key Numbers X7 7 15 X6 6 14 X5 5 13 X4 4 12 X3 3 11 X2 2 10 X1 1 9 X0 0 8 Key numbers Each key is sampled in a burst of acquisition pulses whose length is determined by the Setups parameter BL (Section 4.2 on page 5); this can be set on a per-key basis. A burst is completed entirely before the next key is sampled; at the end of each burst the resulting signal is converted to digital form and processed. The burst length directly impacts key gain; each key can have a unique burst length in order to allow tailoring of key sensitivity on a key-by-key basis. 4 AT42QT2160 9502A-AT42-07/08 AT42QT2160 4.2 Burst Paring Keys that are disabled by setting their burst length to zero have their bursts removed from the scan sequence to save scan time and thus power. The QT2160 operates on a fixed 16 ms cycle and will go to sleep after all acquisitions and processing is done till the next 16ms cycle starts. As a consequence, the fewer keys, the less power is consumed. 4.3 Cs Sample Capacitor Operation Cs capacitors (Cs0...Cs1) absorb charge from the key electrodes on the rising edge of each X pulse. On each falling edge of X, the Y matrix line is clamped to ground to allow the electrode and wiring charges to neutralize in preparation for the next pulse. With each X pulse charge accumulates on Cs causing a staircase increase in its differential voltage. After the burst completes, the device clamps the Y line to ground causing the opposite terminal to go negative. The charge on Cs is then measured using an external resistor to ramp the negative terminal upwards until a zero crossing is achieved. The time required to zero cross becomes the measurement result. The Cs capacitors should be connected as shown in Figure 4-8 on page 15. The value of these capacitors is not critical but 4.7 nF is recommended for most cases. They should be 10 percent X7R ceramic. If the transverse capacitive coupling from X to Y is large enough the voltage on a Cs capacitor can saturate, destroying gain. In such cases the burst length should be reduced and/or the Cs value increased. See Section 4.4. If a Y line is not used its corresponding Cs capacitor may be omitted and the pins left floating. 4.4 Sample Capacitor Saturation Cs voltage saturation at a pin YnB is shown in Figure 4-1. Saturation begins to occur when the voltage at a YnB pin becomes more negative than -0.25V at the end of the burst. This nonlinearity is caused by excessive voltage accumulation on Cs inducing conduction in the pin protection diodes. This badly saturated signal destroys key gain and introduces a strong thermal coefficient which can cause phantom detection. The cause of this is either from the burst length being too long, the Cs value being too small, or the X-Y transfer coupling being too large. Solutions include loosening up the key structure interleaving, more separation of the X and Y lines on the PCB, increasing Cs, and decreasing the burst length. Increasing Cs will make the part slower; decreasing burst length will make it less sensitive. A better PCB layout and a looser key structure (up to a point) have no negative effects. Cs voltages should be observed on an oscilloscope with the matrix layer bonded to the panel material; if the Rs side of any Cs ramps more negative than -0.25 volts during any burst (not counting overshoot spikes which are probe artifacts), there is a potential saturation problem. Figure 4-2 shows a defective waveform similar to that of Figure 4-1, but in this case the distortion is caused by excessive stray capacitance coupling from the Y line to AC ground; for example, from running too near and too far alongside a ground trace, ground plane, or other traces. The excess coupling causes the charge-transfer effect to dissipate a significant portion of the received charge from a key into the stray capacitance. This phenomenon is more subtle; it can be best detected by increasing BL to a high count and watching what the waveform does as it descends towards and below -0.25V. The waveform will appear deceptively straight, but it will slowly start to flatten even before the -0.25V level is reached. A correct waveform is shown in Figure 4-3. Note that the bottom edge of the bottom trace is substantially straight (ignoring the downward spikes). 5 9502A-AT42-07/08 Unlike other QT circuits, the Cs capacitor values on QT2160 devices have no effect on conversion gain. However, they do affect conversion time. Unused Y lines should be left open. Figure 4-1. VCs - Nonlinear During Burst (Burst too long, or Cs too small, or X-Y transcapacitance too large) X Drive YnB Figure 4-2. VCs - Poor Gain, Nonlinear During Burst (Excess capacitance from Y line to Gnd) X Drive YnB Figure 4-3. VCs - Correct X Drive YnB 6 AT42QT2160 9502A-AT42-07/08 AT42QT2160 Figure 4-4. Drive Pulse Roll-off and Dwell Time X drive Lost charge due to inadequate settling before end of dwell time Dwell time Y gate Note: The Dwell time is a minimum of ~250ns - see Section 4.7 4.5 Sample Resistors The sample resistors (Rs0...Rs1) are used to perform single-slope ADC conversion of the acquired charge on each Cs capacitor. These resistors directly control acquisition gain; larger values of Rs will proportionately increase signal gain. For most applications Rs should be 1M. Unused Y lines do not require an Rs resistor. 4.6 Signal Levels The signal values should normally be in the range of 200 to 750 counts with properly designed key shapes and values of Rs. However, long adjacent runs of X and Y lines can also artificially boost the signal values, and induce signal saturation; this is to be avoided. The X-to-Y coupling should come mostly from intra-key electrode coupling, not from stray X-to-Y trace coupling. The signal swing from the smallest finger touch should preferably exceed 8 counts, with 12 being a reasonable target. The signal threshold setting (NTHR) should be set to a value guaranteed to be less than the signal swing caused by the smallest touch. Increasing the burst length (BL) parameter will increase the signal strengths, as will increasing the sampling resistor (Rs) values. 4.7 Matrix Series Resistors The X and Y matrix scan lines can use series resistors (Rx0...Rx7 and Ry0...Ry1 respectively) for improved EMC performance (Figure 4-8 on page 15). X drive lines require Rx in most cases to reduce edge rates and thus reduce RF emissions. Values range from 1 k to 20 k, typically 1 k. Y lines need Ry to reduce EMC susceptibility problems and in some extreme cases, ESD. Typical Y values are about 1 k. Y resistors act to reduce noise susceptibility problems by forming a natural low-pass filter with the Cs capacitors. It is essential that the Rx and Ry resistors and Cs capacitors be placed very close to the chip. Placing these parts more than a few millimeters away opens the circuit up to high frequency interference problems (above 20 MHz) as the trace lengths between the components and the chip start to act as RF antennae. The upper limits of Rx and Ry are reached when the signal level and hence key sensitivity are clearly reduced. The limits of Rx and Ry will depend on key geometry and stray capacitance, and thus an oscilloscope is required to determine optimum values of both. 7 9502A-AT42-07/08 Dwell time is the duration in which charge coupled from X to Y is captured (Figure 4-4 on page 7). Increasing Rx values will cause the leading edge of the X pulses to increasingly roll off, causing the loss of captured charge (and hence loss of signal strength) from the keys. The dwell time is a minimum of 250 ns. If the X pulses have not settled within 250 ns, key gain will be reduced; if this happens, either the stray capacitance on the X line(s) should be reduced (by a layout change, for example by reducing X line exposure to nearby ground planes or traces), or, the Rx resistor needs to be reduced in value (or a combination of both approaches). One way to determine X line settling time is to monitor the fields using a patch of metal foil or a small coin over the key (Figure 4-5). Only one key along a particular X line needs to be observed, 250 ns dwell time should exceed the observed 95 percent settling of the X-pulse by 25 percent or more. In almost all cases, Ry should be set equal to Rx, which will ensure that the charge on the Y line is fully captured into the Cs capacitor. Figure 4-5. Probing X-Drive Waveforms With a Coin 4.8 Key Design Circuits can be constructed out of a variety of materials including conventional FR-4, Flexible Printed Circuit Boards (FPCB), silver silk-screened on PET plastic film, and even inexpensive punched single-sided CEM-1 and FR-2. The actual internal pattern style is not as important as the need to achieve regular X and Y widths and spacings of sufficient size to cover the desired graphical key area or a little bit more; ~3mm oversize is acceptable in most cases, since the key's electric fields drop off near the edges anyway. The overall key size can range from 6mm x 6mm up to 100mm x 100mm but these are not hard limits. The keys can be any shape including round, rectangular, square, etc. The internal pattern can be interdigitated as shown in Figure 4-6. For small, dense keypads, electrodes such as shown in the lower half of Figure 4-6 can be used. Where the panels are thin (under 2 mm thick) the electrode density can be quite high. 8 AT42QT2160 9502A-AT42-07/08 AT42QT2160 For better surface moisture suppression, the outer perimeter of X should be as wide as possible, and there should be no ground planes near the keys. The variable "T" in this drawing represents the total thickness of all materials that the keys must penetrate. Figure 4-6. Recommended Key Structure Y0 X0 Y1 Note: "T" should ideally be similar to the complete thickness the fields need to penetrate to the touch surface. Smaller dimensions will also work but will give less signal strength. If in doubt, make the pattern coarser. The lower figure shows a simpler structure used for compact key layouts, for example for mobile phones. A layout with a common X drive and two receive electrodes is depicted 4.9 4.9.1 Setting the Slider Introduction Groups of keys can be configured as a slider, in addition to their use as keys. The slider uses the Y0 line of the matrix and must start at X0, with the keys placed in consecutive numerical order. The slider can take up a programmable number of keys on the Y0 line. The remaining keys on that Y line behave as normal. Positional data is calculated in a customizable range of 2 bits (0-3) to 8 bits (0-255). Geometric constraints may mean that the data will not reach the full range. Thinner dielectric or the use of more keys in a slider will increase the data range towards the ends. Stability of the reported position will be dependent on the amount of signal on the slider keys. Running at higher resolutions, with a thick panel might produce a fluctuating reported position. 9 9502A-AT42-07/08 Key sizes should be in the 5-7mm range when used in the slider to get the best linearity. The slider should be made up of however many of these elements are required to fit their dimensions. The slider will be treated as an object in the Adjacent Key Suppression (AKS) groupings. The keys in the slider would normally be set to the same burst length and threshold, although adjustments can be made in these at the expense of linearity. 4.9.2 AKS Technology and the Slider There can be up to three AKS groups, implemented so that only one key in each group may be reported as being touched at any one time. The AKS technique will lock onto the dominant key, and until this key is released, other keys in the group will not be reported as in detection. This allows a user to slide a finger across multiple keys with only the dominant key reporting touch. Each key may be in one of the groups 1...3, or in group 0 meaning that it is not AKS enabled. Keys in the slider are not able to use AKS technique against each other. This is necessary to enable smooth scrolling. Multiple keys within the slider can be in detect at the same time, regardless of the AKS settings. The AKS technique will, however, work against keys outside the object or within another object. For example, if a slider is in the same AKS group as keys, then touching anywhere on the slider will cause the AKS technique to suppress the keys. Similarly touching the keys first will suppress the slider. Note: For normal operation all keys in the slider should be placed in the same AKS group. 4.10 4.10.1 PCB Layout, Construction Overview It is best to place the chip near the touch keys on the same PCB so as to reduce X and Y trace lengths, thereby reducing the chances for EMC problems. Long connection traces act as RF antennae. The Y (receive) lines are much more susceptible to noise pickup than the X (drive) lines. Even more importantly, all signal related discrete parts (resistors and capacitors) should be very close to the body of the chip. Wiring between the chip and the various resistors and capacitors should be as short and direct as possible to suppress noise pickup. Ground planes, if used, should be placed under or around the QT chip itself and the associated resistors and capacitors in the circuit, under or around the power supply, and back to a connector. Ground planes can be used to shield against radiated noise, but at the expense of a reduction in sensitivity as described previously. Note: When using ground planes/floods, parasitic capacitance on Y lines can lead to reduced chargetransfer efficiency. For noise suppression, ground planes/floods can be beneficial around and between keys on the touch side of the PCB. However, it is advisable to route Y lines on the PCB layer furthest away from the plane/flood, to reduce parasitic capacitance. Cross-hatched ground patterns can act as effective shields, while helping to reduce parasitic capacitance. Ground planes/floods around the chip are generally acceptable, taking into account the same considerations as for the Y line parasitics. 4.10.2 LED Traces and Other Switching Signals Digital switching signals near the Y lines will induce transients into the acquired signals, deteriorating the SNR performance of the device. Such signals should be routed away from the Y lines, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). 10 AT42QT2160 9502A-AT42-07/08 AT42QT2160 LED terminals which are multiplexed or switched into a floating state and which are within or physically very near a key structure (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 10nF capacitor to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type. LED terminals which are constantly connected to Vss or Vdd do not need further bypassing. 4.10.3 Tracks The central pad on the underside of the chip should be connected to ground. Do not run any tracks underneath the body of the chip, only ground. Figure 4-7. Position of Tracks Example of good tracking Example of bad tracking 4.10.4 PCB Cleanliness All capacitive sensors should be treated as highly sensitive circuits which can be influenced by stray conductive leakage paths. QT devices have a basic resolution in the femtofarad range; in this region, there is no such thing as "clean flux". Flux absorbs moisture and becomes conductive between solder joints, causing signal drift and resultant false detections or transient losses of sensitivity or instability. Conformal coatings will trap in existing amounts of moisture which will then become highly temperature sensitive. The designer should specify ultrasonic cleaning as part of the manufacturing process, and in cases where a high level of humidity is anticipated, the use of conformal coatings after cleaning to keep out moisture. 4.11 Power Supply Considerations See Section 10.2 on page 43 for the Vdd range and short-term power supply fluctuations. If the power supply fluctuates slowly with temperature, the device will track and compensate for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism will not be able to keep up, causing sensitivity anomalies or false detections. As the device uses the power supply itself as an analog reference, the power should be very clean and come from a separate regulator. A standard inexpensive Low Dropout (LDO) type regulator should be used that is not also used to power other loads such as LEDs, relays, or other high current devices. Load shifts on the output of the LDO can cause Vdd to fluctuate enough to cause false detection or sensitivity shifts. 11 9502A-AT42-07/08 Caution: A regulator IC shared with other logic devices can result in erratic operation and is not advised. A regulator can be shared among two or more QT devices on one board. Refer to page 15 for suggested regulator manufacturers. A single ceramic 0.1uF bypass capacitor, with short traces, should be placed very close to supply pins 3 and 4 of the IC. Failure to do so can result in device oscillation, high current consumption, erratic operation etc. Pins 16 and 17 do not require bypassing if the traces between these pins and power traces are short. 4.12 Startup/Calibration Times The device requires initialization times of approximately 70ms. The CHANGE line will go low and calibration will start (takes 15 matrix scans), after this start up period is over. 4.13 Calibration Calibration does not occur periodically. Keys are only calibrated on power-up and when: * Enabled AND - held in detect for too long. The negative recalibration delay (NRD) period is specified by the user OR - the signal delta value is greater than the positive threshold value, defined as reference value plus three-quarters of the negative threshold OR - the user issues a recalibrate command An interrupt on the CHANGE pin occurs when there is a change in the key status bytes. An interrupt will occur on calibration only if at least one of the keys or objects was in detect as recalibration will then cause a status change. 4.14 Reset Input The RST pin can be used to reset the device to simulate a power-down cycle, in order to bring the device up into a known state should communications with the device be lost. The pin is active low, and a low pulse lasting at least 10s must be applied to this pin to cause a reset. If an external hardware reset is not used, the reset pin may be connected to Vdd. 12 AT42QT2160 9502A-AT42-07/08 AT42QT2160 4.15 Spread Spectrum Acquisitions QT2160 uses spread-spectrum burst modulation. This has the effect of drastically reducing the possibility of EMI effects on the sensor keys, while simultaneously spreading RF emissions. This feature is hard-wired into the device and cannot be disabled or modified. Spread spectrum is configured as a frequency chirp over a wide range of frequencies for robust operation. 4.16 Detection Integrator See also Section 4.2 on page 5. The device features a detection integration mechanism, which acts to confirm a detection in a robust fashion. A per-key counter is incremented each time the key has exceeded its threshold and stayed there for a number of acquisitions. When this counter reaches a preset limit the key is finally declared to be touched. For example, if the limit value is 10, then the device has to exceed its threshold and stay there for 10 acquisitions in succession without going below the threshold level, before the key is declared to be touched. If on any acquisition the signal is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. 4.17 Sleep The device operates on a fixed 16ms cycle time basis. The device will perform a set of measurements and then sleep for the rest of the cycle to conserve power. There are two user-configurable sleep modes; Low Power (LP) mode and SLEEP mode. The LP setting (see Section 4.2 on page 5) is used for conserving power when there are no touches and is set to be a long time period. This will determine how often the device wakes up to do drift compensation. It also determines the maximum response time to the first touch after inactivity. When a valid touch is registered, the device enters minimum cycle time (16ms) for a faster response to key touch and object operation. The device will stay in this mode if it continues to see keys being touched and released. There is a user-selectable inactivity timeout i.e. the awake timeout. The measurement period needs to be shorter than the 16ms fixed cycle time for optimum operation. If the measurement time exceeds the 16ms fixed cycle time, a CYCLE OVERRUN bit is set in the general status register. The QT2160 will still operate if the 16ms fixed cycle time is exceeded, but the timing for the timed parameters, e.g. drift compensation negative recalibration time out etc. will slightly change. A low power setting of zero causes the device to enter an ultra-low power mode (SLEEP), where no measurements are carried out. SLEEP mode also stops the internal watchdog timer, so that the part is totally dormant, and current drain is <2A. The PWM function will not be carried out during SLEEP, therefore it is recommended driving the GPIOs/GPOs to known states before entering SLEEP mode. The QT2160 wakes from SLEEP mode if there is an address match on the I2C-compatible bus, a hardware reset on the RST pin or an LP mode is set. If the Wake option is set for the dedicated GPIO inputs, then the QT2160 will trigger the CHANGE line if a change in status (either positive or negative going edge) of the respective GPIO is detected, in SLEEP mode. 13 9502A-AT42-07/08 4.18 General Purpose Inputs/Outputs There are three dedicated GPIOs (GPIO1...3) and eight GPOs shared with X lines (X0...7). Shared GPOs are always outputs, whereas dedicated GPIOs can be set to be outputs or inputs. GPIOs set to input can be used for reading dome switches or logic signals. Outputs can be used to drive LEDs, or other devices. It is recommended driving external devices through the use of bipolar transistors or MOSFETs, so as not to affect capacitive sensing if a load fluctuates the power rail by drawing/sinking too much current. All GPOs and GPIOs set to output can be PWM driven, if the corresponding PWM bit is set. Note that the PWM duty cycle will be an approximation, as GPIOs will not be switched during acquisition bursts. The dedicated GPIOs have a Wake option, that if enabled will enable dedicated GPIOs set as inputs, to be read in SLEEP mode. Note that shared GPOs (X0...X7) are driven by the burst pulses during acquisition bursts, if the corresponding X line is used in the keys/slider. A low pass filter can be inserted to eliminate these burst pulses, as shown in Figure 4-9 on page 16. 14 AT42QT2160 9502A-AT42-07/08 AT42QT2160 4.19 Wiring Wiring Diagram follow regulator manufacturers recommended values for input and output bypass capacitors. tightly wire a 100nF bypass capacitor between Vdd and Vss (pins 3 and 4). Figure 4-8. Vunreg VREG VDD Rx7 VDD Rx5 Rx4 Rp SDA SCL VDD Rchg CHANGE Ry0 I2C ADDRESS SELECT MATRIX Y SCAN IN General purpose inputs/outputs Rp Rx3 MATRIX X DRIVE Rx6 QT2160 Rx2 Rx1 Rx0 I2C Cs0 Ry1 Cs1 Rs1 Rs0 Notes: 1) the central pad on the underside of the chip is a Vss pin and should be connected to ground. Do not put any other tracks underneath the body of the chip. 2) it is important to place all Rx, Ry, Cs and Rs components physically near to the chip. 3) leave YnA, YnB unconnected if not used. Suggested regulator manufacturers: * Toko (XC6215 series) * Seiko (S817 series) * BCDSemi (AP2121 series) Re Figure 4-8 check the following sections for component values: * Section 4.3 on page 5: Cs capacitors (Cs0...Cs1) * Section Note: on page 7: Sample resistors (Rs0...Rs1) * Section 4.7 on page 7: Matrix resistors (Rx0...Rx7, Ry0...Ry1) * Section 4.11 on page 11: Voltage levels * Section 6.4 on page 22: SDA, SCL pull-up resistors (Rp) * Section 4.2 on page 5: CHANGE resistor (Rchg) * Section 4.2 on page 5: I2C-compatible addresses 15 9502A-AT42-07/08 Figure 4-9. Inputs/Outputs 16 AT42QT2160 9502A-AT42-07/08 AT42QT2160 5. I2C-compatible Bus Operation 5.1 Interface Bus More detailed information about the I 2 C-compatible bus protocol is available from www.i2C-bus.org. Devices are connected onto the I2C-compatible bus as shown in Figure 5-1. Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I2C-compatible devices must be open-drain type. This implements a wired-AND function which allows any and all devices to drive the bus, one at a time. A low level on the bus is generated when a device outputs a zero. Figure 5-1. I2C-compatible Interface Bus Vdd Device 1 Device 2 Device 3 Device n R1 R2 SDA SCL Table 5-1. Parameter I2C-compatible Bus Specifications Unit 7-bit 100 kHz 4 s minimum 4 s minimum 4.7 s minimum 1 s maximum Address space Maximum bus speed (SCL) Hold time START condition Setup time for STOP condition Bus free time between a STOP and START condition Rise times on SDA and SCL 5.2 Transferring Data Bits Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high; The only exception to this rule is for generating START and STOP conditions. 17 9502A-AT42-07/08 Figure 5-2. Data Transfer SDA SCL Data Stable Data Stable Data Change 5.3 START and STOP Conditions The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START condition on the bus, and is terminated when the host issues a STOP condition. Between START and STOP conditions, the bus is considered busy. As shown below, START and STOP conditions are signaled by changing the level of the SDA line when the SCL line is high. Figure 5-3. START and STOP Conditions SDA SCL START 5.4 Address Packet Format STOP All address packets are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise a write operation is performed. When the device recognizes that it is being addressed, it will acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The most significant bit of the address byte is transmitted first. The address sent by the host must be consistent with that selected with the option jumpers. 18 AT42QT2160 9502A-AT42-07/08 AT42QT2160 Figure 5-4. Address Packet Format Addr MSB SDA Addr LSB R/W ACK SCL 1 START 2 7 8 9 5.5 Data Packet Format All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the host generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signaled. 5.6 Combining Address and Data Packets Into a Transmission A transmission consists of a START condition, an SLA+R/W, one or more data packets and a STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between the host and the device. The device extends the SCL low period by pulling the SCL line low whenever it needs extra time for processing between the data transmissions. Holding down either SCL or SDA for clock stretching or any other purpose will slow down the operation of the QT2160. If SCL or SDA is continuously held low for more than ~12ms, this will be deemed as a error condition and the I2C-compatible unit reset. Note: Each write or read cycle must end with a STOP condition. The QT2160 may not respond correctly if a cycle is terminated by a new START condition. 19 9502A-AT42-07/08 Figure 5-6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP. Figure 5-5. Data Packet Format Data MSB Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master SLA+R/W Data LSB ACK 1 2 7 Data Byte 8 9 STOP or Next Data Byte Figure 5-6. SDA Packet Transmission Addr MSB Addr LSB R/W ACK Data MSB Data LSB ACK SCL 1 START 2 SLA+R/W 7 8 9 1 2 Data Byte 7 8 9 STOP 20 AT42QT2160 9502A-AT42-07/08 AT42QT2160 6. Interfaces 6.1 I2C-compatible Protocol The I2C-compatible protocol is based around access to an address table and supports multibyte reads and writes. Note: Each write or read cycle must end with a stop condition. The QT2160 may not respond correctly if a cycle is terminated by a new start condition. 6.2 I2C-compatible Addresses Four preset I2C-compatible addresses are selectable through pin I2CA0 and I2CA1 (Table 6-1). Table 6-1. I2C-compatible Addresses I2CA1 0 0 1 1 I2CA0 0 1 0 1 Address 0x0D 0x17 0x44 0x6B 6.3 6.3.1 Data Read/Write Writing Data to the Device The sequence of events required to write data to the device is shown next. Host to Device S SLA+W A MemAddress A Device to Host Data A P Key S SLA+W A MemAddress Data P Start condition Slave address plus write bit Acknowledge bit Target memory address within device Data to be written Stop condition The host initiates the transfer by sending the START condition, and follows this by sending the slave address of the device together with the Write-bit. The device sends an ACK. The host then sends the memory address within the device it wishes to write to. The device sends an ACK. The host transmits one or more data bytes; each will be acknowledged by the device. 21 9502A-AT42-07/08 If the host sends more than one data byte, they will be written to consecutive memory addresses. The device automatically increments the target memory address after writing each data byte. After writing the last data byte, the host should send the STOP condition. The host should not try to write beyond address 255 because the device will not increment the internal memory address beyond this. 6.3.2 Reading Data From the Device The sequence of events required to read data from the device is shown next. Host to Device S SLA+W Data 1 A A MemAddress A P Data 2 A S Device to Host SLA+R Data n A /A P The host initiates the transfer by sending the START condition, and follows this by sending the slave address of the device together with the Write-bit. The device sends an ACK. The host then sends the memory address within the device it wishes to read from. The device sends an ACK. The host must then send a STOP and a START condition followed by the slave address again but this time accompanied by the Read-bit. The device will return an ACK, followed by a data byte. The host must return either an ACK or NACK. If the host returns an ACK, the device will subsequently transmit the data byte from the next address. Each time a data byte is transmitted, the device automatically increments the internal address. The device will continue to return data bytes until the host responds with a NACK. The host should terminate the transfer by issuing the STOP condition. 6.4 SDA, SCL The I2C-compatible bus transmits data and clock with SDA and SCL. They are open-drain; that is I2C-compatible master and slave devices can only drive these lines low or leave them open. The termination resistors (Rp) pull the line up to Vdd if no I2C-compatible device is pulling it down. The termination resistors commonly range from 1k to 10k and should be chosen so that the rise times on SDA and SCL meet the I2C-compatible specifications (1s maximum). 6.5 CHANGE Pin The CHANGE pin is an active low open drain output that can be used to alert the host of any changes to any of the 5 status bytes (address 2 to 6), thus reducing the need for wasteful I 2 C-compatible communications. After setting up the QT2160, the host can simply not communicate with the device, except when the CHANGE pin goes active. CHANGE goes inactive again only when the host performs a read from all status bytes which have changed. Poll rate: The host can make use of the CHANGE pin output to initiate a communication; this will guarantee the optimal polling rate. If the host cannot make use of the CHANGE pin, the poll rate should be no faster than once per matrix scan (see Section 10.4 on page 44). Anything faster will not provide new information and will slow down the chip operation. The CHANGE pin requires a pull-up resistor, with a typical value of ~100k. 22 AT42QT2160 9502A-AT42-07/08 AT42QT2160 7. Communications Protocol 7.1 Introduction The device is address mapped. All communications consist of writes to, and reads from, locations in an 8-bit address map. Table 7-1 shows the address map of QT2160. Table 7-1. Memory Map Use Chip ID Major/minor code version General Status Key Status 1 Key Status 2 Slider Touch Position GPIO Read Sub-revision Reserved - 0x00 Calibrate Reset LP Mode Burst Repetition Reserved - 0x00 Neg Drift Compensation Pos Drift Compensation Normal DI Limit Neg Recal Delay Drift Hold Time/AWAKE Slider Control Slider Options Key 0 - 15 Key Control Key 0 - 15 Neg Threshold Key 0 - 15 Burst Length GPIO/GPO Drive 1 Access Read Read Read Read Read Read Read Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Address 0 1 2 3 4 5 6 7 8...9 10 11 12 13 14 15 16 17 18 19 20 21 22...37 38...53 54...69 70 23 9502A-AT42-07/08 Table 7-1. Memory Map (continued) Use GPIO/GPO Drive 2 Reserved - 0x00 GPIO Direction 2 GPIO/GPO PWM 1 GPIO/GPO PWM 2 PWM Level GPIO Wake Common change Keys 1 Common change Keys 2 Reserved - 0x00 Key 0 - 15 Signals Key 0 - 15 References Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Read Address 71 72 73 74 75 76 77 78 79 80...99 100...131 132...163 Note: Reserved areas can be read or written to, to simplify communications. If written to, only write 0x00. 7.2 Address 0: Chip ID Table 7-2. Address 0 Chip ID b7 b6 b5 b4 Chip ID b3 b2 b1 b0 There is an 8-bit chip ID, which is set at 0x11. 7.3 Address 1: Code Version Table 7-3. Address 1 Code Version b7 b6 b5 b4 b3 b2 b1 b0 Major Version Minor Version There is an 8-bit major and minor version of firmware code revision. The top nibble of the firmware version register contains the major version (e.g. 4.0) and the bottom nibble contains the minor version (e.g. 4.0). 24 AT42QT2160 9502A-AT42-07/08 AT42QT2160 7.4 Address 2: General Status Table 7-4. Address General Status b7 b6 CYCLE OVER RUN b5 b4 b3 b2 b1 b0 2 RESET 0 0 0 0 CC SDET These bits indicate the general status of the device. A change in this byte will cause the CHANGE line to trigger. RESET: this bit is set after a reset. This bit is clear after this byte is read back by the host. CYCLE OVERRUN: this bit is set if the cycle time is more than 16ms. It will be cleared when the cycle time is less than 16ms. Note: holding any of the I 2 C-compatible lines, for clock stretching or other purposes, will increase the cycle time. CC: this common change bit is set if all the selected keys (address 78...79) have a signal change of more than half the detection threshold, NTHR. The CC bit is not debounced. This bit can be used to indicate a common change in signals, e.g. In a notebook application, where the cover is closing, so that the host can suppress key detections. Note: the CC bit will be set to 1 if no keys are selected to be in the Common Change group (see Section 7.27 on page 35). SDET: this bit is set if a touch is detected on the slider. 7.5 Address 3...4: Key Status Table 7-5. Address 3 4 Key Status and Numbering b7 k7 k15 b6 k6 k14 b5 k5 k13 b4 k4 k12 b3 k3 k11 b2 k2 k10 b1 k1 k9 b0 k0 k8 Address 3: detect status for keys 0 to 7 Address 4: detect status for keys 8 to 15 Each location indicates all keys in detection, if any, as a bitfield; touched keys report as "1", untouched or disabled keys report as "0". A change in this byte will cause the CHANGE line to trigger. 25 9502A-AT42-07/08 7.6 Address 5: Slider Touch Position Table 7-6. Address 5 Slider Touch Position b7 b6 b5 b4 Position b3 b2 b1 b0 Position: Last position of the touch on the slider A change in this byte will cause the CHANGE line to trigger. 7.7 Address 6: GPIO Read Table 7-7. Address 6 GPIO Read b7 0 b6 0 b5 0 b4 GPIO3 b3 GPIO2 b2 GPIO1 b1 0 b0 0 GPIO1...3: If GPIO1...3 are set as inputs, returns the logic level on the respective pin. If a GPIO is set as an output, the respective bit in GPIO Read will always report "0". GPIOs set as inputs are only read once every cycle, i.e. every 16ms. A change in this byte will cause the CHANGE line to trigger. 7.8 Address 7: Sub-revision Table 7-8. Address 7 Sub-revision b7 b6 b5 b4 b3 b2 b1 b0 Sub-revision This is an 8-bit sub-revision number that follows the code version (e.g. 4.0.0). 7.9 Address 10: Calibrate Table 7-9. Address 10 Calibrate b7 b6 b5 b4 b3 b2 b1 b0 CALIBRATE Writing any nonzero value into this address will trigger the QT2160 to start a recalibration on all enabled keys. 26 AT42QT2160 9502A-AT42-07/08 AT42QT2160 7.10 Address 11: Reset Table 7-10. Address 11 Reset b7 b6 b5 b4 RESET b3 b2 b1 b0 Any nonzero value will trigger the device to reset. After a reset, the device will revert to default settings. After receiving a reset command the QT2160 will start not acknowledging I 2 C-compatible communications and make CHANGE inactive within 16ms. The chip will reset after another ~16ms. 7.11 Address 12: LP Mode Table 7-11. Address 12 LP Mode b7 b6 b5 b4 b3 b2 b1 b0 LP_MODE LP mode sets the sleep time between bursts. A higher value causes more sleep time between acquisitions resulting in lower power consumption, but slower response time. The values are between 1...255, with each incrementing the sleep time by 16ms steps. For example, 1 = 16ms LP, 2 = 32ms LP, 3 = 48ms LP, etc. A value of zero causes the device to enter an ultra-low power mode (SLEEP), where no measurements are carried out (see Section 4.17 on page 13). The QT2160 is designed to sleep as much as possible to conserve power. Note: the longer the LP mode, the longer the response time at first touch. The response time for the first touch includes the digital filter's settling time (a few measurement cycles) and the DI process. Above 256ms LP mode the power consumption does not reduce as much, even with longer LP mode durations. Refer to Table 10-1 on page 45 for typical power consumptions. Default value: 1 (6ms LP) 7.12 Address 13: Burst Repetition Table 7-12. Address 13 Burst Repetition b7 0 b6 0 b5 b4 b3 BREP b2 b1 b0 Burst Repetition (BREP) is a feature that enables the QT2160 to make multiple measurements and take the average result; this improves the device's ability to operate in noisy environments. The number of burst repetitions can be reduced in low noise environments for faster response time. The BREP value can range between 1...63 repetitions. Do not set to 0 because it is not valid. Default value:1 (one measurement burst) 27 9502A-AT42-07/08 7.13 Address 15...16: Neg/Pos Drift Compensation Table 7-13. Address 15 16 Neg/Pos Drift Compensation b7 0 0 b6 b5 b4 b3 NDRIFT PDRIFT b2 b1 b0 Signals can drift because of changes in Cx and Cs over time and temperature. It is crucial that such drift be compensated, else false detections and sensitivity shifts can occur. Drift compensation (see Figure 7-1) is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect. The rate of adjustment must be performed slowly, otherwise legitimate detections could be ignored. The parameters can be configured in increments of 0.16s. Figure 7-1. Thresholds and Drift Compensation Reference Hysteresis Threshold Signal Output The device drift compensates using a slew-rate limited change to the reference level; the threshold and hysteresis values are slaved to this reference. When a finger is sensed, the signal falls since the human body acts to absorb charge from the cross-coupling between X and Y lines. An isolated, untouched foreign object (a coin, or a water film) will cause the signal to rise very slightly due to an enhancement of coupling. This is contrary to the way most capacitive sensors operate. Once a finger is sensed, the drift compensation mechanism ceases since the signal is legitimately detecting an object. Drift compensation only works when the signal in question has not crossed the negative threshold level. The drift compensation mechanism can be asymmetric; the drift-compensation can be made to occur in one direction faster than it does in the other simply by changing the NDRIFT and PDRIFT Setup parameters. This is a global configuration. Specifically, drift compensation should be set to compensate faster for increasing signals than for decreasing signals. Decreasing signals should not be compensated quickly, since an approaching finger could be compensated for partially or entirely before even touching the touchpad (NDRIFT). 28 AT42QT2160 9502A-AT42-07/08 AT42QT2160 However, an obstruction over the sense pad, for which the sensor has already made full allowance, could suddenly be removed leaving the sensor with an artificially suppressed reference level and thus become insensitive to touch. In this latter case, the sensor should compensate for the object's removal by raising the reference level relatively quickly (PDRIFT). Drift compensation and the detection time-outs work together to provide for robust, adaptive sensing. The time-outs provide abrupt changes in reference calibration depending on the duration of the signal 'event'. If PDRIFT or NDRIFT is set to 0 then the drift compensation in the respective direction is disabled. Note: it is recommended that the drift compensation rate be more than four times the LP mode period. This is to prevent undersampling, which decreases the algorithm's efficiency. Default NDRIFT: 20 (3.2s/reference level) Default PDRIFT: 5 (0.8s/reference level) 7.14 Address 17: Detect Integrator Table 7-14. Address 17 Detect Integrator b7 0 b6 0 b5 0 b4 b3 b2 NDIL b1 b0 NDIL is used to provide signal filtering. To suppress false detections caused by spurious events like electrical noise, the device incorporates a 'detection integrator' or DI counter mechanism. A per-key counter is incremented each time the key has exceeded its threshold and stayed there for a number of acquisitions in succession, without going below the threshold level. When this counter reaches a preset limit the key is finally declared to be touched. If on any acquisition the signal is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. The QT2160 has a built in minimum of 1 DI counts in addition to the NDIL value. Therefore, if setting a NDIL value of 3, the actual number of consecutive acquisitions is 4. Available NDIL values are from 1 to 31. Default: 3 (4 DI value) 7.15 Address 18: Negative Recal Delay Table 7-15. Address 18 Negative Recal Delay b7 b6 b5 b4 NRD b3 b2 b1 b0 If an object unintentionally contacts a key resulting in a detection for a prolonged interval it is usually desirable to recalibrate the key in order to restore its function, perhaps after a time delay of some seconds. 29 9502A-AT42-07/08 The Negative Recal Delay timer monitors such detections; if a detection event exceeds the timer's setting, the key will be automatically recalibrated. After a recalibration has taken place, the affected key will once again function normally even if it is still being contacted by the foreign object. This feature is set globally. NRD can be disabled by setting it to zero (infinite timeout) in which case the key will never autorecalibrate during a continuous detection (but the host could still command it). NRD is set globally, which can range in value from 1...255. NRD above 0 is expressed in 0.16s increments. Default: 255 (40.8s) 7.16 Address 19: Drift Hold Time/Awake Timeout Table 7-16. Address 19 Drift Hold Time/Awake Timeout b7 b6 b5 b4 b3 b2 b1 b0 DHT/AWAKE The DHT/AWAKE value is used for Drift Hold Time and Awake Timeout parameters. Drift Hold Time (DHT) This is used to restrict drift on all keys while one or more keys are activated. DHT defines the length of time the drift is halted after a key detection. This feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit any touch detection. Awake Timeout (AWAKE) After each matrix scan, the part will automatically go to sleep whenever possible to conserve power, unless there has been a key state change. The AWAKE timeout feature determines how long the device will remain in the minimum LP mode from the last key state change. Subsequent key state changes reinitialize the AWAKE interval. Once the part has been awakened by a change, the key response time will be fast for as long as the keyboard remains in use. Once key activity lapses for a period longer than the AWAKE timeout, the part will return to the assigned LP mode. DHT/AWAKE can be configured to a value of between 0.32s and 40.8s, in increments of 0.16s. Values of 0 and 1 are invalid and should not be used. Note: It is recommended having a DHT/AWAKE of at least two seconds to prevent unintended key sensitivity drifts and the slider being unresponsive in longer LP modes. DHT/AWAKE Default: 25 (4s) 30 AT42QT2160 9502A-AT42-07/08 AT42QT2160 7.17 Address 20: Slider Control Table 7-17. Address 20 Slider Control b7 b6 HYST b5 b4 b3 b2 b1 b0 NUM_KEYS HSYT: Set the hysteresis value for the slider's reported position. Hysteresis is the number of positions the user has to move back, before the new touch position is reported when the direction of scrolling is changed and during first scroll after touch down. At lower resolutions, where skipping of reported positions will be noticed, hysteresis can be set to 0 (1 position). At higher resolutions (6...8 bits), it would be recommended to have a hysteresis of at least 2 positions or more. HYST can range from 0 (1 position) to 15 (16 positions). The hysteresis is carried out at 8 bits resolution internally and scaled to the desired resolution; therefore at resolutions lower than 8 bits, there might be a difference of 1 reported position from the HYST setting, depending on where the touch down is. Note: it is not valid to have a hysteresis value more than the available positions in a resolution. For example, do not have a HYST of 5 positions with a resolution of 2 bits (4 positions). NUM_KEYS: Set the number of keys to be used in the slider. For proper slider operation, valid values are between 2 and 8. Setting a value of 0, will disable the slider. HYST Default: 0 (1 position), NUM_KEYS Default: 5 (5 keys) 7.18 Address 21: Slider Options Table 7-18. Address 21 Slider Options b7 0 b6 0 b5 0 b4 0 b3 0 b2 b1 RESOLUTION b0 RESOLUTION: Resolution of reported position of touch on the slider. Valid values are between 0 (8 bits) to 6 (2 bits). The keys used for the slider starts at X0 and is on the Y0 line. Table 7-19. Value 0 1 2 3 Resolution Resolution 8 bits (0-255) 7 bits (0-127) 6 bits (0-63) 5 bits (0-31) Value 4 5 6 Resolution 4 bits (0-15) 3 bits (0-7) 2 bits (0-3) Note: For better stability of the reported position at higher resolutions, increase the number of keys used to construct the slider, reduce the front panel thickness, reduce the loading on the slider keys or increase the burst length to gain more signal. Default: 4 (4 bits) 31 9502A-AT42-07/08 7.19 Address 22...37: Key Control Table 7-20. Address 22...37 Key Control b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 b0 AKS GROUP AKS GROUP: these bits configure which AKS group a key is within (0 - AKS disabled, 1, 2 or 3). Keys in the same group cannot both be in detect at the same time, unless they both form part of the slider (see Section 4.9.2 on page 10). Default: 0 (AKS disabled) 7.20 Address 38...53: Negative Threshold Table 7-21. Address 38...53 Negative Threshold b7 b6 b5 b4 b3 b2 b1 b0 THRESHOLD The negative threshold value is established relative to a key's signal reference value. The threshold is used to determine key touch when crossed by a negative-going signal swing after having been filtered by the detection integrator. Larger absolute values of threshold desensitize keys since the signal must travel farther in order to cross the threshold level. Conversely, lower thresholds make keys more sensitive. As Cx and Cs drift, the reference point drift-compensates for these changes at a user-settable rate; the threshold level is recomputed whenever the reference point moves, and thus it also is drift compensated. The amount of NTHR required depends on the amount of signal swing that occurs when a key is touched. Thicker panels or smaller key geometries reduce "key gain", i.e. signal swing from touch, thus requiring smaller NTHR values to detect touch. Negative hysteresis: this is fixed at two less than the negative threshold value and cannot be altered. It is implemented to stop keys from dithering in and out of detect. NTHR Typical values:7 to 12 NTHR Default value: 10 (10 counts of threshold) 7.21 Address 54...69: Burst Length Table 7-22. Address 54...69 Burst Length b7 b6 b5 b4 b3 b2 b1 b0 BURST LENGTH The QT2160 uses a fixed number of pulses which are executed in burst mode. This number is set in groups of four. Therefore, the value send to the QT2160 is multiplied by four to get the actual number of burst pulses. 32 AT42QT2160 9502A-AT42-07/08 AT42QT2160 The burst length is the number of times the charge-transfer (QT) process is performed on a given key. Each QT process is simply the pulsing of an X line once, with a corresponding Y line enabled to capture the resulting charge passed through the key's capacitance Cx. Increasing burst length directly affects key sensitivity. This occurs because the accumulation of charge in the charge integrator is directly linked to the burst length. The burst length of each key can be set individually, allowing for direct digital control over the signal gains of each key individually. Apparent touch sensitivity is also controlled by the Negative Threshold level (NTHR). Burst length and NTHR interact; normally burst lengths should be kept as short as possible to reduce scan time and limit RF emissions, but NTHR should be kept above 6 to reduce false detections due to external noise. The detection integrator mechanism also helps to prevent false detections. Note: setting a burst length of zero for a specific key, disables that key. Typical values: 8 to 32 (32 to 128 burst pulses) Default: 4 (16 burst pulses) 7.22 Address 70...71: GPIO/GPO Drive Table 7-23. Address 70 71 GPIO/GPO Drive b7 X7 0 b6 X6 0 b5 X5 0 b4 X4 GPIO3 b3 X3 GPIO2 b2 X2 GPIO1 b1 X1 0 b0 X0 0 If the GPIOs are set to outputs, the drive for the individual GPIO is set according to the corresponding bit in GPIO Drive bytes. Setting the bit to 1 will drive the corresponding GPIO pin to Vdd, while setting it to 0, will drive the corresponding GPIO pin to ground. Enabling PWM on a GPIO pin will override the drive on the pin. Shared X line GPOs will be only driven when not doing any measurements. During measurements, burst pulses will be driven from the X lines, make sure that the driven device will not be affected. Default: 0 (All driven low) 7.23 Address 73: GPIO Direction Table 7-24. Address 73 GPIO Direction b7 0 b6 0 b5 0 b4 GPIO3 b3 GPIO2 b2 GPIO1 b1 0 b0 0 Sets the direction of the GPIOs: 1 = driven outputs, 0 = floating inputs. If set as inputs, the GPIO will only be read every 16ms (fixed cycle time). 33 9502A-AT42-07/08 Shared X line GPOs are always outputs. By default, the dedicated GPIOs are set as inputs. Make sure to drive (set to outputs) these GPIOs if not used, as floating pins may consume unnecessary current. Default: 0 (All inputs) 7.24 Address 74...75: GPIO/GPO PWM Table 7-25. Address 74 75 GPIO/GPO PWM b7 X7 0 b6 X6 0 b5 X5 0 b4 X4 GPIO3 b3 X3 GPIO2 b2 X2 GPIO1 b1 X1 0 b0 X0 0 Setting the corresponding GPIO PWM bit to 1 will enable PWM on the respective pin. The pin will be driven according to the duty cycle specified in PWM Level (address 76). PWM will only be enabled on GPIOs that have their GPIO direction set to 1 (output). Shared X line GPOs will only be driven when not doing any measurements. During measurements, burst pulses will be driven from the X lines, making sure that the driven device will not be affected. All PWM enabled GPIOs/GPOs will only be switched when not doing any measurements. Therefore, the PWM duty cycle's accuracy will depend on the burst lengths of keys, as the longer the burst length, the longer the periods of no PWM switching. Default: 0 (PWM disabled) 7.25 Address 76: PWM Level Table 7-26. Address 76 PWM Level b7 b6 b5 b4 b3 b2 b1 b0 DUTY_CYC This sets the Duty Cycle of the PWM enabled pins. Valid values are between 0 to 255. A value of 0...10 will be 100 percent duty cycle (always on), and a value of 250...255 will be 0 percent duty cycle (always off). Default: 0 (100 percent duty cycle) 34 AT42QT2160 9502A-AT42-07/08 AT42QT2160 7.26 Address 77: GPIO Wake Table 7-27. Address 77 GPIO Wake b7 0 b6 0 b5 0 b4 GPIO3 b3 GPIO2 b2 GPIO1 b1 0 b0 0 If the corresponding bit is set to 1, dedicated GPIO pins set to inputs will still be read during SLEEP mode (no capacitive sensing carried out). When a change in the state of the inputs is detected, the CHANGE line will be triggered and the QT2160 will go back to SLEEP. Default: 0 (Wake disabled) 7.27 Address 78...79: Common Change Keys Table 7-28. Address 78 79 Common Change Keys b7 k7 k15 b6 k6 k14 b5 k5 k13 b4 k4 k12 b3 k3 k11 b2 k2 k10 b1 k1 k9 b0 k0 k8 k0...k15: represents the respective keys. If set to 1, the respective key is included in the common change comparisons. Note: if no keys are included in the Common Change group, the CC bit is set to 1. Default: 0 (not included) 7.28 Address 100...163: Signals and References Addresses 100...131 allow signal data to be read for each key. There are two bytes of data for each key. These are the key's 16-bit signal which is accessed as two 8-bit bytes, stored LSB first. Addresses 132...163 allow reference data to be read for each key. There are two bytes of data for each key. These are the key's 16-bit reference which is accessed as two 8-bit bytes, stored LSB first. There are a total of 16 keys and 4 bytes of data per key, yielding a total of 64 addresses. These addresses are read-only. Table 7-29. Address 100 101 102 103 104...131 Signal and References Key # 0 0 1 1 2...15 Use Signal LSB Signal MSB Signal LSB Signal MSB Address 132 133 134 135 136...163 Key # 0 0 1 1 2...15 Use Reference LSB Reference MSB Reference LSB Reference MSB 35 9502A-AT42-07/08 8. Setups Block Setups data is sent from the host to the QT2160 using the I2C-compatible interface. The setups block is memory mapped onto this interface. Thus each setup can be accessed by reading/writing the appropriate address. Setups can be accessed individually or as a block. Table 8-1. Address Setups Table Bytes Parameter Symbol Valid Range Bits Key Scope Default Value Description 0: SLEEP mode (no capacitive sensing) 1- 255: Low Power mode, increments in steps of 16ms Range is 1...63 burst repetitions Range is in 0.16s increments, 1 = 0.16s/reference level Range is in 0.16s increments, 1 = 0.16s/reference level Normal DI limit: take the operand and add 2 to get the value Range is in 0.16s increments; 0 = infinite; default = 40.8s Range is {infinite, 0.16...40.8s} Range in 0.2s increments; default = 4s 0...8: hysteresis for slider's reported position 0: disables slider mode NUM_KEYS 0, 2...8 4 Slider 5 (5 keys) 2...8: number of keys in slider Slider Keys start at X0 and are on Y0 Resolution of reported slider touch position 8 bits (0) to 2 bits (6) 0...3 1...255 0...255 3 8 8 1 1 1 0 (AKS off) 10 4 (16 pulses) 0: Key disabled 1...255: Burst length = BL x 4 0: AKS disabled 1...3: AKS groups 32 32 32 31 Page 12 1 LP Mode LP_MODE 0 - 255 8 16 1 27 13 15 1 1 Burst Repetition Neg Drift Comp BREP NDRIFT 1...63 0...127 6 7 16 16 1 20 27 28 16 1 Pos Drift Comp PDRIFT 0...127 7 16 5 28 17 1 Normal DI Limit NDIL 1...31 5 16 3 29 18 1 Neg recal delay NRD 0...255 8 16 255 (40.8s) 29 19 1 Drift Hold Time/Awake Timeout DHT/AWAKE 2...255 8 16 25 (4s) 30 HYST 20 1 Slider Control 0...15 4 Slider 0 (1 position) 21 1 Slider Options RESOLUTIO N 0...6 3 Slider 25 (4s) 31 22...37 38...53 54...69 16 16 16 Key Control Neg threshold Burst Length KEY_CONT NTHR BL 36 AT42QT2160 9502A-AT42-07/08 AT42QT2160 Table 8-1. Address Setups Table (continued) Bytes Parameter Symbol X7 X6 X5 X4 Valid Range 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 - Bits 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Key Scope - Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Page 70 1 GPO Drive 1 X3 X2 X1 X0 GPIO3 0: GPO driven low 1: GPO driven high 33 If GPIO set to output, 0: GPIO driven low 33 1: GPIO driven high 71 1 GPIO Drive 2 GPIO2 GPIO1 GPIO3 73 1 GPIO Direction GPIO2 GPIO1 - 0: GPIO is floating input 1: GPIO is push-pull output 33 37 9502A-AT42-07/08 Table 8-1. Address Setups Table (continued) Bytes Parameter Symbol X7 X6 X5 X4 Valid Range 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 0...1 - Bits 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Key Scope - Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Page 74 1 GPO PWM 1 X3 X2 X1 X0 GPIO3 0: PWM disabled 1: PWM enabled 34 If GPIO set to output, 0: PWM disabled 34 1: PWM enabled 75 1 GPIO PWM 2 GPIO2 GPIO1 - If PWM enabled, 0...10: 100% duty cycle (always ON) 11...249: varying duty cycles 250...255: 0% duty cycle (always OFF) GPIO3 77 1 GPIO Wake GPIO2 GPIO1 78...79 2 Common Change Keys k0...k15 0...1 0...1 0...1 1 1 1 1 16 16 0 0 0 0 0 35 0...1 1 1 1 1 0 0 0 0 If GPIO set to output, 0: GPIO not read in SLEEP 1: GPIO read in SLEEP 35 76 1 PWM Level DUTY_CYC 0...255 8 GPIOs 0 34 38 AT42QT2160 9502A-AT42-07/08 AT42QT2160 9. Getting Started With the QT2160 9.1 Using the I2C-compatible Bus The QT2160 is an address-mapped part. All commands and data transfers consist of reads from, and writes to, memory locations. 9.2 Establishing Contact To establish that the device is present and running, write a zero to it (see Section 9.3). Now read a single byte (see Section 9.4). This byte should be the ID of the device (0x11). If this is the case the device is present and running. 9.3 Writing to the Device A write cycle to the device consists of a start condition followed by the I2C-compatible address of the device (see Section 6.1). The next byte is the address of the location into which the writing will start. This address is then stored as the address pointer. Subsequent bytes in a multibyte transfer will be written to the location of the address pointer, location of the address pointer +1, location of the address pointer +2 etc. This ends with the stop condition on the I2C-compatible bus. A new write cycle will involve sending another address pointer. It is possible to stop the write after the address pointer is sent if no data is required to be written to the device. This is done when setting the address pointer for reading data. 9.4 Reading From the Device A read cycle consists of a start condition followed by the I2C-compatible address of the device (see Section 6.1). Bytes can then be read starting at the location pointed to by the address pointer set by the last write operation. The address is internally incremented for each byte read during a multibyte read. The stop condition at the end of the transfer causes the internal address pointer to revert to the value written during the last write operation. This means that if a set of data bytes needs to be read many times (such as the status bytes) then it is not necessary to keep sending an address pointer. It can be set to the first location and multibyte reads will always then start there. 9.5 Keys The default setting of the QT2160 is for 16 keys with AKS disabled. This will be the default setting when the device first powers up. A coin placed over any key can be used to pick up the burst signal to see the activity on the keys as explained in Section 3 of the application note "Secrets of a Successful Touch Sensor Design" which can be downloaded from the Quantum area of the Atmel website. The CHANGE line will go low indicating there is new data to be read. Reading the status bytes (address 2...6) will cause the CHANGE line to go inactive, as the data has been read. If a key is now touched, the CHANGE line will go active again, indicating that there is new data again. The CHANGE line will remain active until the status location containing the status for that key is read. If the CHANGE line does not go low then it is likely the sensitivity of the key is not high enough. The burst length should be increased to increase the sensitivity. 39 9502A-AT42-07/08 A change in burst length should be followed by a calibration command (set the calibration byte to a nonzero value) to ensure reliable operation. It is also possible to adjust the sensitivity using the negative threshold for that key. Note that thresholds below 6 counts may cause sensitivity to noise and thresholds above 12 counts will require longer burst lengths than strictly necessary. All unused keys should be switched off by setting their burst lengths to zero. This will reduce the power requirements of the device. 9.6 Slider A group of keys on the Y0 line can be configured as a slider. These have to be placed in numerical order starting with X0 and with no missing keys in the sequence. The keys should be 5-7mm wide along the length of the slider for good linearity. The number of keys needed in a slider will simply be the number of the size required to form the desired slider length. The slider can now be enabled by setting the NUM_KEYS bits in Slider Control byte to the number of keys which are used in the slider. This can be from 2 to 8 keys. For example, to enable a slider of five keys, set NUM_KEYS to five. Note that the higher the resolution, the more keys will be required to get a stable response out of the slider. As a general rule, the number of keys must be at least the number of bits, e.g. at least 4 keys for a 4 bit slider. Now the slider is enabled, touching it will result in a slider position being reported in the Slider Touch Position byte. Note that the keys forming the slider will still cause key detections and will still report their status in the key status registers. If the slider position is noisy, try reducing the panel thickness or increasing the sensitivities of the keys forming the slider, to get more signal for positional calculations. Increasing the hysteresis (Section 4.2 on page 5) will also help. Keys within the same slider are normally in the same AKS group and have the same burst length and threshold. 9.7 Adjacent Key Suppression (AKS) Technology Adjacent Key Suppression (AKS) technology is a patented method to detect which key is pressed, when keys are located close together. A touch in a group of AKS keys will only be indicated on the key with the largest signal. This is assumed to be the intended key. Once a key in an AKS group is in detect, there can be no further detections on keys in that group until the key is released. By default, the AKS technique is disabled on all keys; therefore, the keys can detect, regardless of the state of any other keys. The AKS technology works slightly differently when keys are in a slider which act like a single AKS object. Any number of keys can go into detect with a slider but if any keys within one of these objects are in detect then the AKS technology will lock out anything else in the same AKS group. Similarly, a key in the same AKS group as the slider can lock out the slider as a whole object. Note: for normal operation all keys in the slider should be placed in the same AKS group. 40 AT42QT2160 9502A-AT42-07/08 AT42QT2160 9.8 GPIOs By default, the dedicated GPIOs (GPIO1...GPIO3) are set as inputs. Make sure to drive (set to outputs) these GPIOs if not used, as floating pins may consume unnecessary current. By default, shared GPOs are push-pull outputs driven low when not measuring. Table 9-1 shows a summary of the GPIO options, and the precedence of each setting. GPIO Direction 0 GPIO PWM X GPIO Drive X Wake Dedicated GPIO Function Input - read only in LP mode so CHANGE event possible only in LP mode Input - read in LP and Sleep modes so CHANGE event possible in both modes Output - Gnd Output - Vdd Output - PWM Shared GPO Function X Always output 0 1 1 1 X 0 0 1 X 0 1 X 1 X X X Always output Output - Gnd Output - Vdd Output - PWM 9.9 Typical Initialization and Usage Figure 9-1 on page 42 shows a typical example of communicating with the QT2160. 1. After a reset/power-up, wait for CHANGE to go low, indicating the QT2160 has initialized and is ready to communicate. 2. Send all the setup parameters that need to be changed from the startup default values. Drive all unused GPIOs to outputs, to prevent unnecessary increase in current consumption. 3. After setting up the QT2160, send a Calibrate command. 4. Read all status bytes once (address 2 to 6), to return the CHANGE line to an inactive state. 5. If CHANGE line goes low, perform a read of the required status byte. All the status bytes that have changed need to be read, to ensure that the CHANGE line goes inactive again. 6. Process the received byte accordingly. 7. Check the reset bit in the general status byte (address 2). If it is a 1, go to step 2 to resend all the setup parameters, as a reset has occurred. If it is a 0, proceed to the next step. 8. Repeat steps 5, 6 and 7. Steps 5 and 6 are the continuous normal operating loop sequence after initialization. 41 9502A-AT42-07/08 Figure 9-1. Typical Initialization and Usage Reset/Power Up CHANGE pin active (low)? No Yes Send setup parameters to set up QT2160 Send Calibrate command Read all status bytes (Address 2...6) to restore CHANGE pin to inactive (high) CHANGE pin active (low)? No Yes Read required Status bytes and other status bytes that changed, to restore CHANGE pin to inactive (high). Host processes received status bytes Yes `Reset occurred' bit = 1? No 42 AT42QT2160 9502A-AT42-07/08 AT42QT2160 10. Specifications 10.1 Vdd Max continuous pin current, any control or drive pin Short circuit duration to ground, any pin Short circuit duration to Vdd, any pin Voltage forced onto any pin Absolute Maximum Specifications -0.5 to +6V 10 mA infinite infinite -0.6V to (Vdd + 0.6) Volts CAUTION: Stresses beyond those listed under "Absolute Maximum Specifications" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification conditions for extended periods may affect device reliability. 10.2 Recommended Operating Conditions -40oC to +85oC -55oC to +125oC +1.8V to 5.5V 25 mV 50 mV 2 to 20 pF Operating temp Storage temp Vdd Supply ripple+noise* (<1MHz) Supply ripple+noise* (>1MHz) Cx transverse load capacitance per key Note: *Applicable to QT2160 on a typical setup, with Burst Repetition (BREP) = 2. The effects of supply ripple and noise on performance is more prominent the nearer it is to the burst center frequency. 43 9502A-AT42-07/08 10.3 DC Specifications Vdd = 5.0V, Cs = 4.7nF, Rs = 1M, Ta = recommended range, unless otherwise noted Parameter Description Average supply current, running (LP16ms) Min Typ 476 955 1127 <1.5 <2 <3 0.2Vdd 0.6Vdd 0.2 4.2 1 10 60 Max Units Vdd = 1.8V Vdd = 3.3V Vdd = 5.0V Vdd = 1.8V Vdd = 3.3V Vdd = 5.0V 1.8V A Idds Average supply current, sleeping (SLEEP) Low input logic level High input logic level Low output voltage High output voltage Input leakage current Acquisition resolution Internal RST pull-up resistor A Vil Vhl Vol Voh Iil Ar Rrst V V V V A bits k 10.4 Timing Specifications Description Min Typ Max Units Notes BL = 4 (4x4 = 16 actual pulses) BL = 8 (8x4 = 32 actual pulses) BL = 12 (12x4 = 48 actual pulses) BL = 16 (16x4 = 64 actual pulses) Parameter TBS Burst duration 40 80 120 160 s Fc Fm TDW TPW Burst center frequency Burst modulation, percentage Dwell time Pulse width 250 400 8 500 1000 kHz % ns ns 44 AT42QT2160 9502A-AT42-07/08 AT42QT2160 10.5 Power Consumption Average Current Consumption Test condition: 16 keys enabled, BL = 16 (4 x 16 = 64 actual pulses), BREP = 1 Idd (A) at Vdd = LP Mode 1.8V SLEEP LP 16 ms LP 32 ms LP 64 ms LP 128 ms LP 256 ms LP 512 ms LP 1024 ms <1.5 476 311 229 188 167 157 152 3.3V <2 955 609 436 350 306 285 274 5V <3 1,127 770 592 502 458 435 424 Table 10-1. 45 9502A-AT42-07/08 10.6 Mechanical Dimensions Figure 10-1. Mechanical Dimensions D C 1 2 3 Pin 1 ID E SIDE VIEW TOP VIEW A A1 y K D2 1 0.45 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A MIN 0.80 0.00 0.17 NOM 0.90 0.02 0.22 0.20 REF 3.95 2.35 3.95 2.35 4.00 2.40 4.00 2.40 0.45 0.35 0.00 0.20 0.40 - - 0.45 0.08 - 4.05 2.45 4.05 2.45 MAX 1.00 0.05 0.27 NOTE R 0.20 2 3 E2 b A1 b C D L e BOTTOM VIEW D2 E E2 e L y Note: The terminal #1 ID is a Laser-marked Feature. K 9/7/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 28M1 REV. A R 46 AT42QT2160 9502A-AT42-07/08 AT42QT2160 10.7 Marking Either part marking can be supplied. 28 Pin 1 ID 1 Chip Assembly Lotcode (for traceability) AT42 QT2160 -MMU LTCODE 28 Part number; AT42QT2160-MMU Pin 1 ID 1 Abbreviation of Part number; AT42QT2160 LTCODE Chip Assembly Lotcode (for traceability) 2160 AT Program week code number 1-52 where: A = 1, B = 2...Z = 26 then using the underscore A = 27...Z = 52 10.8 Part Number Part Number AT42QT2160-MMU Description 28-pin 4 x 4mm MLF RoHS compliant IC 10.9 Moisture Sensitivity Level (MSL) MSL Rating MSL3 Peak Body Temperature 260oC Specifications IPC/JEDEC J-STD-020C 47 9502A-AT42-07/08 10.10 Revision History Revision No. Revision A - July 2008 History * Initial Release 48 AT42QT2160 9502A-AT42-07/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Touch Technology Division 1 Mitchell Point Ensign Way Hamble Southampton Hampshire SO31 4RF UNITED KINDGOM Tel: (44) 023-8056-5600 Fax: (44) 023-8045-3939 Product Contact Web Site www.atmel.com Technical Support qprox.support@atmel.com Sales Contact qprox.sales@atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, and others are registered trademarks, QSlideTM, QMatrixTM, and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 9502A-AT42-07/08 |
Price & Availability of AT42QT2160
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |