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HD74HC299
8-bit Universal Shift/Storage Register (with 3-state outputs)
REJ03D0609-0200 (Previous ADE-205-488) Rev.2.00 Jan 31, 2006
Description
The HD74HC299 features multiplexed inputs/outputs to achieve full 8-bit data handling in a single 20-pin package. Due to the large output drive capability and 3-state feature, this device is ideally suited for interfacing with bus lines in a bus oriented system. Two function select inputs and two output control inputs are used to choose the mode of operation as listed in the function table. Synchronous parallel loading is accomplished by taking both function select lines S0 and S1 high. This places the 3-state outputs in a high impedance state, which permits data applied to the input/output lines to be clocked into the register. Reading out of the register can be done while the outputs are enabled in any mode. A direct overriding clear input is provided to clear the register whether the outputs are enabled or disabled.
Features
* * * * * * High Speed Operation High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC299FPEL HD74HC299RPEL Package Type SOP-20 pin (JEITA) SOP-20 pin (JEDEC) Package Code (Previous Code) PRSP0020DD-B (FP-20DAV) PRSP0020DC-A (FP-20DBV) Package Abbreviation FP RP Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (1,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.2.00 Jan 31, 2006 page 1 of 8
HD74HC299
Function Table
Inputs Mode Clear L L H H H H H H H Function Select S0 S1 X L L X L L X X L H L H H L H L H H Output Control Clock G1 G2 L L X L L X L L X L L L L L L L L L L L X X Serial SL X X X X X X H L X SR X X X X H L X X X A/QA L L QA0 QA0 H L QBn QBn a B/QB L L QB0 QB0 QAn QAn QCn QCn b Inputs/Outputs C/QC L L QC0 QC0 QBn QBn QDn QDn c D/QD L L QD0 QD0 QCn QCn QEn QEn d E/QE L L QE0 QE0 QDn QDn QFn QFn e F/QF L L QF0 QF0 QEn QEn QGn QGn f G/QG L L QG0 QG0 QFn QFn QHn QHn g H/QH L L QH0 QH0 QGn QGn H L h Outputs QA' L L QA0 QA0 H L QBn QBn a QH' L L QH0 QH0 QGn QGn H L h
Clear Hold Shift Right Shift Left Load
Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are loaded into the flipflop outputs are isolated from the input/output terminals. 2. QA0 to QH0; the level of QA through QH, respectively, before the indicated steady-state input conditions were established. transition of the clock. 3. QAn to QHn; the level of QA through QH, respectively, before the most-recent 4. ; When one or both output controls are high the eight input/output terminals are disabled to the highimpedance state, however, sequential operation or clearing of the register is not affected. 5. When clear is low, outputs of QA' and QH' are low, in spite of other inputs.
Pin Arrangement
S0 Output controls G1 G2 G/QC E/QE C/QC A/QA QA Clear 1 2
G S0 S1 SL G/QG E/QE C/QC A/QA QA Clear SR QH H/QH F/QF D/QD B/QB CK
20 VCC 19 S1 18 Shift left SL
3 4 5 6 7 8 9
17 QH 16 H/QH 15 F/QF 14 D/QD 13 B/QB 12 Clock 11 Shift right SR
GND 10 (Top view)
Rev.2.00 Jan 31, 2006 page 2 of 8
HD74HC299
Logic Diagram
Sift right serial-input S1 Sift left serial-input
S0
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
Clear Clock G1 G2
C C CLR
C C CLR
C C CLR
C C CLR
C C CLR
C C CLR
C C CLR
C C CLR
Q/A
A/QA
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG QH
H/QH
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 35 75 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Rev.2.00 Jan 31, 2006 page 3 of 8
HD74HC299
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 Ta = 25C Min Typ Max 1.5 -- -- 3.15 -- -- 4.2 -- -- -- -- 0.5 -- -- 1.35 -- -- 1.8 1.9 2.0 -- 4.4 4.5 -- 5.9 6.0 -- 4.18 -- -- 5.68 -- -- 4.18 -- -- 5.68 -- -- -- 0.0 0.1 -- 0.0 0.1 -- 0.0 0.1 -- -- 0.26 -- -- 0.26 -- -- 0.26 -- -- 0.26 -- -- 0.5 -- -- -- -- 0.1 4.0 Ta = -40 to+85C Unit Test Conditions Min Max 1.5 -- V 3.15 -- 4.2 -- -- 0.5 V -- 1.35 -- 1.8 1.9 -- V Vin = VIH or VIL IOH = -20 A 4.4 -- 5.9 -- 4.13 -- IOH = -4 mA QA' & QH' Outputs 5.63 -- IOH = -5.2 mA 4.13 -- IOH = -6 mA A/QA thru H/QH Outputs IOH = -7.8 mA 5.63 -- -- 0.1 V Vin = VIH or VIL IOL = 20 A -- 0.1 -- 0.1 -- 0.33 IOH = 4 mA QA' & QH' Outputs -- 0.33 IOH = 5.2 mA -- 0.33 IOH = 6 mA A/QA thru H/QH Outputs IOH = 7.8 mA -- 0.33 -- 5.0 A Vin = VIH or VIL, Vout = VCC or GND -- 1.0 A Vin = VCC or GND -- 40 A Vin = VCC or GND, Iout = 0 A
VIL
Output voltage
VOH
VOL
Off-state output current Input current Quiescent supply current
IOZ Iin ICC
Rev.2.00 Jan 31, 2006 page 4 of 8
HD74HC299
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 5 5 5 50 10 9 80 16 14 -- -- -- -- -- -- -- Ta = 25C Typ Max -- 5 -- 25 -- 29 -- 190 -- 38 -- 32 -- 220 -- 44 -- 37 -- 190 -- 38 -- 32 -- 220 -- 44 -- 37 -- 160 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 32 27 160 32 27 -- -- -- -- -- -- -- -- -- -- -- -- 60 12 10 75 15 13 10 Ta = -40 to +85C Unit Test Conditions Min Max -- 4 MHz -- 20 -- 23 -- 240 ns Clock to QA' or QH' -- 48 -- 41 -- 275 ns Clear to QA' or QH' -- 55 -- 47 -- 240 ns Clock to QA - QH -- 48 -- 41 -- 275 ns Clear to QA - QH -- 55 -- 47 -- 200 ns -- -- -- -- -- 125 25 21 5 5 5 65 13 11 100 20 17 -- -- -- -- -- -- -- 40 34 200 40 34 -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 95 19 16 10
tPLH tPHL tPHL
tPLH tPHL tPHL
Output enable time
tZH tZL tHZ tLZ tsu
Output disable time Setup time
ns
ns
Select
Hold time
th
ns
Select
Removal time
trem
ns
Clear
Pulse width
tw
ns
Output rise/fall time
tTLH tTHL
ns
A/QA thru H/QH outputs
ns
QA' & QH' outputs
Input capacitance
Cin
pF
Rev.2.00 Jan 31, 2006 page 5 of 8
HD74HC299
Test Circuit
VCC G1 Input
See Function Table
VCC Output G G2 S1 S0 SR Clock SL Clear QH' CL = 50 pF QA' Output CL = 50 pF A/QA to H/QH Output 1 k CL = 50 pF TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ S1 OPEN GND VCC S1 OPEN GND VCC
Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
Note : 1. CL includes probe and jig capacitance.
Waveforms
* Waveform - 1
tf
90 % 50 % 10 %
tr
90 % 50 %
VCC 0V VCC
50 %
Clock
th t rem Clear
50 %
0V t su VCC SR or SL
50 % 50 %
0V t su VCC S0 or S1
50 % 50 %
0V tPLH, tPHL QA', QH' QA, QH
90 % 50 % 10 %
tPHL, tPLH
90 % 50 % 10 %
t PHL VOH
50 %
VOL
tTLH, tTHL
tTHL, tTLH
Note : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns
Rev.2.00 Jan 31, 2006 page 6 of 8
HD74HC299
* Waveform - 2
tr
90 % 50 % 10 % 90 % 10 %
tf VCC 0V
Clock tr S0, S1
10 %
tf
90 % 50 % 90 % 50 % 10 %
VCC
50 % 50 %
0V VIH
t su
th
A to H
50 %
50 %
VIL
VOH QA to QH VOL A to H enabled A to H disabled A to H enabled QA to QH disabled A to H disabled QA to QH enabled
QA to QH disabled QA to QH enabled
Note : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns
* Waveform - 3
90 % 50 %
tf
tr 90 % 50 % 10 % t ZL 10 % t LZ 50 % t ZH t HZ 90 % VCC 0V VOH
G1, G2
Waveform - A
10 % VOL VOH VOL
Waveform - B
50 %
Notes : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns 2. Waveform- A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform- B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement.
Rev.2.00 Jan 31, 2006 page 7 of 8
HD74HC299
Package Dimensions
JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B Previous Code FP-20DAV MASS[Typ.] 0.31g
*1
D 11
F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
20
bp
E
HE
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 12.60 5.50 Max 13.0
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2 A1 0.00
10 bp x M L1
0.10
0.20 2.20
A bp b1 c c
1
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 7.50 7.80 1.27
8 8.00
y
e x y
A1
L
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
JEITA Package Code P-SOP20-7.5x12.8-1.27
RENESAS Code PRSP0020DC-A
Previous Code FP-20DBV
MASS[Typ.] 0.52g
*1
D
F 11 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET.
20
bp
*2
HE
E
Index mark
Reference Symbol
c
Dimension in Millimeters Min Nom 12.80 7.50 Max 13.2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
10 bp x M L1
A1 A bp b1 c c
1
0.10
0.20
0.30 2.65
0.34
0.40
0.46
0.20
0.25
0.30
A
HE
0 10.00 10.40 1.27
8 10.65
A1
y L
e x y Z
0.12 0.15 0.935 0.40
1
Detail F
L L
0.70 1.45
1.27
Rev.2.00 Jan 31, 2006 page 8 of 8
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