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ST
Sitronix
1. INTRODUCTION
2
ST7545T
66 x 102 Dot Matrix LCD Controller/Driver
The ST7545T is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102 segments and 65 commons with 1 ICON driver circuits. This chip is connected directly to a microprocessor, accepts 8-bit parallel interface3-line or 4-line serial peripheral interface (SPI)I C interface, display data can stores in an on-chip display data RAM of 66 x 102 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Single-chip LCD controller & driver Driver Output Circuits 102-segment x 65-common + 1 ICON On-chip Display Data ram Capacity: 66X102=6,732 bits Generation of intermediate LCD bias voltages Oscillator requires no external components (external clock also supported) Voltage Booster (x4, x5) Voltage regulator(temperature gradient -0.11%/C) Voltage follower On-chip electronic contrast control function (128 steps) External RESB (reset) pin Supply voltage range VDD1 -VSS : 1.7 to 3.3V VDD2 -VSS : 2.4 to 3.3V VOUTIN -VSS : 13.5V (max)
Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series or 8080-series 4-line SPI (serial peripheral interface) available (only write operation) 3-line SPI (serial peripheral interface) available I C (Inter-Integrated Circuit) Interface
2
On-chip Low Power Analog Circuit Generation of LCD supply voltage (external VOUT voltage supply is supported)
Temperature range: -30 to +85 degree
ST7545T-G2
6800 , 8080 , 4-Line , 3-Line interface (without I2C interface) I2C interface
ST7545Ti-G2
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3. ST7545T-G2 Pad Arrangement (COG)
Chip Size: 8,200 um x 1020 um Bump Pitch: PAD NO 1 ~ 11 , 12 ~ 147 , 207 ~ 230 : 55 um ; PAD NO 148 ~ 216 : max : 175 um , min : 72 um Bump Size: PAD NO 188 ~ 193 : 45 (x)um x 60 (y) um ; ; ; ; PAD NO 11 ~ 12 : 56 um ;
PAD NO 148 ~ 187 , 194 ~ 206 : 55 (x) um x 60 (y) um PAD NO 124 ~ 137 , 217 ~ 230: 96 (x) um x 37 (y) um PAD NO 1 ~ 123 , 138 ~ 147 , 207 ~ 216 : Bump Height: 17 um Chip Thickness: 480 um
37 (x) um x 96 (y) um
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Pad Center Coordinates (TMY=0)
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN Name COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] COM[32] Reserved SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] X 3677 3622 3567 3512 3457 3402 3347 3292 3237 3182 3127 3071 3016 2961 2906 2851 2796 2741 2686 2631 2576 2521 2466 2411 2356 2301 2246 2191 2136 2081 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 PAD NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN Name SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] X 2026 1971 1916 1861 1806 1751 1696 1641 1586 1531 1476 1421 1366 1311 1256 1201 1146 1091 1036 981 926 871 816 761 706 651 596 541 486 431 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371
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PAD NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PIN Name SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] X 376 321 266 211 156 101 46 -9 -64 -119 -174 -229 -284 -339 -394 -449 -504 -559 -614 -669 -724 -779 -834 -889 -944 -999 -1054 -1109 -1164 -1219 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 PAD NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] COMS COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] X -1274 -1329 -1384 -1439 -1494 -1549 -1604 -1659 -1714 -1769 -1824 -1879 -1934 -1989 -2044 -2099 -2154 -2209 -2264 -2319 -2374 -2429 -2484 -2540 -2595 -2650 -2705 -2760 -2815 -2870 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371
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PAD NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PIN Name COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] Reserved TMX TMY VDD1 X -2925 -2980 -3035 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3678 -3623 -3568 -3513 -3458 -3403 -3348 -3293 -3238 -3183 -2194 -2075 -2002 Y 371 371 371 352 297 242 187 132 77 22 -33 -88 -143 -198 -253 -308 -363 -371 -371 -371 -371 -371 -371 -371 -371 -371 -371 -389 -389 -389 PAD NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PIN Name VDD1 VDD1 VDD1 PS0 PS1 PS2 BR VSS T6 T7 CP T8 T9 VDD2 VDD2 VDD2 VDD2 RESB CSB /WR /RD A0 VDD1 D7 D6 D5 D4 D3 D2 D1 X -1929 -1856 -1783 -1710 -1591 -1518 -1399 -1326 -1253 -1134 -1061 -942 -869 -766 -693 -620 -547 -410 -291 -218 -99 -26 77 150 269 342 461 534 653 726 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389
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PAD NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 PIN Name D0 OSC VSS VSS VSS VSS VRS T0 T1 T2 T3 T4 T5 VSS VSS VSS VSS VOUTOUT VOUTOUT VOUTIN VOUTIN V0 V1 V2 V3 V4 COMS COM[64] COM[63] COM[62] X 845 918 1021 1094 1167 1240 1313 1385 1534 1609 1784 1859 2034 2108 2181 2254 2327 2415 2488 2561 2634 2793 2883 2956 3029 3102 3183 3238 3293 3348 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -371 -371 -371 -371 PAD NO. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 PIN Name COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] X 3403 3458 3513 3568 3623 3678 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 Y -371 -371 -371 -371 -371 -371 -363 -308 -253 -198 -143 -88 -33 22 77 132 187 242 297 352
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Pad Center Coordinates(TMY=1)
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN Name COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] Reserved Reserved SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] X 3677 3622 3567 3512 3457 3402 3347 3292 3237 3182 3127 3071 3016 2961 2906 2851 2796 2741 2686 2631 2576 2521 2466 2411 2356 2301 2246 2191 2136 2081 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 PAD NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN Name SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] X 2026 1971 1916 1861 1806 1751 1696 1641 1586 1531 1476 1421 1366 1311 1256 1201 1146 1091 1036 981 926 871 816 761 706 651 596 541 486 431 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371
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PAD NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PIN Name SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] X 376 321 266 211 156 101 46 -9 -64 -119 -174 -229 -284 -339 -394 -449 -504 -559 -614 -669 -724 -779 -834 -889 -944 -999 -1054 -1109 -1164 -1219 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 PAD NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] COMS COM[64] COM[63] COM[62] COM[61] COM[60] COM[59] X -1274 -1329 -1384 -1439 -1494 -1549 -1604 -1659 -1714 -1769 -1824 -1879 -1934 -1989 -2044 -2099 -2154 -2209 -2264 -2319 -2374 -2429 -2484 -2540 -2595 -2650 -2705 -2760 -2815 -2870 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371
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PAD NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PIN Name COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] COM[32] TMX TMY VDD1 X -2925 -2980 -3035 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3678 -3623 -3568 -3513 -3458 -3403 -3348 -3293 -3238 -3183 -2194 -2075 -2002 Y 371 371 371 352 297 242 187 132 77 22 -33 -88 -143 -198 -253 -308 -363 -371 -371 -371 -371 -371 -371 -371 -371 -371 -371 -389 -389 -389 PAD NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PIN Name VDD1 VDD1 VDD1 PS0 PS1 PS2 BR VSS T6 T7 CP T8 T9 VDD2 VDD2 VDD2 VDD2 RESB CSB /WR /RD A0 VDD1 D7 D6 D5 D4 D3 D2 D1 X -1929 -1856 -1783 -1710 -1591 -1518 -1399 -1326 -1253 -1134 -1061 -942 -869 -766 -693 -620 -547 -410 -291 -218 -99 -26 77 150 269 342 461 534 653 726 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389
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PAD NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 PIN Name D0 OSC VSS VSS VSS VSS VRS T0 T1 T2 T3 T4 T5 VSS VSS VSS VSS VOUTOUT VOUTOUT VOUTIN VOUTIN V0 V1 V2 V3 V4 COMS COM[0] COM[1] COM[2] X 845 918 1021 1094 1167 1240 1313 1385 1534 1609 1784 1859 2034 2108 2181 2254 2327 2415 2488 2561 2634 2793 2883 2956 3029 3102 3183 3238 3293 3348 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -371 -371 -371 -371 PAD NO. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 PIN Name COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] X 3403 3458 3513 3568 3623 3678 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 Y -371 -371 -371 -371 -371 -371 -363 -308 -253 -198 -143 -88 -33 22 77 132 187 242 297 352
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4. BLOCK DIAGRAM
/RD(E) A0 /CSB /RESB
Fig.1 block diagram
DB7 WR(R/W)
DB0 DB1 DB2 DB3 DB4 DB5 DB6
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5. PINNING DESCRIPTIONS
Pin Name
Lcd driver outputs LCD segment driver outputs This display data and the M signal control the output voltage of segment driver. Segment driver output voltage Display data M (Internal) Normal display Reverse display SEG0 to SEG101
I/O
Description
No. of Pins
O
H H H L L H L L Power down mode
V0 VSS V2 V3 VSS
V2 V3 V0 VSS VSS
102
COM0 to COM64
O
LCD common driver outputs This internal scanning data and M signal control the output voltage of common driver. Common driver output voltage Display data M(Internal) Normal display Reverse display H H VSS H L V0 L H V1 L L V4 Power down mode VSS Common output for the icons. The output signals of two pins are same. When not used, this pin should be left open. Microprocessor interface select input pin PS0 "L" "L" "L" "L" "H" PS1 "L" "L" "H" "H" "H" PS2 "L" "H" "L" "H" "H" State 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface 2 I C interface
65
COMS
O
2
MICROPROCESSOR INTERFACE
PS[2:0]
I
3
CSB
I
RESB
I
A0
I
Chip select input pins Data/instruction I/O is enabled only when CSB is " L ". When chip select is non-active, DB0 to DB7 is high impedance. This pin only be used in 8-bit parallel interface. When using serial interface , this pin must be fixed to "H" Reset input pin When RESB is " L ", initialization is executed. It determines whether the data bits are data or a command. A0=" H ": Indicates that D0 to D7 are display data. A0=" L ": Indicates that D0 to D7 are control data. This pin only be used in 8-bit parallel interface. When using serial interface , this pin must be fixed to "H"
1
1
1
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Read/Write execution control pin PS2 H /WR(R/W) I L 8080-series /WR MPU type 6800-series /WR(R/W) R/W Description Read/Write control input pin R/W=" H ": read R/W=" L": write Write enable clock input pin The data on D0 to D7 are latched at the rising edge of the /WR signal
1
When in the serial interface must fix to " H" Read/Write execution control pin (PS[0:1]=[L:H]) PS2 MPU Type /RD (E) Description Read/Write control input pin R/W=" H ": When E is " H ", D0 to D7 are in an output status. R/W=" L ": The data on D0 to D7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is " L ", D0 to D7 are in an output status.
/RD (E)
I
H
6800-series
E
1
L
8080-series
/RD
When in the serial interface must fix to " H" When using 8-bit parallel interface: 6800 / 8080 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When chip select is not active, D0 to D7 is high impedance. When using serial interface: 4-LINE / 3-LINE D7: serial input clock (SCLK) ; D6: serial input data (SDA) D5: command/data selection (A0) ; D4: chip select pin(CSB) D3,D2.D1.D0: must fix to " H" When using 3-line A0 must fix to "H" 2 When using I C interface D7: serial clock input (SCLK) D6: serial input data (SDA_IN) 2 D3, D2: (SDA_OUT) serial data acknowledge for the I C interface. By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully 2 I C interface compatible. Having the acknowledge output separated from the serial data line is advantageous in chip on glass (COG) applications. In COG application where the track resistance from the SDA_OUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It is possible that during the acknowledge cycle the ST7545T will not be able to create a valid logic 0 level. By splitting the SDA_IN input from the SDA_OUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDA_OUT pad to the system SDA line to guarantee a valid low level. D6, D3,D2 must be connected together (SDA) D4, D5: must fix to " H" D1, D0: Are slave address (SA0,SA1), must fix to "H" or "L" Chip select input pins "CSB" not used must fix to "H"
D7(SCLK) D6(SDA) D5(A0) D4(CSB) D3 to D0
I/O D7(SCLK) D6 (SDA_IN) D5(X) D4(X) D3 to D2 (SDA_OUT) D1 (SA1) D0 (SA0)
8
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LCD DRIVER SUPPLY When the on-chip oscillator is used, this input must be connected to VDD. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS the display is not clocked and may be left in a DC state. To avoid this, the chip should always be put into Power Down Mode before stopping the clock. Ground. 9 Digital Supply voltage. The 2 supply rails VDD1 and VDD2 could be connected together. If Digital Option pin is high, must be this level Analog Supply voltage. The 2 supply rails VDD1 and VDD2 could be connected together. This pad is the power source of the internal voltage regulator. If the internal voltage generator uses internal booster output, the V OUTIN & VOUTOUT must be connected together. If the internal voltage generator uses external booster, V OUTOUT has to be left open and the external supply voltage can be supplied through the VOUTIN pad. If the internal voltage booster is used, the VOUTIN & VOUTOUT must be connected together with one capacitor connected to VSS If an external supply is used this pin must be left open. This is a multi-level power supply for the liquid crystal. 5 VOUTIN V0 V1V2V3V4VSS Monitor Voltage Regulator reference voltage level, must be left open. 1
OSC
I
1
Power Supply Pins VSS Power Supply Power Supply Power Supply
VDD1
5
VDD2
4
VOUTIN
Power Supply
2
VOUTOUT
Power Supply Power Supply Power Supply
2
V0, V1, V2, V3, V4
VRS Configuration Pins
TMX
I
Mirror X: SEG bi-direction selection TMX connect to VSS : normal direction (SEG0aSEG101) TMX connect to VDD : reverse direction (SEG101aSEG0) Mirror Y: COM bi-direction selection TMY connect to VSS (TMY=0): normal direction TMY connect to VDD (TMY=1): reverse direction See Pad Center Coordinates at page 3~10.
1
TMY
I
1
CP BR Test Pin T0~T9 Reserved
I I
Set Booster stages. (VSS=4X;VDD=5X) Set LCD bias ratio. (VSS=1/7;VDD=1/9) After reset, the bias ratio will be the setting value.
1 1
T -
T0~T5 must floating T7.T8 .T9 must connect to VDD T6 must connect to VSS All Reserved pins must floating
10 2
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ST7545T I/O PIN ITO Resister Limitation PIN Name PS[2:0], OSC, CP, BR, T6~T9, TMX, TMY T0~T5, VRS, V1, V2, V3, V4 VDD1, VDD2, VSS, VOUTIN, VOUTOUT V0 A0, /WR, /RD, CSB, D0...D7 RESB ITO Resister No Limitation Floating <100 <500 <1K <10K
6. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The ST7545T can interface with an MPU when CSB is "L". When CSB is "H", these pins are set to any other combination, A0, /RD(E), and /WR(R/W) inputs are disabled and D0 to D7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface ST7545T has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS [0:2] pin as shown in table 1. Table 1. Parallel/Serial Interface Mode PS0 "L" "L" "L" "L" "H" PS1 "L" "L" "H" "H" "H" PS2 "L" "H" "L" "H" "H" State 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface 2 I C interface
Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 as shown in table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in table 3. Table 2. Microprocessor Selection for Parallel Interface PS2 CSB A0 /RD (E) /WR (R/W) DB0 to DB7 MPU bus H CSB A0 E R/W DB0 to DB7 6800-series L CSB A0 /RD /WR DB0 to DB7 8080-series Table 3. Parallel Data Transfer 8080-series Description /RD /WR (E) (R/W) L H Display data read out H L Display data write L H Register status read H L Writes to internal register (instruction)
PS0 L L
PS1 H H
Common A0 H H L L
6800-series E R/W (/RD) (/WR) H H H L H H H L
NOTE: When /RD (E) pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, /WR(R/W) as in case of 6800-series mode.
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Serial Interface Serial Mode 4-line SPI interface 3-line SPI interface I C interface
2
PS0 L L H
PS1 L L H
PS2 L H H
PS0=" L ", PS1=" L ", PS2=" L ": 4-line SPI interface When the ST7545T is active (CSB="L"), serial data (D1) and serial clock (D0) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select (A0) Pin, based on the setting of PS[2:0]. When the A0 pin is used , data is display data when A0 is high, and command data when A0 is low. When A0 is not used , the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data direction command to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are sending, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into D0 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string are handled as command data.
/CSB SDA SCLK A0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6
Fig. 2
4-line SPI Timing
PS0=" L ", PS1=" L ", PS2=" H ": 3-line SPI interface
/CSB SDA SCLK
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0
Fig. 3
3-line SPI Timing
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PS0="H", PS1="H", PS2="H": I C Interface The I C interface receives and executes the commands sent via the I C Interface. It also receives RAM data and sends it to 2 the RAM. The I C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCLK). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes on the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.4. START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.5. SYSTEM CONFIGURATION The system configuration is illustrated in Fig.6. * Transmitter: the device, which sends the data to the bus * Receiver: the device, which receives the data from the bus * Master: the device, which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices. ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during the time that master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after receiving each byte. A master receiver must also generate an acknowledge after receiving each byte which is clocked out by the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data from the transmitter and stop generating an acknowledge on the last byte which has been clocked out by the slave. In this moment, the transmitter must leave the data line HIGH and let the master to generate a STOP 2 condition. Acknowledgement on the I C Interface is illustrated in Fig.7.
2 2 2
SDA SCL
Data line stable; Data valid change of data allowed
Fig .4 Bit transfer
SDA SCL S
START condition
Fig .5 Definition of START and STOP conditions
P
STOP condition
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MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER (1) 0111100 SLAVE RECEIVER (2) 0111101 SLAVE RECEIVER (3) 0111110 SLAVE RECEIVER (4) 0111111
SDA SCL
Fig .6 System configuration
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER 1 2
not acknowledge acknowledge 8 9 clock pulse for acknowledge ment
2
S
START condition
Fig .7 Acknowledgement on the I C Interface
I C Interface protocol The ST7545T supports command, data write addressed slaves on the bus. 2 Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses (0111100,0111101, 0111110 and 0111111) are reserved for the ST7545T. The least significant bit of the slave address is set by connecting the input SA0 and SA1 to either logic 0 (or logic 1 (VDD1). 2 The I C Interface protocol is illustrated in Fig.8. The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address. 2 All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7545T device. If the A0 bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received 2 commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I C INTERFACE-bus master issues a STOP condition (P).If the R/W bit is set to logic 1 the chip will output data immediately after the slave address if the A0 bit, which was sent during the last write access, is set to logic 0. If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
2
2
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Fig .8 0 1
IIC Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow. This stream may only be terminated by s STOP or RE-START condition. Another control byte will follow the data byte unless a STOP or RE-START condition is received.
Co
Data Transfer The ST7545T uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 9. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 10. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signal A0 /WR D0 to D7 Internal signals /WR BUS HOLDER COLUMN ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
Fig.9 Write Timing
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MPU signal A0 /W R /RD D0 to D7 Internal signals /W R /RD BUS HOLDER COLUMN ADDRESS N N D(N) D(N) D(N+1) D(N+1) D(N+2) D(N+2) N Dummy D(N) D(N+1)
Fig.10 Read Timing
DISPLAY DATA RAM (DDRAM) The ST7545T contains a 66X102 bit static RAM that stores the display data. The Display Data RAM (DDRAM) stores the dot data for the LCD. The size is 66(8 pageX8 bit +1 pageX1 bit +1 pageX1 bit) X 102 bits. The mapping is directly corresponded to the X-address and column output number. It is 66-row by 102-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into: 8 pages (Page0~7) (COM[0..63]) use full data bits (D7~D0), 8th page (Page8) with single line (COM[64]) uses only one data bit (D0) and 9th page (Page9) with a single line of ICON (COMS) uses only one data bit (D0). Data is read from or written to the DDRAM directly through D0 to D7. The display data (D0 to D7) comes from the corresponded pins of microprocessor. The microprocessor can read from and write to the DDRAM through the I/O port. Since the LCD controller operates independently, data can be written into DDRAM at the same time as data being displayed without causing the LCD flicker. Page Address Circuit This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 9 is a special RAM area for the icons and display data D0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 10. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the MPU cannot access Line Address of icons.
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Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously.
ADDRESSING Data is downloaded in bytes into the RAM matrix of ST7545T. The display RAM has a matrix of 66 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101),Y 0 to 9 (1001) .Addresses outside these ranges are not allowed.In vertical addressing mode (V=1) the Y address increments after each byte. After the last Y address (Y = 8), Y wraps around to 0 and X increments to address the next column.In horizontal addressing mode (V=0) the X address increments after each byte. After the last X address(X = 101) X wraps around to 0 and Y increments to address the next row.After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)
Data structure
D7
MSB
D0
LSB MSB LSB 1 bit 0 X-address 101
0 1 2 3 4 5 6 7 8 9
RAM format, addressing
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Y-address
ST7545T
0 1 2 3 4 5 6 7 8 0
9 10 11 12 13 14 15 16 17
18 19 20 21 22 23 24 25 26 X-address
917 101
0 1 2 3 4 5 6 7 8 9
Sequence of writing data bytes into RAM with vertical addressing (V=1)
012 102103104 204205206 306307308 408409410 510511512 612613614 714715716 816817818 0 X-address
917 101
0 1 2 3 4 5 6 7 8 9
Sequence of writing data bytes into RAM with horizontal addressing (V=0)
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Y-address
Y-address
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Page Address Data D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D0 00 01 02 03 04 05 06 07 08 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H DO 5D 5E 5F 60 61 62 63 64 65 0 When the common output is normal COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 ICON (COMS) Regardless of the display start line address, 1/66duty => 65th line
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1 1
0 0
0 0
0 1
Page 8 Page 9
S100
S101
Display Data RAM Map (66 COM)
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LCD Out
S93
S94
S95
S96
S97
S98
S99
S0
S1
S2
S3
S4
S5
S6
S7
S8
DO
5D
5E
5F
65
64
63
62
61
60
08
07
06
05
04
03
02
01
00
Column address
1
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2006/01/20
ST7545T
Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input. LCD DRIVER CIRCUIT 66-channel common drivers and 102-channel segment drivers configure this driver circuit. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
M
VDD VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0
COM0
COM1
COM2
SEG0
SEG1
SEG 0 1 2 3 4
COM0 to SEG0
COM0 to SEG1
Typical LCD driver waveforms
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7. RESET CIRCUIT
Setting RESB to "L" or Reset instruction can initialize internal function. When RESB becomes "L", following procedure is occurred. Page address: 0 Column address: 0 Display control: Display blank Oscillator: OFF Power down mode (PD = 1) Horizontal addressing (V = 0) Normal instruction set (H = 0) Display blank (E = D = 0) Address counter X [6:0] = 0, Y [3:0] = 0 Bias system (BS [2:0] = BR setting) VOP is equal to 0; the HV generator is switched off (V OP[6:0] = 0) After power-on, RAM data are undefined While RESB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB0. After DB0 becomes "L", any instruction can be accepted. RESB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used.
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8. INSTRUCTION TABLE
WR (R/W)
COMMAND BYTE DESCRIPTION D7 D6 D5 D4 D3 D2 D1 D0
INSTRUCTION H=0 or 1 NOP Function set Write data
A0
0 0 1
0 0 0
0 0 D7
0 0 D6
0 1 D5
0 0 D4
0 0 D3
0 PD D2
0 V D1
0 H D0
No operation Power-down; entry mode; Write data to RAM
INSTRUCTION H=0 Display control Set Y address of RAM Set X address of RAM H=1 Reserved Bias system Reserved Set V0 (VOP) voltage
A0
WR (R/W)
COMMAND BYTE DESCRIPTION D7 D6 D5 D4 D3 D2 D1 D0
0 0 0
0 0 0
0 0 1
0 1 X6
0 0 X5
0 0 X4
1 Y3 X3
D Y2 X2
0 Y1 X1
E Y0 X0
Sets display configuration Sets Y address of RAM 0Y9 Sets X address of RAM 0X101
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 VOP6
0 0 X VOP5
0 1 X VOP4
0 0 X VOP3
0 BS2 X VOP2
1 BS1 X VOP1
X BS0 X
Do not use Sets bias system (BSx) Do not use(reserved for test)
VOP0 Set V0 (VOP) output voltage
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9. INSTRUCTION DESCRIPTION
H="0" or "1"
Function Set
A0 0 Flag
WR(R/W)
0
D7 0
D6 0
D5 1
D4 0
D3 0
D2 PD
D1 V
D0 H
PD
V
H
Description All LCD outputs are fixed at VSS (display off), internal power circuits are turned off, V OUT can be disconnected, oscillator is off (external clock possible), RAM contents not cleared; RAM data can be written. PD=0:chip is active PD=1:chip is in power down mode When V = 0, the horizontal addressing mode is selected. When V = 1, the vertical addressing mode is selected. When H = 0 the commands `display control', `set Y address' and `set X address' can be performed. When H = 1 the others can be executed. The commands `write data' and `function set' can be executed in both cases.
Write data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 1
WR(R/W)
D7
D6
D5
0
D4 D3 Write data
D2
D1
D0
H="0"
Display Control
This bits D and E selects the display mode. A0 0 Flag
WR(R/W)
0
D7 0
D6 0
D5 0
D4 0
D3 1
D2 D
D1 0
D0 E
D,E
Description D E The bits D and E select the display mode. 0 0 Display blank 1 0 Normal display 0 1 All display segments on 1 1 Inverse video mode
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Set Y address of RAM
Y [3:0] defines the Y address vector address of the display RAM. A0 D7 D6 D5 D4 D3 WR(R/W) 0 0 0 1 0 0 Y3 Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1 CONTENT Page0 (display RAM) Page1 (display RAM) Page2 (display RAM) Page3 (display RAM) Page4 (display RAM) Page5 (display RAM) Page6 (display RAM) Page7 (display RAM) Page8 (display RAM) Page9 (display RAM) D2 Y2 D1 Y1 D0 Y0
ALLOWED X-RANGE 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101
Set X address of RAM
The X address points to the columns. The range of X is 0...101. A0 D7 D6 D5 D4 WR(R/W) 0 0 1 X6 X5 X4 X6 0 0 0 0 : 1 1 1 1 X5 0 0 0 0 : 1 1 1 1 X4 0 0 0 0 : 0 0 0 0 X3 0 0 0 0 : 0 0 0 0 X2 0 0 0 0 : 0 0 1 1 X1 0 0 1 1 : 1 1 0 0 D3 X3 X0 0 1 0 1 : 0 1 0 1 D2 X2 D1 X1 D0 X0
Column address 0 1 2 3 : 98 99 100 101
H="1"
System Bias
Select LCD bias ratio of the voltage required for driving the LCD. A0 D7 D6 D5 D4 D3 WR(R/W) 0 0 0 0 0 1 0 BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 Bias 11 10 9 8 7 6 5 4 D2 BS2 D1 BS1 D0 BS0
Recommend Duty 1:100 1:81 1:65/1:68 1:49 1/40:1/36 1/24 1:18/1:16 1:10/1:9/1:8
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Set V0 (VOP) voltage: The operation voltage V0 (VOP) can be set by software. V0=( a + VOPxb ) Typical values for parameter for the HV-Generator programming SYMBOL a b VALUE 6.75 0.03 UNIT V V
(1)
V0
b
a
00
01
02
03
04
05
06
.....
7D
7E
7F
VOP[6:0](programmed) {00 hex... 7F hex} Fig 13. VOP programming of ST7545T
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10. COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RESB Pin="L"
Waiting for Stabilizing the Power
Release the reset state. (/RESB pin="H") Waiting reset circuit stablized(>1ms)
Function set PD=0 ,V=0 , H=1 SET Bias system SET VOP Function set PD=0 , V=0 , H=0 Display control D=1 E=0 (Normal) Set X , Y address
End of Initialization
Initializing with the Built-in Power Supply Circuits
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power Supply Voltage Power supply voltage Power supply voltage (VDD standard) Power supply voltage (VDD standard) Operating temperature Storage temperature VDD1 VDD2 V0, VOUT V1, V2, V3, V4 TOPR TSTR Symbol Conditions -0.5 ~ 5 -0.5 ~ 5 -0.3~13.5 0.3 to VOUTIN -30 to +85 -65 to +150 V V V V C C Unit
Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of V0, V1, V2, V3 and V4 are always such that: VOUTIN V0 V1 V2 V3 V4 Vss
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12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
13. DC CHARACTERISTICS
VDD1 = 1.7 V to 3.3V; VSS = 0 V; Tamb = -30 to +85; unless otherwise specified. Item Symbol Condition Rating Min. 1.7 Typ. -- Max. 3.3 Units Applicable Pin Vss
Operating Voltage (1)
VDD1
V
Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current
VDD2 VIHC VILC VOHC VOLC ILI ILO
(Relative to VSS)
2.4
--
3.3 VDD
V V
VSS
0.7 x VDD -- VSS --
0.3 x VDD V VDD V
0.7 x VDD -- VSS -1.0 -3.0 Ta = VOUTIN = 13.0 V -- -- -- -- 2.0
0.3 x VDD V 1.0 3.0 3.5 K A A
Liquid Crystal Driver ON Resistance
RON
25C
SEGn COMn *6
(Relative VOUTIN To VSS) = 8.0 V
--
3.2
5.4
Frame frequency
FR
65.7
73
80.4
Hz
Item Input Voltage Internal Power Voltage Booster Output Voltage Voltage Regulator Operating Voltage
Symbol VDD1 VOUTOUT
Condition (Relative To VSS) (Relative To VSS)
Rating Min. 1.7 -- Typ. -- -- Max. 3.3 13.5
Units V V
Applicable Pin
VOUTOUT
VOUTIN
(Relative To VSS)
--
--
13.5
V
VOUTIN
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Dynamic Consumption Current: During Display, with the Internal Power Supply OFF Current consumed by total ICs (bare die) Test pattern Symbol Condition VDD = 3.0 V, ISS Booster X4 V0 - VSS = 9.0 V ISS Ta = 25C -- 0.01 2 A -- 300 -- A Rating Min. Typ. Max. Units Notes
Display Pattern SNOW
Power Down
Notes to the DC characteristics 1. The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. Power-down mode. During power down all static currents are switched off. 4. If external VOUTIN, the display load current is not transmitted to I DD. 5. VOUT external voltage applied to VOUTIN pin; VOUTIN disconnected from VOUTOUT (no connect)
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14. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
/CSB tCYC8 tCCLR,tCCLW WR,RD tCCHR,tCCHW tDS8 D0 to D7 (Write) tDH8
tACC8 D0 to D7 (Read)
tOH8
Figure 26.
(VDD = 3.3V , Ta = -30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 10 100 400 80 80 140 80 80 10 -- 5 -- -- 70 50 Max. -- -- -- -- -- -- ns Units
RD
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(VDD = 2.7V , Ta = -30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 15 150 600 220 180 220 180 120 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Units
RD
(VDD = 1.8V , Ta = -30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 30 200 1000 360 280 360 280 200 30 -- 10 -- -- 240 200 Max. -- -- -- -- -- -- ns Units
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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ST7545T
System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0 R/W tAW6 CSB tCYC6 tCCLR,tCCLW E tCCHR,tCCHW tDS6 D0 to D7 (Write) tDH6 tAH6
tACC6 D0 to D7 (Read)
tOH6
Figure 27.
(VDD = 3.3V , Ta = -30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 10 0 240 80 80 80 140 80 10 -- 5 -- -- 70 50 Max. -- -- -- -- -- -- ns Units
RD
Ver 1.5
36/48
2006/01/20
ST7545T
(VDD = 2.7V , Ta = -30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 15 0 400 220 180 220 180 120 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100
Units
RD
ns
(VDD = 1.8V , Ta = -30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 30 0 640 360 280 360 280 200 30 -- 10 Max. -- -- -- -- -- -- -- -- -- 240 200 ns Units
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
Ver 1.5
37/48
2006/01/20
ST7545T
SERIAL INTERFACE(4-Line Interface)
tCCSS tCSH
/CSB
tSAS A0 tSCYC tSLW SCLK
tSAH
tSHW tf tSDS SDA tr tSDH
Fig 28. (VDD = 3.3V , Ta = -30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 150 75 75 20 100 20 10 20 140 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
(VDD = 2.7V , Ta = -30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 300 150 150 30 150 30 20 30 200 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
Ver 1.5
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2006/01/20
ST7545T
(VDD = 1.8V , Ta = -30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 500 250 250 60 250 60 50 40 350 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.5
39/48
2006/01/20
ST7545T
SERIAL INTERFACE(3-Line Interface)
tCCSS /CS1 (CS2="1") tCSH
tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH
Fig 28. (VDD = 3.3V , Ta = -30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 150 75 75 20 10 20 140 Max. -- -- -- -- -- -- -- ns Units
CSB
(VDD = 2.7V , Ta = -30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 300 150 150 30 20 30 200 Max. -- -- -- -- -- -- -- ns Units
CSB
Ver 1.5
40/48
2006/01/20
ST7545T
(VDD = 1.8V , Ta = -30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 500 250 250 60 50 40 350 Max. -- -- -- -- -- -- -- ns Units
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
SERIAL INTERFACE(I C Interface)
2
SD A
tBUF tLOW tHIGH
SCL
tDH;STA tHD;DAT tSU;DAT
(VDD = 3.3V , Ta = -30~85C) Item Signal Symbol SCL SCL SCL SI SI SCL SCL FSCLK TLOW THIGH TSU;Data THD;Data TR TF Cb SI SI TSU;SUA THD;STA TSU;STO TSW TBUF Condition 1.3 0.6 100 0 Rating Min. Max. 400 0.9 Units kHZ us us ns us ns ns pF us us us ns us
SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time SCL,SDA rise time SCL,SDA fall time Capacitive load represented by each bus line Setup time for a repeated START condition Start condition hold time Setup time for STOP condition Tolerable spike width on bus
20+0.1Cb 300 20+0.1Cb 300 0.6 0.6 0.6 1.3 400 50
BUS free time between a STOP and START condition SCL
Ver 1.5
41/48
2006/01/20
ST7545T
15. RESET TIMING
tRW /RES
tR Internal status During reset Reset complete
Fig 29. (VDD = 3.3V , Ta = -30~85C) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 1 Typ. -- -- Max. 1 -- Units us us
(VDD = 2.7V , Ta = -30~85C) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 2.0 Typ. -- -- Max. 2.0 -- Units us us
(VDD = 1.8V , Ta = -30~85C) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 3.0 Typ. -- -- Max. 3.0 -- Units us us
Ver 1.5
42/48
2006/01/20
ST7545T
APPICATION NOTE
Ver 1.5
43/48
2006/01/20
ST7545T
Ver 1.5
44/48
2006/01/20
ST7545T
Ver 1.5
45/48
2006/01/20
ST7545T
Ver 1.5
46/48
2006/01/20
ST7545T
Ver 1.5
47/48
2006/01/20
ST7545T
History
Version V0.x V1.1 History Preliminary 1. 2. 3. 1. 1. 2. 1. Complete release Revise I2C pin description Modify description. Modify pixel order on Page 23. Modify Feature Description. Update Frame Rate Range. Change Dice Thickness and Part Number (ST7545T-G2).
2005/10/19
Notes
V1.2 V1.3 V1.4 V1.5
2005/10/26 2005/11/18 2006/01/12 2006/01/20
Ver 1.5
48/48
2006/01/20

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