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| November 2006 ASMP5P23S04A 3.3V `SpreadTrak' Zero Delay Buffer rev 1.4 Features * * * * * * * * * * * * * Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer "ASM5P23S04A Configurations Table". Input frequency range: 15 MHz to 133 MHz Multiple low-skew outputs. Output-output skew less than 200 pS. Device-device skew less than 500 pS. Two banks of two outputs each. Less than 200 pS cycle-to-cycle jitter * (-1, -1H, -2, -2H). FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250 pS, and the output-to-output skew is guaranteed to be less than 200 pS. The ASM5P23S04A has two banks of two outputs each. Multiple ASM5P23S04A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500 pS. The ASM5P23S04A (Refer is available in two different Available in space saving, 8-pin 150-mil SOIC package. 3.3V operation. Advanced 0.35 CMOS technology. Industrial temperature available. `SpreadTrak'. configurations "ASM5P23S04A Configurations Table). The ASM5P23S04A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P23S04A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The ASM5P23S04A-2 allows the user to obtain Ref and 1/2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. The ASM5P23S04A-2H is a high-drive version with REF/2 on both banks. Functional Description ASM5P23S04A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in a 8-pin package. The part has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven to Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. November 2006 rev 1.4 ASM5P23S04A Configurations Device ASM5P23S04A-1 ASM5P23S04A-1H ASM5P23S04A-2 ASM5P23S04A-2H ASM5P23S04A Feedback From Bank A or Bank B Bank A or Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference Reference Bank B Frequency Reference Reference Reference /2 Reference /2 `SpreadTrak' Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. ASM5P23S04A is designed so as not to filter off the Spread Spectrum feature of the Reference Input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a 1500 significant amount of tracking skew which may cause problems in the systems requiring synchronization. Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. 1000 REF-Input to CLKA/CLKB Delay (ps) 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins To close the feedback loop of the ASM5P23S04A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 15 November 2006 rev 1.4 Pin Configuration REF CLKA1 CLKA2 GND 1 2 3 4 8 FBK ASM5P23S04A ASM5P23S04A 7 6 VDD CLKB2 5 CLKB1 Pin Description for ASM5P23S04A Pin # 1 2 3 4 5 6 7 8 Pin Name REF1 CLKA12 CLKA22 GND CLKB12 CLKB2 2 VDD FBK Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A Ground Buffered clock output, bank B Buffered clock output, bank B 3.3V supply PLL feedback input Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 15 November 2006 rev 1.4 Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) ASM5P23S04A Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 Unit V V V C C C >2000 V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P23S04A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Description Min 3.0 0 Max 3.6 70 30 15 7 Unit V C pF pF pF Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance3 Note: 3. Applies to both Ref Clock and FBK. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 15 November 2006 rev 1.4 Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices ASM5P23S04A Parameter VIL VIH IIL IIH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current VIN = 0V VIN = VDD Test Conditions Min Max 0.8 Unit V V 2.0 50.0 100.0 A A VOL Output LOW Voltage 4 IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 0.4 V VOH Output HIGH Voltage 4 2.4 V TBD TBD mA IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) TBD TBD Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 15 November 2006 rev 1.4 Switching Characteristics for ASM5P23S04A Commercial Temperature Devices Parameter 1/t1 1/t1 1/t1 ASM5P23S04A Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -2H) 5 Duty Cycle = (t2 / t1) * 100 (-1, -2,-1H, -2H) 5 Test Conditions 30 pF load, All devices 20 pF load, -1H, -2H devices 15 pF load, -1, -2 devices Measured at 1.4V, FOUT = 66.66 MHz 30 pF load Measured at 1.4V, FOUT = <50 MHz 15 pF load Measured between 0.8V and 2.0V 30 pF load Measured between 0.8V and 2.0V 15 pF load Measured between 0.8V and 2.0V 30 pF load Measured between 2.0V and 0.8V 30 pF load Measured between 2.0V and 0.8V 15 pF load Measured between 2.0V and 0.8V 30 pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded Min 15 15 15 40.0 45.0 Typ Max Unit 100 133 133 50.0 50.0 60.0 55.0 2.20 1.50 1.50 2.20 1.50 1.25 200 200 200 400 0 0 250 500 pS pS V/nS 175 200 100 400 pS 375 1.0 mS pS pS MHz MHz MHz % % nS nS nS nS nS nS t3 t3 t3 t4 t4 t4 Output Rise Time (-1, -2) Output Rise Time (-1, -2) Output Rise Time (-1H, -2H) Output Fall Time (-1, -2) Output Fall Time (-1, -2) Output Fall Time (-1H, -2H) 5 5 5 5 5 5 Output-to-output skew on same bank 5 (-1, -2) Output-to-output skew (-1H, -2H) t5 Output bank A -to- output bank B skew (-1, -2H) Output bank A to output bank B skew (All outputs equally loaded 2) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge 5 Device-to-Device Skew 5 Output Slew Rate5 Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15 pF load tJ Cycle-to-cycle jitter 5 (-1, -1H, -2H) Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133 MHz, loaded outputs, 15 pF load tJ Cycle-to-cycle jitter 5 (-2) PLL Lock Time 5 Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 66.67 MHz, loaded outputs, 15 pF load Stable power supply, valid clock presented on REF and FBK pins 1 tLOCK Note: 5. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 15 November 2006 rev 1.4 Operating Conditions for ASM5I23S04A Industrial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance6 ASM5P23S04A Description Min 3.0 -40 Max 3.6 85 30 15 7 Unit V C pF pF pF Note: 6. Applies to both Ref Clock and FBK. Electrical Characteristics for ASM5I23S04A Industrial Temperature Devices Parameter VIL VIH IIL IIH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current VIN = 0V VIN = VDD Test Conditions Min Max 0.8 Unit V V 2.0 50.0 100.0 A A VOL Output LOW Voltage 7 IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 0.4 V VOH Output HIGH Voltage 7 2.4 V TBD TBD TBD TBD IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) mA Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 15 November 2006 rev 1.4 Switching Characteristics for ASM5I23S04A Industrial Temperature Devices Parameter t1 t1 t1 ASM5P23S04A Description Output Frequency Output Frequency Output Frequency 8 Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -2H) 8 Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -2H) Test Conditions 30 pF load, All devices 20 pF load, -1H, -2H devices 15 pF load, -1 and -2 devices Min 15 15 15 Typ Max 100 133 133 Unit MHz MHz MHz % % nS nS nS nS nS nS Measured at 1.4V, FOUT = <66.66 MHz 40.0 30 pF load Measured at 1.4V, FOUT = <50 MHz 15 pF load Measured between 0.8V and 2.0V 30 pF load Measured between 0.8V and 2.0V 15 pF load Measured between 0.8V and 2.0V 30 pF load Measured between 2.0V and 0.8V 30 pF load Measured between 2.0V and 0.8V 15 pF load Measured between 2.0V and 0.8V 30 pF load 45.0 50.0 50.0 60.0 55.0 2.50 1.50 1.50 2.50 1.50 1.25 200 200 200 400 t3 t3 t3 t4 t4 t4 Output Rise Time (-1, -2) Output Rise Time (-1, -2) Output Rise Time (-1H, -2H) Output Fall Time (-1, -2) Output Fall Time (-1, -2) Output Fall Time (-1H, -2H) 8 8 8 8 8 8 Output-to-output skew on same bank (All outputs equally loaded 8 1, -2) Output-to-output skew (-1H, -2H) t5 All outputs equally loaded Output bank A -to- output bank B skew All outputs equally loaded (-1, -2H) Output bank A -to- output bank B skew All outputs equally loaded (-2) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Measured at VDD /2 8 Edge Device-to-Device Skew 8 Output Slew Rate8 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs,15 pF load tJ Cycle-to-cycle jitter 8 (-1, -1H, -2H) Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133 MHz, loaded outputs, 15 pF load tJ Cycle-to-cycle jitter (-2) PLL Lock Time 8 8 pS 0 0 1 250 500 pS pS V/nS 180 200 100 400 pS 380 1.0 mS pS Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 66.67 MHz, loaded outputs, 15 pF load Stable power supply, valid clock presented on REF and FBK pins tLOCK Note: 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 15 November 2006 rev 1.4 Switching Waveforms Duty Cycle Timing t1 t2 ASM5P23S04A 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time 2.0 V OUTPUT 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V Output - Output Skew 1.4 V OUTPUT 1.4 V OUTPUT t5 Input - Output Propagation Delay V INPUT DD /2 V OUTPUT DD /2 t6 Device - Device Skew V FBK, Device 1 DD /2 V FBK, Device 2 DD /2 t7 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 15 November 2006 rev 1.4 Test Circuits ASM5P23S04A TEST CIRCUIT #1 +3.3V CLKOUT VDD 0.1uF GND OUTPUT CLOAD TEST CIRCUIT # 2 1K CLKOUT VDD 0.1uF GND OUTPUT 1K 10pF +3.3V For parameter t8 (output skew rate) on -1H devices 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 15 November 2006 rev 1.4 Package Information: 8-lead (150 Mil) Molded SOIC ASM5P23S04A E H D A2 A e B A 1 C L D Dimensions Symbol Min A1 A A2 B C D E e H L Inches Max 0.010 0.069 0.059 0.020 0.010 0.004 0.053 0.049 0.012 0.007 Millimeters Min Max 0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0 1.27 8 0.25 1.75 1.50 0.51 0.25 0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 15 November 2006 rev 1.4 Ordering Codes ASM5P23S04A Ordering Code ASM5P23S04AF-1-08-SR ASM5P23S04AF-1-08-ST ASM5I23S04AF-1-08-SR ASM5I23S04AF-1-08-ST ASM5P23S04AF-1H-08-SR ASM5P23S04AF-1H-08-ST ASM5I23S04AF-1H-08-SR ASM5I23S04AF-1H-08-ST ASM5P23S04AF-2-08-SR ASM5P23S04AF-2-08-ST ASM5I23S04AF-2-08-SR ASM5I23S04AF-2-08-ST ASM5P23S04AF-2H-08-SR ASM5P23S04AF-2H-08-ST ASM5I23S04AF-2H-08-SR ASM5I23S04AF-2H-08-ST Marking 5P23S04AF-1 5I23S04AF-1 5P23S04AF-1 5I23S04AF-1 5P23S04AF-1H 5I23S04AF-1H 5P23S04AF-1H 5I23S04AF-1H 5P23S04AF-2 5I23S04AF-2 5P23S04AF-2 5I23S04AF-2 5P23S04AF-2H 5I23S04AF-2H 5P23S04AF2H 5I23S04AFH Package Type 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free Temperature Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 15 November 2006 rev 1.4 Ordering Codes (Contd...) ASM5P23S04A Ordering Code ASM5P23S04AG-1-08-SR ASM5P23S04AG-1-08-ST ASM5I23S04AG-1-08-SR ASM5I23S04AG-1-08-ST ASM5P23S04AG-1H-08-SR ASM5P23S04AG-1H-08-ST ASM5I23S04AG-1H-08-SR ASM5I23S04AG-1H-08-ST ASM5P23S04AG-2-08-SR ASM5P23S04AG-2-08-ST ASM5I23S04AG-2-08-SR ASM5I23S04AG-2-08-ST ASM5P23S04AG-2H-08-SR ASM5P23S04AG-2H-08-ST ASM5I23S04AG-2H-08-SR ASM5I23S04AG-2H-08-ST Marking 5P23S04AG-1 5I23S04AG-1 5P23S04AG-1 5I23S04AG-1 5P23S04AG-1H 5I23S04AG-1H 5P23S04AG-1H 5I23S04AG-1H 5P23S04AG-2 5I23S04AG-2 5P23S04AG-2 5I23S04AG-2 5P23S04AG-2H 5I23S04AG-2H 5P23S04AG2H 5I23S04AGH Package Type 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green Temperature Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 15 November 2006 rev 1.4 Device Ordering Information ASM5P23S04A ASM5P23S04A F-08 TR R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 15 November 2006 rev 1.4 ASM5P23S04A PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright (c) PulseCore Semiconductor All Rights Reserved Part Number: ASM5P23S04A Document Version: 1.4 Note: This product utilizes US# 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 (c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 15 of 15 |
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