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SC9641
CD DIGITAL SERVO SIGNAL PROCESSOR(SLAVE MODE)
DESCRIPTION
The SC9641 is a single-chip CD processor for digital servo and ASIC circuit. This LSI incorporates CD servo controller, CD signal processor, digital audio DAC and built-in CPU interface.
FEATURES
* Supports 1X to 2X speed playback * Command and sub code transmission adopts tri-line communication or parallel communication * Built-in MCU controls the CD and state feedback by communication instructions of the communication bus.* Supports format of CD-A/V, CD-R, CD-R/W and CD-ROM
QFP-64-14 x 14-0.8
ORDERING INFORMATION APPLICATIONS
* CD, VCD and MP3 player * Desk audio system Device SC9641 Package QFP-64-14X14-0.8
BLOCK DIAGRAM
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SC9641
ABSOLUTE MAXIMUM RATINGS (Tamb=25C)
Characteristic Supply Voltage Input Voltage On Pins Operating Temperature Symbol VDD VIN Tmax Value -0.5 ~ +5.5 -0.5 ~ VDD + 0.5 -20 ~ +75 Unit V V C
ELECTRICAL CHARACTERISTICS(VDD=3.4~5.5V;VSS=0V;Tamb=-10~+60C)
Characteristics Supply Voltage Supply Current RFIN Input Signal Reference Voltage Common Mode DC Output ADC Reference Voltage Input Current Of Central Diode B Input Current Of Central Diode A Input Current Of Central Diode C Input Current Of Central Diode D Input Current Of Satellite Diode F Input Current Of Satellite Diode F Data Slicer Feed-back Current Output LDON Low Level Output Current ERR Output Current DATA_OUT WCLK_OUT SCLK_OUT Output Current DATA_OUT WCLK_OUT SCLK_OUT Low Level Output Voltage DATA_OUT WCLK_OUT SCLK_OUT High Level Output Voltage RAD Output Current FOC Output Current SLED Output Current IRAD IFOC ISLED 0 0 0 1 1 1 mA mA mA
(To be continued)
Symbol VDD IDD VRFIN VIr VVCOM VVadc IB IA IC ID IF IE IIdata ILDON IERR IOH1 IOL1
Test Condition 5V; 1X Speed
Min. 4.5
Typ. 5.0 45 1.0 0.5VDD
Max. 5.5
Unit V mA V V V
2.0 VVCOM+ 0.462 0 0 0 0 0 0 1.9 0 0
2.5 VVCOM+ 2.313 10 10 10 10 5 5 5.5 2 1
V A A A A A A A mA mA
0
1
mA
VOL1
IOL1=1mA
0
0.4
V
VOH1
IOH1=-1mA
VDD-0.4
VDD
V
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SC9641
(Continued)
Characteristics MOTO Output Current RAD, FOC, SLED Low Level Output Voltage RAD, FOC, SLED High Level Output Voltage Moto Low Level Output Voltage Moto high Level Output Voltage RAD, FOC, SLED, MOTO Output 3-state Leakage Current ACK, WR, RD, DATA0 Level Input Voltage ACK, WR, RD, DATA0 Level Input Voltage DATA_IN, WCLK_IN, SCLK_IN, High Level Input Voltage DATA_IN, WCLK_IN, SCLK_IN, Low Level Input Voltage DAC Total Harmonic Distortion Plus Noise 7, Low 7, High
Symbol IMOTO VOL VOH VOLmoto VOHmoto IZO VILH VIHL VOHda VOLda (THD+N)/S
Test Condition
Min. 0
Typ. 10
Max.
Unit mA
IOL=1mA IOH=-1mA IOLmoto=10mA IOHmoto=-10mA
0 VDD0.4 0 VDD-1 -10 2.8 0.6 0.7VDD -0.5 60 65 16.9344 2.8224 44.1 0 3.0
0.4 VDD 1.0 VDD +10 0.7 VDD+0.5 0.3VDD 70 0.001 0.03 -
V V V V A V V V V dB dB dB dB dB dB dB dB dB MHz MHz KHz
0~19 kHz 19~20 kHz 24KHz DA Filter Attenuation Filter_DA 25 ~ 35 KHz 35 ~ 64 KHz 64 ~68 KHz 68KHz 69~ 88KHz Crystal Frequency SCLK Frequency WCLK Frequency Fsystem FSCLK_IN FWCLK_IN
25 40 50 31 35 40
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SC9641
PIN CONFIGURATION
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 Pin name VSSA1 VDDA1 B A C D F E VCOM Vadc Idata Analog Ground 1 Analog Supply 1 Central diode current signal input Central diode current signal input Central diode current signal input Central diode current signal input Satellite diode current signal input Satellite diode current signal input DC voltage input ADC reference voltage output Data signal feed-back current output
(To be continued)
Descriptions
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SC9641
(Continued)
Pin No. 12 13 14 15 16 17 18 19
Pin name RFIN RFREF Ir VSSA2 VDDA2 CRIN CROUT MODE EFM signal input Comparator common mode input Reference current output Analog ground 2 Analog supply 2
Descriptions
Crystal oscillation circuit input. When the master clock is input externally, input it from this pin. Crystal oscillation circuit output. Connect ground. Control the spindle motor (during focusing and jumping, if MOT_CTRL output high level signal, it can control the MOT control port of SA9529 after through 3 voltage drop diodes, then prevent the spindle reverse; in other condition, the MOT-CTRL output low level). D/A interface. LR clock output. D/A interface. Bit clock output. D/A interface. Serial data output C2 error flag D/A interface. LR clock input. D/A interface. Bit clock input. D/A interface. Serial data input Acknowledge Signal output pin (drain open, with pull up resistor). DAC system clock input (16.9344MHz) 16.9344MHZ clock output Data I/O port, it is shared with write port of parallel communication. Control I/O port, it is shared with read port of parallel communication.(drain open, with internal pull-up resistor). Acknowledge signal port (drain open, with internal pull-up resistor). General I/O port, it is shared with data bit 7 (drain open, with internal pull up resistor). General I/O port, it is shared with data bit 6 (drain open, with internal pull up resistor). General I/O port, it is shared with data bit 5 (drain open, with internal pull up resistor). General I/O port, it is shared with data bit 4 (drain open, with internal pull up resistor). General I/O port, it is shared with data bit 3 (drain open, with internal pull up resistor). General I/O port, it is shared with data bit 2 (drain open, with internal pull up resistor). General I/O port, it is shared with data bit 1 (drain open, with internal pull up resistor). General I/O port, it is shared with data bit 0 (drain open, with internal pull up resistor). Test pin. Reset pin (active low) Analog Supply Analog Ground Analog Supply
(To be continued)
20
MOT_CTRL
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
WCLK_OUT SCLK_OUT DATA_OUT ERR WCLK_IN SCLK_IN DATA_IN ACK MCLK_IN CL16 DATA \ WR STB \ RD ACK IO.7 \ DATA7 IO.6 \ DATA6 IO.5 \ DATA5 IO.4 \ DATA4 IO.3 \ DATA3 IO.2 \ DATA2 IO.1 \ DATA1 IO.0 \ DATA0 TEST RESET VDDA VSSO VDD0
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SC9641
(Continued)
Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Pin name VREF R CR CL L RAD FOC SLED VSSP STATUS BCLK MOTO VDDP VDD GND TRAY_SW SLED_SW LDON
Descriptions Internal reference voltage for output channels Digital audio right channel output pin. Digital audio right channel filter pin. Digital audio left channel filter pin. Digital audio left channel output pin. Tracking drive output Focus drive output Sled drive output Ground Shake signal output (high active, used for anti-seismic system) 75Hz frame sync signal output pin. Spindle drive output. Digital power supply. Digital power supply. Digital ground. Tray loading position monitor signal input Sled motor position monitor signal input Laser control signal output (active high)
FUNCTION DESCRIPTION
The system controller sets the mode and readout the status of signal processor and digital servo by the standard CPU interface. The detail of command and interface timing is explained in the following tables. 1. SYSTEM WRITE COMMAND TABLE: PARAMETER (BIN) (HEX) FUNCTION DESCRIPTIONS Set up 8 general I/O ports, one bit control one I/O port, when the bit is 1, 01 XXXXXXXX the corresponding port is set input, and it was set output port when it is 0. IO.7~IO.0 corresponding the high bit to least bit. All ports set input status when power on. 03 XXXXXXXX Set the data of output port. If it is input port, the data is IO.7~IO.0. Set motor speed standard (the initial value is EFH); Motor rotate speed when stable playing: 10000B The low 5 bits set motor rotate speed lower limit: range (00000B~10000B) 08 XXXXXXXX The high 3 bits set motor rotate upper limit : (10000B~10111B) According to the initial value, if the motor speed is in the range of 01111B~100111B , it consider the motor is stable, and can carry the next operation. (To be continued)
COMMAND
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SC9641
(Continued) COMMAND (HEX) PARAMETER (BIN) FUNCTION DESCRIPTIONS Set shield time of the motor error signal (the initial value is 40H), the parameter is 00H~FFH, the internal reference is 8ms, so the shield time is 0C XXXXXXXX 0~2 seconds; if the motor rotate speed is detected in the set range, and detect the shield time of motor error signal is exceed, the system consider the servo is abnormally and need restart. Start play, if not read TOC, then store the TOC data; when play at the 00000010 00000011 00000100 00000101 export section, if the sub-controller at normal play state, the system will receive the command of master controller. read and save TOC information again, and stay in the lay in section. Pause. Fast play, at this time, playing at FAST_STEP, and FAST_TIME interval, after fast forward to export section, it entry pause mode, wait for the next command. Fast backward, playing at FAST_STEP, and FAST_TIME interval. After 00000110 00000111 00010000 fast backward to import section, it enter pause mode and wait for the command of master controller. Stop play, and switch bare head to inside track. If it is in the lay in section, then jump out the lay in section, and play at the target track. The target track set command: 0X11 If it is in the lay in section, then jump out the lay in section, and play at the 0F 00010001 target track. The target track set command: 0X12, 0X13, 0X14 If it is in the lay in section, then jump out the lay in section, and play at the 00010010 00010011 00010100 00010101 relative time of target track. Set command: 0X11, 0X12, 0X13, 0X14 Initialize the servo Closed CD data output. Open CD data output Jump to the next session; if there are a next session, then store the start 00100000 address of program to the NEXT_AMIN, NEXT_ASEC, NEXT_AFRM; If there are no next session, then the NEXT_AMIN, NEXT_ASEC, NEXT_AFRM remain original value or is 0XFF. 00100001 Stop at the former play point, the sled motor will not return. This command used for control sled motor in or out after servo stop: 00100010 5FH + 81H, 0FH + 21H Sled motor sled inside. 5FH + 7FH, 0FH + 21HSled motor sled outside. 5FH + 00H, 0FH + 21HSled motor stop. (To be continued)
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SC9641
(Continued) COMMAND (HEX) 60 PARAMETER (BIN) XXXXXXXX FUNCTION DESCRIPTIONS Set the high 8 bits (0FFH~00H, it need complement code and the default code is 0FDH) of TRACK when the import section (TOC) jump to normal play section. Set the time of jump to the next session; if it is not jump to the next session 61 XXXXXXXX in the set time, the sub controller will set the NEXT_AMIN, NEXT_ASEC, NEXT_AFRM is 0XFF; this command is treat with the copy disc.(he unit of the time is 100ms). BIT2, BIT1, BIT0------set SC9641 internal DAC data input format, the default is B110; BIT2: 1----single data input. 0----double data input. BIT1, BIT0: 00---I2S-BUS 10---LSB FIXED 16 BITS 01---LSB FIXED 18 BITS 11---LSB FIXED 20 BITS BIT7, BIT6: Improve play capability of difficult read disk. 63 XXXXXXXX 00---normal (default) 01--- one step higher than 00 10--- one step higher than 01 11--- one step higher than 11 ( this setting is the easiest read disk, if the disk is not readable in one time in the normal setting, this two bits can set to 11 to read the disk easily ) BIT5: IMPROVE PLAY CAPABILITY OF difficult readable disk, can set with BIT6, BIT7. 0--- normal(default) 1--- read disk more easy (the setting is the same as BIT6, BIT7) 10110011 10111011 1010XXXX 0D 00111010 00111011 00111110 00110010 11 12 13 14 15 16 17 18 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Set 1x speed play Set 2X speed play Set voltage Vadc Set data output format: I2S-BUS CD-ROM mode Set data output format: EIAJ CD-ROM mode Set data output format: I2S-BUS 16-BIT FS mode Set data output format: EIAJ 16-BITS FS MODE set TARGET TNO set TARGET minute set TARGET second set TARGET frame Set jump frame range. Set fast forward and fast backward steps (TRACK). Set step time (10ms) Set NEG FRAME of jump target (0~255)
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SC9641
2. SYSTEM READ COMMAND TABLE: PARAMETER (BIN) XXXXXXXX MINTNO MAXTNO NEXT_AMIN NEXT_ASEC NEXT_AFRM MAXMIN MAXSEC MAXFRM XXXXXX0X XXXXXX1X XXXXX0XX XXXXX1XX XXXX0XXX XXXX1XXX 8A XXX0XXXX XXX1XXXX XX0XXXXX XX1XXXXX X0XXXXXX X1XXXXXX 0XXXXXXX 1XXXXXXX XXXXXXX0 XXXXXXX1 XXXXXX0X XXXXXX1X XXXXX0XX XXXXX1XX XXXX0XXX XXXX1XXX 8B XXX0XXXX XXX1XXXX XX0XXXXX XX1XXXXX X0XXXXXX X1XXXXXX 0XXXXXXX 1XXXXXXX (HEX) 02 81 82 83 84 85 86 87 89 FUNCTION DESCRIPTIONS Read the value of IO.7~IO.0D, if it as output port, it read the output data. The minimum target(HEX) The maximum track no (HEX) The absolute time (minute) of the next session (BCD). The absolute time (second) of the next session (BCD). The absolute time (frame) of the next session (BCD). Maximum play time- min(HEX) Maximum play time- sec(HEX) Maximum play time- frame(HEX) Not store TOC information Store TOC information Not enter play status Enter play status Not enter pause status Enter pause status Not enter pause status Enter fast forward status Not enter fast backward status Enter fast backward status Not enter stop status Enter stop status Not initialize servo parameter Initialize servo parameter 1x, 2x speed switch over. 1x, 2x speeds not switch over. Not find the set target and playing. Find the set target and playing. Servo normal. Servo stop, resuming. Not detect no disc Detect no disc+ Play not at the target track. Playing at the target track. Open CD output. Close CD output. 1x speed play status. 2x speed play status. Not fast forward the export section or not fast backward the import section. It is have been fast forward the export section or fast backward to the lay in section or play to the export section. (To be continued)
COMMAND
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SC9641
(Continued) COMMAND (HEX) 9A A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA PARAMETER (BIN) XXXXX0XX XXXXX1XX QCODE0 QCODE1 QCODE2 QCODE3 QCODE4 QCODE5 QCODE6 QCODE7 QCODE8 QCODE9 QCODE0~9 TRAY_SW=0 TRAY_SW=1 CTRLADR (BCD)disc mode code. TNO (BCD) Tone no. IX (BCD) index no. RMIN (BCD) relative time-minute RSEC (BCD) relative time-second RSEC (BCD) relative time- frame ZERO (BCD) AMIN (BCD) absolute time-minute ASEC (BCD) absolute time-second AFRAME (BCD) absolute time-frame Continue read ten Q sub-code (BCD code), this command is active in the parallel mode. Read motor speed information, normal play: b00010000, stop : DD 000XXXXX b00000000 when the motor is accelerated from 0 to stable play, if it is exceed the b00010000, it will stabilization at b00010000. FUNCTION DESCRIPTIONS
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SC9641
3.
CPU INTERFACE TIMING
Note: The interface protocol adopt fixed communication format. Every frame includes 24 bits, where 16 bits data code, and 8 bits verify code. COMMAND (8bits) + CHECK(4bits) + DATA(8bits) + CHECK(4bits) 4 bits verify code is obtained from high 4 bits XOR low 4 bits of the former 8 bits code. The 8 bits DATA code is the master controller send to SC9641, or the SC9641 request read code. If the COMMAND not set value, then the DATA after COMMAND is invalid, but the DATA cannot omit. COMMAND and DATA send code from MSB to LSB. SC9641 operation according the master controller command and it is single initiative communication.
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SC9641
4.
INTERFACE DESCRIPTION
DATA DATA STB ACK
MCU
STB ACK
SC9641
DATA (pin 31): synchronization and data transmission. STB (pin 32): low level active. ACK (pin 33): acknowledge signal
1 Master controller transmit data
1) The master controller transmitted data is COMMAND or PARAMETER. Every frame of data transmit, the master controller start to synchronize, transmit the 8 bits command, then transmit the 4 bits check data, if sub-controller pass the check data, following transmit continuance or read the command. 2) The ACK send out acknowledge signal, if the sub-controller received data is match to CHECK data, ACK signal become low indicate the check passed; if it is not match, ACK signal keep high level, then exit this communicate. The master controller will operating with the ACK station, the data line keep high when checking the data. 3) In the transmitting, if the master controller or sub-controller not response the request in some time (T<1000us), the system regard this transmit error. The master controller will exit and repeat again or produce other errors. 4) In the transmitting, the master controller transmits the DATA when the ACK is low, and the transmitted DATA is available at STB is high, SC9641 complete write 1 bit after ACK become high.
2 Master controller receive data
1) After master controller transmitted the data code, the sub-controller check the 8 bits command, if it is match the check data, then send the request data to master controller. The STB of master controller complete this process. 2) After transmit the 12 bits data, the sub-controller complete this communication. The master controller check the 12 bits data, if it is match the check data, this communication complete, the receive data available. And if it is not match, the receive data invalid, the master controller transmit the read again command, but it won'transmit check data. t 3) In the receiving, if the master controller or sub-controller not response the request in some time (T<1000us), the system regard this receive error. The master controller will exit and repeat again or produce other error. 4) In the receiving, the sub-controller receive the DATA when the ACK is low, and the DATA is read out at STB is high, SC9641 complete read 1 bit after ACK become high.
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SC9641
5.
PARALLEL COMMUNICATION TIMING WAVEFORM
Note: WR (pin 31), RD (pin 32) is controlled by system (master controller), and ACK (pin 28) is controlled by SC9641 (sub-controller), normal state is high level, and DATA is controlled by all above. 1) Write mode: ACK_H a. The system set WR: begin to write operation: MSB (T1). b. The system wait SC9641 acknowledge: MSB (T2) c. After the system write data to the DATA port, set the WR: LSB (T3). d. The system wait for the response of SC9641: LSB (T4) (After SC9641 read the data, set ACK: LSB) e. After write one byte, according to the a b c d order write the next byte. 2) Read mode: ACK_H a. The system set RD: MSB (T1), and begin to read operation. b. The system wait for SC9461 response ACK: MSB (T2) (SC9641 set ACK after data ready: MSB) c. After the system read out the data, set the RD: LSB (T3). d. The system wait for the response of SC9641: LSB (T4). e. After read one byte, according to the a b c d order perform the next byte read operation. 3) Time of communication protocol: a. system read (SYS READ): T2-T1: >=7us T3-T2: =5us (TYP.), related with the execute speed of master controller. T4-T3: >=6us
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SC9641
b. system write (SYS WRITE): T2-T1: >=6us T3-T2: =5us (TYP.), related with the execute speed of master controller. T4-T3: >=4us 4) Processor of communication error. In order to keep the communication normally, SC9641 design the error process in the program communicate protocol. During the communication, the max time of SC9641 wait system command (WR, RD) is 130us, if the wait time is more than 130us, SC9641 regard this communication error, and end this operation, wait the next communication.
TYPICAL APPLICATIONS CIRCUIT
VDD0
VSS0
VDDA
VREF
RESET
TEST
IO.0\DATA0
IO.1\DATA1
IO.2\DATA2
IO.3\DATA3
IO.4\DATA4
IO.5\DATA5
IO.6\DATA6 Ir
RFREE
VDDA1
IO.7\DATA7 VSSA2
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VDDA2
VSSA1
VCOM
RFIN
Vadc
Idata
C
D
B
A
E
F
ACK
R
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SC9641
PACKAGE OUTLINE
QFP-64-14x14-0.8 UNIT: mm
HANDLING MOS DEVICES:
Electrostatic charges can exist in many things. All of our MOS devices are internally protected against electrostatic discharge but they can be damaged if the following precautions are not taken: * Persons at a work bench should be earthed via a wrist strap. * Equipment cases should be earthed. * All tools used during assembly, including soldering tools and solder baths, must be earthed. * MOS devices should be packed for dispatch in antistatic/conductive containers.
Note: Silan reserves the right to make changes without notice in this specification for the improvement of the design and performance. Silan will supply the best possible product for customers.
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