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LVDS Interface ICs
56bit LVDS Transmitter 56:8 Serializer
BU7988KVT
Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The ROHM's LVDS has low swing mode to be able to expect further low EMI.
Features Wide dot clock range : Single(112MHz)/Dual(224MHz)(NTSC, VGA, SVGA, WXGA UXGA) Support spread spectrum clock generator. Clock edge selectable. Support reduced swing LVDS for low EMI. Power down mode. Package TQFP100V
Applications Flat Plane Display
Precaution This chip is not designed to protect from radioactivity.
Jun. 2008
Block Diagram
LVCMOS Input
CLK_IN (4150MHz)
LVDS Output
PLL
TCLK1 P/N (8112MHz) TA1 P/N
R10R17 G10G17 B10B17
8 8 8
8
PARALLEL TO SERIAL
TB 1 P/N
MUX
8 8
TC 1 P/N
TD 1 P/N
R20R27 G20G27 B20B27
8 8 8 8 8 8
TCLK2 P/N (8112MHz) TA2 P/N
PARALLEL TO SERIAL

TB2 P/N
HSYNC VSYNC DE MODE0 MODE1 XRST OE SEL_BIT RF RS MAP FLIP
TC2 P/N
TD2 P/N
Figure-1
Block Diagram
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TQFP100V
Package Outline and Specification
Product No.
16.00.3 14.00.2 75 76 51 50
BU7988KVT
16.00.3 14.00.2
Lot No.
100 1
1PIN MARK
25
26
1.2MAX 1.00.1 0.10.1
0.20.1
0.5
0.1
Figure-2
TQFP100V Package Outline and Specification
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0.5 0.1250.1
Pin configuration
B15 B16 B17 R20 R21 R22 R23 R24 R25 R26 R27 VDD GND G20 G21 G22 G23 G24 G25 G26 G27 B20 B21 B22 B23
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
B14 B13 B12 GND VDD B11 B10 G17 G16 G15 G14 G13 G12 G11 G10 R17 R16 R15 R14 GND VDD R13 R12 R11 R10
100-Pin TQFP (Top View)
B24 B25 VDD GND B26 B27 HSYNC VSYNC DE CLKIN RF RS Reserved0 MAP MODE1 MODE0 OE SEL_BIT XRST Reserved1 FLIP N/C PLL GND PLL VCC PLL GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
LVDS GND TA1N TA1P TB1N TB1P LVDS VDD TC1N TC1P TCLK1N TCLK1P TD1N TD1P LVDS GND TA2N TA2P TB2N TB2P LVDS VDD TC2N TC2P TCLK2N TCLK2P TD2N TD2P LVDS GND
Figure-3 Pin Diagram (Top View)
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Pin Description
Table 1 : Pin Description Pin Name TA1P, TA1N TB1P, TB1N TC1P, TC1N TD1P, TD1N TCLK1P, TCLK1N TA2P, TA2N TB2P, TB2N TC2P TC2N TD2P, TD2N TCLK2P, TCLK2N R17R10 G17G10 B17B10 R27R20 G27G20 B27B20 DE VSYNC HSYNC CLKIN MAP XRST FLIP Pin No. 48, 49 46, 47 43, 44 39, 40 41, 42 36, 37 34, 35 31, 32 27, 28 29, 30 60, 59, 58, 57, 54, 53, 52, 51 68, 67, 66, 65, 64, 63, 62, 61 78, 77, 76, 75, 74, 73, 70, 69 86, 85, 84, 83, 82, 81, 80, 79 96, 95, 94, 93, 92, 91, 90, 89 6, 5, 2, 1, 100, 99, 98, 97 9 8 7 10 14 19 21 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN IN IN IN IN IN IN IN IN IN DATA-ENABLE input. VSYNC input. HSYNC input. Clock Input. LVDS mapping table select. See Table11-14 and Figure11-14. H : Normal operation, L : Power down (all outputs are Hi-Z) LVDS output pin select. See Table10. 2 Pixel data inputs. 1 Pixel data input. LVDS clock out LVDS data out LVDS clock out LVDS data out Descriptions
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Pin Name
Pin No.
Type
Descriptions LVDS swing mode, RS select.
RS
12
IN
RS VDD GND
LVDS Swing 350mV 200mV
MODE1, MODE0
15, 16
IN
Pixel Data Mode MODE1 MODE0 L L L H H L H H
Mode Dual-in/Dual-out Dual-in/Single-out Single-in/Dual-out Single-in/Single-out
SEL_BIT
18
IN
6bit/8bit color select. H6bit (TDxP/N*1 are Hi-Z), L8bit. Outputs enable. HOutputs enable, LOutput disable (all outputs are Hi-Z) Input Clock Triggering Select H : Rising edge, L : Falling edge Must be open Must be tied to GND Must be open Power Supply Pins for CMOS inputs, output and digital circuitry. Ground Pins for CMOS inputs, outputs and digital circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply for PLL circuitry. Ground Pin for PLL circuitry. *1: X=1,2
OE
17
IN IN
RF N/C Reserved1 Reserved0 VDD
11 22 20 13 3, 55, 71, 87
IN IN Power
GND LVDS VDD LVDS GND PLL VDD PLL GND
4, 56, 72, 88 33, 45 26, 38, 50 24 23, 25
Ground Power Ground Power Ground
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Electrical characteristics
Rating
Table 2 : Absolute Maximum Rating Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Symbol VDD VIN VOUT Tstg Rating Min -0.3 -0.3 -0.3 -55 Max 4.0 VDD+0.3 VDD+0.3 125 Units V V V
Table 3 : Package Power PACKAGE TQFP100V Power Dissipation (mW) 900 1400*2 De-rating (mW/) *1 9.0 14.0*2
*1:At temperature Ta >25 *2:Package power when mounting on the PCB board. The size of PCB board :70x70x1.6mm3 The material of PCB board : The FR4 glass epoxy board.(3% or less copper foil area) (It is recommended to apply the above package power requirement to PCB board when the small swing input mode is used)
Table 4 : Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Range Symbol Min VDD Topr 3.0 -20 0 Rating Typ 3.3 Max 3.6 85 70 V
VDD,LVDSVDD,PLLVDD Clock frequency from 8MHz up to 90MHz Clock frequency from 90MHz up to 112MHz
Units
Conditions
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DC characteristics
Table 5 : CMOS DC SpecificationsVDD=3.0V3.6V, Ta=-20+85 Rating Symbol Parameter Units Min Typ Max VIH VIL IINC
High Level Input Voltage Low Level Input Voltage
Conditions
VDDx0.8 GND -10
-
VDD VDDx0.2 +10
V V A 0VVINVDD
Input Leak Current
Table 6 : LVDS Transmitter DC SpecificationsVDD=3.0V3.6V, Ta=-20+85 Rating Symbol Parameter Units Conditions Min Typ Max Normal swing 250 350 450 mV RS=VDD Differential Output Voltage VOD RL=100 Reduced 120 200 300 mV swing RS=GND VOD VOC VOC IOS IOZ
Change in VOD between complementary output states Common Mode Voltage Change in VOC between complementary output states Output Short Circuit Current Output TRI-STATE Current
1.125 -10
1.25 -
35 1.375 35 -24 +10
mV V mV mA A VOUT=0V, RL=100 XRST=0V, VOUT=0V to VDD RL=100
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Supply Current
Table 7 : Supply Current VDD=3.3V, Ta=25
Rating Min Typ Max
Symbol
Parameter
Units
Conditions
Transmitter Supply
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD -
10 A mA mA mA mA
MODE[1:0]=H H
-
RS=H
MODE[1:0]=H L MODE[1:0]=L H MODE[1:0]=L L MODE[1:0]=H H MODE[1:0]=H L MODE[1:0]=L H MODE[1:0]=L L MODE[1:0]=H H MODE[1:0]=H L MODE[1:0]=L H MODE[1:0]=L L MODE[1:0]=H H MODE[1:0]=H L MODE[1:0]=L H MODE[1:0]=L L XRST=L f=112MHz RL=100 CL=5pF f=112MHz RL=100 CL=5pF
ITCCG
Current (Gray Scale Pattern)
RS=L
Transmitter Supply
-
RS=H
ITCCW
Current (Worst Case pattern)
RS=L
ITCCS
Transmitter Power Down Supply Current
-
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Gray Scale Pattern
CLK_IN Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 x=1,2
Figure-4 Gray scale pattern
Worst Case Pattern (Maximum Power condition)
CLK_IN Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 x=1,2
Figure-5 Worst Case Pattern
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AC characteristics
Table 8 : Switching Characteristics VDD=3.3V, Ta=25
Symbol Parameter
CLK IN Transition time Dual In /Dual Out
Min
Typ
Max
Units
tTCIT
8.9 17.8 6.7 8.9 0.35tTCP 0.35tTCP 2.5 0 8.9 8.9 13.3 8.9 -0.2
0.5tTCP 0.5tTCP TBD TBD TBD 0.6 0.0
5.0 125.0 62.5 250.0 125.0 0.65tTCP 0.65tTCP 125.0 125.0 125.0 125.0 1.5 +0.2
ns
tTCP
CLK IN Period
Dual In / Single Out Single In / Dual Out Single In / Single Out
ns
tTCH tTCL
CLK IN High Time CLK IN Low Time Dual In /Dual Out Single In/Single Out Dual In / Single Out Single In / Dual Out
ns ns
tTCD
CLK IN to TCLK+/-Delay
ns
tTS tTH
CMOS Data Setup to CLK IN CMOS Data Hold from CLK IN Dual In /Dual Out
ns ns
tTCOP
CLK OUT Period
Dual In / Single Out Single In / Dual Out Single In / Single Out
tLVT tTOP1 tTOP0
LVDS Transition Time Output Data Position 0 Output Data Position 1 Output Data Position 2 Output Data Position 3 Output Data Position 4 Output Data Position 5 Output Data Position 6
ns ns
tTOP6 tTOP5 tTOP4
tTOP3 tTOP2 Tck12 tTPLL
tTCP -0.2 7 tTCP 2 -0.2 7 tTCP 3 -0.2 7 tTCP 4 -0.2 7 tTCP 5 -0.2 7 tTCP 6 -0.2 7
tTCP 7 tTCP 2 7 tTCP 3 7 tTCP 4 7 tTCP 5 7 tTCP 6 7
tTCP +0.2 7 tTCP 2 +0.2 7 tTCP 3 +0.2 7 tTCP 4 +0.2 7 tTCP 5 +0.2 7 tTCP 6 +0.2 7
ns ns ns
ns ns ns ns ms
Skew Time between TCLKXP and TCLKYP Phase Lock Loop Set Time
-
-
0.5 10.0
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AC Timing
AC Timing Diagrams
LVCMOS Input
90% CLK IN 10% tTCIT tTCIT 10% 90%
LVDS Output
Vdiff=(TAP)-(TAN) TAP 5pF TAN LVDS Output Load 100
80% Vdiff 20%
80% 20%
tLVT
tLVT
LVCMOS Input
tTCP tTCH CLKIN
VDD/2 VDD/2 VDD/2 RF=L
tTCL tTS Rxn/Gxn/Bxn HSYNC, VSYNC,DE
VDD/2
RF=H
tTH
VDD/2
TCLK1/2P TCLK1/2N
tTCD
VOC
x=1, 2 y=0-7
Figure-6 AC Timing Diagrams
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AC Timing Diagrams
tTOP2 tTOP3 tTOP4 tTOP5 tTOP6 tTOP0 tTOP1
Tyx+/-
Tyx6
Tyx5
Tyx4
Tyx3
Tyx2
Tyx1
Tyx0
Tyx6
Tyx5
Tyx4
Tyx3
Tyx2
Tyx1
TCLK1+
Vdiff = 0V
Vdiff = 0V
tTCOP
TCLK1P+ tCK12 TCLK2P+
Vdiff = 0V
Vdiff = 0V Note Vdiff = (Tyx+) - (Tyx-), (TCLK1P) - (TCLK1N)
Figure-7 AC Timing Diagrams
X=1.2 Y=A,B,C,D
Phase Lock Loop Set Time
XRST VDD/2 3.6V tTPLL
3.0V VDD
CLKIN Vdiff=0V TCLKP/N
Figure-8 Phase Lock Loop Set Time
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Pixel Map Table for Dual Link
Table 9 : Pixel Map Table for Dual Link 1st Pixel Data TFT Panel Data BU7988KVT Input 24Bit 18Bit LSB R10 R10 R11 R11 R12 R10 R12 R13 R11 R13 R14 R12 R14 R15 R13 R15 R16 R14 R16 MSB R17 R15 R17 LSB G10 G10 G11 G11 G12 G10 G12 G13 G11 G13 G14 G12 G14 G15 G13 G15 G16 G14 G16 MSB G17 G15 G17 LSB B10 B10 B11 B11 B12 B10 B12 B13 B11 B13 B14 B12 B14 B15 B13 B15 B16 B14 B16 MSB B17 B15 B17
2nd Pixel Data TFT Panel Data BU7988KVT Input 24Bit 18Bit LSB R20 R20 R21 R21 R22 R20 R22 R23 R21 R23 R24 R22 R24 R25 R23 R25 R26 R24 R26 MSB R27 R25 R27 LSB G20 G20 G21 G21 G22 G20 G22 G23 G21 G23 G24 G22 G24 G25 G23 G25 G26 G24 G26 MSB G27 G25 G27 LSB B20 B20 B21 B21 B22 B20 B22 B23 B21 B23 B24 B22 B24 B25 B23 B25 B26 B24 B26 MSB B27 B25 B27
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LVDS Data Output Table for Function of FLIP pin
Table 10 : LVDS Data Output Pin Name
Output Pin Names Pin No FLIP=L TA1N TA1P TB1N TB1P TC1N TC1P TCLK1N TCLK1P TD1N TD1P TA2N TA2P TB2N TB2P TC2N TC2P TCLK2N TCLK2P TD2N TD2P FLIP=H TD2P TD2N TCLK2P TCLK2N TC2P TC2N TB2P TB2N TA2P TA2N TD1P TD1N TCLK1P TCLK1N TC1P TC1N TB1P TB1N TA1P TA1N
49 48 47 46 44 43 42 41 40 39 37 36 35 34 32 31 30 29 28 27
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LVCMOS Data Input Timing for Dual Link
Example : SXGA+(1400x1050)
HSYNC
DE
C L K _IN
R 1x/G 1x/B 1x
#1
#3
#5
#7
1395
#1397
#1399
R 2x/G 2x/B 2x x=0 9
#2
#4
#6
#8
1396
#1398
#1400
#1
#2
#1399
#1400
T FT Panel (1 4 0 0 x 1 0 5 0 )
Figure-9 LVCMOS Data Input Timing for Dual Link
LVCMOS Data Input Timing for Single Link
Example : SXGA+(1400x1050)
HSYNC
DE
C L K _IN
R 1x/G 1x/B 1x x=0 9
#1
#2
#3
#4
1398
#1399
#1400
#1
#2
#1399
#1400
TFT Panel (1 4 0 0 x 1 0 5 0 )
Figure-10 LVCMOS Data Input Timing for Single Link
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LVDS Output Data Mapping Dual Link / Single Link
LVDS Data Output
R1n,B1n n=07 VDD DATA1n-1 DATA1n DATA1n+1 GND R2n,B2n n=07 VDD DATA2n-1 DATA2n DATA2n+1 GND
LVCMOS Data Input
Figure-11 LVDS Output Data Mapping
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LVCMOS Data Inputs Timing in Dual Link
Dual-in / Dual-out Mode (MODE<1:0>=LL , FLIP=L)
Table 11 : LVCMOS Data Inputs Timing Diagrams in Dual Link 1st Pixel Data LVDS Output Data (1st Pixel Data) TA10 TA11 TA12 TA13 TA14 TA15 TA16 TB10 TB11 TB12 TB13 TB14 TB15 TB16 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TD10 TD11 TD12 TD13 TD14 TD15 TD16 MAP=H Input Pin Name R12 R13 R14 R15 R16 R17 G12 G13 G14 G15 G16 G17 B12 B13 B14 B15 B16 B17 HSYNC VSYNC DE R10 R11 G10 G11 B10 B11 L MAP=L Input Pin Name R10 R11 R12 R13 R14 R15 G10 G11 G12 G13 G14 G15 B10 B11 B12 B13 B14 B15 HSYNC VSYNC DE R16 R17 G16 G17 B16 B17 L LVDS Output Data (2nd Pixel Data) TA20 TA21 TA22 TA23 TA24 TA25 TA26 TB20 TB21 TB22 TB23 TB24 TB25 TB26 TC20 TC21 TC22 TC23 TC24 TC25 TC26 TD20 TD21 TD22 TD23 TD24 TD25 TD26 2nd Pixel Data MAP=H Input Pin Name R22 R23 R24 R25 R26 R27 G22 G23 G24 G25 G26 G27 B22 B23 B24 B25 B26 B27 HSYNC VSYNC DE R20 R21 G20 G21 B20 B21 L MAP=L Input Pin Name R20 R21 R22 R23 R24 R25 G20 G21 G22 G23 G24 G25 B20 B21 B22 B23 B24 B25 HSYNC VSYNC DE R26 R27 G26 G27 B26 B27 L
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LVCMOS Data Inputs Timing Diagrams in Dual Link
Dual-in / Dual-out Mode (MODE<1:0>=LL, FLIP=L, MAP=H)
LVDS Data Output
R1n,B1n n=07 VDD DATA1n-1 DATA1n DATA1n+1 GND R2n,B2n n=07 VDD DATA2n-1 DATA2n DATA2n+1 GND
LVCMOS Data Input
Figure-12 LVCMOS Data Inputs Timing Diagrams in Dual Link
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LVCMOS Data Inputs Timing in Single Link
Dual-in / Single-out Mode (MODE<1:0>=LH, FLIP=L)
Table 12 : LVCMOS Data Inputs Timing Diagrams in Dual Link
LVDS Mapping Mode1 Mapping Mode2 Output Data (Input Pin Name) (Input Pin Name) (1st Pixel Data) TA10 TA11 TA12 TA13 TA14 TA15 TA16 TB10 TB11 TB12 TB13 TB14 TB15 TB16 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TD10 TD11 TD12 TD13 TD14 TD15 TD16 R12/R22 R13/R23 R14/R24 R15/R25 R16/R26 R17/R27 G12/G22 G13/G23 G14/G24 G15/G25 G16/G26 G17/G27 B12/B22 B13/B23 B14/B24 B15/B25 B16/B26 B17/B27 HSYNC VSYNC DE R10/R20 R11/R21 G10/G20 G11/G21 B10/B20 B11/B21 L R10/R20 R11/R21 R12/R22 R13/R23 R14/R24 R15/R25 G10/G20 G11/G21 G12/G22 G13/G23 G14/G24 G15/G25 B10/B20 B11/B21 B12/B22 B13/B23 B14/B24 B15/B25 HSYNC VSYNC DE R16/R26 R17/R27 G16/G26 G17/G27 B16/B26 B17/B27 L
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LVCMOS Data Inputs Timing Diagrams in Single Link
Dual-in / Single-out Mode (MODE<1:0>=LH, FLIP=L, MAP=H)
LVDS Data Output
R1n,B1n n=07
VDD DATA1n-1 DATA1n DATA1n+1 GND
R2n,B2n n=07
VDD DATA2n-1 DATA2n DATA2n+1 GND
LVCMOS Data Input
Figure-13 LVCMOS Data Inputs Timing Diagrams in Single Link
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LVCMOS Data Inputs Timing in Single Link
Single-in / Dual-out Mode (MODE<1:0>=HH, FLIP=L)
Table 13 : LVCMOS Data Inputs Timing Diagrams in Single Link
1st Pixel Data LVDS Output Data (1st Pixel Data) TA10 TA11 TA12 TA13 TA14 TA15 TA16 TB10 TB11 TB12 TB13 TB14 TB15 TB16 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TD10 TD11 TD12 TD13 TD14 TD15 TD16 MAP=H Input Pin Name R12 R13 R14 R15 R16 R17 G12 G13 G14 G15 G16 G17 B12 B13 B14 B15 B16 B17 HSYNC VSYNC DE R10 R11 G10 G11 B10 B11 L MAP=L Input Pin Name R10 R11 R12 R13 R14 R15 G10 G11 G12 G13 G14 G15 B10 B11 B12 B13 B14 B15 HSYNC VSYNC DE R16 R17 G16 G17 B16 B17 L LVDS Output Data (1st Pixel Data) TA20 TA21 TA22 TA23 TA24 TA25 TA26 TB20 TB21 TB22 TB23 TB24 TB25 TB26 TC20 TC21 TC22 TC23 TC24 TC25 TC26 TD20 TD21 TD22 TD23 TD24 TD25 TD26
2nd Pixel Data MAP=H Input Pin Name R12+1 R13+1 R14+1 R15+1 R16+1 R17+1 G12+1 G13+1 G14+1 G15+1 G16+1 G17+1 B12+1 B13+1 B14+1 B15+1 B16+1 B17+1 HSYNC+1 VSYNC+1 DE+1 R10+1 R11+1 G10+1 G11+1 B10+1 B11+1 L MAP=L Input Pin Name R10+1 R11+1 R12+1 R13+1 R14+1 R15+1 G10+1 G11+1 G12+1 G13+1 G14+1 G15+1 B10+1 B11+1 B12+1 B13+1 B14+1 B15+1 HSYNC+1 VSYNC+1 DE+1 R16+1 R17+1 G16+1 G17+1 B16+1 B17+1 L
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LVCMOS Data Inputs Timing in Dual Link
Single-in / Dual-out Mode (MODE<1:0>=HL, FLIP=L, MAP=H)
LVDS Data Output
R1n,G1n,B1n (n=07)
VDD DATA1n-2 DATA1n-1 DATA1n DATA1n+1 DATA1n+2 DATA1n+3 GND
LVCMOS Data Input
Figure-14 LVCMOS Data Inputs Timing in Dual Link
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LVCMOS Data Inputs Timing in Single Link
Single-in / Single-out Mode (MODE<1:0>=HH, FLIP=L)
Table 14 : LVCMOS Data Inputs Timing Diagrams in Single Link
LVDS Output Data (1st Pixel Data) TA10 TA11 TA12 TA13 TA14 TA15 TA16 TB10 TB11 TB12 TB13 TB14 TB15 TB16 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TD10 TD11 TD12 TD13 TD14 TD15 TD16
MAP=H Input Pin Name R12 R13 R14 R15 R16 R17 G12 G13 G14 G15 G16 G17 B12 B13 B14 B15 B16 B17 HSYNC VSYNC DE R10 R11 G10 G11 B10 B11 L
MAP=L Input Pin Name R10 R11 R12 R13 R14 R15 G10 G11 G12 G13 G14 G15 B10 B11 B12 B13 B14 B15 HSYNC VSYNC DE R16 R17 G16 G17 B16 B17 L
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LVCMOS Data Inputs Timing Diagrams in Single Link
Single-in / Single-out Mode (MODE<1:0>=HH, FLIP=L, MAP=H)
LVDS Data Output
R1n,G1n,B1n (n=07)
VDD DATA1n-1 DATA1n DATA1n+1 GND
LVCMOS Data Input
Figure-15 LVCMOS Data Inputs Timing Diagrams in Single Link
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About the Power On Reset
Power On Reset is not mandatory for this device. The PD pin should be set to high level when Power On Reset procedure is not used.
VDD
XRST BU7988KVT
Figure-16 terminal connection when Power On Reset is not used
However, Power On Reset procedure is strongly recommend for internal logic initialization by following two methods. The method of using CR circuit. The method of using external specific IC. It is recommend to do enough examination for target application.
V DD schottky barrier diode
V DD 10K
VDD
XRST
VT
+
220 Be careful of temperature of the capacitor especially over and again. B characteristic ceramics and polymer aluminum are recommended. 2.2F
XRST Internal Reset td td is approximately equal to 20ms when the left RC coleus are applied.
Figure-17 Power On Reset by external a CR circuit
V DD VDD power on IC (open drain output) VOUT
V DD 220K XRST XRST 0.1F Internal Reset td Detection voltage VDD
VT
+
GND
B Characteristic ceramics.
Figure-18 Power On Reset by specific IC
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TQFP100V

16.0 0.3 14.0 0.2
75 76 51 50

Container Quantity Direction of feed
0.5
Tray(with dry pack) 500pcs Direction of product is fixed in a tray.
16.0 0.3 14.0 0.2
100 1 25
26
1.2Max. 1.0 0.1 0.1 0.1
0.125 0.1
0.5
0.2 0.1
0.1
Unit:mm)
1pin
When you order , please order in times the amount of package quantity.
Catalog No.08T241A '08.6 ROHM (c)

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