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Ultralow Distortion, Low Power, Low Noise, High Speed Op Amp ADA4857-1/ADA4857-2
FEATURES
High speed 850 MHz, -3 dB bandwidth (G = +1, RL = 1 k, LFSCP) 750 MHz, -3 dB bandwidth (G = +1, RL = 1 k, SOIC) 2800 V/s slew rate Low distortion: -88 dBc @ 10 MHz (G = +1, RL = 1 k) Low power: 5 mA/amplifier @ 10 V Low noise: 4.4 nV/Hz Wide supply voltage range: 5 V to 10 V Power-down feature Available in 3 mm x 3 mm 8-lead LFCSP (single), 8-lead SOIC (single), and 4 mm x 4 mm 16-lead LFCSP (dual)
CONNECTION DIAGRAMS
ADA4857-1
TOP VIEW (Not to Scale)
PD 1 FB 2 -IN 3 +IN 4 NC = NO CONNECT
8 +VS 7 OUT 6 NC 5 -VS
07040-001
Figure 1. 8-Lead LFCSP (CP)
ADA4857-1
TOP VIEW (Not to Scale) FB 1 -IN 2 +IN 3 -VS 4
8 7 6 5
APPLICATIONS
Instrumentation IF and baseband amplifiers Active filters ADC drivers DAC buffers
PD +VS OUT
07040-002
07040-003
NC
NC = NO CONNECT
Figure 2. 8-Lead SOIC (R)
ADA4857-2
TOP VIEW (Not to Scale)
15 PD1
16 FB1
13 OUT1
12 -VS1 11 NC 10 +IN2 9 -IN2
-IN1 1 +IN1 2 NC 3 -VS2 4
14 +VS1 PD2 7
NC = NO CONNECT
Figure 3. 16-Lead LFCSP (CP)
GENERAL DESCRIPTION
The ADA4857 is a unity gain stable, high speed, voltage feedback amplifier with low distortion, low noise, and high slew rate. With a spurious-free dynamic range (SFDR) of -88 dBc @ 10 MHz, the ADA4857 is an ideal solution in a variety of applications including ultrasounds, ATE, active filters, and ADC drivers. The Analog Devices, Inc., proprietary next-generation XFCB process and innovative architecture enables such high performance amplifiers. The ADA4857 has 850 MHz bandwidth, 2800 V/s slew rate, and settles to 0.1% in 15 ns. With a wide supply voltage range (5 V to 10 V), the ADA4857 is an ideal candidate for systems that require high dynamic range, precision, and speed. The ADA4857-1 amplifier is available in a 3 mm x 3 mm, 8-lead LFCSP and a standard 8-lead SOIC. The ADA4857-2 is available in a 4 mm x 4 mm, 16-lead LFSCP. The LFCSP features an exposed paddle that provides a low thermal resistance path to the PCB. This path enables more efficient heat transfer and increases reliability. The ADA4857 works over the extended industrial temperature range (-40C to +125C).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
OUT2 5
+VS2 6
FB2 8
ADA4857-1/ADA4857-2 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Connection Diagrams...................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Supply ................................................................................... 3 +5 V Supply ................................................................................... 4 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ..............................................9 Test Circuits..................................................................................... 15 Applications Information .............................................................. 16 PD Pin Operation....................................................................... 16 Capacitive Load Considerations .............................................. 16 Recommended Values for Various Gains................................ 16 Noise ............................................................................................ 17 Circuit Considerations .............................................................. 17 PCB Layout ................................................................................. 17 Power Supply Bypassing ............................................................ 17 Grounding ................................................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19
REVISION HISTORY
5/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADA4857-1/ADA4857-2 SPECIFICATIONS
5 V SUPPLY
TA = 25C, G = +2, RG = RF = 499 , RL = 1 k to ground, PD = no connect, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth (LFCSP/SOIC) Conditions G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p, THD < -40 dBc G = +2, VOUT = 2 V p-p, RL = 150 G = +1, VOUT = 4 V step G = +2, VOUT = 2 V step f = 1 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 1 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 100 kHz f = 100 kHz Min 650 Typ 850/750 600/550 400/350 110 75/90 2800 15 -108 -108 -88 -93 -65 -62 4.4 1.5 2 2.3 -2 24.5 50 57 (VCC - 2) (VCC - 4.2) 55 33 58 80 8 4 2 4 -86 10 4 3.7 50 125 10 4.5 -3.3 Max Unit MHz MHz MHz MHz MHz V/s ns dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz mV V/C A nA/C nA dB V V s ns A A M M pF V dB ns V V mA mA pF
Full Power Bandwidth Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) Slew Rate (10% to 90%) Settling Time to 0.1% NOISE/Harmonic PERFORMANCE Harmonic Distortion
Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain PD (Power-Down) Pin PD Input Voltage Turn-Off Time Turn-On Time PD Pin Leakage Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive
VOUT = -2.5 V to +2.5 V Chip powered down Chip enabled 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 Chip enabled Chip powered down Common mode Differential mode Common mode VCM = 1 V VIN = 2.5 V, G = +2 RL = 1 k RL = 100 Sinking and sourcing 30% overshoot, G = +2 -78
Rev. 0 | Page 3 of 20
ADA4857-1/ADA4857-2
Parameter POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Power Down) Positive Power Supply Rejection Negative Power Supply Rejection Conditions Min 4.5 PD VCC - 2 V +VS = 4.5 V to 5.5 V, -VS = -5 V +VS = 5 V, -VS = -4.5 V to -5.5 V 5 350 -62 -68 Typ Max 10.5 5.5 450 Unit V mA A dB dB
-59 -65
+5 V SUPPLY
TA = 25C, G = +2, RF = RG = 499 , RL = 1 k to midsupply, PD = no connect, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth (LFCSP/SOIC) Conditions G = +1, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.2 V p-p G = +1, VOUT = 2 V p-p, THD < -40 dBc G = +2, VOUT = 2 V p-p, RL = 150 G = +1, VOUT = 2 V step G = +2, VOUT = 2 V step f = 1 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 1 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 10 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD2) f = 50 MHz, G= +1, VOUT = 2 V p-p (HD3) f = 100 kHz f = 100 kHz Min 595 Typ 800/750 500/400 360/300 95 50/40 1500 15 -92 -90 -81 -71 -69 -55 4.4 1.5 1 4.6 -1.7 24.5 50 57 (VCC - 2) (VCC - 4.2) 38 30 8 30 8 4 2 1 to 4 -84 4.2 -3.3 Max Unit MHz MHz MHz MHz MHz V/s ns dBc dBc dBc dBc dBc dBc nV/Hz pA/Hz mV V/C A nA/C nA dB V V s ns A A M M pF V dB
Full Power Bandwidth Bandwidth for 0.1 dB Flatness (LFCSP/SOIC) Slew Rate (10% to 90%) Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion
Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain PD (Power-Down) Pin PD Input Voltage Turn-Off Time Turn-On Time PD Pin Leakage Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio
VOUT = 1.25 V to 3.75 V Chip powered down Chip enabled 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 50% off PD to <10% of final VOUT, VIN = 1 V, G = +2 Chip enable Chip powered down Common mode Differential mode Common mode VCM = 2 V to 3 V -76
Rev. 0 | Page 4 of 20
ADA4857-1/ADA4857-2
Parameter OUTPUT CHARACTERISTICS Overdrive Recovery Time Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Power Down) Positive Power Supply Rejection Negative Power Supply Rejection Conditions G = +2 RL = 1 k RL = 100 Sinking and sourcing 30% overshoot, G = +2 4.5 PD VCC - 2 V +VS = 4.5 V to 5.5 V, -VS = 0 V +VS = 5 V, -VS = -0.5 V to +0.5 V 4.5 250 -62 -68 Min Typ 15 1 to 4 1.1 to 3.9 50 75 10 10.5 5 350 Max Unit ns V V mA mA pF V mA A dB dB
-58 -65
Rev. 0 | Page 5 of 20
ADA4857-1/ADA4857-2 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Exposed Paddle Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 11 V See Figure 4 -VS + 0.7 V to +VS - 0.7 V VS -VS -65C to +125C -40C to +125C 300C 150C
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4857 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). PD = Quiescent Power + (Total Drive Power - Load Power)
V V PD = (VS x I S ) + S x OUT 2 RL
VOUT 2 - RL
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RMS output voltages should be considered. If RL is referenced to -VS, as in single-supply operation, the total drive power is VS x IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS x I S ) +
(VS /4 )2
RL
In single-supply operation with RL referenced to -VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduce JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOIC and LFCSP packages on a JEDEC standard 4-layer board. JA values are approximations.
3.0
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for device soldered in circuit board for surface-mount packages. Table 4.
Package Type 8-Lead SOIC 8-Lead LFCSP 16-Lead LFSCP JA 115 94.5 68.2 JC 15 34.8 19 Unit C/W C/W C/W
MAXIMUM POWER DISSIPATION (W)
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4857 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4857. Exceeding a junction temperature of 175C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality.
2.5
2.0 ADA4857-2 (LFCSP) 1.5
1.0 ADA4857-1 (LFCSP) 0.5 ADA4857-1 (SOIC)
07040-004
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. 0 | Page 6 of 20
ADA4857-1/ADA4857-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PD 1 FB 2 -IN 3 +IN 4 NC = NO CONNECT
ADA4857-1
TOP VIEW (Not to Scale)
8 +VS 7 OUT 6 NC 5 -VS
07040-005
FB 1 -IN 2
8
PD
NC = NO CONNECT
Figure 5. 8-Lead LFCSP Pin Configuration
Figure 6. 8-Lead SOIC Pin Configuration
Table 5. 8-Lead LFCSP Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic PD FB -IN +IN -VS NC OUT +VS Description Power Down Feedback Inverting Input Noninverting Input Negative Supply No Connect Output Positive Supply
Table 6. 8-Lead SOIC Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic FB -IN +IN -VS NC OUT +VS PD Description Feedback Inverting Input Noninverting Input Negative Supply No Connect Output Positive Supply Power Down
Rev. 0 | Page 7 of 20
07040-006
+VS TOP VIEW +IN 3 (Not to Scale) 6 OUT -VS 4 5 NC
7
ADA4857-1
ADA4857-1/ADA4857-2
15 PD1 16 FB1 13 OUT1
12 -VS1 11 NC 10 +IN2 9 -IN2
-IN1 1 +IN1 2 NC 3 -VS2 4
ADA4857-2
TOP VIEW (Not to Scale)
14 +VS1 PD2 7
OUT2 5
+VS2 6
FB2 8
NC = NO CONNECT
Figure 7. 16-Lead LFCSP Pin Configuration
Table 7. 16-Lead LFCSP Pin Function Descriptions
Pin No. 1 2 3, 11 4 5 6 7 8 9 10 12 13 14 15 16 Mnemonic -IN1 +IN1 NC -VS2 OUT2 +VS2 PD2 FB2 -IN2 +IN2 -VS1 OUT1 +VS1 PD1 FB1 Description Inverting Input 1 Noninverting Input 1 No Connect Negative Supply 2 Output 2 Positive Supply 2 Power Down 2 Feedback 2 Inverting Input 2 Noninverting Input 2 Negative Supply 1 Output 1 Positive Supply 1 Power Down 1 Feedback 1
Rev. 0 | Page 8 of 20
07040-007
ADA4857-1/ADA4857-2 TYPICAL PERFORMANCE CHARACTERISTICS
T = 25C, (G = +1, RF = 0 , RG open and G = +2, RF = RG = 499 ), unless otherwise noted.
3 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1 VS = 5V RL = 1k VOUT = 0.2V p-p
07040-008
NORMALIZED CLOSED-LOOP GAIN (dB)
NORMALIZED CLOSED-LOOP GAIN (dB)
2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1 VS = 5V RL = 1k VOUT = 2V p-p 10 100 FREQUENCY (MHz) 1000
07040-011
07040-013 07040-012
G = +1 G = +2
G = +1 G = +2
G = +10 G = +5
G = +10 G = +5
10
100 FREQUENCY (MHz)
1000
Figure 8. Small Signal Frequency Responses for Various Gains (LFCSP)
3 2 1
Figure 11. Large Signal Frequency Responses for Various Gains (LFCSP)
9 8 7 6 10pF 5pF
CLOSED-LOOP GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1 G = +1 RL = 1k VOUT = 0.2V p-p 10 100 FREQUENCY (MHz) 1000
07040-009
CLOSED-LOOP GAIN (dB)
0
5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 1 G = +2 VS = 5V RL = 1k VOUT = 0.2V p-p 10 100 FREQUENCY (MHz) 1000 NO CAP LOAD
5V
+5V
Figure 9. Small Signal Frequency Response for Various Supply Voltages (LFCSP)
3 2 1
Figure 12. Small Signal Frequency Response for Various Capacitive Loads (LFCSP)
3 2 1 1V p-p
CLOSED-LOOP GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 -8 G = +1 VS = 5V -9 RL = 1k VOUT = 0.2V p-p -10 1 10
-40C
CLOSED-LOOP GAIN (dB)
0
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 G = +1 VS = 5V RL = 100 1 10 100 FREQUENCY (MHz) 1000 4V p-p
+25C +125C
100 FREQUENCY (MHz)
1000
Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP)
07040-010
-10
Figure 13. Large Signal Frequency Response vs. VOUT (LFCSP)
Rev. 0 | Page 9 of 20
ADA4857-1/ADA4857-2
9 8 7 6 RL = 1k 3 2 1
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 1 G = +2 VS = 5V VOUT = 0.2V p-p
07040-014
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 G = +1 VS = 5V VOUT = 2V p-p 1 10 100 FREQUENCY (MHz) RL = 100
RL = 1k
RL = 100
10
100 FREQUENCY (MHz)
1000
1000
Figure 14. Small Signal Frequency Response for Various Resistive Loads (LFCSP)
3
Figure 17. Large Signal Frequency Response for Various Resistive Loads (LFCSP)
3
NORMALIZED CLOSED-LOOP GAIN (dB)
NORMALIZED CLOSED-LOOP GAIN (dB)
2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1 VS = 5V RL = 1k VOUT = 0.2V p-p
07040-015
2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1 VS = 5V RL = 1k VOUT = 0.2V p-p 10 100 FREQUENCY (MHz) G = +10 G = +5
G = +1
G = +1
G = +2
G = +2
G = +10 G = +5
10
100 FREQUENCY (MHz)
1000
1000
Figure 15. Small Signal Frequency Response for Various Gains (LFCSP)
-40 -50 -60
Figure 18. Small Signal Frequency Response for Various Gains (SOIC)
-40 -50 -60
VS = 5V VOUT = 2V p-p RL= 1k
G = +1 VS = 5V VOUT = 2V p-p
DISTORTION (dBc)
-70 -80 G = +2, HD2 -90 -100 -110
G = +1, HD2
DISTORTION (dBc)
RL = 100, HD3 -70 -80 -90 RL = 1k, HD2 -100 -110 RL = 100, HD2
G = +1, HD3
G = +2, HD3
07040-016
RL = 1k, HD3 1 10 FREQUENCY (MHz) 100
07040-019
-120 0.2
1
10 FREQUENCY (MHz)
100
-120 0.2
Figure 16. Harmonic Distortion vs. Frequency and Gain (LFCSP)
Figure 19. Harmonic Distortion vs. Frequency and Load (LFCSP)
Rev. 0 | Page 10 of 20
07040-018
07040-017
-10
ADA4857-1/ADA4857-2
-40 -50 -60 -70 -80 -90 -100 -110
07040-020
G = +2 VS = 5V RL= 1k HD3, f = 10MHz
0.5 0.4 0.3 SETTLING TIME (%) 0.2 0.1 OUTPUT 0 -0.1 -0.2 -0.3 -0.4 INPUT
07040-023
VOUT = 2V p-p G = +2 VS = 5
DISTORTION (dBc)
HD2, f = 10MHz
HD3, f = 1MHz HD2, f = 1MHz
-120
1
2
3
4
5
6
7
8
-0.5
TIME (5ns/DIV)
OUTPUT VOLTAGE (V p-p)
Figure 20. Harmonic Distortion vs. Output Voltage
6.3
Figure 23. Short-Term Settling Time (LFCSP)
6.3
6.2
VS = 5V G = +2 RL= 150
6.2
VS = 5V G = +2 RL= 150
CLOSED-LOOP GAIN (dB)
6.1 VOUT = 2V p-p 6.0
CLOSED-LOOP GAIN (dB)
6.1
6.0 VOUT = 2V p-p 5.9 VOUT = 0.2V p-p 5.8
5.9 VOUT = 0.2V p-p
5.8
07040-021
1
10 FREQUENCY (MHz)
100
1
10 FREQUENCY (MHz)
100
Figure 21. 0.1 dB Flatness vs. Frequency for Various Output Voltages (SOIC)
2.5 4V p-p 2.0 1.5 2V p-p
OUTPUT VOLTAGE (V)
Figure 24. 0.1 dB Flatness vs. Frequency for Various Output Voltages (LFCSP)
2.5
VS = 5V RL = 1k G = +2
4V p-p
2.0 1.5
OUTPUT VOLTAGE (V)
VS = 5V RL = 1k G = +1
1.0 0.5 0 -0.5 -1.0 -1.5
07040-022
2V p-p 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 TIME (10ns/DIV)
07040-025
-2.0 -2.5 TIME (10ns/DIV)
Figure 22. Large Signal Transient Response for Various Output Voltages (SOIC)
Figure 25. Large Signal Transient Response for Various Output Voltages (LFCSP)
Rev. 0 | Page 11 of 20
07040-024
5.7
5.7
ADA4857-1/ADA4857-2
0.25 0.20 0.15
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.0 VS = 5V RL = 1k G = +1 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2
07040-026
VS = 5V G = +2
0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 TIME (10ns/DIV) CL = 10pF CL = 1.5pF
RL = 1k
-1.6 -2.0 TIME (10ns/DIV)
Figure 26. Small Signal Transient Response for Various Capacitive Loads (LFCSP)
0.25 0.20 0.15 VS = 5V RL = 1k G = +1
Figure 29. Large Signal Transient Response for Various Load Resistances (SOIC)
2.0 1.6 1.2
OUTPUT VOLTAGE (V)
VS = 5V G = +1 RL = 1k
OUTPUT VOLTAGE (V)
0.10 0.05 0 -0.05 -0.10 -0.15
07040-027
0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 TIME (10ns/DIV)
07040-030
VS = 2.5V
-0.20 -0.25 TIME (10ns/DIV)
RL = 100
Figure 27. Small Signal Transient Response for Various Supply Voltages (LFCSP)
1000
CLOSED-LOOP OUTPUT IMPEDANCE ()
Figure 30. Large Signal Transient Response for Various Load Resistances (LFCSP)
100
VS = 5V
CLOSED-LOOP INPUT IMPEDANCE (k)
VS = 5V G = +2
100
10
10
1
1
G = +5
G = +2
0.1
07040-028
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 28. Output Impedance vs. Frequency for Various Gains
Figure 31. Closed-Loop Input Impedance vs. Frequency
Rev. 0 | Page 12 of 20
07040-031
0.1 0.1
0.01
07040-029
RL = 100
ADA4857-1/ADA4857-2
70 60 50 40 30 -100 20 10 0 -10 0.1 -120 -140 -160
07040-032
PHASE
VS = 5V RL = 1k
0 -20 -40
OPEN-LOOP PHASE (Degrees)
0 -10 -20
G = +2 VS = 5V RL = 1k PD = 3V
SOIC
OPEN-LOOP GAIN (dB)
-60 -80
PD ISOLATION (dB)
GAIN
-30 -40 -50 LFCSP -60 -70 -80 -90 1 10 FREQUENCY (MHz) 100 1000
07040-035 07040-037 07040-036
1
10 FREQUENCY (MHz)
100
-180 1000
-100 0.1
Figure 32. Open-Loop Gain and Phase vs. Frequency
8 6 4
OUTPUT VOLTAGE (V)
8 6 4
Figure 35. PD Isolation vs. Frequency
VS = 5V G = +1
VS = 5V G = +2
2 0 -2 -4
07040-033
OUTPUT VOLTAGE (V)
2 0 -2 -4 -6 -8 TIME (200ns/DIV) 2 x INPUT OUTPUT RL = 1k
OUTPUT RL = 100
-6 -8
OUTPUT RL = 1k INPUT TIME (40ns/DIV)
OUTPUT RL = 100
Figure 33. Input Overdrive Recovery for Various Resistive Loads
10 0 -10 -20 -30 -40 -50 -60 +PSRR
Figure 36. Output Overdrive Recovery for Various Resistive Loads
-30
VS = 5V RL= 1k
VS = 5V RL= 1k
-40
-50
CMRR (dB)
-PSRR 1 10 FREQUENCY (MHz) 100 1000
07040-034
PSRR (dB)
-60
-70
-80 -70 -80 0.1 -90 0.1
1
10 FREQUENCY (MHz)
100
1000
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 37. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. 0 | Page 13 of 20
ADA4857-1/ADA4857-2
100 VS = 5V 1000 VS = 5V
CURRENT NOISE (pA/Hz)
VOLTAGE NOISE (nV/Hz)
07040-050
100
10
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38. Input Current Noise vs. Frequency
3.5 3.0 2.5
VOLTAGE (V)
Figure 40. Input Voltage Noise vs. Frequency
50 N = 238 MEAN: 5.00 SD: 0.02 40
PD INPUT
COUNT
30
2.0 1.5 1.0 0.5 OUTPUT
20
10
07040-043
0
07040-042
0 4.85
4.90
4.95
5.00
5.05
5.10
5.15
-0.5 TIME (20s/DIV)
SUPPLY CURRENT (mA)
Figure 39. Supply Current
Figure 41. Disable/Enable Switching Speed
Rev. 0 | Page 14 of 20
07040-041
1 10
1
ADA4857-1/ADA4857-2 TEST CIRCUITS
+VS 10F
+VS 10F
+
+
0.1F VIN 49.9 10F 0.1F VOUT RL
RG
RF 0.1F 0.1F 40 RSNUB 49.9 10F
+
07040-049
VIN
07040-047
VOUT CL RL
+
0.1F -VS
0.1F -VS
Figure 42. Noninverting Load Configuration
+VS AC 49.9
Figure 45. Typical Capacitive Load Configuration
+VS 10F
+
0.1F VOUT RL 49.9 RL AC
07040-045
VOUT
10F
+
-VS
-VS
Figure 43. Positive Power Supply Rejection
+VS 10F
+
Figure 46. Negative Power Supply Rejection
1k 1k VIN 1k 53.6 1k 10F
+
07040-046
0.1F
0.1F VOUT RL
0.1F -VS
Figure 44. Common-Mode Rejection
Rev. 0 | Page 15 of 20
07040-048
0.1F
ADA4857-1/ADA4857-2 APPLICATIONS INFORMATION
PD PIN OPERATION
The PD pin is used to power down the chip, which reduces the quiescent current and the overall power consumption. It is low enabled which means that the chip is on with full power when the PD pin input voltage is low (see Table 8). Note that PD does not put the output in a high-Z state, which means that the ADA4857 should not be used as a multiplexer.
Table 8. PD Operation Table Guide
PD Pin Voltage +0.8 V +3 V -1.7 V +0.5 V +0.8 V +3 V No connect Supply Voltage 5 V 5 V 2.5 V 2.5 V +5 V +5 V All Chip Enabled Powered down Enabled Powered down Enabled Powered down Enabled
CAPACITIVE LOAD CONSIDERATIONS
When driving a capacitive load, RSNUB is used to reduce the peaking (see Figure 45). An optimum resistor value of 40 is found to maintain the peaking within 1 dB for any capacitive load up to 40 pF.
B
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 9 provides a useful reference for determining various gains and associated performance. Resistors RF and RG are kept low to minimize their contribution to the overall noise performance of the amplifier.
Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = 5 V, TA = 25C, RL = 1 k, RT = 49.9
Gain +1 +2 +5 +10 RF () 0 499 499 499 RG () N/A 499 124 56.2 -3 dB SS BW (MHz), VOUT = 200 mV p-p 850 360 90 43 Slew Rate (V/s), VOUT = 2 V Step 2350 1680 516 213 ADA4857 Voltage Noise (nV/Hz), RTO 4.4 8.8 22.11 43.47 Total System Noise (nV/Hz), RTO 4.49 9.89 23.49 45.31
Rev. 0 | Page 16 of 20
ADA4857-1/ADA4857-2
NOISE
To analyze the noise performance of an amplifier circuit, identify the noise sources and then determine if the source has a significant contribution to the overall noise performance of the amplifier. To simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nV/Hz, is equivalent to the noise in a 1 Hz bandwidth). The noise model shown in Figure 47 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally referred to input (RTI), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise.
VN, R2 4kTR2 B VN, R1 4kTR1 VN, R3 4kTR3 R1 IN- VN R3 IN+ R2 GAIN FROM = A TO OUTPUT NOISE GAIN = R2 NG = 1 + R1 VOUT GAIN FROM = - R2 B TO OUTPUT R1
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the ADA4857 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier.
PCB LAYOUT
Because the ADA4857 can operate up to 850 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4857 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on the SOIC footprint can add as much as 0.2 pF of capacitance to ground if the ground plane is not cleared from under the mounting pads. The low distortion pinout of the ADA4857 increases the separation distance between the inputs and the supply pins, which improves the second harmonics. In addition, the feedback pin reduces the distance between the output and the inverting input of the amplifier, which helps minimize the parasitic inductance and capacitance of the feedback path, reducing ringing and peaking.
A
POWER SUPPLY BYPASSING
Power supply bypassing for the ADA4857 was optimized for frequency response and distortion performance. Figure 42 shows the recommended values and location of the bypass capacitors. The 0.1 F bypassing capacitors should be placed as close as possible to the supply pins. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The capacitor between the two supplies helps improve PSR and distortion performance. The 10 F electrolytic capacitors should be close to the 0.1 F capacitors but it is not as critical. In some cases, additional paralleled capacitors can help improve frequency and transient response.
VN2 + 4kTR3 + 4kTR1 RTI NOISE =
R2 R1 + R2
2
2
RTO NOISE = NG x RTI NOISE
Figure 47. Op Amp Noise Analysis Model
All resistors have a Johnson noise that is calculated by
(4kBTR) .
where: k is Boltzmann's Constant (1.38 x 10-23 J/K). B is the bandwidth in Hertz. T is the absolute temperature in Kelvin. R is the resistance in ohms. A simple relationship that is easy to remember is that a 50 resistor generates a Johnson noise of 1 nV/Hz at 25C. In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table 9.
07040-073
+ IN+2R32 + IN-2 R1 x R2 R1 + R2
+ 4kTR2
R1 R1 + R2
2
GROUNDING
Ground and power planes should be used where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input, output terminations, bypass capacitors, and RG should all be kept as close to the ADA4857 as possible. The output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, overshoot and to improve distortion performance. The ADA4857 LFSCP packages feature an exposed paddle. For optimum electrical and thermal performance, solder this paddle to ground. For more information on high speed circuit design, see A Practical Guide to High-Speed Printed-Circuit-Board Layout at www.analog.com.
Rev. 0 | Page 17 of 20
ADA4857-1/ADA4857-2 OUTLINE DIMENSIONS
3.25 3.00 SQ 2.75 0.60 MAX 0.60 MAX
5 8
0.50 BSC
PIN 1 INDICATOR
TOP VIEW
2.95 2.75 SQ 2.55
EXPOSED PAD
(BOT TOM VIEW)
1.60 1.45 1.30 PIN 1 INDICATOR
4
1
0.90 MAX 0.85 NOM SEATING PLANE
12 MAX
0.70 MAX 0.65 TYP
0.50 0.40 0.30 0.05 MAX 0.01 NOM
1.89 1.74 1.59
Figure 48. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters
5.00 (0.1968) 4.80 (0.1890)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 49. 8-Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches)
4.00 BSC SQ
0.60 MAX 0.60 MAX 0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50
(BOTTOM VIEW)
PIN 1 INDICATOR
13 12
16
PIN 1 INDICATOR
1
TOP VIEW
2.25 2.10 SQ 1.95
5 4
9
8
0.25 MIN 1.95 BSC
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 50. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters
Rev. 0 | Page 18 of 20
021207-A
SEATING PLANE
0.35 0.30 0.25
0.20 REF
COPLANARITY 0.08
012407-A
061507-B
0.30 0.23 0.18
0.20 REF
ADA4857-1/ADA4857-2
ORDERING GUIDE
Model ADA4857-1YCPZ-R2 1 ADA4857-1YCPZ-RL1 ADA4857-1YCPZ-R71 ADA4857-1YRZ1 ADA4857-1YRZ-R71 ADA4857-1YRZ-RL1 ADA4857-2YCPZ-R21 ADA4857-2YCPZ-RL1 ADA4857-2YCPZ-R71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-lead SOIC_N 8-lead SOIC_N 8-lead SOIC_N 16-Lead LFSCP_VQ 16-Lead LFSCP_VQ 16-Lead LFSCP_VQ
Package Option CP-8-2 CP-8-2 CP-8-2 R-8 R-8 R-8 CP-16-4 CP-16-4 CP-16-4
Ordering Quantity 250 5,000 1,500 250 5,000 1,500 250 5,000 1,500
Branding H15 H15 H15
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADA4857-1/ADA4857-2 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07040-0-5/08(0)
Rev. 0 | Page 20 of 20

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