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STK15C88
256 Kbit (32K x 8) PowerStore nvSRAM
Features

Functional Description
The Cypress STK15C88 is a 256Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrapTM technology producing the world's most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. PowerStore nvSRAM products depend on the intrinsic system capacitance to maintain system power long enough for an automatic store on power loss. If the power ramp from 5 volts to 3.6 volts is faster than 10 ms, consider our 14C88 or 16C88 for more reliable operation.
25 ns and 45 ns access times Pin compatible with industry standard SRAMs Automatic nonvolatile STORE on power loss Nonvolatile STORE under Software control Automatic RECALL to SRAM on power up Unlimited Read/Write endurance Unlimited RECALL cycles 1,000,000 STORE cycles 100 year data retention Single 5V+10% power supply Commercial and Industrial Temperatures 28-pin (300 mil and 330 mil) SOIC packages RoHS compliance
Logic Block Diagram
Cypress Semiconductor Corporation Document Number: 001-50593 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 29, 2009
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STK15C88
Pin Configurations
Figure 1. Pin Diagram - 28-Pin SOIC
Table 1. Pin Definitions - 28-Pin SOIC Pin Name A0-A14 DQ0-DQ7 WE CE OE VSS VCC W E G Alt IO Type Input Input or Output Input Input Input Ground Description Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. Bidirectional Data IO lines. Used as input or output lines depending on operation. Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 001-50593 Rev. **
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STK15C88
Device Operation
The STK15C88 is a versatile memory chip that provides several modes of operation. The STK15C88 can operate as a standard 32K x 8 SRAM. It has a 32K x 8 nonvolatile element shadow to which the SRAM information can be copied, or from which the SRAM can be updated in nonvolatile mode.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK15C88 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation.
SRAM Read
The STK15C88 performs a READ cycle whenever CE and OE are LOW while WE is HIGH. The address specified on pins A0-14 determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0-7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The STK15C88 uses the intrinsic system capacitance to perform an automatic STORE on power down. As long as the system power supply takes at least tSTORE to decay from VSWITCH down to 3.6V, the STK15C88 will safely and automatically store the SRAM data in nonvolatile elements on power down. In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. If the STK15C88 is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC.
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STK15C88
Hardware Protect
The STK15C88 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage conditions. When VCAPNoise Considerations
The STK15C88 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the STK15C88 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 2 and Figure 3 show the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK15C88 depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for accesses 3. The ratio of READs to WRITEs 4. CMOS versus TTL input levels 5. The operating temperature 6. The VCC level 7. IO loading Figure 2. Current Versus Cycle Time (WRITE)
Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites, sometimes, reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume a NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration and cold or warm boot status should always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs and incoming inspection routines).
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STK15C88
Table 2. Software STORE/RECALL Mode Selection CE L WE H A13 - A0 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0FC0 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL IO Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Notes
[1, 2]
L
H
[1, 2]
Notes 1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. 2. While there are 15 addresses on the STK15C88, only the lower 14 are used to control software modes.
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STK15C88
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Temperature under bias .............................. -55C to +125C Supply Voltage on VCC Relative to GND.......... -0.5V to 7.0V Voltage on Input Relative to Vss ............-0.6V to VCC + 0.5V Voltage on DQ0-7 ...................................-0.5V to Vcc + 0.5V Power Dissipation ......................................................... 1.0W DC output Current (1 output at a time, 1s duration) .... 15 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 4.5V to 5.5V 4.5V to 5.5V
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V) Parameter ICC1 Description Test Conditions Min Max 97 70 100 70 3 10 Unit mA mA mA mA mA mA Average VCC Current tRC = 25 ns Commercial tRC = 45 ns Dependent on output loading and cycle rate. Values Industrial obtained without output loads. IOUT = 0 mA. Average VCC Current All Inputs Do Not Care, VCC = Max during STORE Average current for duration tSTORE Average VCC Current WE > (VCC - 0.2V). All other inputs cycling. at tRC= 200 ns, 5V, Dependent on output loading and cycle rate. Values obtained without output loads. 25C Typical Average Current during AutoStore Cycle All Inputs Do Not Care, VCC = Max Average current for duration tSTORE Commercial Industrial
ICC2 ICC3
ICC4 ISB1[3]
2
mA
Average VCC Current tRC=25ns, CE > VIH tRC=45ns, CE > VIH (Standby, Cycling TTL Input Levels)
30 22 31 23 1.5
mA mA mA
ISB2[3]
VCC Standby Current CE > (VCC - 0.2V). All others VIN < 0.2V or > (VCC - 0.2V). (Standby, Stable CMOS Input Levels) Input Leakage Current Off State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOUT = -4 mA Output LOW Voltage IOUT = 8 mA VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL -1 -5 2.2 VSS - 0.5 2.4
IIX IOZ VIH VIL VOH VOL
+1 +5 VCC + 0.5 0.8
A A V V V
0.4
V
Note 3. CE > VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
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STK15C88
Data Retention and Endurance
Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 100 1,000 Unit Years K
Capacitance
In the following table, the capacitance parameters are listed.[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V Max 5 7 Unit pF pF
Thermal Resistance
Parameter
In the following table, the thermal resistance parameters are listed.[4] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 28-SOIC (300 mil) TBD TBD 28-SOIC (330 mil) TBD TBD Unit C/W C/W
JA JC
Figure 4. AC Test Loads R1 480 5.0V Output 30 pF R2 255
AC Test Conditions
Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels ................... 1.5 V
Note 4. These parameters are guaranteed by design and are not tested.
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STK15C88
AC Switching Characteristics
SRAM Read Cycle
Parameter Cypress Alt Parameter tACE tELQV [5] tAVAV, tELEH tRC tAA [6] tAVQV tDOE tGLQV tAXQX tOHA [6] tLZCE [7] tELQX tHZCE [7] tEHQZ [7] tGLQX tLZOE tHZOE [7] tGHQZ tPU [4] tELICCH tEHICCL tPD [4] 25 ns Description Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Min 25 25 10 5 5 10 0 10 0 25 0 45 0 15 5 5 15 Max 25 45 45 20 45 ns Min Max 45 Unit ns ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [5, 7]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5]
Notes 5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles. 6. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected. 7. Measured 200 mV from steady state output voltage.
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STK15C88
Table 3. SRAM Write Cycle Parameter Cypress Alt Parameter tWC tAVAV tWLWH, tWLEH tPWE tELWH, tELEH tSCE tSD tDVWH, tDVEH tWHDX, tEHDX tHD tAVWH, tAVEH tAW tSA tAVWL, tAVEL tWHAX, tEHAX tHA [7,8] tWLQZ tHZWE tLZWE [7] tWHQX
25 ns Description Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write Min 25 20 20 10 0 20 0 0 10 5 5 Max
45 ns Min 45 30 30 15 0 30 0 0 15 Max Unit ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled [8]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 8. SRAM Write Cycle 2: CE Controlled [8]
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Notes 8. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 9. CE or WE must be greater than VIH during address transitions.
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STK15C88
AutoStore or Power Up RECALL
Parameter tHRECALL [10] tSTORE [6] VRESET VSWITCH Alt tRESTORE tHLHZ Description Power up RECALL Duration STORE Cycle Duration Low Voltage Reset Level Low Voltage Trigger Level STK15C88 Min Max 550 10 3.6 4.0 4.5 Unit s ms V V
Switching Waveforms
Figure 9. AutoStore/Power Up RECALL
Notes 10. tHRECALL starts from the time VCC rises above VSWITCH.
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STK15C88
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [11, 12] Parameter tRC tSA
[11]
Alt tAVAV tAVEL tELEH tELAX
Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration
25 ns Min 25 0 20 20 20 Max Min 45 0 30 20
45 ns Max
Unit ns ns ns ns
tCW[11] tHACE[7, 11] tRECALL
20
s
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle [12]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
tSA
CE
tSCE
tHACE
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
Notes 11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence). 12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
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STK15C88
Part Numbering Nomenclature STK15C88 - N F 45 I TR
Packaging Option: TR = Tape and Reel Blank = Tube
Temperature Range: Blank - Commercial (0 to 70C) I - Industrial (-40 to 85C)
Speed: 25 - 25 ns 45 - 45 ns
Lead Finish F = 100% Sn (Matte Tin) Package: N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 330 mil SOIC
Ordering Information
Speed (ns) 25 Ordering Code STK15C88-NF25TR STK15C88-NF25 STK15C88-SF25TR STK15C88-SF25 STK15C88-NF25ITR STK15C88-NF25I STK15C88-SF25ITR STK15C88-SF25I 45 STK15C88-NF45TR STK15C88-NF45 STK15C88-SF45TR STK15C88-SF45 STK15C88-NF45ITR STK15C88-NF45I STK15C88-SF45ITR STK15C88-SF45I Package Diagram 51-85026 51-85026 51-85058 51-85058 51-85026 51-85026 51-85058 51-85058 51-85026 51-85026 51-85058 51-85058 51-85026 51-85026 51-85058 51-85058 Package Type 28-Pin SOIC (300 mil) 28-Pin SOIC (300 mil) 28-Pin SOIC (330 mil) 28-Pin SOIC (330 mil) 28-Pin SOIC (300 mil) 28-Pin SOIC (300 mil) 28-Pin SOIC (330 mil) 28-Pin SOIC (330 mil) 28-Pin SOIC (300 mil) 28-Pin SOIC (300 mil) 28-Pin SOIC (330 mil) 28-Pin SOIC (330 mil) 28-Pin SOIC (300 mil) 28-Pin SOIC (300 mil) 28-Pin SOIC (330 mil) 28-Pin SOIC (330 mil) Industrial Commercial Industrial Operating Range Commercial
All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts
Document Number: 001-50593 Rev. **
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STK15C88
Package Diagrams
Figure 11. 28-Pin (300 mil) SOIC (51-85026)
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX.
14
1
0.291[7.39] 0.300[7.62]
4. PACKAGE WEIGHT 0.85gms
*
0.394[10.01] 0.419[10.64]
15
28
0.026[0.66] 0.032[0.81]
PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG.
0.697[17.70] 0.713[18.11]
SEATING PLANE
0.092[2.33] 0.105[2.67] 0.004[0.10] 0.013[0.33] 0.050[1.27] TYP. 0.019[0.48] 0.004[0.10] 0.0118[0.30] * 0.015[0.38] 0.050[1.27] 0.0091[0.23] 0.0125[3.17] *
51-85026-*D
51 85127 *A
Document Number: 001-50593 Rev. **
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STK15C88
Package Diagrams (continued)
Figure 12. 28-Pin (330 mil) SOIC (51-85058)
51-85058-*A
Document Number: 001-50593 Rev. **
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STK15C88
Document History Page
Document Title: STK15C88 256 Kbit (32K x 8) PowerStore nvSRAM Document Number: 001-50593 Rev. ** ECN No. 2625096 Orig. of Change GVCH/PYRS Submission Date 12/19/08 New data sheet Description of Change
Sales, Solutions and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-50593 Rev. **
Revised January 29, 2009
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AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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