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PRELIMINARY
FEMTOCLOCKTM CRYSTAL/LVCMOS-TOLVDS/LVCMOS FREQUENCY SYNTHESIZER
ICS8440258-46
GENERAL DESCRIPTION
The ICS8440258-46 is an 8 output synthesizer IC S optimized to generate Ethernet clocks and a HiPerClockSTM member of the HiPerClock S TM family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the device will generate both 125MHz and 25MHz clocks with mixed LVDS and LVCMOS/LVTTL output logic. The ICS8440258-46 uses IDT's 3rd generations low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8440258-46 is packaged in a small, 5mm x 5mm VFQFN package.
FEATURES
* Four differential LVDS outputs at 125MHz Two LVCMOS/LVTTL single-ended outputs at 125MHz Two LVCMOS/LVTTL single-ended outputs at 25MHz * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * VCO range: 490MHz - 680MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.34ps (typical) * Full 2.5V operating supply * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS6) packages
nXTAL_SEL XTAL_OUT nPLL_SEL REF_CLK XTAL_IN
PIN ASSIGNMENT
Q0 nQ0 GND Q1 nQ1 VDD 1 2 3 4 5 6 7 8
VDDA
VDD
32 31 30 29 28 27 26 25 24 23 nc nc nc GND Q7 VDDO2 Q6 GND
ICS8440258-46
32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
9 10 11 12 13 14 15 16
VDDO1 GND GND VDD Q3 Q4 nQ3 Q5
MR
22 21 20 19 18 17
BLOCK DIAGRAM
MR Pulldown Q0 nPLL_SEL Pulldown
Q2 nQ2
nQ0 Q1 nQ1
25MHz
XTAL_IN
Q2
OSC
XTAL_OUT REF_CLK Pulldown
0 Phase Detector 1 VCO
490-680MHz
1 /5 0
nQ2 Q3 nQ3 Q4
nXTAL_SEL Pulldown
/25
Q5
Q6
Q7
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT TM / ICSTM LVDS/LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 12, 16, 17, 21 4, 5 6, 11, 27 7, 8 9, 10 13, 15, 18, 20 14 19 22, 23, 24 25 Name Q0, nQ0 GND Q1, nQ1 VDD Q2, nQ2 Q3, nQ3 Q4, Q5, Q6, Q7 VDDO1 VDDO2 nc VDDA Type Output Power Output Power Output Output Output Power Power Unused Power Description Differential clock outputs. LVDS interface levels. Power supply ground. Differential clock outputs. LVDS interface levels. Core supply pin. Differential clock outputs. LVDS interface levels. Differential clock outputs. LVDS interface levels. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power output supply pin for Q4 and Q5 LVCMOS outputs. Power output supply pin for Q6 and Q7 LVCMOS outputs. No connect.
Analog supply pin. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = 26 nPLL_SEL Input Pulldown reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are 28 MR Input Pulldown reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 29 REF_CLK Input Pulldown Single-ended LVCMOS/LVTTL reference clock input. Selects between the crystal or REF_CLK inputs as the PLL reference 30 nXTAL_SEL Input Pulldown source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 31, XTAL_OUT, Crystal oscillator interface. XTAL_OUT is the output. Input 32 XTAL_IN XTAL_IN is the input. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical 4 8 51 22 Maximum Units pF pF k
IDT TM / ICSTM LVDS/LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVCMOS) Outputs, IO (LVDS) Continuous Current Surge Current Operating Temperature Range, TA Storage Temperature, TSTG Package Thermal Impedance, JA 10mA 15mA -40C to +85C -65C to 150C 37C/W (0 mps) 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V 5%,TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD, IDDO1, IDDO2 IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 VDD - 0.13 2.375 Typical 2.5 2.5 2.5 170 13 Maximum 2.625 VDD 2.625 Units V V V mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V 5%,TA = 0C TO 70C
Symbol Parameter VIH VIL IIH IIL VOH Input High Voltage Input Low Voltage Input High Current Input Low Current MR, REF_CLK, nPLL_SEL, nXTAL_SEL MR, REF_CLK, nPLL_SEL, nXTAL_SEL VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V -5 Test Conditions Minimum Typical 1.7 -0.3 Maximum VDD + 0.3 0.7 150 Units V V A A
Output High Voltage; Q4:Q7 1.8 VDDO1, VDDO1 = 2.625V5% NOTE 1 Output Low Voltage; Q4:Q7 VOL VDDO1, VDDO1 = 2.625V5% NOTE 1 NOTE 1: Outputs terminated with 50 to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit diagram.
V
0.5
V
IDT TM / ICSTM LVDS/LVCMOS FREQUENCY SYNTHESIZER
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TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V 5%,TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 390 50 1.25 50 Maximum Units mV mV V mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical 25 50 7 1 Maximum Units MHz pF mW Fundamental
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO1 = VDDO2 = 2.5V 5%,TA = 0C TO 70C
Symbol fOUT Parameter Q0:3/nQ0:3 Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle Q4, Q5 Q6, Q7 Q0:3/nQ0:3 Q4:Q7 Q0:3/nQ0:3 Q4, Q5 Q0:3/nQ0:3 Q4:Q7 Q0:3/nQ0:3 125MHz, (1.875MHz - 20MHz) 125MHz, (1.875MHz - 20MHz) 20% to 80% 20% to 80% Test Conditions Minimum Typical 125 125 25 50 50 0.34 0.37 480 1.4 50 54 Maximum Units MHz MHz MHz ps ps ps ps ps ns % %
tsk(o) tjit(O)
tR / tF odc
Q4:Q7 46 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDOX/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
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TYPICAL PHASE NOISE AT 125MHZ (LVCMOS)
-10 -20 -30 -40 -50
Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical)
0
NOISE POWER dBc Hz
-60 -70 -80 -90 -100
Raw Phase Noise Data
-110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100
1k 10k
Phase Noise Result by adding Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ (LVDS)
-10 -20 -30 -40 -50
Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.34ps (typical)
0
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -180 -190 -200 10 100 1k 10k -170
Raw Phase Noise Data
OFFSET FREQUENCY (HZ)
IDT TM / ICSTM LVDS/LVCMOS FREQUENCY SYNTHESIZER
Phase Noise Result by adding Ethernet Filter to raw data
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.25V5% 1.25V5% VDD, VDDO1, VDDO2 LVCMOS
SCOPE
VDDA
Qx
SCOPE
2.5V5% POWER SUPPLY + Float GND -
VDD, VDDO1, VDDA VDDO2
Qx
LVDS
nQx
GND
-1.25V5%
2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
nQx
V
Qx Qx
DDO
2
nQy
V
Qy Qy
DDO
tsk(o)
2 tsk(o)
LVDS OUTPUT SKEW
LVCMOS OUTPUT SKEW
80% Clock Outputs
80% VOD
80% 20% tR
80% 20% tF
20% tR tF
20%
Clock Outputs
LVDS OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
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Phase Noise Plot
Noise Power
nQ0:nQ3 Q0:Q3
Phase Noise Mask
t PW
t
PERIOD
f1
Offset Frequency
f2
odc =
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
V
DDO
Q4:Q7 t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8440258-46 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDO1 and VDDO2 should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA.
2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8440258-46 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT TM / ICSTM LVDS/LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver
VDD
(Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. LVDS OUTPUTS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached.
IDT TM / ICSTM LVDS/LVCMOS FREQUENCY SYNTHESIZER
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2.5V LVDS DRIVER TERMINATION
Figure 4 shows a typical ter mination for LVDS driver in characteristic impedance of 100 differential (50 single)
transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs.
2.5V 2.5V LVDS_Driv er + R1 100
-
100 Ohm Differential Transmission Line Differential Transmission Line 100
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
IDT TM / ICSTM LVDS/LVCMOS FREQUENCY SYNTHESIZER
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8440258-46. Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS840258-46 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Core and LVDS Output Power Dissipation
*
Power (core, LVDS) = VDD_MAX * (IDD + IDDO1 + IDDO2 + IDDA ) = 2.625V * (170mA + 13mA) = 480.4mW
LVCMOS Output Power Dissipation
* * * *
Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 2.625V / [2 * (50 + 12)] = 21.2mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 12 * (21.2mA)2 = 5.4mW per output Total Power Dissipation on the ROUT
Total Power (ROUT) = 5.4mW * 4 = 21.6mW
Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDDO)2 = 8pF * 125MHz * (2.625V)2 = 6.9mW per output
Total Power (125MHz) = 6.9mW * 2 = 13.8mW
*
Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * frequency * (VDDO)2 = 8pF * 25MHz * (2.625V)2 = 1.4 mW per output
Total Power (25MHz) = 1.4mW * 2 = 2.8mW
Total Power Dissipation
*
Total Power = Power (core, LVDS) + Total Power (ROUT) + Total Power (125MHz) + Total Power (25MHz) = 480.4mW + 21.6mW + 13.8mW + 2.8mW = 518.6mW
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2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 6. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.519W * 37C/W = 89.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
32-LEAD VFQFN, FORCED CONVECTION
JA vs. Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
JA vs. Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
TRANSISTOR COUNT
The transistor count for ICS8440258-46 is: 2589
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PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL N A A1 A3 b ND NE D D2 E E2 e L 0.30 1.25 1.25 5.00 BASIC 2.25 5.00 BASIC 2.25 0.50 BASIC 0.40 0.50 3.25 3.25 0.18 0.80 0 MINIMUM NOMINAL 32 --0.25 Ref. 0.25 0.30 8 8 1.00 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8440258AK-46 ICS8440258AK-46T ICS8440258AK-46LF ICS8440258AK-46LFT Marking ICS40258A46 ICS40258A46 ICS0258A46L ICS0258A46L Package 32 Lead VFQFN 32 Lead VFQFN 32 Lead "Lead-Free" VFQFN 32 Lead "Lead-Free" VFQFN Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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