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THIS SPEC IS OBSOLETE
Spec No: 38-07333
Spec Title: CY22K7 133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7(R) Processor and AMD-750 Chipset Sunset Owner: Rose Galindez (RGL)
Replaced by: None
1CY22K7
CY22K7
133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7(R) Processor and AMD-750 Chipset
Features Benefits * Multiple output clocks running at different frequencies Main clock generator for PC motherboard designs using the (R) -- Three open-drain differential CPU outputs running up AMD-K7 processor and AMD-750 Chipset to 133 MHz -- Supports up to two CPUs and chipset -- Eight 3.3V synchronous PCI clocks (one free running) -- Support for 4 PCI slots and chipset -- Two 3.3V AGP clocks at 2xPCI -- Supports designs using AGP -- One dedicated 3.3V USB clock at 48 MHz -- Supports designs using USB -- One 3.3V USB/IO clock at 48 MHz or 24 MHz, selectable -- Allows for one additional USB output or support for I/O via power-on latch input chip from various vendors -- One 3.3V SDRAM clock output running at the CPU fre-- Supports SDRAM memory architecture with external quency PLL buffer -- Two 3.3V Reference clocks at 14.318 MHz -- Supports ISA slots and I/O chip * Spread Spectrum clocking -- 33 kHz modulation frequency -- -0.6% downspread margin * Dedicated inputs for various functions -- PCI_STOP -- CPU_STOP -- PWR_DWN -- SPREAD -- TEST -- USB/IO -- FS [0:1] * Serial Programming Interface * 48-Pin SSOP package EMI reduction
Provides system design flexibility and power management -- Stops all PCI clocks (except PCICLK_F0) when LOW -- Stops all CPU clocks when LOW -- Power is removed from internal logic when LOW -- Activates Spread Spectrum for lower EMI -- Used to enter Test Mode -- Selects USB or SuperIO Clock -- Power-on latched inputs for frequency select options Dynamic control of output clock signals via SMBus Industry-standard package provides cost and space savings
Logic Block Diagram
XTALIN XTALOUT CPU_STOP SPREAD
CPU PLL STOP LOGIC 14.318 MHz Xtal Oscillator
REF [0:1] SDRAM_OUT CPUCLKT [0:2] CPUCLKC [0:2]
FSO FS1 TEST SCLK SDATA PCI_STOP
SYSTEM PLL /2 DIVIDER CONTROL LOGIC STOP LOGIC 2X
AGPCLK [0:1] PCICLK [0:6] PCICLK_F USB0 USB/IO
PWR_DWN
LATCH
USB/IO
Cypress Semiconductor Corporation Document #: 38-07333 Rev. OBS
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 01, 2004
CY22K7
Pin Configuration
48-pin SSOP Top View
FS0/REF0 FS1/REF1 VSSREF XTALIN XTALOUT VSSPCI PCICLK_F PCICLK0 VDDPCI PCICLK1 PCICLK2 VSSPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 VDDAGP AGP0 AGP1 VSSAGP VDDUSB USB0 USB/IO (SELECT) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF VSSSDRAM SDRAM_OUT VDDSDRAM RESERVED CPUCLKC2 CPUCLKT2 VSSCPU CPUCLKC1 CPUCLKT1 VSSCPU CPUCLKC0 CPUCLKT0 RESERVED AVDD AVSS PCI_STOP CPU_STOP PWR_DWN SPREAD TEST SDATA SCLK VSSUSB
Pin Summary[1]
Pin Number 34 33 48 3 1, 2 4 5 9, 15 6, 12 7 8, 10, 11, 13, 14, 16, 17 18 21 19, 20 22 25 23 24 26 27 28 Pin Name AVDD AVSS VDDREF VSSREF FS[0:1]/REF[0:1] XTALIN[2] XTALOUT VDDPCI VSSPCI PCICLK_F PCICLK[0:6] VDDAGP VSSAGP AGP[0:1] VDDUSB VSSUSB USB0 USB/IO (SELECT) SCLK SDATA TEST Type PWR PWR PWR PWR IN/OUT IN OUT PWR PWR OUT OUT PWR PWR OUT PWR PWR OUT IN/OUT IN/OUT IN/OUT IN Isolated power for core Isolated ground for core Power for REF[0:1], XTALIN, XTALOUT Ground for REF[0:1] outputs Frequency select input at power-on/14.318-MHz output 14.318-MHz reference crystal input 14.318-MHz reference crystal feedback Power for PCICLK outputs Ground for PCICLK outputs Free running PCI output PCI clock outputs, TTL compatible 3.3V Power for AGP outputs Ground for AGP outputs AGP clock outputs Power for USB outputs Ground for USB outputs USB clock output USB or Super I/O output selected at power-on by latched input resistor: LOW = 48 MHz, HIGH = 24 MHz SMBus Clock SMBus Data Three-state or Test Mode when LOW Description
Document #: 38-07333 Rev. OBS
CY22K7
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CY22K7
Pin Summary[1] (continued)
Pin Number 29 30 31 32 45 47 46 38, 41 36, 39, 42 37, 40, 43 35, 44 Pin Name SPREAD PWR_DWN[3] CPU_STOP PCI_STOP VDDSDRAM VSSSDRAM SDRAM_OUT VSSCPU CPUCLKT[0:2] CPUCLKC[0:2] RESERVED
[2]
Type IN IN IN IN PWR PWR OUT PWR OUT OUT -
Description Enables spread spectrum when LOW Power-down when LOW, removes power from internal logic Stops CPU clocks when LOW Stops PCI clocks when LOW Power for SDRAM_OUT Ground for SDRAM_OUT CPU reference clock for SDRAM zero delay buffer Ground for CPU outputs shorted to SDRAM ground "True" clocks of differential pair for CPU and host clock outputs "Complementary" clocks of differential pair for CPU and host clock outputs Reserved for future CPU power rail
Function Table
TEST 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPUCLK SDRAM_OUT Hi-Z 50 66 TCLK/2 90 133 120 100 PCICLK PCICLK_F Hi-Z 25 33 TCLK/6 30 33.3 30 33.3 AGP Hi-Z 50 66 TCLK/3 60 66.6 60 66.6 USB/IO Hi-Z 48/24 48/24 TCLK/4[4] 48/24 48/24 48/24 48/24 REF Hi-Z 14.318 14.318 TCLK 14.318 14.318 14.318 14.318
Power Management Modes
PCI_ PWR_DWN CPU_STOP 0 1 1 1 1 X 0 0 1 1 STOP X 0 1 0 1 CPU+ Low Low Low Running Running CPUHigh High High Running Running PCICLK Low Low Running Low Running PCICLK_ F Low Running Running Running Running Other Clocks Low Running Running Running Running
Oscillator Off Running Running Running Running
PLLs Off Running Running Running Running
Notes: 1. All control pins have internal pull-ups of 56K including: USB/IO, TEST, SPREAD, PWR_DWN, CPU_STOP, PCI_STOP. 2. Part will go into test mode if three rising edges come on PCI_STOP while XTALIN is held LOW. 3. Part will consume more shutdown current if external pull-ups are connected on latched input/outputs during power-down. 4. TCLK/4 if Select = 0; TCLK/8 if Select = 1.
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CY22K7
Spread Spectrum Clocking
Spread Spectrum Disabled
Spread Spectrum Enabled
Amplitude (dB)
Frequency (MHz)
Description Modulation Frequency Output CPUCLK, PCICLK, SDRAM_OUT, AGPCLK Min 30.0 0.0 Max 33.0 -0.6 Unit kHz %
Downspread margin at the fundamental frequency CPUCLK, PCICLK, SDRAM_OUT, AGPCLK
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CY22K7
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * SPI Address for the CY22K7 is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W -
Bytes 0 to 3 will be ignored.
Byte 4: Clock Control Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 Pin # 1 24 23 20 19 42, 43 39, 40 36, 37 Default Active Active Active Active Active Active Active Active REF0 USB/IO USB0 AGP1 AGP0 CPUCLK2 (both of differential pair, "True" and "Complementary") CPUCLK1 (both of differential pair, "True" and "Complementary") CPUCLK0 (both of differential pair, "True" and "Complementary") Description
Byte 5: PCI/REF Clock Control Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 Pin # 2 17 16 14 13 11 10 8 Default Active Active Active Active Active Active Active Active REF1 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Description
Byte 6: SDRAM Clock & Generator Mode Control Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 Pin # - - - - - - - 46 Default Inactive Active Active Active Active Active Inactive Active Spread Spectrum Bits[6:4] correspond to the Function Table on page 3 Bit 6 = TEST, Bit 5 = FS1, Bit 4 = FS0 example: Bits[6:4] = `111' -- 100-MHz CPUCLK and SDRAM_OUT clocks Reserved Reserved SPI (directs the generator to utilize either SPI feature selection if bit is enabled or pin-based feature if bit is disabled) SDRAM_OUT Description
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CY22K7
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage .................................................- 0.5 to +4.0V Input Voltage ........................................... - 0.5V to VDD + 0.5 Storage Temperature (Non-Condensing) .. - 65C to +150C Junction Temperature............................................... +150C Package Power Dissipation........................................... 0.7W Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
CY22K7 DC Operating Conditions Over which the DC Characteristics are Guaranteed
Parameter VDD TA CL Description 3.3V Power Supply Voltages Operating Temperature, Ambient Maximum Capacitive Load on SDRAM_OUT PCICLK PCICLK_F AGPCLK USB, REF Reference Frequency, Oscillator Nominal Value Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 14.318 0.05 Min. 3.135 0 Max. 3.465 70 30 30 30 30 20 14.318 50 Unit V C pF
fREF tPU
MHz ms
Electrical Characteristics Over the Operating Range
Parameter VIH VIL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage Input High Current Input Low Current High-level Output Current Except Crystal Pads 0 < VIN < VDD 0 < VIN < VDD SDRAM_OUT PCICLK PCICLK_F AGPCLK USB, USB/IO, REF IOL Low-level Output Current CPUCLK SDRAM_OUT PCICLK PCICLK_F AGPCLK USB, USB/IO, REF IOZ IDD IDDPD VIHS VILS Output Leakage Current Three-state 3.3V Power Supply Current VDD = 3.465V, FCPU = 133 MHz 3.3V Shutdown Current VDD = 3.465V SMBus Input High Level SMBus Input Low Level 0.7 0.3 VOUT = 2.0V VOUT = 2.0V VOUT = 2.0V VOUT = 2.0V VOUT = 2.0V VOUT = 0.3V VOUT = 0.8V VOUT = 0.8V VOUT = 0.8V VOUT = 0.8V VOUT = 0.8V 16 12 19 12 19 16 10 175 200 A mA A V V Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 10 50 -19 -26 -19 -26 -22 mA V V A A mA
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CY22K7
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
CY22K7 CPUCLK Driver Characteristics (Open Drain)[7]
Parameter VDIF Vx VX Description Differential Voltage Differential Crossover Voltage Differential Crossover Voltage Conditions See Note 5 Vpullup is to 1.5V Vpullup (External) = 1.4 to 1.9V Min. = (Vpullup (External)/2) - 150 mV Max. = (Vpullup (External)/2) + 150 mV Min. 0.4 550 550 750 750 Typ. Max. Vpullup (External) + 0.6 950 1100 Unit V mV mV
CY22K7 Switching Characteristics[6, 7] Over the Operating Range @ 100 MHz
Parameter t1 t2 t2 t2 t2 t2 t2 t3 t3 t3 t3 t3 t3 t4 t4 t4 t4 t4 t5 All CPU CPU PCI AGP USB, REF CPU CPU PCI AGP USB, REF CPU, PCI CPU, AGP CPU, CPU PCI, PCI CPU Output Description Output Duty Cycle Rising Edge Rate Rising Edge Rate Rise Time Rise Time Rise Time Falling Edge Rate Falling Edge Rate Fall Time Fall Time Fall Time CPU-PCI Offset CPU-AGP Skew CPU-CPU Skew PCI-PCI Skew Cycle-Cycle Clock Jitter t1A/t1B[8] At Output of CY22K7 CPU As measured at Observation Point in Figure 1 Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.4V At Output of CY22K7 CPU As measured at Observation Point in Figure 1 Between 2.4V and 0.4V Between 2.4V and 0.4V Between 2.4V and 0.4V Between 2.4V and 0.4V Load shown in Figure 1 & Figure 2 Load shown in Figure 1 & Figure 2 Load shown in Figure 1 & Figure 2 Load shown in Figure 1 Load shown in Figure 2 Measured at VX, t5A-t5B 500 500 0.4 1.0 0.4 2.0 2.0 2.0 4.0 700 700 1000 250 500 250 0.4 Test Conditions Min. 45 1.0 0.4 2.0 2.0 2.0 4.0 Typ. Max. 55 Unit % V/ns V/ns ns ns ns ns V/ns V/ns ns ns ns ns ps ps ps ps ps ps
SDRAM_OUT Rise Time
SDRAM_OUT Fall Time
CPU, SDRAM CPU-SDRAM Skew
Notes: 5. VDIF specifies the minimum input differential voltages (VTR - VCP) required for switching, where VTR is the `true' input level and VCP is the `complement' input level. 6. All parameters specified with loaded outputs. 7. All parameters for CPU are measured at observation point shown in Figure 1 on page 10 and parameters for PCI, SDRAM & AGP are measured at observation point shown in Figure 2 on page 11 unless otherwise mentioned. 8. For 133-MHz Output Duty Cycle will be guaranteed at 40% Min., 60% Max.
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CY22K7
Switching Waveforms
Differential Clock Parameters
VDDCPU VTR
VDIF VCP VSS VX
Duty Cycle Timing
t1A OUTPUT
t1B
All Outputs Rise/Fall Time
VDD OUTPUT t2 t3 0V
Output_A-Output_B Clock Skew
OUTPUT_A
OUTPUT_B t4
Cycle-Cycle Clock Jitter
t5A CLK CLK t5B
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CY22K7
Switching Waveforms (continued)
CPU_STOP Timing
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPU, CPU/2, AGP (External)
[9,10]
PCI_STOP
CPUCLK (Internal) PCICLK (Internal) PCICLK
(Free-Running)
PCI_STOP PCICLK (External)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal
[11]
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Notes: 9. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 10. CPU_STOP may be applied asynchronously. It is synchronized internally. 11. USB, USB/IO, REF are not synchronized when entering/leaving power-down.
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CY22K7
VDD
VDDCPU
V1 VDD VDD
V2
R11 R8 T1 T2
R1 C1 T3
VDDCPU R4
CPUCLK_T
R5 R2 R9 T4 T5 C2 T6 VDDCPU R6
Observation Point
C3
CPUCLK_C
R7 C4
CY22K7
R10 VDD VDD
R3
K7 CLOCK INPUT
Figure 1. AMD CPU Load Circuit
Component Values
Symbol V1 V2 R1,3 R2 R4,5,6,7 R8,9 R10,11 C1,2 C3,4 T1,4 T2,5 T3,6 Value 3.3V 1.5V 95 360 500 50 150 680 pF 20 pF Z0 = 50 length = 5" Z0 = 50 length = 3" Z0 = 50 length = 1"
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CY22K7
Observation Point PCI, SDRAM, AGP 33 Zo=50, 5" 12 pF
Figure 2. Test Circuit for PCI/SDRAM/AGP
Ordering Information
Ordering Code CY22K7PVC-1 Package Name O48 Package Type 48-pin SSOP Operating Range Commercial
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-B
AMD-K7 is a registered trademark of Advanced Micro Devices.
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY22K7
Revision History
Document Title: CY22K7 133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7(R) Processor and AMD-750 Chipset Document Number: 38-07333 REV. ** *A OBS ECN NO. 111732 121856 294235 Issue Date 12/16/01 12/14/02 See ECN Orig. of Change DSG RBI RGL Description of Change Change from Spec number: 38-00745 to 38-07333 Power up requirements added to Operating Conditions Information To Obsolete the DS
Document #: 38-07333 Rev. OBS
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